Descriptor scheduling method, computer equipment, storage medium and program product

Abstract

The invention relates to a descriptor scheduling method, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: determining a head and tail pointer deviation when each descriptor queue processes a prefetched descriptor; the prefetch descriptors are sent by a plurality of hosts to descriptor queues corresponding to the hosts respectively, and the prefetch descriptors are used for outputting data of messages; determining each active queue in each descriptor queue according to the head and tail pointer deviation; obtaining a descriptor batch value corresponding to each active queue according to a ratio between an active resource space and the number of the active queues; and outputting the prefetched descriptors in the active queues according to the descriptor batch values corresponding to the active queues. By adopting the method, the resource space can be fully utilized, and the delay of sending the message is effectively shortened.

Description

Descriptor scheduling methods, computer devices, storage media and program products Technical Field

[0001] This application relates to the fields of computer networks and communication technology, and in particular to a descriptor scheduling method, computer equipment, computer-readable storage medium, and computer program product. Background Technology

[0002] With the development of network interface card (NIC) technology, descriptor prefetching technology has emerged. This solution anticipates the data flow requirements that the NIC will soon process and loads information such as descriptors into the NIC's local memory pool or cache in advance, thus avoiding pauses in packet processing due to waiting for descriptor generation or transmission.

[0003] In traditional solutions, the core challenge facing current high-performance network interface cards (NICs) lies in the fixed-threshold prefetching mechanism, which forces each queue to pre-store 500 descriptor spaces to handle data transmission across the entire queue. Real-world testing shows that under typical workloads, 80% of the prefetch space remains idle, impacting SRAM and other storage resources. Summary of the Invention

[0004] Therefore, it is necessary to provide a descriptor scheduling method, computer device, computer-readable storage medium, and computer program product to address the above-mentioned technical problems, which can make fuller use of resource space and effectively shorten the delay of sending messages.

[0005] Firstly, this application provides a descriptor scheduling method, including:

[0006] Determine the head and tail pointer offsets when each descriptor queue processes the prefetch descriptor; the prefetch descriptor is sent by multiple hosts to the respective descriptor queue of each host, and the prefetch descriptor is the data used to output the packet;

[0007] Based on the head and tail pointer deviation, determine each active queue in each of the descriptor queues;

[0008] The descriptor batch value corresponding to each active queue is obtained based on the ratio between the active resource space and the number of active queues;

[0009] Based on the batch value of the descriptor corresponding to each active queue, the prefetch descriptors in each active queue are output.

[0010] Secondly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the descriptor scheduling method in the first aspect.

[0011] Thirdly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the steps of the descriptor scheduling method in the first aspect.

[0012] Fourthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the steps of the descriptor scheduling method in the first aspect.

[0013] The aforementioned descriptor scheduling method, computer device, computer-readable storage medium, and computer program product determine the head and tail pointer offset when each descriptor queue processes prefetched descriptors. Since prefetched descriptors are stored in the descriptor queues in advance, message output lag caused by real-time descriptor generation is avoided. The head and tail pointer offset reflects the number of prefetched descriptors in each descriptor queue. Therefore, based on the head and tail pointer offset, each active queue in each descriptor queue is determined, further refining the descriptor queues into active queues. Then, based on the ratio between the active resource space and the number of active queues, the descriptor batch value corresponding to each active queue is obtained. Based on the descriptor batch value corresponding to each active queue, the prefetched descriptors in each active queue are output. Since the active resource space is the resource space applied to the active queues, it is a resource space that does not need to be allocated to inactive queues, resulting in a larger resource space occupied by the active queues. The active queues can ensure effective processing of descriptors through more resource space. Therefore, by determining the active queue through the deviation of the first and last pointers, and allocating descriptor batch values ​​and corresponding resource space for the active queue, the resource space is utilized more fully, and the delay of sending messages is effectively shortened. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 is an application environment diagram of the descriptor scheduling method in one embodiment;

[0016] Figure 2 is a flowchart of a descriptor scheduling method in one embodiment;

[0017] Figure 3 is a flowchart of a descriptor scheduling method in one embodiment;

[0018] Figure 4 is a structural block diagram of a descriptor scheduling device in one embodiment;

[0019] Figure 5 is an internal structure diagram of a computer device in one embodiment. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0021] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0022] In traditional technologies, network interface card (NIC) queue sizes are limited (typically ≤64 queues), and the impact of a fixed large prefetch size on chip area is controllable. To avoid descriptor supply interruptions under burst traffic, hardware designs tend to employ conservative space allocation strategies. However, as single-machine network bandwidth exceeds 200Gbps and queue sizes expand to 4000+, the prefetch space footprint has surged from 5% to 38%, becoming a key bottleneck restricting chip integration.

[0023] A deeper problem lies in the mismatch between static prefetching and dynamic services: storage-related services require large prefetch volumes (8-16 per queue) to ensure throughput, while latency-sensitive services such as RDMA only require small prefetch volumes (1-3 per queue). Traditional solutions cannot differentiate between queue types, uniformly using the maximum prefetch value, resulting in low-activity queues occupying 60% of the invalid cache. Especially in multi-service mixed scenarios (such as 30% RDMA + 50% storage + 20% TCP), this coarse-grained management leads to less than 40% utilization of storage space such as SRAM, while also causing power imbalance—the prefetch control logic accounts for 65% of power consumption, while the actual data transmission unit utilization is less than 30%. This resource mismatch is amplified in 200Gbps+ network environments, causing chip design to fall into a vicious cycle of "area expansion - power consumption surge - performance limitation".

[0024] Therefore, the core flaw of traditional network interface card (NIC) scheduling technology lies in the dual imbalance between scheduling strategy and hardware resources: On the one hand, the fixed threshold prefetching mechanism requires pre-storing 500 descriptors per queue to cope with the worst-case scenario (all queues active). Actual tests show that 80% of the prefetch space is idle under typical business loads, resulting in a serious waste of SRAM resources. On the other hand, single queue performance and overall system performance cannot be balanced—when the number of active queues > 2000, insufficient prefetch space causes the packet loss rate of critical services to surge by 0.12%; while when the number of active queues < 500, the fixed large prefetch amount triggers head-of-line blocking, causing low-priority traffic to block high-priority queues.

[0025] At this point, if traditional flow control (TC) is used, its decoupling of buffer detection and prefetching strategy makes it impossible to adjust the number of prefetch descriptors according to real-time congestion. Moreover, due to service congestion, the host experiences read latency as high as 2.5μs. Furthermore, the prefetch descriptors are unrelated to service priority, causing latency fluctuations of up to 30% for sensitive services such as RDMA under burst traffic. These shortcomings are amplified in 200Gbps+ network environments, making it difficult for traditional solutions to balance the relationship between storage area, power consumption, and service quality.

[0026] The descriptor scheduling method provided in this application embodiment can be applied to the application environment shown in Figure 1. Each host 102 sends its generated prefetch descriptors to the network interface card scheduler 104 (DWRR). The scheduler 104 buffers the prefetch descriptors into each descriptor queue and processes them sequentially. Multiple descriptor queues are represented by one or more Traffic Classes (TCs). In the DCB (Data Center Bridging) protocol, Traffic Class 106 (TC) is the traffic control method of ETS (Enhanced Transport Selection), used for classifying traffic of different priorities in the network. Each TC can correspond to multiple priority queues. TC_CMD manages the TC buffer size, controlling the number of prefetch descriptors read by the corresponding descriptor queue. The prefetch descriptors output by Traffic Class 106 reach the scheduler 106, and are then parsed by the Read Command Finite State Machine 110 (RD_CMD FSM) to generate packets based on the parsed data. Scheduler 104 and scheduler 106 can be the same scheduler in different states, or they can be different schedulers. CMD stands for Descriptor Cache Control, which can be configured with different weights for different hosts, and the amount of descriptor data prefetched is controlled by DWRR arbitration.

[0027] Each host 102 has its own backpressure mechanism, which is triggered when any backpressure condition is met. When multiple backpressure conditions are not met, an arbitration condition is met. When the arbitration condition is met, schedulers 104 and 106 execute this scheme. For example, when the pcie-proc host-level backpressure is 0, the number of host-level outstanding commands is less than the configuration, and the host-level outstanding data volume is less than the configuration (the configuration is less than the SDB buffer size), then the arbitration condition is met. TC_CMD manages the TC buffer size, controlling the number of prefetch descriptors read from the corresponding descriptor queue. Scheduler 108 is controlled by the Output Queue Manager (OQM) and the Acknowledgment (ACK) signal. The Output Queue Manager is responsible for managing the queue of output packets, handling packet enqueueing, dequeueing, and scheduling logic to complete packet buffering and output. The Acknowledgment signal is used to determine that a packet has been sent and can proceed with generating the next packet.

[0028] For downstream TC management, the amount of descriptor data prefetched from the corresponding TC queue is controlled by the size of the TC buffer sent to the downstream stage, i.e., the size of the packet in the buffer. For example, if the downstream data storage is about to be full, the number of prefetched descriptors needs to be reduced to avoid congestion. If the space of a downstream TC is insufficient, the active resource space allocation for the descriptor batch value and resource space of the queues contained in that TC will be reduced accordingly. TC descriptors can also be scheduled using DWRR or SP. TCs with higher priority can output the prefetched descriptors first to read data, thereby outputting the packet.

[0029] In an exemplary embodiment, as shown in FIG2, a descriptor scheduling method is provided. Taking the application of this method to the scheduler 104 in FIG1 as an example, the method includes the following steps 202 to 208. Wherein:

[0030] Step 202: Determine the head and tail pointer offsets when each descriptor queue processes the prefetch descriptor; the prefetch descriptor is sent by multiple hosts to the corresponding descriptor queue of each host, and the prefetch descriptor is the data used to output the message.

[0031] A descriptor queue is a queue used to process prefetched descriptors. Within the same descriptor queue, prefetched descriptors are retrieved sequentially according to the order in which they were input. Data is then read from the prefetched descriptors and output as a message, following a first-in, first-out (FIFO) order. By allocating resources across different descriptor queues based on shared resources, the allocated resource space for each queue can be determined, and subsequent processing can be performed based on the allocated resource space for each queue.

[0032] A prefetch descriptor is a descriptor stored in the resource space before the message transmission phase. The descriptor is the metadata structure of the message; the actual message data to be sent is obtained by processing the descriptor. The descriptor records the location and attributes of the data packet corresponding to the message. The data packet location can be the buffer address of the message or the address the message needs to reach; the data packet attributes include control information such as the message length or checksum. Because the prefetch descriptor is stored in the descriptor queue in advance, during the message output phase, there is no need to wait for the descriptor generation process; the prefetch descriptor can be directly output as the message, avoiding the lag caused by the real-time generation of descriptors.

[0033] A host is a device that transmits data via a network interface card (NIC). A host can be a local device where the NIC resides, a remote device connected to the NIC via a signal, or even a processor on the same chip as the NIC. Each host's NIC driver independently generates the prefetch descriptors required for its own services and then distributes them to a pre-allocated descriptor queue within the NIC. The NIC allocates resource space through hardware or software isolation mechanisms to ensure that the descriptor queues of different hosts do not interfere with each other.

[0034] In some embodiments, when the host driver controls the network card to send packets, it will initialize and generate prefetch descriptors in the descriptor queue in advance. Then, when the software issues the corresponding send command, the network card controller does not need to wait for the processor to generate descriptors in real time. It can directly read the cached prefetch descriptors, obtain the packet storage location, encapsulate the data into a packet, and then send the packet out.

[0035] The head-to-tail pointer offset is the descriptor offset between the head and tail pointer positions of each descriptor queue. It indicates the number of prefetched descriptors that each descriptor queue needs to process. A larger head-to-tail pointer offset means more prefetched descriptors need to be processed in the descriptor queue, and a smaller offset means fewer prefetched descriptors need to be processed. Prefetched descriptors are data used for output packets and are sent from multiple hosts to their respective descriptor queues.

[0036] In some embodiments, determining the head-to-tail pointer offset when processing prefetched descriptors in each descriptor queue includes: determining the head pointer position of each descriptor queue based on the prefetched descriptors received by each descriptor queue; the prefetched descriptors received by each descriptor queue are sent by the respective hosts corresponding to each descriptor queue; determining the tail pointer position of each descriptor queue based on the output messages of the prefetched descriptors of each descriptor queue; and determining the head-to-tail pointer offset of each descriptor queue based on the number of descriptors between the head pointer position and the tail pointer position of each descriptor queue. Thus, the received prefetched descriptors are arranged sequentially from the head of the descriptor queue, and the prefetched descriptors are output sequentially as messages from the tail of the descriptor queue, forming a pointer chasing strategy.

[0037] Optionally, each host sequentially sends a preset number of prefetch descriptors to multiple empty descriptor queues corresponding to each host in each round, resulting in a filled descriptor queue. The filled descriptor queue is changed to an empty descriptor queue when all the prefetch descriptors in the filled descriptor queue are output as packets.

[0038] Step 204: Determine the active queues in each descriptor queue based on the head and tail pointer deviations.

[0039] An active queue is a queue whose head-to-tail pointer deviation falls within a pointer deviation range. This pointer deviation range is used to identify descriptor queues containing a certain number of prefetched descriptors, thus determining whether a descriptor queue is an active queue. Optionally, the active queue is determined based on the head-to-tail pointer deviation at a specific time granularity; for example, the active queue could be determined based on the head-to-tail pointer deviation at 1 or 5 nanoseconds (ns).

[0040] In some embodiments, each active queue in each descriptor queue can be determined based on the descriptor queues whose head-to-tail pointer deviation is greater than the head-to-tail pointer deviation threshold; for example, each active queue can be determined based on the descriptor queues whose head-to-tail pointer deviation is greater than the head-to-tail pointer deviation threshold.

[0041] Step 206: Based on the ratio between the number of active resource spaces and the number of active queues, obtain the descriptor batch value corresponding to each active queue.

[0042] The active resource space is the shared resource space of the active queues, which belongs to the resource space within Random Access Memory (RAM). By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). For example, the resource space of a prefetch descriptor can be determined by examining the resource space in SRAM.

[0043] Since the active resource space is the resource space applied to the active queue, it is a resource space that does not need to be allocated to the inactive queue. This allows the active queue to occupy a larger resource space, and the active queue can ensure that its descriptor can be processed effectively through more resource space.

[0044] The descriptor batch value is the number of prefetch descriptors that each active queue can support converting into packets within a batch. Because the descriptor batch value is set for both active queues and active resource space, its size is moderate. A batch value that is not too small avoids latency caused by multiple cache accesses, while a batch value that is not too large ensures moderate cache time and resource consumption for each prefetch descriptor, thereby reducing latency.

[0045] The descriptor batch value is determined based on the ratio between the number of active resource spaces and the number of active queues. Therefore, the descriptor batch value is positively correlated with the active resource space and negatively correlated with the number of active queues. The negative correlation means that there is a dynamic inverse relationship between the number of active queues and the descriptor batch value. In this case, the larger the number of active queues, the smaller the descriptor batch value; conversely, the smaller the number of active queues, the larger the descriptor batch value.

[0046] In some embodiments, obtaining the descriptor batch value corresponding to each active queue based on the ratio between the number of active resource spaces and the number of active queues includes: using the ratio between the number of active resource spaces and the number of active queues as the descriptor batch value corresponding to each active queue.

[0047] In some embodiments, obtaining the descriptor batch value corresponding to each active queue based on the ratio between the number of active resource spaces and the number of active queues includes: using the ratio between the number of active resource spaces and the number of active queues as the baseline value corresponding to each active queue; adjusting the baseline value corresponding to each active queue according to the priority of the host corresponding to each active queue to obtain the descriptor batch value corresponding to each active queue; wherein, the higher the priority of the active queue, the larger its corresponding descriptor batch value; the lower the priority of the active queue, the smaller its corresponding descriptor batch value.

[0048] For example, if a fixed threshold latency is used in a traditional approach, a 2k descriptor queue needs to guarantee a performance of 100Mpps and a host read latency of 2.5us. In this case, each queue needs 100Mpps * 2.5us = 250 descriptor storage spaces, and prefetching descriptors requires a total of 2K * 250 = 500K of storage space. In contrast, this embodiment does not require allocating active resource space to inactive queues, thus only requiring 500 (250 * 2, reserving twice) shared storage spaces. Furthermore, additional storage resources corresponding to two queue keep-alive spaces per queue can be added, meaning 500 + 4K = 4.5K descriptor storage spaces are sufficient to meet the performance requirements of the active queues.

[0049] In one embodiment, the software supports setting the initial prefetch quantity and timeout range according to queue type. Different initial prefetch quantities and timeout ranges can be initialized for different use cases. The default value for the initial prefetch quantity is 8 prefetch descriptors per descriptor queue; the minimum value for the timeout range is 50 nanoseconds (ns), and the maximum value is 1 microsecond (μs). Remote Direct Memory Access (RDMA) is a latency-sensitive service. RDMA prefetch quantities are relatively small, with each descriptor queue containing 1-3 prefetch descriptors. When using this embodiment for this latency-sensitive service, it is sufficient to read descriptors from active queues with available space for transmission, effectively shortening the latency of message transmission. Simultaneously, the descriptor queue used for storage can be configured with a larger value, potentially 8-16 prefetch descriptors.

[0050] Step 208: Output the prefetch descriptors in each active queue according to the batch value of the descriptor corresponding to each active queue.

[0051] In some embodiments, the prefetch descriptors in each active queue are output according to the descriptor batch value corresponding to each active queue. This includes: selecting prefetch descriptors from each active queue that prefetch the descriptor batch value corresponding to each active queue; and outputting the selected prefetch descriptors to the next node. The next node can be TC class 106 or the next scheduler 108; however, when scheduler 106 and scheduler 108 are the same scheduler in different states, the next node can be the read command finite state machine 110. Thus, the prefetch descriptor used for each message transition is determined by the descriptor batch value, resulting in more efficient message output.

[0052] In some embodiments, outputting prefetch descriptors in each active queue according to the descriptor batch value corresponding to each active queue includes: if the batch value of the i-th descriptor corresponding to the i-th active queue is less than or equal to the number of prefetch descriptors in the i-th active queue, then selecting the prefetch descriptor with the batch value of the i-th descriptor from the prefetch descriptors in the i-th active queue for output; if the batch value of the i-th descriptor is greater than the number of prefetch descriptors in the i-th active queue, then outputting the prefetch descriptors in the i-th active queue; where i is a positive integer and i is less than or equal to the number of active queues.

[0053] In the aforementioned descriptor scheduling method, the head and tail pointer offsets are determined when each descriptor queue processes prefetched descriptors. Since prefetched descriptors are stored in the descriptor queues beforehand, the real-time generation of descriptors avoids message output delays. The head and tail pointer offsets reflect the number of prefetched descriptors in each descriptor queue. Therefore, based on these offsets, active queues within each descriptor queue are determined, further refining the descriptor queues into active queues. Then, based on the ratio between the number of active resource spaces and the number of active queues, the descriptor batch value corresponding to each active queue is obtained. Based on the descriptor batch value corresponding to each active queue, the prefetched descriptors in each active queue are output. Because the active resource space is applied to active queues and does not need to be allocated to inactive queues, active queues occupy more resource space, ensuring efficient processing of their descriptors. Thus, by determining active queues through head and tail pointer offsets and allocating descriptor batch values ​​and corresponding resource spaces for active queues, resource space is utilized more fully, effectively shortening message transmission latency.

[0054] In some embodiments, determining each active queue in each descriptor queue based on the head-tail pointer deviation includes: statistically analyzing the duration for which the head-tail pointer deviation of each descriptor queue is greater than a deviation threshold to obtain the active duration of each descriptor queue; and determining each active queue based on the descriptor queues whose active duration is greater than the active duration threshold.

[0055] The deviation threshold is a statistical indicator of the duration of the active queue. When the deviation between the first and last pointers exceeds the deviation threshold, the prefetched descriptors in the descriptor queue need to be processed, and packets need to be output. By timing this duration when the deviation between the first and last pointers exceeds the deviation threshold, the active duration of the descriptor queue can be obtained, thus introducing a time dimension to the head-and-tail pointer tracking.

[0056] Active duration is a time-based control attribute of the descriptor queue. Active duration is the duration for which the head and tail pointers deviate significantly. It indicates the duration for which prefetched descriptors exist in each descriptor queue. The longer the active duration, the longer the prefetched descriptors exist in the descriptor queue; the shorter the active duration, the shorter the prefetched descriptors exist in the descriptor queue.

[0057] The active duration threshold is an indicator for judging the duration of active queues. When the active duration exceeds the active duration threshold, the descriptor queue has a relatively longer time for prefetched descriptors, and the output packet time period is relatively longer. When the active duration exceeds the active duration threshold, active resource space can be allocated to these descriptor queues, allowing them to use more resource space to process prefetched descriptors. Using both active duration and the active duration threshold can avoid misidentifying active queues due to momentary head-tail pointer deviations, thereby controlling the update frequency of active queues.

[0058] In this embodiment, not only is the delay controlled by chasing the first and last pointers, but also by the duration during which the deviation between the first and last pointers exceeds the deviation threshold, a time-dimensional control method is formed. This ensures that the minimum adjustment frequency of the active queue is determined according to the active duration threshold, thereby determining the descriptor batch value more precisely.

[0059] In some embodiments, the method further includes: allocating keep-alive resource space according to the number of each descriptor queue to obtain a queue keep-alive space corresponding to each descriptor queue; and outputting prefetched descriptors in each descriptor queue according to the queue keep-alive space corresponding to each descriptor queue; wherein the keep-alive resource space and the active resource space are different resource spaces, and each descriptor queue includes each active queue.

[0060] The keep-alive resource space is the resource space that each descriptor queue has, which is located within Random Access Memory (RAM). The keep-alive resource space is different from the active resource space. By using the keep-alive resource space, we can ensure that the business is not affected by sudden traffic surges, thereby guaranteeing normal data transmission.

[0061] When the descriptor queue uses the active resource space, the high-priority active queue can output prefetched descriptors first. When using both active and keep-alive resource spaces, each descriptor queue is assigned a dedicated keep-alive space to prevent all space resources from being filled by a single or a few queues. Therefore, low-priority descriptor queues will not be completely blocked.

[0062] The queue keep-alive space is a resource space allocated to each descriptor queue. When using the queue keep-alive space, each descriptor queue has its own independent resource space, ensuring that the prefetched descriptors of each descriptor are all processable.

[0063] In some embodiments, the network interface card's (NIC) resource space is divided into an active resource space and a keep-alive resource space according to a preset ratio; for example, the active resource space occupies 95% of the NIC's cache space, while the keep-alive resource space occupies 5% of the NIC's cache space.

[0064] In some embodiments, the keep-alive resource space is allocated according to the number of each descriptor queue to obtain the queue keep-alive space corresponding to each descriptor queue. This includes: determining the queue keep-alive space corresponding to each descriptor queue based on the ratio between the keep-alive resource space and the number of each descriptor queue. Thus, the keep-alive resource space is evenly divided to obtain the queue keep-alive space.

[0065] In some embodiments, the keep-alive resource space is allocated according to the number of each descriptor queue to obtain the queue keep-alive space corresponding to each descriptor queue. This includes: determining a reference value for the queue keep-alive space corresponding to each descriptor queue based on the ratio between the keep-alive resource space and the number of each descriptor queue; and adjusting the reference value for the queue keep-alive space according to the priority of each descriptor queue to obtain the queue keep-alive space corresponding to each descriptor queue. Thus, based on equal allocation, further adjustment is made using priority to ensure that descriptor queues with higher priority have larger queue keep-alive spaces, thereby guaranteeing that high-priority active queues can output prefetched descriptors first.

[0066] In this embodiment, a double buffer structure is formed by keeping-alive resource space and active resource space. The active queues share the resources in the active resource space, and the active queues and inactive queues also have their own corresponding queue keep-alive spaces. Therefore, when the descriptor queue uses the active resource space and the high-priority active queue can output prefetch descriptors first, it can prevent all space resources from being filled by a single or a few queues. Thus, the low-priority descriptor queues will not be completely blocked.

[0067] In some embodiments, the descriptor batch value corresponding to each active queue is obtained based on the ratio between the number of active resource spaces and the number of active queues, including: determining the number of queues to be allocated based on the sum of the number of active queues and the number of spare queues; obtaining the descriptor batch value corresponding to each active queue and the descriptor batch value corresponding to the spare queue based on the ratio between the active resource space and the number of queues to be allocated; wherein, the descriptor batch value corresponding to the spare queue is used to output based on the prefetch descriptors in the spare queue.

[0068] The spare queue is used to reduce the impact of latency; the number of queues to be allocated is the sum of the number of active queues and the number of spare queues. The number of active queues is adaptively adjusted based on the head-tail pointer deviation, while the number of spare queues can be a preset value or a dynamically set value. In this embodiment, implemented by a network interface card, the number of spare queues can be fixed at one. Optionally, multiple hosts corresponding to the spare queue can send prefetch descriptors to the spare queue and then execute the corresponding data for the output prefetch descriptor to avoid data latency issues.

[0069] The number of queues to be allocated is the amount of active resource space to be allocated to the active queue and the surplus queue. Using the number of queues to be allocated increases the number of ways prefetch descriptors can be resolved.

[0070] In some embodiments, determining the number of queues to be allocated based on the sum of the number of active queues and the number of spare queues includes: summing the number of active queues and the number of spare queues to obtain the number of queues to be allocated.

[0071] In one exemplary embodiment, the descriptor batch values ​​corresponding to each active queue and the descriptor batch values ​​corresponding to the surplus queue are adaptively and evenly distributed, and their expression is as follows:

[0072] N_prefetch=Total_cache / (Active_QP+1)

[0073] Where N_prefetch is the descriptor batch value, Total_cache is the size of the active space resource, Active_QP is the number of active queues, and 1 is the number of spare queues.

[0074] In this embodiment, since the prefetch descriptors in the descriptor queue are sent by the host, there may be a data delay in reaching the network card. The active queue has a first-in-first-out characteristic, which makes it impossible for some related descriptor batch values ​​to be output in the order of transmission. By forming two queues in the active resource space through the reserve queue and the active queue, the reserve queue is used to deal with the situation of delayed data transmission, so that the prefetch descriptors that are delayed in being sent to the network card can be closer to their related prefetch descriptors, thereby ensuring the efficiency of packet output.

[0075] In some embodiments, the prefetch descriptors in each active queue are output according to the descriptor batch value corresponding to each active queue, including: if the batch value of the i-th descriptor corresponding to the i-th active queue is less than or equal to the i-th quantity, then the prefetch descriptor with the batch value of the i-th descriptor is selected from the prefetch descriptors in the i-th active queue and output; if the batch value of the i-th descriptor is greater than the i-th quantity, then when there is a prefetch descriptor in the i-th active queue and the duration of the batch value of the i-th descriptor being greater than the i-th quantity is greater than the output duration threshold, the prefetch descriptors in the i-th active queue are output; where i is a positive integer, and i is less than or equal to the number of active queues; the i-th quantity is the number of prefetch descriptors in the i-th active queue.

[0076] The output duration threshold is an output indicator when the active queue contains a small number of prefetch descriptors. If the duration of prefetch descriptors in the active queue exceeds the output duration threshold, it is determined that the host has sent the complete prefetch descriptor to the descriptor queue, and a complete packet can be output.

[0077] In some embodiments, selecting a prefetch descriptor for the batch value of the i-th descriptor from the prefetch descriptors in the i-th active queue includes: selecting prefetch descriptors for the batch value of the i-th descriptor in the i-th active queue according to the order in which the prefetch descriptors were input into the i-th active queue, generating and outputting them sequentially.

[0078] In some embodiments, when it is determined that the batch value of the i-th descriptor is greater than the i-th quantity, a timer is used to measure the duration for which the i-th active queue contains prefetched descriptors and the batch value of the i-th descriptor is greater than the i-th quantity, so that when the duration is greater than the output duration threshold, the prefetched descriptors in the i-th active queue are output.

[0079] In some embodiments, outputting the prefetch descriptors in the i-th active queue includes: in the prefetch descriptors in the i-th active queue, according to the order in which the prefetch descriptors are input into the i-th active queue, sequentially selecting each prefetch descriptor in the i-th active queue to generate and output the data in the prefetch descriptor, so as to obtain a message based on the data in the prefetch descriptor.

[0080] For example, if the batch value of the i-th descriptor corresponding to the i-th active queue is 10, and the number of prefetch descriptors in the i-th active queue is 21, and the host does not send prefetch descriptors to the active queue, then in the prefetch descriptors in the i-th active queue, the first time 10 prefetch descriptors are selected and output as packets, and the second time 10 prefetch descriptors are selected and output as packets; when selecting prefetch descriptors for the third time, the time when there is 1 remaining prefetch descriptor in the i-th active queue is timed to determine that there is a prefetch descriptor in the i-th active queue and the batch value of the i-th descriptor is greater than the duration of the i-th number; only when this duration is greater than the output duration threshold is a packet output based on the prefetch descriptors in the i-th active queue.

[0081] In this embodiment, when the active queue contains a large number of prefetch descriptors, the prefetch descriptors of the descriptor batch value are selected for output to reduce latency; while when the number of prefetch descriptors in the active queue is small, the prefetch descriptors in the active queue are output after a certain period of time to prevent residual data.

[0082] In some embodiments, before obtaining the descriptor batch value corresponding to each active queue based on the ratio between the number of active resource spaces and the number of active queues, the method further includes: combining the number of active queues and the number of prefetch descriptors in each active queue to determine the size of the active resource space; wherein the number of active queues and the number of prefetch descriptors in each active queue are both positively correlated with the size of the active resource space.

[0083] In some embodiments, the size of the active resource space is determined by combining the number of active queues and the number of prefetch descriptors in each active queue, including: multiplying the number of active queues and the number of prefetch descriptors in each active queue to obtain the amount of prefetch descriptors to be processed; and determining the size of the active resource space that is positively correlated with the amount of prefetch descriptors to be processed.

[0084] Since the prefetch descriptors in the active queue are sent by the host, and the active queue is determined by the head-tail pointer offset, it can adaptively adjust with the number of prefetch descriptors. Therefore, the active resource space is obtained by synchronously adjusting these two variables, making it similar to a sliding window. The total buffer size, obtained by multiplying the number of prefetches and the number of active queues, is then used to calculate the descriptor batch value for each active queue, which represents the number of descriptors to be read, given the constantly changing number of queues.

[0085] In this embodiment, the size of the active resource space required for the network card cache is determined by combining the number of active queues and the number of prefetch descriptors in each active queue. This allows the active space resources to change dynamically with the active queues, ensuring sufficient cache size when packets need to be output.

[0086] In some embodiments, the method further includes: determining a flow host whose number of packets in the buffer meets the flow control conditions; and reducing the number of prefetch descriptors sent by the flow host.

[0087] The packets in the buffer are those that did not meet the sending conditions. These conditions include the network interface card's (NIC) sending port being idle, allowing the sending port to receive packets forwarded by the NIC. A new packet is retrieved from the buffer and sent to the NIC's downstream node only after the subsequent module has finished sending the previous packet. Sending ports include, but are not limited to, MAC layer sending units and physical layer interfaces.

[0088] Flow control conditions are backpressure metrics set for packets in the buffer. When the number of packets in the buffer meets the flow control conditions, prefetch descriptors in the descriptor queue cannot be converted into packets, potentially causing congestion. Therefore, the number of prefetch descriptors sent by the host is reduced to avoid invalid prefetch descriptors. Optionally, the flow control condition can be that the number of packets in the buffer reaches a threshold, for example, a preset percentage or a preset number of packets of the total buffer size. The host to be flow controlled is the host whose backpressure processing is performed by the network interface card (NIC).

[0089] In this embodiment, the number of packets in the network card's cache is used to regulate the corresponding host to be controlled, thereby controlling the number of prefetch descriptors and avoiding unnecessary congestion.

[0090] In one embodiment, the software supports setting the initial prefetch quantity and timeout range according to queue type. Different initial prefetch quantities and timeout ranges can be initialized for different use cases. The default value for the initial prefetch quantity is 8 prefetch descriptors per descriptor queue; the minimum value for the timeout range is 50 nanoseconds (ns), and the maximum value is 1 microsecond (μs). Remote Direct Memory Access (RDMA) is a latency-sensitive service. RDMA prefetch quantities are relatively small, with each descriptor queue containing 1-3 prefetch descriptors. When using this embodiment for this latency-sensitive service, it is sufficient to read descriptors from active queues with available space for transmission, effectively shortening the latency of message transmission. Therefore, different initial prefetch quantities and timeout ranges can be initialized for different use cases.

[0091] Data needs to be read from multiple hosts in the preceding stage. At this point, to reduce the latency of host-initiated memory read operations (mem-rd), the amount of data in the prefetch descriptors and the number of outstanding reads are controlled. The outstanding command refers to an instruction issued by the host but not yet processed by the network interface card (NIC), which is the prefetch descriptor. The number of outstanding reads per instance is the descriptor batch value. Multiplying the number of outstanding reads by the number of reads per instance gives the total amount of prefetched data, which can be used to determine the resource space occupied by the prefetch descriptors on the host side. Therefore, the NIC's downstream scheduler reads data from the upstream scheduler to identify the hosts to be controlled and to control the input of prefetch descriptors to the downstream scheduler.

[0092] In this embodiment, a double buffer structure is formed by keeping-alive resource space and active resource space. The active queues share the resources in the active resource space, and the active queues and inactive queues also have their own corresponding queue keep-alive spaces. Therefore, when the descriptor queue uses the active resource space and the high-priority active queue can output prefetch descriptors first, it can prevent all space resources from being filled by a single or a few queues. Thus, the low-priority descriptor queues will not be completely blocked.

[0093] Then, identify the host whose number of packets in the buffer meets the flow control conditions and reduce the number of prefetch descriptors sent by the host whose flow is under control.

[0094] In one embodiment, a two-pointer tracking mechanism is employed: the descriptor queue is determined to be active by comparing the nanosecond-level deviation (precision ±1 descriptor) between the Head and Tail pointers. When the duration of Head=Tail reaches 5ns, the list of active queues is updated. When Head=Tail for 5ns, the queue is determined to be inactive, and no shared buffer needs to be allocated for it, but a keep-alive region is reserved for it. The head and tail pointers are chased; when the tail stops (software stops sending messages), the hardware slowly processes the sent data, and the head slowly moves to equal the tail. At this point, the head-tail deviation value is 0, and all prefetched descriptors in the descriptor queue have been processed. A timeout counter (32-bit precision / 10ns resolution) automatically triggers the enqueueing of residual data to prevent deadlock caused by improper threshold settings.

[0095] In one embodiment, as shown in Figure 3, the descriptors in Figure 3 include Desc WB (descriptor has been written), waiting for hardware processing (Write Back); Desc HW (hardware is using or has processed the descriptor); Desc SW (prefetch descriptor), a software-prepared descriptor waiting for hardware to read; and Blank, an idle or unallocated descriptor.

[0096] For scenarios with thousands of queues, a sliding window algorithm is designed to dynamically divide the boundaries between the common area and the keep-alive area. The common area is the active resource space, and the keep-alive area is the keep-alive resource space. Within the descriptor queues, the number of active descriptors in each queue can be obtained based on the head and tail pointer deviations. Queues containing more than a threshold of active descriptors are considered active queues. Because the active resource space is a shared buffer with a limited size, when reading descriptors based on active queues, more active queues mean less resource space occupied by each active queue, resulting in a smaller descriptor batch size.

[0097] The sliding window algorithm calculates the total buffer size by multiplying the number of prefetched descriptors by the number of active queues. Each logical cycle calculates the current window size in real time to update the size of the active resource space.

[0098] For the constantly changing number of queues, a sliding calculation is performed to determine the number of descriptors each queue should read. Increasing by 1 reserves one queue as a margin; this queue is the margin queue. Adding other numbers provides even greater margins; in some cases, the margin of one queue is sufficient to cover the impact of data stream latency within the chip.

[0099] Each queue has an independent timeout control. When the active queue contains a large number of prefetch descriptors, the prefetch descriptors of the batch value of the descriptors are selected and output as packets to reduce latency. When the number of prefetch descriptors in the active queue is small, the prefetch descriptors in the active queue are output as packets after a certain period of time to prevent residual data.

[0100] As shown in Figure 3, qn represents the resource space of each descriptor queue QPn. q1, q2, and q3 are active queues, and therefore are allocated both queue keep-alive space and active resource space. This resource space includes queue keep-alive space and active resource space dynamically allocated with the active queues. The queue keep-alive space ensures that each descriptor queue has its own dedicated space, preventing all space from being filled by a single or a few descriptor queues, thus completely blocking some low-priority queues. Here, n is a positive integer representing each queue.

[0101] When prefetch descriptors are converted from data to packets (pkt), the number of prefetch descriptors can be controlled by the number of packets in the buffer. In this case, the actual data of the sent packet can be read based on the content within the descriptor, and the descriptor batch size used by the descriptor queue to read descriptors can be adjusted according to the actual data volume. For example, if the data volume of the packet corresponding to each prefetch descriptor is small, the descriptor batch size when reading descriptors from that descriptor queue needs to be increased to ensure the output throughput of that descriptor queue; conversely, if the data volume of the packet corresponding to each prefetch descriptor is large, the descriptor batch size when reading descriptors should be decreased.

[0102] In one exemplary embodiment, the descriptor batch values ​​corresponding to each active queue and the descriptor batch values ​​corresponding to the surplus queue are adaptively and evenly distributed, and their expression is as follows:

[0103] N_prefetch=Total_cache / (Active_QP+1)

[0104] Where N_prefetch is the descriptor batch value, Total_cache is the size of the active space resource, Active_QP is the number of active queues, and 1 is the number of spare queues.

[0105] If a fixed threshold latency is used in a traditional approach, a 2k descriptor queue needs to guarantee a performance of 100Mpps and a host read latency of 2.5us. This requires 100Mpps * 2.5us = 250 descriptor storage spaces per queue, and a total of 2K * 250 = 500K storage space for prefetching descriptors. In contrast, this embodiment does not require allocating active resource space to inactive queues, thus only requiring 500 shared storage spaces (250 * 2, reserving twice the space). Furthermore, additional storage resources corresponding to two queue keep-alive spaces per queue can be added, resulting in 500 + 4K = 4.5K descriptor storage spaces sufficient to meet the performance requirements of the active queues.

[0106] Since the prefetch descriptors in the descriptor queue are sent by the host, there may be data delays in reaching the network card. The active queue has a first-in-first-out characteristic, which means that some related descriptor batch values ​​cannot be output as packets in the order of sending. By forming two queues in the active resource space through the reserve queue and the active queue, the reserve queue can deal with the situation of delayed data transmission, so that the prefetch descriptors sent to the network card with delays can be closer to their related prefetch descriptors, thereby ensuring packet output efficiency.

[0107] Based on this, according to the difference between the head and tail pointers of the descriptor queue and the back pressure of the egress TC, the descriptors in the active queue that have space to be sent can be read, effectively shortening the delay of sending messages.

[0108] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0109] Based on the same inventive concept, this application also provides a descriptor scheduling apparatus for implementing the descriptor scheduling method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more descriptor scheduling apparatus embodiments provided below can be found in the limitations of the descriptor scheduling method described above, and will not be repeated here.

[0110] In an exemplary embodiment, as shown in FIG4, a descriptor scheduling apparatus is provided, comprising:

[0111] The deviation determination module 402 is used to determine the head and tail pointer deviation when each descriptor queue processes the prefetch descriptor; the prefetch descriptor is sent by multiple hosts to the descriptor queue corresponding to each host, and the prefetch descriptor is data used to output the message;

[0112] The active queue determination module 404 is used to determine each active queue in each of the descriptor queues based on the head and tail pointer deviation.

[0113] Batch value determination module 406 is used to obtain the descriptor batch value corresponding to each active queue based on the ratio between the active resource space and the number of active queues;

[0114] The descriptor output module 408 is used to output the prefetched descriptors in each of the active queues according to the descriptor batch value corresponding to each of the active queues.

[0115] In one embodiment, the active queue determination module 404 is configured to:

[0116] The duration during which the head and tail pointer deviations of each descriptor queue are greater than the deviation threshold is statistically analyzed to obtain the active duration of each descriptor queue.

[0117] Each active queue is determined based on the descriptor queues whose active duration is greater than the active duration threshold.

[0118] In one embodiment, the descriptor output module 408 is configured to:

[0119] Based on the number of each descriptor queue, the keep-alive resource space is allocated to obtain the queue keep-alive space corresponding to each descriptor queue;

[0120] Based on the queue keep-alive space corresponding to each descriptor queue, the prefetched descriptors in each descriptor queue are output;

[0121] The keep-alive resource space and the active resource space are different resource spaces, and each descriptor queue includes each active queue.

[0122] In one embodiment, the batch value determination module 406 is configured to:

[0123] The number of queues to be allocated is determined based on the sum of the number of active queues and the number of spare queues;

[0124] Based on the ratio between the active resource space and the number of queues to be allocated, the descriptor batch value corresponding to each active queue and the descriptor batch value corresponding to the remaining queue are obtained.

[0125] The descriptor batch value corresponding to the surplus queue is used to output messages based on the prefetch descriptors in the surplus queue.

[0126] In one embodiment, the descriptor output module 408 is configured to:

[0127] If the batch value of the i-th descriptor corresponding to the i-th active queue is less than or equal to the i-th quantity, then the prefetch descriptor with the batch value of the i-th descriptor is selected from the prefetch descriptors in the i-th active queue and output.

[0128] If the batch value of the i-th descriptor is greater than the i-th quantity, then when there are prefetch descriptors in the i-th active queue and the duration of the batch value of the i-th descriptor being greater than the duration of the i-th quantity is greater than the output duration threshold, the prefetch descriptors in the i-th active queue will be output.

[0129] Where i is a positive integer, and i is less than or equal to the number of active queues; the i-th number is the number of prefetch descriptors in the i-th active queue.

[0130] In one embodiment, before obtaining the batch value of the descriptor corresponding to each active queue based on the ratio between the active resource space and the number of active queues, the batch value determination module 406 is configured to:

[0131] The size of the active resource space is determined by combining the numerical values ​​of the number of active queues and the number of prefetch descriptors in each active queue.

[0132] The number of active queues and the prefetch descriptors in each active queue are both positively correlated with the size of the active resource space.

[0133] In one embodiment, the descriptor output module 408 is configured to:

[0134] Identify the host whose number of packets in the cache meets the flow control conditions;

[0135] Reduce the number of prefetch descriptors sent by the host controlling the stream.

[0136] Each module in the aforementioned descriptor scheduling device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can invoke and execute the operations corresponding to each module.

[0137] In an exemplary embodiment, a computer device is provided, which may be a scheduler, and its internal structure diagram is shown in Figure 5. The computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is connected to the system bus via the I / O interfaces. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes non-volatile storage media and internal memory. The non-volatile storage media stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The I / O interfaces of the computer device are used for exchanging information between the processor and external devices. The communication interface of the computer device is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a descriptor scheduling method.

[0138] Those skilled in the art will understand that the structure shown in Figure 5 is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or may combine certain components, or may have different component arrangements.

[0139] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0140] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0141] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0142] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0143] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0144] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0145] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A descriptor scheduling method, characterized in that, The method includes: determining the head-to-tail pointer offset when each descriptor queue processes a prefetch descriptor; the prefetch descriptor is sent by multiple hosts to the respective descriptor queue of each host, and the prefetch descriptor is data used for outputting packets; determining each active queue in each descriptor queue based on the head-to-tail pointer offset; obtaining the descriptor batch value corresponding to each active queue based on the ratio between the active resource space and the number of active queues; and outputting the prefetch descriptors in each active queue based on the descriptor batch value corresponding to each active queue.

2. The method according to claim 1, characterized in that, The step of determining each active queue in each descriptor queue based on the head-tail pointer deviation includes: statistically analyzing the duration for which the head-tail pointer deviation of each descriptor queue is greater than a deviation threshold to obtain the active duration of each descriptor queue; and determining each active queue based on the descriptor queues whose active duration is greater than the active duration threshold.

3. The method according to claim 1, characterized in that, The method further includes: allocating the keep-alive resource space according to the number of each descriptor queue to obtain the queue keep-alive space corresponding to each descriptor queue; and outputting the prefetched descriptors in each descriptor queue according to the queue keep-alive space corresponding to each descriptor queue; wherein the keep-alive resource space and the active resource space are different resource spaces, and each descriptor queue includes each active queue.

4. The method according to claim 1, characterized in that, The step of obtaining the descriptor batch value corresponding to each active queue based on the ratio between the active resource space and the number of active queues includes: determining the number of queues to be allocated based on the sum of the number of active queues and the number of spare queues; obtaining the descriptor batch value corresponding to each active queue and the descriptor batch value corresponding to the spare queue based on the ratio between the active resource space and the number of queues to be allocated; wherein, the descriptor batch value corresponding to the spare queue is used to output packets based on the prefetch descriptors in the spare queue.

5. The method according to claim 1, characterized in that, The step of outputting prefetch descriptors in each active queue according to the descriptor batch value corresponding to each active queue includes: if the batch value of the i-th descriptor corresponding to the i-th active queue is less than or equal to the i-th quantity, then the prefetch descriptor with the batch value of the i-th descriptor is selected from the prefetch descriptors in the i-th active queue and output; if the batch value of the i-th descriptor is greater than the i-th quantity, then when there is a prefetch descriptor in the i-th active queue and the duration of the batch value of the i-th descriptor being greater than the i-th quantity is greater than the output duration threshold, the prefetch descriptor in the i-th active queue is output; where i is a positive integer, and i is less than or equal to the number of active queues; the i-th quantity is the number of prefetch descriptors in the i-th active queue.

6. The method according to claim 1, characterized in that, Before obtaining the descriptor batch value corresponding to each active queue based on the ratio between the active resource space and the number of active queues, the method further includes: combining the number of active queues and the number of prefetch descriptors in each active queue to determine the size of the active resource space; wherein the number of active queues and the number of prefetch descriptors in each active queue are both positively correlated with the size of the active resource space.

7. The method according to claim 1, characterized in that, The method further includes: determining a host whose number of packets in the cache meets the flow control conditions; and reducing the number of prefetch descriptors sent by the host whose flow is under control.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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