Timing alignment method, apparatus, medium, and device

Abstract

The application discloses a timing alignment method, device, medium and equipment, relates to the technical field of communication, and comprises the following steps: determining the buffered parallel data corresponding to a target clock cycle from the parallel data stream corresponding to the current receiving round; performing shift selection on the buffered parallel data to obtain a plurality of to-be-retrieved data segments; retrieving each to-be-retrieved data segment in the plurality of to-be-retrieved data segments based on a preset delimiter, determining first delimiting indication information corresponding to the buffered parallel data; determining second delimiting indication information corresponding to the buffered parallel data based on the first delimiting indication information corresponding to the buffered parallel data and a decision window corresponding to the target clock cycle; and extracting the buffered parallel data according to the second delimiting indication information corresponding to the buffered parallel data to obtain aligned parallel data corresponding to the target clock cycle. The application can perform timing alignment on the data stream in a clock cycle-by-clock cycle manner, and can guarantee the recovery and alignment of the data timing when a disturbance occurs.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to timing alignment methods, apparatus, media, and devices. Background Technology

[0002] Next-generation Passive Optical Network (PON) broadband access networks utilize passive optical network technology to achieve the last mile of fiber optic deployment to homes and offices. Standardized passive optical networks provide bidirectional operation from multiple optical network units (ONUs) located at or near the user to the optical line terminal (OLT) at the network provider.

[0003] In passive optical network systems, optical network units and optical line terminals are the most important components. When testing the function and performance of optical line terminals, it is necessary to restore the normal timing after receiving the parallel data stream obtained by serialization according to a certain encoding order. Furthermore, as the optical power changes, bit jumps or offsets may occur in the received parallel data stream, which increases the difficulty of timing recovery and alignment. Summary of the Invention

[0004] To accurately perform time alignment of parallel data in a parallel data stream, this application provides a time alignment method, apparatus, medium, and device. The technical solution is as follows:

[0005] Firstly, this application provides a timing alignment method, the method comprising:

[0006] From the parallel data stream corresponding to the current receiving round, determine the buffered parallel data corresponding to the target clock cycle; the target clock cycle is any clock cycle in the parallel data stream.

[0007] Based on a preset delimiter, the cached parallel data corresponding to the target clock cycle is shifted and selected to obtain multiple data segments to be retrieved.

[0008] Based on the preset delimiter, each of the plurality of data segments to be retrieved is retrieved to determine the first delimiting indication information corresponding to the cached parallel data;

[0009] Based on the first delimiting indication information corresponding to the cached parallel data and the adjudication window corresponding to the target clock cycle, the second delimiting indication information corresponding to the cached parallel data is determined; the current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous reception round.

[0010] If the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, the cached parallel data is extracted according to the second delimiting indication information corresponding to the cached parallel data to obtain the aligned parallel data corresponding to the target clock cycle.

[0011] Optionally, determining the buffered parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round includes:

[0012] Based on the selection window corresponding to the current receiving round and the parallel data stream corresponding to the current receiving round, determine the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle relative to the target clock cycle;

[0013] The parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle are merged to obtain the cached parallel data corresponding to the target clock cycle.

[0014] Optionally, based on a preset delimiter, the buffered parallel data corresponding to the target clock cycle is shifted and selected to obtain multiple data segments to be retrieved, including:

[0015] Using the first bit in the cached parallel data as the starting selection position, extract a continuous data segment of a preset length from the cached parallel data, and move the starting selection position bit by bit to extract multiple segments to obtain the multiple data segments to be retrieved.

[0016] The preset length is the same as the length of the preset delimiter.

[0017] Optionally, the step of searching each of the plurality of data segments to be searched based on the preset delimiter to determine the first delimiting indication information corresponding to the cached parallel data includes:

[0018] Perform a bitwise XOR operation between each data segment to be retrieved and the preset delimiter to obtain the calculation result corresponding to each data segment to be retrieved;

[0019] Based on the calculation results corresponding to each data segment to be retrieved, the difference information between each data segment to be retrieved and the preset delimiter is determined;

[0020] Based on the preset fault tolerance threshold and the difference information, the first delimiting indication information corresponding to the cached parallel data is determined; the first delimiting indication information corresponding to the cached parallel data indicates whether there is a data segment to be retrieved whose difference bit length between the preset delimiter and the preset delimiter is less than the preset fault tolerance threshold, and indicates the position of the data segment to be retrieved in the cached parallel data whose difference bit length between the preset delimiter and the preset fault tolerance threshold is less than the preset fault tolerance threshold.

[0021] Optionally, determining the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to the cached parallel data and the decision window corresponding to the target clock cycle includes:

[0022] Within the current duration of the adjudication window corresponding to the target clock cycle, if the first delimiting indication information corresponding to the cached parallel data indicates the existence of the target data segment, and the difference in bit length between the target data segment and the preset delimiter is less than the preset fault tolerance threshold, then based on the position of the target data segment in the cached parallel data, the second delimiting indication information corresponding to the cached parallel data is determined; the second delimiting indication information corresponding to the cached parallel data indicates the existence of the target data segment that is the same as or similar to the preset delimiter in the cached parallel data, and indicates the position of the target data segment in the cached parallel data.

[0023] Optionally, determining the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to the cached parallel data and the decision window corresponding to the target clock cycle includes:

[0024] If, within the current duration of the adjudication window corresponding to the target clock cycle, the first delimiting indication information corresponding to the cached parallel data indicates that the difference in bit length between each data segment to be retrieved and the preset delimiter is not less than the preset fault tolerance threshold, then the timing alignment for the target clock cycle is skipped.

[0025] Optionally, the method further includes:

[0026] In the first receiving round, if the first delimiting indication information corresponding to the cached parallel data indicates the existence of the target data segment, and the difference in the number of bits between the target data segment and the preset delimiter is less than the preset fault tolerance threshold, then based on the position of the target data segment in the cached parallel data, the second delimiting indication information corresponding to the cached parallel data is determined; the second delimiting indication information corresponding to the cached parallel data indicates the existence of the target data segment that is the same as or similar to the preset delimiter in the cached parallel data, and indicates the position of the target data segment in the cached parallel data.

[0027] Optionally, determining the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to the cached parallel data and the decision window corresponding to the target clock cycle includes:

[0028] If, within the current duration of the adjudication window corresponding to the target clock cycle, the first delimiting indication information corresponding to the cached parallel data indicates the existence of multiple target data segments, then, based on the position of the target data segment with the smallest difference bit length between itself and the preset delimiter in the cached parallel data, the second delimiting indication information corresponding to the cached parallel data is determined.

[0029] Optionally, the method further includes:

[0030] When the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the boundary position of the parallel data corresponding to the target clock cycle, the first duration of the decision window is determined.

[0031] When the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at a non-boundary position of the parallel data corresponding to the target clock cycle, the second duration of the decision window is determined.

[0032] The first duration or the second duration is the next duration of the decision window corresponding to the target clock cycle in the next reception round.

[0033] Optionally, the method further includes:

[0034] After determining the second delimiting indication information corresponding to the target clock cycle in the previous receiving round, a target counter corresponding to the target clock cycle is started; the initial value of the target counter is the same as the length of the clock cycle of the parallel data stream; the value of the target counter is decremented by 1 after each clock cycle.

[0035] When the value of the target counter decreases to a preset threshold corresponding to the current duration, the adjudication window corresponding to the target clock cycle is opened until the target counter finishes counting and the adjudication window corresponding to the target clock cycle is closed, so as to determine the second delimitation indication information corresponding to the buffered parallel data in the current receiving round within the current duration of the adjudication window corresponding to the target clock cycle.

[0036] Secondly, this application provides a timing alignment apparatus, the apparatus comprising:

[0037] The data acquisition module is used to determine the cached parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round; the target clock cycle is any clock cycle in the parallel data stream.

[0038] The shift selection module is used to shift and select the cached parallel data corresponding to the target clock cycle based on a preset delimiter to obtain multiple data segments to be retrieved;

[0039] The first delimiting module is used to search each of the plurality of data segments to be searched based on the preset delimiter, and determine the first delimiting indication information corresponding to the cached parallel data.

[0040] The second delimiting module is used to determine the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to the cached parallel data and the adjudication window corresponding to the target clock cycle; the current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous receiving round.

[0041] The data extraction module is used to extract the cached parallel data according to the second delimiting indication information corresponding to the cached parallel data when the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, so as to obtain the aligned parallel data corresponding to the target clock cycle.

[0042] Thirdly, this application provides a computer-readable storage medium storing at least one instruction or at least one program, which is loaded and executed by a processor to implement the timing alignment method as described in the first aspect.

[0043] Fourthly, this application provides a computer device including a processor and a memory, wherein the memory stores at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by the processor to implement the timing alignment method as described in the first aspect.

[0044] Fifthly, this application provides a computer program product comprising computer instructions that, when executed by a processor, implement the timing alignment method as described in the first aspect.

[0045] The timing alignment method, apparatus, medium, and device provided in this application have the following technical advantages:

[0046] The scheme provided in this application determines the cached parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round, so as to perform a delimitation search on the target clock cycle, wherein the target clock cycle is any clock cycle in the parallel data stream; the scheme provided in this application shifts and selects the cached parallel data corresponding to the target clock cycle based on a preset delimiter to obtain multiple data segments to be searched, which serve as the objects of the delimitation search; the scheme provided in this application searches each of the multiple data segments to be searched based on the preset delimiter to determine the first delimitation indication information corresponding to the cached parallel data, and then, based on the first delimitation indication information corresponding to the cached parallel data... The delimiting indication information and the adjudication window corresponding to the target clock cycle are used to determine the second delimiting indication information corresponding to the buffered parallel data. The current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous reception round. If the second delimiting indication information corresponding to the buffered parallel data indicates the existence of a target data segment in the buffered parallel data corresponding to the target clock cycle that is the same as or similar to a preset delimiter, the buffered parallel data can be extracted according to the second delimiting indication information to obtain the aligned parallel data corresponding to the target clock cycle for accurate deserialization. The scheme provided in this application can accurately perform clock cycle-by-clock timing alignment of the parallel data stream, and by splitting and retrieving the buffered parallel data, it ensures stable recovery and alignment of data timing even when disturbances occur.

[0047] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0048] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a schematic diagram of the implementation environment of a timing alignment method provided in an embodiment of this application;

[0050] Figure 2 This is a flowchart illustrating a timing alignment method provided in an embodiment of this application;

[0051] Figure 3 This is a schematic flowchart illustrating a method for determining first delimitation indication information provided in an embodiment of this application;

[0052] Figure 4This is a schematic diagram of the structure of a hardware implementation module provided in an embodiment of this application;

[0053] Figure 5 This is a schematic diagram of a timing alignment device provided in an embodiment of this application;

[0054] Figure 6 This is a schematic diagram of the hardware structure of a device for implementing a timing alignment method provided in an embodiment of this application. Detailed Implementation

[0055] To accurately align parallel data in a parallel data stream in terms of timing, embodiments of this application provide timing alignment methods, apparatus, media, and devices. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0056] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0057] Please see Figure 1 This is a schematic diagram illustrating the implementation environment of a timing alignment method provided in an embodiment of this application, as shown below. Figure 1As shown, this implementation environment can include at least an Optical Network Unit (ONU), an optical fiber link, an Optical Line Terminal (OLT), and a serializer / deserializer (Serdes). The ONU acts as the transmitter, and the OLT as the receiver. It receives the serialized parallel data stream transmitted through the optical fiber link and deserializes the parallel data stream using the serializer / deserializer. To test the functionality and performance of the OLT, such as its error rate capability, it is necessary to restore the normal timing sequence after receiving the parallel data stream serialized according to a certain encoding order. Only with timing alignment can effective and accurate testing be performed. However, under conditions of varying optical power or very low optical power, or due to the impact of serial RF signal transmission delays, the serialized parallel data stream output by the OLT or received by the serializer / deserializer may experience bit offsets. The delimiters used for data stream alignment may have bit errors. When the serializer / deserializer receives the data stream and converts it into parallel data, the position of the delimiters may be incorrectly identified or difficult to identify, resulting in a change in the position of the deserialized data structure within the parallel data compared to before transmission.

[0058] In a timing alignment method provided in this application, buffered parallel data corresponding to a target clock cycle is determined from the parallel data stream received from the optical line terminal corresponding to the current reception round, so as to perform a delimitation search on the target clock cycle. The target clock cycle is any clock cycle in the parallel data stream. The timing alignment method provided in this application, based on a preset delimiter, shifts and selects the buffered parallel data corresponding to the target clock cycle to obtain multiple data segments to be searched, which serve as the data objects for delimitation search. The timing alignment method provided in this application, based on a preset delimiter, searches each of the multiple data segments to be searched to determine the first delimitation indication information corresponding to the buffered parallel data, and then proceeds... Based on the first delimiting indication information corresponding to the cached parallel data and the adjudication window corresponding to the target clock cycle, the second delimiting indication information corresponding to the cached parallel data is determined. The current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous reception round. If the second delimiting indication information indicates the presence of a target data segment in the cached parallel data corresponding to the target clock cycle that is identical or similar to a preset delimiter, the cached parallel data can be extracted according to the second delimiting indication information to obtain the aligned parallel data corresponding to the target clock cycle for accurate deserialization. The timing alignment method provided in this application can accurately perform clock-cycle-by-clock-cycle timing alignment of parallel data streams and stably ensure data timing recovery and alignment even during disturbances.

[0059] Please see Figure 2This is a flowchart illustrating a timing alignment method provided in an embodiment of this application. This application provides the operational steps of the method described in the embodiment or flowchart, but based on conventional or non-inventive methods, more or fewer operational steps may be included. The order of steps listed in the embodiment is merely one possible execution order among many and does not represent the only possible execution order. In actual system or server product execution, the method can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment) as shown in the embodiment or accompanying drawings. Figure 2 As shown, a timing alignment method provided in this application embodiment may include the following steps:

[0060] S210: Determine the buffered parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round.

[0061] In this embodiment, the parallel data stream is a serialized signal. Under conditions such as changes in optical power, very low optical power, or the influence of uncertain transmission delay of serial radio frequency signals, bit offsets or bit jumps may occur in the parallel data stream, which may easily cause the position of the deserialized data structure in the parallel data to change compared to before transmission.

[0062] In the embodiments of this application, the target clock period is any clock period in the parallel data stream.

[0063] In one embodiment of this application, the aforementioned parallel data stream may employ a fixed-length encoding method.

[0064] In one embodiment of this application, step S210 can be implemented as follows:

[0065] S211: Based on the selection window corresponding to the current receiving round and the parallel data stream corresponding to the current receiving round, determine the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle relative to the target clock cycle.

[0066] For example, if the selection window corresponding to the current receiving round indicates that the duration is two clock cycles, the aforementioned adjacent clock cycle can be the next clock cycle after the target clock cycle.

[0067] For example, when the selection window corresponding to the current receiving round indicates that the duration is three clock cycles, the aforementioned adjacent clock cycles can be the previous clock cycle and the next clock cycle of the target clock cycle, or the aforementioned adjacent clock cycles can be the next clock cycle and the next two clock cycles of the target clock cycle.

[0068] S212: Merge the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle to obtain the cached parallel data corresponding to the target clock cycle.

[0069] The parallel data corresponding to multiple clock cycles are concatenated to obtain the cached parallel data corresponding to the target clock cycle, which serves as the data range for delimiting the search of the target clock cycle.

[0070] When the adjacent clock cycle is the clock cycle following the target clock cycle, the above step S212 can be implemented as follows:

[0071] Use the parallel data corresponding to the target clock cycle as the high-order data in the cached parallel data;

[0072] The parallel data corresponding to the next clock cycle is used as the low-order data in the cached parallel data.

[0073] For example, the parallel data corresponding to the i-th clock cycle can be denoted as... The parallel data corresponding to the next clock cycle can be denoted as That is, the parallel data corresponding to each clock cycle is M bits wide. The parallel data corresponding to the i-th clock cycle and the parallel data corresponding to the (i+1)-th clock cycle are merged into a 2*M-bit wide data set, which is used as the cached parallel data corresponding to the i-th clock cycle, and can be denoted as... ,in:

[0074] It can be used as high-order data, that is In ;

[0075] It can be used as low-order data, that is In .

[0076] It is understandable that, due to the transmission delay, the W-bit delimiter has a certain probability of being separated into parallel data corresponding to two clock cycles (the parallel data corresponding to each clock cycle is M bits wide). Therefore, the M-bit parallel data corresponding to two consecutive clock cycles can be merged into 2*M-bit wide data as cached parallel data so that the delimiter in the parallel data corresponding to each clock cycle can be accurately retrieved.

[0077] In the above embodiments, by flexibly setting the selection window in different receiving rounds, the data retrieval range for the target clock cycle during timing alignment can be dynamically adjusted, and problems such as bit offset or bit transition can be dealt with, thereby improving the accuracy of timing alignment.

[0078] S220: Based on a preset delimiter, the cached parallel data corresponding to the target clock cycle is shifted and selected to obtain multiple data segments to be retrieved.

[0079] In this embodiment, based on the bit width of a preset delimiter, the cached parallel data corresponding to the target clock cycle is shifted and selected to obtain multiple data segments to be retrieved, which serve as the minimum data object for delimitation retrieval. The bit width of each data segment to be retrieved can be the same as the bit width of the preset delimiter.

[0080] Among them, the default delimiter is a symbol used to delimit characters, and its main function is to identify the start or end position of data.

[0081] In one embodiment of this application, step S220 can be implemented as follows:

[0082] S221: Using the first bit in the cached parallel data as the starting selection position, extract a continuous data segment of a preset length from the cached parallel data, and move the starting selection position bit by bit to extract multiple segments to be retrieved; the preset length is the same as the length of the preset delimiter.

[0083] For example, the cached parallel data corresponding to the target clock cycle can be denoted as data_in_buffer<2*M-1:0>, and the parallel data corresponding to the target clock cycle is located in the high-order bits of the cached parallel data. The preset delimiter can be denoted as Delimiter. <w-1:0>That is, the default delimiter width is W; the highest bit of the cached parallel data is used as the starting selection position for the first extraction, extracting a data segment of width W, and then performing a shift selection by shifting the starting selection position by 1 bit each time (that is, moving it by one bit width), forming M data segments of width W to be searched, which can be denoted as search_data. <j> <w-1:0>, where 0≤j<M, and j is an integer.

[0084] For example, the data corresponding to the M W-bit wide data segments to be retrieved can be represented as:

[0085] search_data <0> <w-1:0><= data_in_buffer<2*M-1: 2*M-W>;

[0086] search_data<1> <w-1:0><= data_in_buffer<2*M-2: 2*M-W-1>;

[0087] search_data<2> <w-1:0><= data_in_buffer<2*M-3: 2*M-W-2>;

[0088] ……

[0089] search_data <j> <w-1:0><= data_in_buffer<2*M-j-1: 2*M-W-j>;

[0090] ……

[0091] search_data <m-1> <w-1:0><= data_in_buffer<M: M-W+1>;

[0092] with search_data <j> <w-1:0>For example, search_data <j> <w-1:0>The expression `<= data_in_buffer<2*Mj-1: 2*MWj>` means that the data from positions 2*Mj-1 to 2*MWj in `data_in_buffer<2*Mj-1: 2*MWj>` can be assigned to `search_data`. <j> <w-1:0>.

[0093] S230: Based on a preset delimiter, search each of the multiple data segments to be searched to determine the first delimiting indication information corresponding to the cached parallel data.

[0094] The first delimiting indication information corresponding to the cached parallel data may include indication identification information and delimiting position information. The indication identification information indicates whether there is a data segment to be retrieved whose degree of difference with the preset delimiter meets the first preset difference condition. The delimiting position information indicates the position of the data segment to be retrieved in the cached parallel data corresponding to the target clock cycle whose degree of difference with the preset delimiter meets the first preset difference condition.

[0095] The degree of difference can be represented by the number of bits that differ, and the first preset difference condition can be a preset fault tolerance threshold to indicate the acceptable number of bits that differ.

[0096] In one specific implementation, such as Figure 3 As shown, step S230 can be implemented as follows:

[0097] S231: Perform a bitwise XOR operation between each data segment to be retrieved and a preset delimiter to obtain the calculation result corresponding to each data segment to be retrieved.

[0098] Since the bit width of each data segment to be retrieved is the same as the bit width of the preset delimiter, a bitwise XOR operation can be performed on each data segment to be retrieved and the preset delimiter. If the bits at the same position are the same, the XOR result at that position can be 0. If the bits at the same position are different, the XOR result at that position can be 1. That is, for each data segment to be retrieved, after the bitwise XOR operation, a calculation result with the same bit width can be obtained. The value of each bit in the calculation result indicates whether the bits at the corresponding position of the data segment to be retrieved and the preset delimiter are the same.

[0099] S232: Based on the calculation results corresponding to each data segment to be retrieved, determine the difference information between each data segment to be retrieved and the preset delimiter.

[0100] Based on the foregoing, we can use 1 to indicate that the bit at the same position of the data segment to be retrieved is different from that of the preset delimiter. Then we can count the number of "1"s in the calculation result corresponding to each data segment to be retrieved to obtain difference information indicating the degree of difference between each data segment to be retrieved and the preset delimiter. The difference information is the number of "1"s in the corresponding calculation result. The more "1"s there are, the greater the degree of difference.

[0101] For example, for M W-bit wide data segments to be retrieved, each data segment search_data <j> <w-1:0>The bits in the array are all delimited by the preset delimiter of the W-bit width. <w-1:0>Perform a bitwise XOR operation, and the result is a W-bit wide data value, which is then assigned to Bits_xor. <j> <w-1:0>, where 0≤j<M.

[0102] For example, Bits_xor <0> <= search_data <0> ^ Delimiter;

[0103] Bits_xor <1> <= search_data <1> ^ Delimiter;

[0104] ...

[0105] Bits_xor <m-1><= search_data <m-1>^ Delimiter;

[0106] Then regarding Bits_xor <j> <w-1:0>The number of 1s in search_data is counted. <j>The number of bits that differ from the Delimiter at the same position can be denoted as: compare_num <j>,compare_num <j>It can form an array compare_num <m-1:0>The array compare_num <m-1:0>This provides difference information to indicate the degree of difference between each data segment to be retrieved and the preset delimiter.

[0107] S233: Based on the preset fault tolerance threshold and difference information, determine the first delimitation indication information corresponding to the cached parallel data.

[0108] The first delimiting indication information corresponding to the cached parallel data indicates whether there is a data segment to be retrieved that has a difference bit length between itself and the preset delimiter that is less than a preset fault tolerance threshold, and indicates the position of the data segment to be retrieved that has a difference bit length between itself and the preset delimiter that is less than the preset fault tolerance threshold in the cached parallel data corresponding to the target clock cycle.

[0109] The preset fault tolerance threshold can be a pre-set upper limit for tolerating delimiter disturbances. For example, it can be set to two bits. That is, if the difference information between the data segment to be retrieved and the preset delimiter indicates that the number of bits between the data segment to be retrieved and the preset delimiter is no more than two, then the data segment to be retrieved can be considered to be the same as or similar to the preset delimiter. The preset fault tolerance threshold reflects the upper limit for tolerating transmission disturbances in the method provided in this application embodiment, and also reflects the fault tolerance capability for delimitation retrieval and timing alignment.

[0110] For example, the preset fault tolerance threshold fau_tol_thod = 2, and the array compare_num <m-1:0>Each data point in the array is compared to a preset fault tolerance threshold, fau_tol_thod. If the array compare_num... <m-1:0>The data in the k-th position (0 ≤ k < M) is compared_num <k>If the value is less than or equal to the preset fault tolerance threshold fau_tol_thod, then set the indicator flag information Match_flag = 1 and define the delimited position information Match_ID = k; otherwise, Match_flag = 0 and Match_ID remains unchanged.

[0111] S240: Based on the first delimiting indication information corresponding to the cached parallel data and the decision window corresponding to the target clock cycle, determine the second delimiting indication information corresponding to the cached parallel data.

[0112] The second delimiting indication information corresponding to the cached parallel data indicates whether there is a target data segment in the cached parallel data that is the same as or similar to the preset delimiter, and indicates the position of the target data segment in the cached parallel data if there is a target data segment in the cached parallel data that is the same as or similar to the preset delimiter.

[0113] In this embodiment, by verifying the first delimiting indication information corresponding to the cached parallel data, the second delimiting information corresponding to the cached parallel data corresponding to the target clock cycle is determined. The aforementioned target data segment can be a data segment among multiple data segments to be retrieved that is the same as or similar to a preset delimiter.

[0114] In one specific implementation, step S240 may include:

[0115] S241: Within the current duration of the adjudication window corresponding to the target clock cycle, if the first delimiting indication information corresponding to the cached parallel data indicates the existence of a target data segment, and the difference in bit length between the target data segment and the preset delimiter is less than a preset fault tolerance threshold, then based on the position of the target data segment in the cached parallel data, the second delimiting indication information corresponding to the cached parallel data is determined; the second delimiting indication information corresponding to the cached parallel data indicates the existence of a target data segment in the cached parallel data that is the same as or similar to the preset delimiter, and indicates the position of the target data segment in the cached parallel data.

[0116] Specifically, we can first determine whether there exists a target data segment in the cached parallel data corresponding to the target clock cycle that has a difference bit length between the target data segment and the preset delimiter that is less than a preset fault tolerance threshold, based on whether the Match_flag information in the first delimiting indication information corresponding to the cached parallel data is 1. If Match_flag is 1, we can determine the second delimiting indication information corresponding to the cached parallel data based on the delimiting position information Match_ID in the first delimiting indication information corresponding to the cached parallel data, which can be denoted as Select_ID. The second delimiting indication information can also indicate the starting position of the preset delimiter in the cached parallel data corresponding to the target clock cycle.

[0117] In one specific implementation, step S240 may further include:

[0118] S242: Within the current duration of the adjudication window corresponding to the target clock cycle, if the first delimiting indication information corresponding to the buffered parallel data indicates that the difference bit length between each data segment to be retrieved and the preset delimiter is not less than the preset fault tolerance threshold, then the timing alignment of the target clock cycle is skipped, that is, it can be maintained as the second delimiting indication information corresponding to the target clock cycle in the previous receiving round.

[0119] Alternatively, the range of cached parallel data can be expanded to redetermine the cached parallel data corresponding to the target clock cycle, and the above delimitation retrieval process can be re-executed.

[0120] In one specific implementation, step S240 may further include:

[0121] S243: Within the current duration of the adjudication window corresponding to the target clock cycle, if the first delimiting indication information corresponding to the cached parallel data indicates the existence of multiple target data segments, then the second delimiting indication information corresponding to the cached parallel data is determined based on the position of the target data segment with the smallest difference bit length from the preset delimiter in the cached parallel data.

[0122] In practice, there is usually at most one target data segment. However, if the first delimiting indication information corresponding to the cached parallel data indicates that there are multiple target data segments, in addition to selecting the target data segment with the smallest difference from the preset delimiter, the cached parallel data corresponding to the target clock cycle can be re-determined, and the above delimiting retrieval process can be re-executed.

[0123] For example, in the current receiving round, when the flag Window_D = 1 in the decision window corresponding to the target clock cycle, it is determined whether the indication flag information Match_flag is 1. If Match_flag = 1 (that is, indicating that there is a data segment to be retrieved whose difference from the preset delimiter meets the first preset difference condition), then the delimiting position information Match_ID is used as the second delimiting indication information Select_ID corresponding to the cached parallel data corresponding to the newly determined target clock cycle; if Match_flag = 0, that is, indicating that no delimiter was retrieved, the second delimiting indication information Select_ID corresponding to the cached parallel data can be kept the same as in the previous receiving round and not updated.

[0124] In another embodiment of this application, the above method may further include:

[0125] In the first receiving round, if the first delimiting indication information corresponding to the cached parallel data indicates the existence of a target data segment, and the difference in the number of bits between the target data segment and the preset delimiter is less than a preset fault tolerance threshold, then based on the position of the target data segment in the cached parallel data, the second delimiting indication information corresponding to the cached parallel data is determined; the second delimiting indication information corresponding to the cached parallel data indicates the existence of a target data segment in the cached parallel data that is the same as or similar to the preset delimiter, and indicates the position of the target data segment in the cached parallel data.

[0126] That is, in the first receiving round, since the adjudication window has not yet been started, the second delimitation indication information corresponding to the cached parallel data can be determined directly based on the first delimitation indication information corresponding to the cached parallel data without the adjudication window.

[0127] S250: When the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, the cached parallel data is extracted according to the second delimiting indication information corresponding to the cached parallel data to obtain the aligned parallel data corresponding to the target clock cycle.

[0128] In this embodiment of the application, the cached parallel data is extracted into continuous data segments according to the second delimiting indication information corresponding to the cached parallel data. The bit width of the aligned parallel data corresponding to the target clock cycle is the same as the bit width of the parallel data corresponding to the target clock cycle. The aligned parallel data corresponding to the target clock cycle is a data segment with a bit width starting from the target data segment (or it can be considered as starting from the preset delimiter).

[0129] In one embodiment of this application, if the second delimiting indication information Select_ID corresponding to the cached parallel data is k (0≤k<M), it indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, and the target data segment is the k-th data segment to be searched, search_data. <k> <w-1:0>Therefore, the position of the preset delimiter in the buffered parallel data corresponding to the target clock cycle can be assumed to be data_in_buffer<2*Mk-1:2*MWk>. Then, starting from the 2*Mk-1th bit of the buffered parallel data data_in_buffer<2*M-1:0> corresponding to the target clock cycle, M bits of data can be extracted to obtain the M-bit aligned parallel data data_out corresponding to the target clock cycle. <m-1:0>When the target clock cycle is the i-th clock cycle, the aligned parallel data corresponding to the i-th clock cycle can be represented as: , that is yes The data segment from bit 2*Mk-1 to bit Mk.

[0130] In one embodiment of this application, the above method may further include:

[0131] S310: When the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the boundary position of the parallel data corresponding to the target clock cycle, determine the first duration of the decision window.

[0132] The boundary position refers to the highest T bits or the lowest T bits of the above parallel data. T can be 1 or 2, etc., and there is no restriction here.

[0133] For example, if the parallel data bit width corresponding to the target clock cycle is M, and the second delimiting indication information Select_ID = M-1 or Select_ID = 0 corresponding to the buffered parallel data, then the determined target data segment can be considered to be located at the boundary position of the parallel data corresponding to the current clock. In subsequent receiving rounds, due to external environmental disturbances or errors in the data stream, the parallel data corresponding to a certain clock cycle may experience a bit offset or error, which may affect the retrieval result of the preset delimiter in the buffered parallel data corresponding to that clock cycle. For example, the preset delimiter may not be retrieved, or the aligned parallel data of the specified bit width may not be extracted.

[0134] For example, when the second delimiting indication information Select_ID = 0 corresponding to the cached parallel data, it means that the target data segment is in the high bit of the parallel data corresponding to the target clock cycle. In subsequent reception rounds, the problem of left offset may easily occur. Therefore, the first duration of the decision window can be set to three clock cycles.

[0135] For example, when the second delimiting indication information Select_ID = M-1 corresponding to the cached parallel data, it indicates that the target data segment is in the low bit of the parallel data corresponding to the target clock cycle. In subsequent reception rounds, the problem of right offset is likely to occur. Therefore, the first duration of the decision window can be set to three clock cycles.

[0136] S320: When the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the non-boundary position of the parallel data corresponding to the target clock cycle, determine the second duration of the decision window.

[0137] Non-boundary locations refer to the portion of the parallel data other than the boundary locations mentioned above.

[0138] For example, if the parallel data bit width corresponding to the target clock cycle is M, and the second delimiting indication information corresponding to the buffered parallel data is 0 < Select_ID < M-1, even if a bit offset or error occurs, the preset delimiter will still appear in the buffered parallel data corresponding to the target clock cycle in subsequent receiving rounds. And according to the determined position of the target data segment, M-bit width aligned parallel data can be extracted. Therefore, the second duration of the adjudication window corresponding to the target clock cycle in subsequent receiving rounds can be set to one clock cycle.

[0139] The aforementioned first or second duration is the next duration of the decision window corresponding to the target clock cycle in the next reception round. In subsequent reception rounds, by dynamically adjusting the duration of the decision window corresponding to the target clock cycle in the subsequent reception rounds, sufficient opportunity is provided to determine or update the second delimitation indication information based on the cached parallel data corresponding to the target clock cycle in the subsequent reception rounds, thereby ensuring the effectiveness and accuracy of delimitation retrieval.

[0140] In one embodiment of this application, taking the current reception round as an example, the control of the current duration of the adjudication window corresponding to the target clock cycle can be achieved through the following steps:

[0141] S410: After determining the second delimitation indication information corresponding to the target clock cycle in the previous reception round, start the target counter corresponding to the target clock cycle.

[0142] The initial value of the target counter is the same as the length of the clock cycle of the parallel data stream; the value of the target counter is decremented by 1 every clock cycle.

[0143] S420: When the value of the target counter decreases to a preset threshold corresponding to the current duration, the adjudication window corresponding to the target clock cycle is opened until the target counter finishes counting and the adjudication window corresponding to the target clock cycle is closed, so as to determine the second delimitation indication information corresponding to the buffered parallel data in the current receiving round within the current duration of the adjudication window corresponding to the target clock cycle.

[0144] For example, when the current duration is one clock cycle, the preset threshold is 0; when the current duration is three clock cycles, the preset threshold is 2. Feasibly, after determining the second delimitation indication information corresponding to the target clock cycle in the previous reception round, a pulse signal (Loadtimer_flag) can be triggered. When Loadtimer_flag=1, the target counter corresponding to the target clock cycle is started. The target counter can be a decrementing counter. The initial value of the target counter is the same as the length of the clock cycle of the parallel data stream. When the pulse signal arrives, the target counter starts decrementing, and the value of the target counter automatically decreases by 1 every clock cycle. If the second delimiting indication information Select_ID corresponding to the target clock cycle in the previous reception round indicates that the preset delimiter is not at the boundary position, then when the value of the target counter decreases to 0, a decision window of one clock cycle will be generated. If the second delimiting indication information Select_ID corresponding to the target clock cycle in the previous reception round indicates that the preset delimiter is at the boundary position, then when the value of the target counter is 2, 1, or 0, a decision window of one clock cycle will be generated respectively, thus forming a decision window with a current duration of three clock cycles. Furthermore, in the current reception round, after determining the second delimiting indication information corresponding to the buffered parallel data, a target counter corresponding to the target clock cycle will also be generated to control the duration of the decision window corresponding to the target clock cycle in the next reception round as the next duration.

[0145] In one embodiment of this application, in order to identify and remove pseudo-random codes in the parallel data stream to achieve time alignment of valid data, a timer or clock cycle counter can be set. When the parallel data stream is received, a pulse signal is generated synchronously. The pulse signal is used to trigger the timer and set an initial value of timer_count = L, which corresponds to the length of the pseudo-random code (L M bits wide, occupying L clock cycles). After each clock cycle, timer_count is decremented by 1. When timer_count is 0, delimitation search and data alignment processing are performed clock cycle by clock cycle.

[0146] Figure 4 This is a schematic diagram of the structure of a hardware implementation module provided in an embodiment of this application, such as... Figure 4 As shown, the parallel data buffer pool is used for parallel data data_in of M bits width for each clock cycle based on the selection window corresponding to the current reception round. <m-1:0>The system performs caching and merging; for example, it merges the parallel data corresponding to the target clock cycle and the next clock cycle to obtain the cached parallel data data_in_buffer<2*M-1:0> corresponding to the target clock cycle. The feature location retrieval module is used to retrieve the delimiter D in the cached parallel data. First, it splits the cached parallel data to obtain M data segments to be retrieved, Search_data. <j>Compare M data segments to be retrieved with delimiter D, and output M comparison_num values ​​indicating the differences between the data segments to be retrieved and delimiter D. <j>If the k-th difference information compare_num <k>If the value is less than or equal to the preset fault tolerance threshold fau_tol_thod, then the indicator flag information Match_flag = 1, and the delimited position information Match_ID = k. Match_flag and Match_ID constitute the first delimited indication information corresponding to the buffered parallel data. The alignment adjudication module is used to determine the second delimited indication information Select_ID corresponding to the buffered parallel data within the current duration of the adjudication window corresponding to the target clock cycle based on the output Match_flag and Match_ID, and to re-determine the next duration of the adjudication window Window_D corresponding to the next reception round by triggering a pulse signal (Loadtimer_flag). The sorting module is used to extract data from the buffered parallel data according to the second delimited indication information Select_ID corresponding to the buffered parallel data to obtain the aligned parallel data Data_out corresponding to the target clock cycle. <m-1:0>The above process can be referred to the foregoing embodiments, and will not be repeated here.

[0147] As can be seen from the above embodiments, the timing alignment method provided in this application determines the buffered parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round, so as to perform a delimitation search on the target clock cycle, wherein the target clock cycle is any clock cycle in the parallel data stream; the scheme provided in this application shifts and selects the buffered parallel data corresponding to the target clock cycle based on a preset delimiter to obtain multiple data segments to be searched, which are used as objects for delimitation search; the scheme provided in this application searches each of the multiple data segments to be searched based on the preset delimiter to determine the first delimitation indication information corresponding to the buffered parallel data, and then... Based on the first delimiting indication information corresponding to the cached parallel data and the adjudication window corresponding to the target clock cycle, a second delimiting indication information corresponding to the cached parallel data is determined. The current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous reception round. If the second delimiting indication information indicates the presence of a target data segment in the cached parallel data corresponding to the target clock cycle that is identical or similar to a preset delimiter, the cached parallel data can be extracted according to the second delimiting indication information to obtain aligned parallel data corresponding to the target clock cycle for accurate deserialization. The scheme provided in this application can accurately perform clock-cycle-by-clock-cycle timing alignment of parallel data streams, and by splitting and retrieving the cached parallel data, it ensures stable recovery and alignment of data timing even during disturbances.

[0148] This application also provides a timing alignment device 500, such as... Figure 5 As shown, the device may include:

[0149] The data acquisition module 510 is used to determine the cached parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round; the target clock cycle is any clock cycle in the parallel data stream.

[0150] The shift selection module 520 is used to shift and select the cached parallel data corresponding to the target clock cycle based on a preset delimiter to obtain multiple data segments to be retrieved;

[0151] The first delimiting module 530 is used to search each of the plurality of data segments to be searched based on the preset delimiter, and determine the first delimiting indication information corresponding to the cached parallel data.

[0152] The second delimiting module 540 is used to determine the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to the cached parallel data and the adjudication window corresponding to the target clock cycle; the current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous receiving round.

[0153] The data extraction module 550 is used to extract the cached parallel data according to the second delimiting indication information corresponding to the cached parallel data when the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, so as to obtain the aligned parallel data corresponding to the target clock cycle.

[0154] In one embodiment of this application, the data acquisition module 510 includes:

[0155] A data caching unit is used to determine the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle relative to the target clock cycle based on the selection window corresponding to the current receiving round and the parallel data stream corresponding to the current receiving round.

[0156] The data merging unit is used to merge the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle to obtain the cached parallel data corresponding to the target clock cycle.

[0157] In one embodiment of this application, the shift selection module 520 includes:

[0158] The shift extraction unit is used to take the first bit in the cached parallel data as the starting selection position, extract a continuous data segment of a preset length from the cached parallel data, and move the starting selection position bit by bit to extract multiple times to obtain the multiple data segments to be retrieved.

[0159] The preset length is the same as the length of the preset delimiter.

[0160] In one embodiment of this application, the first delimiting module 530 includes:

[0161] The bitwise XOR unit is used to perform a bitwise XOR calculation on each data segment to be retrieved and the preset delimiter to obtain the calculation result corresponding to each data segment to be retrieved.

[0162] The difference determination unit is used to determine the difference information between each data segment to be retrieved and the preset delimiter based on the calculation result corresponding to each data segment to be retrieved;

[0163] The first delimiting unit is used to determine the first delimiting indication information corresponding to the cached parallel data based on a preset fault tolerance threshold and the difference information; the first delimiting indication information corresponding to the cached parallel data indicates whether there is a data segment to be retrieved that has a difference bit length between itself and the preset delimiter that is less than the preset fault tolerance threshold, and indicates the position of the data segment to be retrieved that has a difference bit length between itself and the preset delimiter that is less than the preset fault tolerance threshold in the cached parallel data.

[0164] In one embodiment of this application, the second delimiting module 540 includes:

[0165] The second delimiting unit is configured to, within the current duration of the adjudication window corresponding to the target clock cycle, if the first delimiting indication information corresponding to the cached parallel data indicates the existence of the target data segment, and the difference in bit length between the target data segment and the preset delimiter is less than the preset fault tolerance threshold, determine the second delimiting indication information corresponding to the cached parallel data based on the position of the target data segment in the cached parallel data; the second delimiting indication information corresponding to the cached parallel data indicates the existence of the target data segment that is the same as or similar to the preset delimiter in the cached parallel data, and indicates the position of the target data segment in the cached parallel data.

[0166] In one embodiment of this application, the second delimiting module 540 includes:

[0167] The third delimiting unit is used to skip timing alignment of the target clock cycle if, within the current duration of the adjudication window corresponding to the target clock cycle, the first delimiting indication information corresponding to the cached parallel data indicates that the difference in the number of bits between each data segment to be retrieved and the preset delimiter is not less than the preset fault tolerance threshold.

[0168] In one embodiment of this application, the device 500 further includes:

[0169] The fourth delimiting unit is used, in the first receiving round, if the first delimiting indication information corresponding to the cached parallel data indicates the existence of the target data segment, and the difference in the number of bits between the target data segment and the preset delimiter is less than the preset fault tolerance threshold, then based on the position of the target data segment in the cached parallel data, it determines the second delimiting indication information corresponding to the cached parallel data; the second delimiting indication information corresponding to the cached parallel data indicates the existence of the target data segment in the cached parallel data that is the same as or similar to the preset delimiter, and indicates the position of the target data segment in the cached parallel data.

[0170] In one embodiment of this application, the second delimiting module 540 includes:

[0171] The fifth delimiting unit is used to determine the second delimiting indication information corresponding to the cached parallel data based on the position of the target data segment with the smallest difference bit length from the preset delimiter in the cached parallel data, if the first delimiting indication information corresponding to the cached parallel data indicates the existence of multiple target data segments, within the current duration of the adjudication window corresponding to the target clock cycle.

[0172] In one embodiment of this application, the device 500 further includes:

[0173] The first window unit is used to determine the first duration of the decision window when the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the boundary position of the parallel data corresponding to the target clock cycle.

[0174] The second window unit is used to determine the second duration of the decision window when the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the non-boundary position of the parallel data corresponding to the target clock cycle;

[0175] The first duration or the second duration is the next duration of the decision window corresponding to the target clock cycle in the next reception round.

[0176] In one embodiment of this application, the device 500 further includes:

[0177] The timing start unit is used to start a target counter corresponding to the target clock cycle after determining the second delimitation indication information corresponding to the target clock cycle in the previous receiving round; the initial value of the target counter is the same as the length of the clock cycle of the parallel data stream; the value of the target counter is decremented by 1 after each clock cycle.

[0178] The window persistence unit is used to open the adjudication window corresponding to the target clock cycle when the value of the target counter decreases to a preset threshold corresponding to the current persistence duration, and close the adjudication window corresponding to the target clock cycle after the target counter finishes counting, so as to determine the second delimitation indication information corresponding to the cached parallel data in the current receiving round within the current persistence duration of the adjudication window corresponding to the target clock cycle.

[0179] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0180] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0181] This application provides a computer device including a processor and a memory. The memory stores at least one instruction or at least one program, which is loaded and executed by the processor to implement a timing alignment method as provided in the above method embodiments.

[0182] Figure 6 A schematic diagram of the hardware structure of a device for implementing a timing alignment method provided in an embodiment of this application is shown. This device may participate in or include the apparatus or system provided in the embodiment of this application. Figure 6 As shown, device 10 may include one or more processors ( Figure 6 The image uses processors 1002a, 1002b, ..., 1002n to illustrate the process. These processors may include, but are not limited to, processing devices such as microprocessors (MCUs) or programmable logic devices (FPGAs), a memory 1004 for storing data, and a transmission device 1006 for communication functions. In addition, it may include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports in the I / O interface), a network interface, a power supply, and / or a camera. Those skilled in the art will understand that... Figure 6 The structure shown is for illustrative purposes only and does not limit the structure of the electronic device described above. For example, device 10 may also include a... Figure 6 The more or fewer components shown, or having the same Figure 6 The different configurations shown.

[0183] It should be noted that the aforementioned one or more processors and / or other data processing circuits are generally referred to herein as "data processing circuits". These data processing circuits may be wholly or partially embodied in software, hardware, firmware, or any other combination thereof. Furthermore, the data processing circuits may be a single, independent processing module, or wholly or partially integrated into any other element within device 10 (or the mobile device). As involved in the embodiments of this application, the data processing circuits serve as a processor control mechanism (e.g., selection of a variable resistor termination path connected to an interface).

[0184] The memory 1004 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the method described in the embodiments of this application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory 1004, thereby implementing the timing alignment method described above. The memory 1004 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 1004 may further include memory remotely located relative to the processor, and these remote memories can be connected to the device 10 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0185] The transmission device 1006 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the communication provider of device 10. In one example, the transmission device 1006 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 1006 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0186] The display may be, for example, a touchscreen liquid crystal display (LCD) that allows the user to interact with the user interface of device 10 (or mobile device).

[0187] This application embodiment also provides a computer-readable storage medium, which can be disposed in a server to store at least one instruction or at least one program related to implementing a timing alignment method in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the timing alignment method provided in the above method embodiment.

[0188] Optionally, in this embodiment, the storage medium may be located at at least one of the multiple network servers in a computer network. Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0189] This invention also provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a timing alignment method provided in the various optional embodiments described above.

[0190] As can be seen from the embodiments of the timing alignment method, apparatus, medium, and device provided in this application, the technical solution provided in this application determines the buffered parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round, so as to perform a delimitation search on the target clock cycle; the solution provided in this application shifts and selects the buffered parallel data corresponding to the target clock cycle based on a preset delimiter to obtain multiple data segments to be searched, which serve as the objects of the delimitation search; the solution provided in this application searches each of the multiple data segments to be searched based on the preset delimiter to determine the first delimitation indication information corresponding to the buffered parallel data, and then performs a delimitation search based on the buffered parallel data. The first delimiting indication information and the adjudication window corresponding to the target clock cycle are used to determine the second delimiting indication information corresponding to the buffered parallel data. The current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous reception round. If the second delimiting indication information corresponding to the buffered parallel data indicates the presence of a target data segment in the buffered parallel data corresponding to the target clock cycle that is the same as or similar to a preset delimiter, the buffered parallel data can be extracted according to the second delimiting indication information to obtain the aligned parallel data corresponding to the target clock cycle for accurate deserialization. The scheme provided in this application can accurately perform clock cycle-by-clock timing alignment of the parallel data stream, and by splitting and retrieving the buffered parallel data, it ensures stable recovery and alignment of data timing even when disturbances occur.

[0191] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired results. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are also possible or may be advantageous.

[0192] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device, equipment, and storage medium embodiments are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0193] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0194] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application. < / k> < / j> < / j> < / k> < / k> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / m-1> < / j> < / j>

Claims

1. A timing alignment method, characterized in that, The method includes: From the parallel data stream corresponding to the current receiving round, determine the buffered parallel data corresponding to the target clock cycle; the target clock cycle is any clock cycle in the parallel data stream. Based on a preset delimiter, the cached parallel data corresponding to the target clock cycle is shifted and selected to obtain multiple data segments to be retrieved. Based on the preset delimiter, each of the plurality of data segments to be retrieved is retrieved to determine the first delimiting indication information corresponding to the cached parallel data; Based on the first delimiting indication information corresponding to the cached parallel data and the adjudication window corresponding to the target clock cycle, the second delimiting indication information corresponding to the cached parallel data is determined; the current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous reception round. If the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, the cached parallel data is extracted according to the second delimiting indication information corresponding to the cached parallel data to obtain the aligned parallel data corresponding to the target clock cycle. The step of determining the cached parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round includes: Based on the selection window corresponding to the current receiving round and the parallel data stream corresponding to the current receiving round, determine the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle relative to the target clock cycle; The parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle are merged to obtain the cached parallel data corresponding to the target clock cycle.

2. The method according to claim 1, characterized in that, The method involves shifting and selecting the cached parallel data corresponding to the target clock cycle based on a preset delimiter to obtain multiple data segments to be retrieved, including: Using the first bit in the cached parallel data as the starting selection position, extract a continuous data segment of a preset length from the cached parallel data, and move the starting selection position bit by bit to extract multiple segments to obtain the multiple data segments to be retrieved. The preset length is the same as the length of the preset delimiter.

3. The method according to claim 1, characterized in that, The step of searching each of the plurality of data segments to be searched based on the preset delimiter to determine the first delimiting indication information corresponding to the cached parallel data includes: Perform a bitwise XOR operation between each data segment to be retrieved and the preset delimiter to obtain the calculation result corresponding to each data segment to be retrieved; Based on the calculation results corresponding to each data segment to be retrieved, the difference information between each data segment to be retrieved and the preset delimiter is determined; Based on the preset fault tolerance threshold and the difference information, the first delimiting indication information corresponding to the cached parallel data is determined; the first delimiting indication information corresponding to the cached parallel data indicates whether there is a data segment to be retrieved whose difference bit length between the preset delimiter and the preset delimiter is less than the preset fault tolerance threshold, and indicates the position of the data segment to be retrieved in the cached parallel data whose difference bit length between the preset delimiter and the preset fault tolerance threshold is less than the preset fault tolerance threshold.

4. The method according to claim 3, characterized in that, The step of determining the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to the cached parallel data and the decision window corresponding to the target clock cycle includes: Within the current duration of the adjudication window corresponding to the target clock cycle, if the first delimiting indication information corresponding to the cached parallel data indicates the existence of the target data segment, and the difference in bit length between the target data segment and the preset delimiter is less than the preset fault tolerance threshold, then based on the position of the target data segment in the cached parallel data, the second delimiting indication information corresponding to the cached parallel data is determined; the second delimiting indication information corresponding to the cached parallel data indicates the existence of the target data segment that is the same as or similar to the preset delimiter in the cached parallel data, and indicates the position of the target data segment in the cached parallel data.

5. The method according to claim 3, characterized in that, The step of determining the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to the cached parallel data and the decision window corresponding to the target clock cycle includes: If, within the current duration of the adjudication window corresponding to the target clock cycle, the first delimiting indication information corresponding to the cached parallel data indicates that the difference in bit length between each data segment to be retrieved and the preset delimiter is not less than the preset fault tolerance threshold, then the timing alignment for the target clock cycle is skipped.

6. The method according to claim 3, characterized in that, The method further includes: In the first receiving round, if the first delimiting indication information corresponding to the cached parallel data indicates the existence of the target data segment, and the difference in the number of bits between the target data segment and the preset delimiter is less than the preset fault tolerance threshold, then based on the position of the target data segment in the cached parallel data, the second delimiting indication information corresponding to the cached parallel data is determined; the second delimiting indication information corresponding to the cached parallel data indicates the existence of the target data segment that is the same as or similar to the preset delimiter in the cached parallel data, and indicates the position of the target data segment in the cached parallel data.

7. The method according to claim 3, characterized in that, The step of determining the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to the cached parallel data and the decision window corresponding to the target clock cycle includes: If, within the current duration of the adjudication window corresponding to the target clock cycle, the first delimiting indication information corresponding to the cached parallel data indicates the existence of multiple target data segments, then, based on the position of the target data segment with the smallest difference bit length between itself and the preset delimiter in the cached parallel data, the second delimiting indication information corresponding to the cached parallel data is determined.

8. The method according to claim 4 or 7, characterized in that, The method further includes: When the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at the boundary position of the parallel data corresponding to the target clock cycle, the first duration of the decision window is determined. When the second delimitation indication information corresponding to the cached parallel data indicates that the target data segment is located at a non-boundary position of the parallel data corresponding to the target clock cycle, the second duration of the decision window is determined. The first duration or the second duration is the next duration of the decision window corresponding to the target clock cycle in the next reception round.

9. The method according to claim 1, characterized in that, The method further includes: After determining the second delimiting indication information corresponding to the target clock cycle in the previous receiving round, a target counter corresponding to the target clock cycle is started; the initial value of the target counter is the same as the length of the clock cycle of the parallel data stream; the value of the target counter is decremented by 1 after each clock cycle. When the value of the target counter decreases to a preset threshold corresponding to the current duration, the adjudication window corresponding to the target clock cycle is opened until the target counter finishes counting and the adjudication window corresponding to the target clock cycle is closed, so as to determine the second delimitation indication information corresponding to the buffered parallel data in the current receiving round within the current duration of the adjudication window corresponding to the target clock cycle.

10. A timing alignment device, characterized in that, The device includes: The data acquisition module is used to determine the cached parallel data corresponding to the target clock cycle from the parallel data stream corresponding to the current receiving round; the target clock cycle is any clock cycle in the parallel data stream. The shift selection module is used to shift and select the cached parallel data corresponding to the target clock cycle based on a preset delimiter to obtain multiple data segments to be retrieved; The first delimiting module is used to search each of the plurality of data segments to be searched based on the preset delimiter, and determine the first delimiting indication information corresponding to the cached parallel data. The second delimiting module is used to determine the second delimiting indication information corresponding to the cached parallel data based on the first delimiting indication information corresponding to the cached parallel data and the adjudication window corresponding to the target clock cycle; the current duration of the adjudication window corresponding to the target clock cycle is determined based on the second delimiting indication information corresponding to the target clock cycle in the previous receiving round. The data extraction module is used to extract the cached parallel data according to the second delimiting indication information corresponding to the cached parallel data when the second delimiting indication information corresponding to the cached parallel data indicates that there is a target data segment in the cached parallel data corresponding to the target clock cycle that is the same as or similar to the preset delimiter, so as to obtain the aligned parallel data corresponding to the target clock cycle. The data acquisition module includes: A data caching unit is used to determine the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle relative to the target clock cycle based on the selection window corresponding to the current receiving round and the parallel data stream corresponding to the current receiving round. The data merging unit is used to merge the parallel data corresponding to the target clock cycle and the parallel data corresponding to the adjacent clock cycle to obtain the cached parallel data corresponding to the target clock cycle.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one instruction or at least one program segment, which is loaded and executed by a processor to implement a timing alignment method as described in any one of claims 1 to 9.

12. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by the processor to implement a timing alignment method as described in any one of claims 1 to 9.

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