Germanium-silicon heterojunction npn type bipolar transistor and preparation method thereof
By introducing negative charges at the critical interface of the germanium-silicon heterojunction npn bipolar transistor and optimizing the doping process, the problem of high base resistance was solved, and the RF performance of the device, especially fmax and noise performance, was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON TECH INNOVATION CENT(BEIJING) CORP
- Filing Date
- 2025-12-17
- Publication Date
- 2026-05-01
AI Technical Summary
Existing germanium-silicon heterojunction npn bipolar transistors have a contradiction in the doping and diffusion process of the connection base region, resulting in high parasitic base region resistance, which affects the RF performance of the device, especially the maximum oscillation frequency fmax and RF noise performance.
By introducing negative charges at interfaces such as the field region silicon oxide layer, the base region-collector region isolation silicon oxide layer, and the L-shaped silicon oxide inner wall, positive charges are reduced. Furthermore, the germanium silicon carbon epitaxial inner base region and the connecting base region are formed by the p-type in-situ doped germanium silicon carbon selective epitaxial growth method, thereby optimizing the doping and diffusion process of the connecting base region.
It effectively reduces the parasitic resistance of the base region and the parasitic capacitance between the base and collector regions, increases the maximum oscillation frequency fmax of the device, reduces the RF noise figure, and improves RF power gain and noise performance.
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Figure CN121968608A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device and integrated circuit process design and manufacturing, specifically to a germanium-silicon heterojunction npn bipolar transistor and its fabrication method. Background Technology
[0002] A key process step of a germanium-silicon heterojunction npn bipolar transistor is to simultaneously grow an intrinsic inner base region located below the region surrounded by the inner sidewall of silicon nitride and a connection base region located below the polysilicon layer cantilever and the inner sidewall of silicon nitride in the outer base region by using a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method.
[0003] The epitaxial base region, the core intrinsic region of the device obtained through selective epitaxial growth, roughly comprises a silicon buffer layer, a germanium-silicon-carbon layer, and a silicon capping layer in the order of growth. The buffer and capping layers are undoped. Even the germanium-silicon-carbon layer, when subdivided, includes several epitaxial layers, with only the innermost layer being boron-doped. This ensures that the final base region is sufficiently thin to minimize the carrier density over time, thus maximizing the device's cutoff frequency f. T .
[0004] However, since the connecting base region is grown simultaneously with the inner base region, the doping situation of the connecting base region during the growth process is roughly similar to that of the inner base region. That is, only the innermost layer is boron-doped, while the other layers are undoped. Although some boron impurities can diffuse from the heavily doped outer polysilicon layer during growth and subsequent thermal processes, in order to ensure the final ultra-thin inner base region, the diffusion of boron impurities during growth and subsequent thermal processes must be minimized. In other words, there are contradictory requirements for boron doping and diffusion in the inner base region and the connecting base region. Therefore, under the premise of ensuring the requirements of the intrinsic inner base region, the boron doping and diffusion of the connecting base region grown simultaneously cannot be fully optimized independently. This inevitably results in a considerable portion of the final connecting base region having relatively low doping concentration, that is, areas with high resistance. The high resistance of the connecting base region will inevitably lead to the inability to sufficiently reduce the parasitic base region resistance of the entire device.
[0005] As a representative of high-performance silicon-based radio frequency semiconductor devices, the germanium-silicon bipolar transistor, even with structural and process optimizations including the intrinsic region of the base region, achieves very high f-values. T However, if the base region parasitic resistance, one of the most important parasitic parameters, cannot be sufficiently reduced, the final device performance will be significantly compromised, not only in terms of its relationship with f. T Another performance metric that is equally or even more important is the highest oscillation frequency f. maxThe base region parasitic resistance is not small enough, so it cannot be fully improved, thus failing to ensure that the device obtains a sufficiently high RF power gain under high frequency operating conditions. Moreover, a high base region parasitic resistance will directly cause the deterioration of RF noise performance.
[0006] This section is intended to provide background or context for the embodiments of this application set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention
[0007] In order to solve at least one of the above-mentioned problems in the prior art, embodiments of this application provide a germanium-silicon heterojunction npn bipolar transistor and a method for fabricating the same.
[0008] This application provides a germanium-silicon heterojunction npn bipolar transistor, including:
[0009] p-type lightly doped silicon substrate;
[0010] An n-type heavily doped silicon buried collector region is formed on the substrate;
[0011] An n-type lightly doped silicon epitaxial collector region is formed on the buried layer collector region;
[0012] The SiC region is formed in the silicon epitaxial collector region by SiC ion implantation process;
[0013] A field region silicon oxide layer is formed on the buried layer current collector region and located on the side of the silicon epitaxial current collector region. The field region silicon oxide layer reduces positive charge through process means, and negative charge is introduced at the interface between the field region silicon oxide layer and the buried layer current collector region and the silicon epitaxial current collector region through process means.
[0014] p-type in-situ doped germanium silicon-carbon epitaxial base region is formed on the SiC region;
[0015] A connection base region is formed on the SiC region and the silicon epitaxial collector region;
[0016] A base-collector isolation silicon oxide layer is formed on the silicon epitaxial collector region and the field region silicon oxide layer. The base-collector isolation silicon oxide layer reduces positive charge through process means, and negative charge is introduced at the interface between the base-collector isolation silicon oxide layer and the silicon epitaxial collector region through process means.
[0017] L-shaped silicon oxide inner walls are formed on the germanium-silicon-carbon epitaxial inner base region and the connecting base region. The bottom of the L-shaped silicon oxide inner walls forms a window region. The positive charge of the L-shaped silicon oxide inner walls is reduced by process means, and the negative charge is introduced at the interface between the bottom of the L-shaped silicon oxide inner walls and the germanium-silicon-carbon epitaxial inner base region and the connecting base region by process means.
[0018] A single-crystal emitter region is formed on the inner base region of the germanium-silicon-carbon epitaxial layer and located below the window region;
[0019] p-type heavily doped polycrystalline silicon outer base region is formed on the base region-collector region isolation silicon oxide layer and the connecting base region and located on the side of the inner wall of the L-shaped silicon oxide;
[0020] An emitter-base isolation silicon oxide layer is formed on the outer base region of the polycrystalline silicon and located on the side of the inner sidewall of the L-shaped silicon oxide.
[0021] The n-type heavily doped polycrystalline silicon emitter region is formed inside and above the inner wall of the L-shaped silicon oxide and extends outward to the emitter-base isolation silicon oxide layer.
[0022] In some embodiments, at least one of the field region silicon oxide layer, the base region-collector region isolation silicon oxide layer, and the L-shaped silicon oxide inner wall has its positive charge reduced by an annealing process;
[0023] At the interface where the silicon oxide layer in the field region meets the buried current collector region and the silicon epitaxial current collector region, negative charges are introduced through electron or ion implantation.
[0024] At the interface between the base region-collector region isolation silicon oxide layer and the epitaxial collector region, a negative charge is introduced through an electron or ion implantation process.
[0025] At the interface between the bottom of the L-shaped silicon oxide inner wall and the germanium-silicon-carbon epitaxial inner base region and the connecting base region, a negative charge is introduced through an electron or ion implantation process.
[0026] In some embodiments, it further includes: a silicon oxide outer wall formed on the outer side of the base-collector isolation silicon oxide layer, the polysilicon outer base region, the emitter-base isolation silicon oxide layer, and the polysilicon emitter region.
[0027] In some embodiments, the upper surfaces of the field region silicon oxide layer and the silicon epitaxial collector region are flush; the upper surfaces of the connecting base region, the germanium-silicon-carbon epitaxial inner base region, and the base-collector region isolation silicon oxide layer are flush.
[0028] In some embodiments, it also includes:
[0029] The emitter is connected to the polycrystalline silicon emitter region;
[0030] The base is connected to the outer base region of the polycrystalline silicon.
[0031] The collector electrode is electrically connected to the buried layer current collection region;
[0032] The substrate electrode is electrically connected to the substrate.
[0033] In some embodiments, the emitter includes an emitter silicide electrode formed on the polysilicon emitter region; the base includes a base silicide electrode formed on the exposed upper surface of the polysilicon outer base region.
[0034] In some embodiments, heavy doping refers to impurity concentrations of 10. 19 cm -3 The above refers to light doping, which means an impurity concentration of 10. 16 cm -3 the following.
[0035] This application also provides a method for fabricating a germanium-silicon heterojunction npn bipolar transistor, including:
[0036] An npn bipolar transistor basic structure is provided, the npn bipolar transistor basic structure includes a p-type lightly doped silicon substrate, an n-type heavily doped silicon buried collector region formed on the substrate, and an n-type lightly doped silicon epitaxial collector region and a field region silicon oxide layer formed on the buried collector region, wherein the field region silicon oxide layer is located on the side of the silicon epitaxial collector region;
[0037] The positive charge in the field region silicon oxide layer is reduced by means of process, and the negative charge is introduced at the interface where the field region silicon oxide layer connects with the buried layer current collector region and the silicon epitaxial current collector region by means of process.
[0038] A base-collector region isolation silicon oxide layer is deposited, and the positive charge in the base-collector region isolation silicon oxide layer is reduced by process means, and a negative charge is introduced at the interface where the base-collector region isolation silicon oxide layer and the silicon epitaxial collector region are connected by process means.
[0039] A p-type heavily doped outer base region polycrystalline silicon layer, an emitter-base region isolation silicon oxide layer, and a first silicon nitride layer are deposited sequentially.
[0040] Photolithography is performed on the collector region window. The first silicon nitride layer, the emitter-base region isolation silicon oxide layer and the outer base region polysilicon layer are sequentially etched using photoresist as a mask until the base region-collector region isolation silicon oxide layer is exposed, forming the collector region window.
[0041] SiC ion implantation is performed through the collector region window to form a SiC region in the area of the silicon epitaxial collector region opposite the collector region window, and then the photoresist is removed.
[0042] First, a second silicon nitride layer is deposited, and then the silicon nitride is etched anisotropically to form an inner wall of silicon nitride inside the window of the collector region.
[0043] Using the remaining silicon nitride layer and the inner wall of the silicon nitride as a mask, the exposed base-collector region isolation silicon oxide layer is wet-etched away, and the base-collector region isolation silicon oxide layer is further etched laterally, so that a part of the silicon epitaxial collector region is exposed.
[0044] Using a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method, a germanium-silicon-carbon epitaxial inner base region located below the region surrounded by the silicon nitride inner sidewall, a cantilever of the polycrystalline silicon layer in the outer base region, and a connection base region located below the silicon nitride inner sidewall are simultaneously grown.
[0045] The remaining silicon nitride layer and the inner wall of the silicon nitride are removed by wet etching;
[0046] A silicon oxide isolation layer is deposited, and the positive charge in the silicon oxide isolation layer is reduced by means of a process, and a negative charge is introduced at the interface where the silicon oxide isolation layer is connected to the germanium silicon carbon epitaxial inner base region and the connecting base region by means of a process.
[0047] First, an n-type heavily doped first polysilicon layer is deposited, and then the first polysilicon layer is anisotropically dry etched to form the inner sidewall of the emitter region polysilicon.
[0048] The exposed silicon oxide isolation layer is removed by wet etching using the polycrystalline silicon inner wall as a mask to form an L-shaped silicon oxide inner wall, wherein the bottom of the L-shaped silicon oxide inner wall forms a window area.
[0049] A second polysilicon layer heavily doped with n-type is deposited, and the second polysilicon layer is combined with the inner sidewall of the emitter polysilicon layer to form an n-type heavily doped emitter polysilicon layer.
[0050] Photolithography is performed on the polycrystalline silicon emitter region, and the n-type heavily doped emitter region polycrystalline silicon layer and the emitter region-base region isolation silicon oxide layer are sequentially etched using photoresist as a mask to form the n-type heavily doped polycrystalline silicon emitter region. Then the photoresist is removed.
[0051] Photolithography is performed on the polysilicon outer base region, and the polysilicon layer of the outer base region and the base-collector isolation silicon oxide layer are etched using photoresist as a mask to form a p-type heavily doped polysilicon outer base region. Then the photoresist is removed.
[0052] Rapid thermal annealing is performed to allow impurities in the polycrystalline silicon emitter region to diffuse into the germanium-silicon-carbon epitaxial inner base region, forming an n-type heavily doped single-crystal emitter region.
[0053] In some embodiments, after the deposition of the base-collector region isolation silicon oxide layer, the positive charge in the base-collector region isolation silicon oxide layer is reduced by an annealing process, and a negative charge is introduced at the interface between the base-collector region isolation silicon oxide layer and the silicon epitaxial collector region by an electron or ion implantation process.
[0054] After the silicon oxide isolation layer is deposited, the positive charge in the silicon oxide isolation layer is reduced by an annealing process, and negative charge is introduced at the interface where the silicon oxide isolation layer meets the germanium silicon carbon epitaxial inner base region and the connecting base region by an electron or ion implantation process.
[0055] After the silicon oxide isolation layer is deposited, the positive charge in the silicon oxide isolation layer is reduced by an annealing process, and negative charge is introduced at the interface where the silicon oxide isolation layer meets the germanium-silicon-carbon epitaxial inner base region and the connecting base region by an electron or ion implantation process.
[0056] In some embodiments, after forming the p-type heavily doped polysilicon substrate region and then removing the photoresist, and before performing rapid thermal annealing, the method further includes:
[0057] Deposit a silicon oxide layer on the outer wall;
[0058] After the rapid thermal annealing, the method further includes:
[0059] The outer wall silicon oxide layer is etched using anisotropic dry etching to form a silicon oxide outer wall.
[0060] In some embodiments, the method further includes:
[0061] An emitter, a base, a collector, and a substrate are formed, such that the emitter is connected to the polysilicon emitter region, the base is connected to the polysilicon outer base region, the collector is electrically connected to the buried layer collector region, and the substrate is electrically connected to the substrate.
[0062] In some embodiments, forming the emitter and base includes:
[0063] Emitter silicide electrodes and base silicide electrodes are formed by silicide reaction between refractory metal and the exposed polycrystalline silicon emitter region and polycrystalline silicon base region, which are self-aligned and isolated by the outer wall of the silicon oxide.
[0064] The germanium-silicon heterojunction npn bipolar transistor and its fabrication method provided in this application require, through process means, not only to reduce the positive charge in the field region silicon oxide layer in the basic structure, but also to introduce negative charge at the interface between the silicon oxide layer and silicon (including the uppermost silicon capping layer in the inner base region). The effect is as follows:
[0065] The negative charge introduced at the interface between the inner wall of the L-shaped silicon oxide and the uppermost silicon capping layer of the germanium-silicon-carbon epitaxial base region can cause or enhance the hole accumulation state of the lower side of the inner wall of the L-shaped silicon oxide and the adjacent p-type connection base region, thereby increasing the hole concentration in the corresponding region and effectively reducing the parasitic resistance of the corresponding connection base region.
[0066] The negative charge introduced at the interface between the field region silicon oxide layer and the n-type heavily doped silicon buried layer collector region and the n-type lightly doped silicon epitaxial collector region can cause or enhance the electron depletion state of the n-type heavily doped silicon buried layer collector region and the n-type lightly doped silicon epitaxial collector region adjacent to the field region silicon oxide layer, thereby reducing the electron concentration in the corresponding region and effectively reducing the parasitic capacitance of the corresponding base-collector region.
[0067] The negative charge introduced at the interface between the base-collector isolation silicon oxide layer and the n-type lightly doped silicon epitaxial collector region can cause or enhance the electron depletion state of the n-type lightly doped silicon epitaxial collector region adjacent to the base-collector isolation silicon oxide layer, thereby reducing the electron concentration in the corresponding region and effectively reducing the parasitic capacitance of the corresponding base-collector region.
[0068] Reducing the parasitic resistance of the connection base region can decrease the parasitic base region resistance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor in this embodiment. This not only reduces the resistance at a given ft value... T Increase f under the condition max Furthermore, it can effectively reduce the RF noise figure; and reducing the parasitic capacitance between the base and collector regions can also reduce the noise figure at a given f. T Increase f under the condition max In other words, reducing the parasitic base region resistance and the parasitic base-collector region capacitance can improve the overall device performance, such as RF power and noise, of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor used as an RF device. Attached Figure Description
[0069] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:
[0070] Figure 1 This is a schematic flowchart illustrating a method for fabricating a germanium-silicon heterojunction npn bipolar transistor according to an embodiment of this application.
[0071] Figures 2 to 16 This is a schematic diagram of the semiconductor structure obtained by each key process step in the fabrication method of a germanium-silicon heterojunction npn bipolar transistor provided in the embodiments of this application.
[0072] [Attached image labels]
[0073] A. Current collection area window;
[0074] 1. Substrate;
[0075] 2. Buried layer current collection area;
[0076] 3. Silicon epitaxial collector region;
[0077] 4. Silica layer in the field area;
[0078] 5. Base-collector region isolation silicon oxide layer;
[0079] 6. Polycrystalline silicon layer in the outer base region;
[0080] 6a. Polycrystalline silicon outer base region;
[0081] 7. Emitter-base isolation silicon oxide layer;
[0082] 8. First silicon nitride layer;
[0083] 9. Photoresist;
[0084] 9a. Window area;
[0085] 10. SIC Zone;
[0086] 11. Germanium-silicon-carbon epitaxial inner base region;
[0087] 12. Connect the base region;
[0088] 13. Silicon oxide insulating layer;
[0089] 13a. L-shaped silica inner wall;
[0090] 14. Emitter region polycrystalline silicon layer;
[0091] 14a. Inner wall of polysilicon emitter region;
[0092] 14b. Polycrystalline silicon emitter region;
[0093] 15. Single-crystal emitter region;
[0094] 16. Emitter silicide electrode;
[0095] 17. Base silicide electrode;
[0096] 18. Silicon oxide layer on the outer wall;
[0097] 18a. Silica outer wall;
[0098] 19. Silicon nitride inner wall;
[0099] 20. The remaining silicon nitride layer. Detailed Implementation
[0100] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0101] Specific embodiments of this application are disclosed in detail with reference to the following description and accompanying drawings, indicating how the principles of this application can be adopted. It should be understood that the embodiments of this application are not limited in scope. Within the spirit and scope of the appended claims, embodiments of this application include many changes, modifications, and equivalents.
[0102] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.
[0103] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.
[0104] In order to solve at least one of the above-mentioned problems in the prior art, embodiments of this application provide a germanium-silicon heterojunction npn bipolar transistor and a method for fabricating the same.
[0105] Figure 1 This is a schematic flowchart illustrating a method for fabricating a germanium-silicon heterojunction npn bipolar transistor according to an embodiment of this application. Figure 1As shown in the embodiment of this application, a method for fabricating a germanium-silicon heterojunction npn bipolar transistor includes:
[0106] S1. Provide an npn bipolar transistor basic structure, the npn bipolar transistor basic structure including a p-type lightly doped silicon substrate 1, an n-type heavily doped silicon buried collector region 2 formed on the substrate 1, and an n-type lightly doped silicon epitaxial collector region 3 and a field region silicon oxide layer 4 formed on the buried collector region 2, wherein the field region silicon oxide layer 4 is located on the side of the silicon epitaxial collector region 3;
[0107] In step S1, the basic structure of the npn bipolar transistor is as follows: Figure 2 As shown.
[0108] S2. Reduce the positive charge in the field region silicon oxide layer 4 by means of process, and introduce negative charge at the interface where the field region silicon oxide layer 4 connects with the buried layer current collector region 2 and the silicon epitaxial current collector region 3 by means of process.
[0109] In step S2, see Figure 2 For the silicon oxide layer 4 in the field region, the positive charge therein is minimized to the maximum extent through process techniques, and a sufficient amount of negative charge is introduced at its interface with silicon, such as... Figure 2 The negative sign in the text is shown.
[0110] S3. Deposit a base region-collector region isolation silicon oxide layer 5, and reduce the positive charge in the base region-collector region isolation silicon oxide layer 5 by means of process, and introduce negative charge at the interface where the base region-collector region isolation silicon oxide layer 5 and the silicon epitaxial collector region 3 are connected by means of process.
[0111] In step S3, see Figure 3 A base-collector isolation silicon oxide layer 5 is deposited on the basic structure of the npn bipolar transistor, and the positive charge in the base-collector isolation silicon oxide layer 5 is minimized by means of the process, and a sufficient amount of negative charge is introduced at the interface where the base-collector isolation silicon oxide layer 5 is connected to the silicon epitaxial collector region 3 by means of the process.
[0112] S4. Sequentially deposit a p-type heavily doped outer base region polycrystalline silicon layer 6, an emitter-base region isolation silicon oxide layer 7, and a first silicon nitride layer 8;
[0113] In step S3, see Figure 3 The p-type heavily doped outer base region polycrystalline silicon layer 6, the emitter-base region isolation silicon oxide layer 7, and the first silicon nitride layer 8 are then deposited sequentially. Specifically, the p-type heavily doped outer base region polycrystalline silicon layer 6 can be a p-type in-situ boron heavily doped outer base region polycrystalline silicon layer 6.
[0114] S5. Perform photolithography on collector region window A. Using photoresist 9 as a mask, sequentially etch the first silicon nitride layer 8, the emitter-base region isolation silicon oxide layer 7 and the outer base region polysilicon layer 6 until the base region-collector region isolation silicon oxide layer 5 is exposed to form collector region window A.
[0115] In step S5, see Figure 4 Photolithography is performed on the collector region window A to form photoresist 9 on the first silicon nitride layer 8, and a window region 9a is formed on the photoresist 9; see also Figure 5 Using photoresist 9 as a mask, the first silicon nitride layer 8, the emitter-base region isolation silicon oxide layer 7, and the outer base region polysilicon layer 6 are etched sequentially to expose the base region-collector region isolation silicon oxide layer 5, forming the collector region window A.
[0116] S6. Perform SIC ion implantation through the collector region window A to form an SIC region 10 in the area of the silicon epitaxial collector region 3 opposite to the collector region window A, and then remove the photoresist 9.
[0117] In step S6, see Figure 5 Before removing the photoresist 9 after etching, selective implantation of the collector region (SIC) is performed on the exposed base-collector region isolation silicon oxide layer 5, thereby forming a selectively implanted collector region, i.e., the SIC region 10, in the area of the lightly doped silicon epitaxial collector region 3 opposite the collector region window A. Then, the photoresist 9 is removed.
[0118] S7. First, deposit the second silicon nitride layer, then anisotropically dry etch the silicon nitride to form a silicon nitride inner wall 19 inside the collector region window A.
[0119] In step S7, see Figure 6 First, a second silicon nitride layer is deposited, and then silicon nitride is anisotropically etched to form an inner sidewall 19 of silicon nitride at the edge of the collector window A.
[0120] S8. Using the remaining silicon nitride layer 20 and the inner wall 19 of the silicon nitride as a mask, wet etching is used to remove the exposed base-collector region isolation silicon oxide layer 5, and the base-collector region isolation silicon oxide layer 5 is further etched laterally, so that a part of the silicon epitaxial collector region 3 is exposed.
[0121] In step S8, see Figure 7 Using the remaining silicon nitride layer 20 and the silicon nitride inner sidewall 19 as a mask, the exposed base-collector region isolation silicon oxide layer 5 is wet-etched away, and the base-collector region isolation silicon oxide layer 5 is further etched laterally, so that a part of the silicon epitaxial collector region 3 is exposed.
[0122] S9. Using a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method, a germanium-silicon-carbon epitaxial inner base region 11 located below the region surrounded by the silicon nitride inner sidewall 19 and a cantilever of the polycrystalline silicon layer 6 in the outer base region and a connecting base region 12 located below the silicon nitride inner sidewall 19 are simultaneously grown.
[0123] In step S9, see Figure 8 By using a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method, a germanium-silicon-carbon epitaxial inner base region 11 (intrinsic inner base region) and an outer base region polycrystalline silicon layer 6 cantilever and a connecting base region 12 under the silicon nitride inner sidewall 19 are simultaneously grown.
[0124] S10. Wet etching removes the remaining silicon nitride layer 20 and the silicon nitride inner wall 19;
[0125] In step S10, see Figure 9 The remaining silicon nitride layer 20 and the silicon nitride inner wall 19 are removed by wet etching.
[0126] S11. Deposit a silicon oxide isolation layer 13, and reduce the positive charge in the silicon oxide isolation layer 13 by means of a process, and introduce a negative charge at the interface where the silicon oxide isolation layer 13 is connected to the germanium silicon carbon epitaxial inner base region 11 and the connecting base region 12 by means of a process.
[0127] In step S11, see Figure 10 A thin silicon oxide isolation layer 13 is deposited, and through process means, the positive charge in the silicon oxide isolation layer 13 is minimized, and through process means, a sufficient amount of negative charge is introduced at the interface where the silicon oxide isolation layer 13 is connected to the germanium silicon carbon epitaxial inner base region 11 and the connecting base region 12, that is, a sufficient amount of negative charge is introduced at the interface between it and the silicon capping layer of the germanium silicon carbon epitaxial inner base region 11.
[0128] S12. First, deposit an n-type heavily doped first polysilicon layer, and then anisotropically dry etch the first polysilicon layer to form the emitter region polysilicon inner sidewall 14a.
[0129] In step S12, see Figure 10 First, an n-type in-situ heavily doped inner sidewall emitter polysilicon layer (first polysilicon layer) is deposited, and then anisotropic dry etching is used to form the emitter polysilicon inner sidewall 14a.
[0130] S13. Using the inner wall 14a of the emitter region as a mask, wet etching is used to remove the exposed silicon oxide isolation layer 13 to form an L-shaped silicon oxide inner wall 13a, wherein the bottom of the L-shaped silicon oxide inner wall 13a forms a window area.
[0131] In step S13, see Figures 10 to 11 The exposed silicon oxide isolation layer 13 is removed by wet etching using the inner sidewall 14a of the emitter region as a mask, forming an L-shaped silicon oxide inner sidewall 13a (also called an L-shaped silicon oxide isolation layer). The bottom of the L-shaped silicon oxide inner sidewall 13a forms a window area.
[0132] S14. Deposit an n-type heavily doped second polysilicon layer. The second polysilicon layer and the inner sidewall 14a of the emitter region polysilicon layer form an n-type heavily doped emitter region polysilicon layer 14.
[0133] In step S14, see Figure 11 An in-situ heavily doped n-type polysilicon layer is deposited, and the second polysilicon layer is combined with the inner sidewall 14a of the emitter region polysilicon to form an n-type heavily doped emitter region polysilicon layer 14.
[0134] S15. Perform polysilicon emitter region photolithography, and sequentially etch the n-type heavily doped emitter region polysilicon layer 14 and the emitter region-base region isolation silicon oxide layer 7 using photoresist as a mask to form the n-type heavily doped polysilicon emitter region 14b, and then remove the photoresist.
[0135] In step S15, see Figure 12 Photolithography of the polysilicon emitter region is performed, and the exposed n-type in-situ heavily doped emitter region polysilicon layer 14 and the underlying emitter-base isolation silicon oxide layer 7 are sequentially etched away using photoresist as a mask to form the n-type heavily doped polysilicon emitter region 14b. Then the photoresist is removed.
[0136] S16. Perform photolithography on the polysilicon outer base region, and use photoresist as a mask to etch the polysilicon layer 6 of the outer base region and the base region-collector region isolation silicon oxide layer 5 to form a p-type heavily doped polysilicon outer base region 6a, and then remove the photoresist.
[0137] In step S16, see Figure 13 Photolithography is performed on the polysilicon outer substrate, and the exposed polysilicon outer substrate layer 6 and the underlying base-collector isolation silicon oxide layer 5 are sequentially etched away using photoresist as a mask to form a p-type heavily doped polysilicon outer substrate region 6a. Then the photoresist is removed.
[0138] S17. Perform rapid thermal annealing to allow impurities in the polycrystalline silicon emitter region 14b to diffuse into the germanium-silicon-carbon epitaxial inner base region 11 to form an n-type heavily doped single crystal emitter region 15.
[0139] In step S17, see Figure 14 Rapid thermal annealing (RTA) is performed, which on the one hand allows impurities in the polycrystalline silicon emitter region 14b to diffuse into the germanium-silicon-carbon epitaxial inner base region 11 to form an n-type heavily doped single crystal emitter region 15, and on the other hand achieves impurity activation.
[0140] The method for fabricating a germanium-silicon heterojunction npn bipolar transistor provided in this application requires, through process means, not only to reduce the positive charge in the field region silicon oxide layer 4 in the basic structure, but also to introduce negative charge at the interface between the silicon oxide layer 4 and silicon (including the uppermost silicon capping layer in the germanium-silicon-carbon epitaxial base region 11). The effect is as follows:
[0141] The negative charge introduced at the interface between the L-shaped silicon oxide inner sidewall 13a and the uppermost silicon capping layer of the germanium-silicon-carbon epitaxial inner base region 11 can cause or enhance the hole accumulation state of the lower side of the L-shaped silicon oxide inner sidewall 13a and its adjacent p-type connection base region 12, thereby increasing the hole concentration in the corresponding region and effectively reducing the parasitic resistance of the corresponding connection base region 12.
[0142] The negative charge introduced at the interface between the field region silicon oxide layer 4 and the n-type heavily doped silicon buried layer collector region 2 and the n-type lightly doped silicon epitaxial collector region 3 can cause or enhance the electron depletion state of the n-type heavily doped silicon buried layer collector region 2 and the n-type lightly doped silicon epitaxial collector region 3 adjacent to the field region silicon oxide layer 4, thereby reducing the electron concentration in the corresponding region and effectively reducing the parasitic capacitance of the corresponding base region-collector region.
[0143] The negative charge introduced at the interface between the base-collector region isolation silicon oxide layer 5 and the n-type lightly doped silicon epitaxial collector region 3 can cause or enhance the electron depletion state of the n-type lightly doped silicon epitaxial collector region 3 adjacent to the base-collector region isolation silicon oxide layer 5, thereby reducing the electron concentration in the corresponding region and effectively reducing the parasitic capacitance of the corresponding base-collector region.
[0144] Reducing the parasitic resistance of the connection base region 12 can reduce the parasitic base region resistance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor in this embodiment. This not only reduces the resistance at a given f... T Increase f under the condition max Furthermore, it can effectively reduce the RF noise figure; and reducing the parasitic capacitance between the base and collector regions can also reduce the noise figure at a given f. T Increase f under the condition max In other words, reducing the parasitic base region resistance and the parasitic base-collector region capacitance can improve the overall device performance, such as RF power and noise, of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor used as an RF device.
[0145] In some embodiments, after depositing the base-collector region isolation silicon oxide layer 5, the positive charge in the base-collector region isolation silicon oxide layer 5 is reduced by processes such as annealing, and a negative charge is introduced at the interface where the base-collector region isolation silicon oxide layer 5 connects to the silicon epitaxial collector region 3 by processes such as electron implantation or ion implantation; after depositing the silicon oxide isolation layer 13, the positive charge in the silicon oxide isolation layer 13 is reduced by processes such as annealing, and a negative charge is introduced at the interface where the silicon oxide isolation layer 13 connects to the germanium-silicon-carbon epitaxial inner base region 11 and the connecting base region 12 by processes such as electron implantation or ion implantation; after depositing the silicon oxide isolation layer 13, the positive charge in the silicon oxide isolation layer 13 is reduced by processes such as annealing, and a negative charge is introduced at the interface where the silicon oxide isolation layer 13 connects to the germanium-silicon-carbon epitaxial inner base region 11 and the connecting base region 12 by processes such as electron implantation or ion implantation. In some embodiments, after step S16 and before step S17, the method further includes:
[0146] S17-0, deposit the outer wall silicon oxide layer 18.
[0147] In step S17-0, see Figure 14 , depositing a silicon oxide layer 18 on the outer wall.
[0148] In some embodiments, after depositing the outer wall silicon oxide layer 18 and performing rapid thermal annealing, the method further includes:
[0149] S18. The outer wall silicon oxide layer 18 is etched using anisotropic dry etching to form a silicon oxide outer wall 18a.
[0150] In step S18, see Figure 15 Anisotropic dry etching is used to etch the outer wall silicon oxide layer 18 to form the silicon oxide outer wall 18a.
[0151] In some embodiments, after step S18 described above, the method further includes:
[0152] S19. An emitter, a base, a collector, and a substrate are formed, such that the emitter is connected to the polysilicon emitter region 14b, the base is connected to the polysilicon outer base region 6a, the collector is electrically connected to the buried layer collector region 2, and the substrate is electrically connected to the substrate 1.
[0153] In some embodiments, the formation of the emitter and base includes: forming an emitter silicide electrode 16 and a base silicide electrode 17 by silicide reaction of a refractory metal with the exposed polycrystalline silicon emitter region 14b and the polycrystalline silicon base region 6a, which are self-aligned and isolated by the silicon oxide outer wall 18a.
[0154] For details, see Figure 16 By utilizing the silicide reaction between refractory metal and exposed monocrystalline and polycrystalline silicon, a low-resistance metal silicide layer is formed through self-alignment, thereby forming an emitter silicide electrode 16 and a base silicide electrode 17, respectively.
[0155] Finally, the germanium-silicon heterojunction npn bipolar transistor can also be fabricated using back-end metallization processes in this field. It should be noted that, considering that this application does not impose any restrictions on the collector and substrate lead-out methods, or the number and relative positions of the emitter, base, collector, and substrate electrodes of the germanium-silicon heterojunction npn bipolar transistor, the electrode lead-out methods of the collector and substrate regions and all electrode configurations are not fully illustrated in the specification and related process flow diagrams of this application. However, all of these can be implemented using common techniques in this field.
[0156] Based on the same inventive concept, this application also provides a germanium-silicon heterojunction npn bipolar transistor.
[0157] Figure 16 This is a schematic diagram of the structure of a germanium-silicon heterojunction npn bipolar transistor provided in an embodiment of this application. Figure 16 As shown in the embodiment of this application, a germanium-silicon heterojunction npn bipolar transistor 001 includes:
[0158] p-type lightly doped silicon substrate 1;
[0159] n-type heavily doped silicon buried layer collector region 2 is formed on the substrate 1;
[0160] n-type lightly doped silicon epitaxial collector region 3 is formed on the buried layer collector region 2;
[0161] The SIC region 10 is formed in the silicon epitaxial collector region 3 by the SIC ion implantation process;
[0162] A field region silicon oxide layer 4 is formed on the buried layer current collector region 2 and located on the side of the silicon epitaxial current collector region 3. The field region silicon oxide layer 4 reduces positive charge through process means, and negative charge is introduced at the interface where the field region silicon oxide layer 4 connects with the buried layer current collector region 2 and the silicon epitaxial current collector region 3 through process means.
[0163] p-type in-situ doped germanium silicon-carbon epitaxial base region 11 is formed on the SiC region 10;
[0164] A connecting base region 12 is formed on the SiC region 10 and the silicon epitaxial collector region 3;
[0165] A base-collector isolation silicon oxide layer 5 is formed on the silicon epitaxial collector region 3 and the field region silicon oxide layer 4. The base-collector isolation silicon oxide layer 5 reduces positive charge through process means, and negative charge is introduced at the interface between the base-collector isolation silicon oxide layer 5 and the silicon epitaxial collector region 3 through process means.
[0166] L-shaped silicon oxide inner sidewall 13a is formed on the germanium-silicon-carbon epitaxial inner base region 11 and the connecting base region 12. The bottom of the L-shaped silicon oxide inner sidewall 13a forms a window region. The positive charge of the L-shaped silicon oxide inner sidewall 13a is reduced by process means, and the negative charge is introduced at the interface between the bottom of the L-shaped silicon oxide inner sidewall 13a and the germanium-silicon-carbon epitaxial inner base region 11 and the connecting base region 12 by process means.
[0167] A single-crystal emitter region 15 is formed on the germanium-silicon-carbon epitaxial inner base region 11 and located below the window region;
[0168] p-type heavily doped polycrystalline silicon outer base region 6a is formed on the base region-collector region isolation silicon oxide layer 5 and the connecting base region 12 and is located on the side of the L-shaped silicon oxide inner sidewall 13a;
[0169] An emitter-base isolation silicon oxide layer 7 is formed on the outer base region 6a of the polysilicon and is located on the side of the inner sidewall 13a of the L-shaped silicon oxide.
[0170] The n-type heavily doped polysilicon emitter region 14b is formed inside and above the L-shaped silicon oxide inner sidewall 13a and extends outward to the emitter-base isolation silicon oxide layer 7. The germanium-silicon heterojunction npn bipolar transistor provided in this application requires, through process means, not only to reduce the positive charge in the field region silicon oxide layer 4 in the basic structure, but also to introduce negative charges at the interface between it and silicon (including the uppermost silicon capping layer in the germanium-silicon-carbon epitaxial base region 11). The effect is:
[0171] The negative charge introduced at the interface between the L-shaped silicon oxide inner sidewall 13a and the uppermost silicon capping layer of the germanium-silicon-carbon epitaxial inner base region 11 can cause or enhance the hole accumulation state of the lower side of the L-shaped silicon oxide inner sidewall 13a and its adjacent p-type connection base region 12, thereby increasing the hole concentration in the corresponding region and effectively reducing the parasitic resistance of the corresponding connection base region 12.
[0172] The negative charge introduced at the interface between the field region silicon oxide layer 4 and the n-type heavily doped silicon buried layer collector region 2 and the n-type lightly doped silicon epitaxial collector region 3 can cause or enhance the electron depletion state of the n-type heavily doped silicon buried layer collector region 2 and the n-type lightly doped silicon epitaxial collector region 3 adjacent to the field region silicon oxide layer 4, thereby reducing the electron concentration in the corresponding region and effectively reducing the parasitic capacitance of the corresponding base region-collector region.
[0173] The negative charge introduced at the interface between the base-collector region isolation silicon oxide layer 5 and the n-type lightly doped silicon epitaxial collector region 3 can cause or enhance the electron depletion state of the n-type lightly doped silicon epitaxial collector region 3 adjacent to the base-collector region isolation silicon oxide layer 5, thereby reducing the electron concentration in the corresponding region and effectively reducing the parasitic capacitance of the corresponding base-collector region.
[0174] Reducing the parasitic resistance of the connection base region 12 can reduce the parasitic base region resistance of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor in this embodiment. This not only reduces the resistance at a given f... T Increase f under the condition max Furthermore, it can effectively reduce the RF noise figure; and reducing the parasitic capacitance between the base and collector regions can also reduce the noise figure at a given f. T Increase f under the condition max In other words, reducing the parasitic base region resistance and the parasitic base-collector region capacitance can improve the overall device performance, such as RF power and noise, of the dual polycrystalline self-aligned germanium-silicon heterojunction npn bipolar transistor used as an RF device.
[0175] In some embodiments, at least one of the field region silicon oxide layer 4, the base region-collector region isolation silicon oxide layer 5, and the L-shaped silicon oxide inner sidewall 13a reduces positive charge through processes such as annealing; negative charge is introduced at the interface between the field region silicon oxide layer 4 and the buried layer collector region 2 and the silicon epitaxial collector region 3 through processes such as electron or ion implantation; negative charge is introduced at the interface between the base region-collector region isolation silicon oxide layer 5 and the silicon epitaxial collector region 3 through processes such as electron or ion implantation; negative charge is introduced at the interface between the bottom of the L-shaped silicon oxide inner sidewall 13a and the germanium-silicon-carbon epitaxial inner base region 11 and the connecting base region 12 through processes such as electron or ion implantation.
[0176] In some embodiments, it also includes:
[0177] The silicon oxide outer wall 18a is formed on the outer side of the base region-collector region isolation silicon oxide layer 5, the polysilicon outer base region 6a, the emitter region-base region isolation silicon oxide layer 7, and the polysilicon emitter region 14b.
[0178] In some embodiments, the upper surfaces of the field region silicon oxide layer 4 and the silicon epitaxial collector region 3 are flush; the upper surfaces of the connecting base region 12, the germanium-silicon-carbon epitaxial inner base region 11, and the base region-collector region isolation silicon oxide layer 5 are flush.
[0179] In some embodiments, it also includes:
[0180] The emitter is connected to the polycrystalline silicon emitter region 14b;
[0181] The base is connected to the polycrystalline silicon outer base region 6a;
[0182] The collector electrode is electrically connected to the buried layer collector region 2.
[0183] The substrate electrode is electrically connected to the substrate 1.
[0184] In some embodiments, the emitter includes an emitter silicide electrode 16, which is formed on the polysilicon emitter region 14b;
[0185] The base includes a base silicide electrode 17, which is formed on the exposed upper surface of the polysilicon outer base region 6a.
[0186] In some embodiments, heavy doping refers to impurity concentrations of 10. 19 cm -3 The above refers to light doping, which means an impurity concentration of 10. 16 cm -3 the following.
[0187] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The terms "upper," "lower," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and for simplification, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0188] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments in this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0189] This application uses specific embodiments to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A germanium-silicon heterojunction npn-type bipolar transistor, characterized in that, include: p-type lightly doped silicon substrate; An n-type heavily doped silicon buried collector region is formed on the substrate; An n-type lightly doped silicon epitaxial collector region is formed on the buried layer collector region; The SiC region is formed in the silicon epitaxial collector region by SiC ion implantation process; A field region silicon oxide layer is formed on the buried layer current collector region and located on the side of the silicon epitaxial current collector region. The field region silicon oxide layer reduces positive charge through process means, and negative charge is introduced at the interface between the field region silicon oxide layer and the buried layer current collector region and the silicon epitaxial current collector region through process means. p-type in-situ doped germanium silicon-carbon epitaxial base region is formed on the SiC region; A connection base region is formed on the SiC region and the silicon epitaxial collector region; A base-collector isolation silicon oxide layer is formed on the silicon epitaxial collector region and the field region silicon oxide layer. The base-collector isolation silicon oxide layer reduces positive charge through process means, and negative charge is introduced at the interface between the base-collector isolation silicon oxide layer and the silicon epitaxial collector region through process means. L-shaped silicon oxide inner walls are formed on the germanium-silicon-carbon epitaxial inner base region and the connecting base region. The bottom of the L-shaped silicon oxide inner walls forms a window region. The positive charge of the L-shaped silicon oxide inner walls is reduced by process means, and the negative charge is introduced at the interface between the bottom of the L-shaped silicon oxide inner walls and the germanium-silicon-carbon epitaxial inner base region and the connecting base region by process means. A single-crystal emitter region is formed on the inner base region of the germanium-silicon-carbon epitaxial layer and located below the window region; p-type heavily doped polycrystalline silicon outer base region is formed on the base region-collector region isolation silicon oxide layer and the connecting base region and located on the side of the inner wall of the L-shaped silicon oxide; An emitter-base isolation silicon oxide layer is formed on the outer base region of the polycrystalline silicon and located on the side of the inner sidewall of the L-shaped silicon oxide. The n-type heavily doped polycrystalline silicon emitter region is formed inside and above the inner wall of the L-shaped silicon oxide and extends outward to the emitter-base isolation silicon oxide layer.
2. The germanium-silicon heterojunction npn bipolar transistor according to claim 1, characterized in that, At least one of the field region silicon oxide layer, the base region-collector region isolation silicon oxide layer, and the L-shaped silicon oxide inner wall has its positive charge reduced by an annealing process. At the interface where the silicon oxide layer in the field region meets the buried current collector region and the silicon epitaxial current collector region, negative charges are introduced through electron or ion implantation. At the interface between the base region-collector region isolation silicon oxide layer and the epitaxial collector region, a negative charge is introduced through an electron or ion implantation process. At the interface between the bottom of the L-shaped silicon oxide inner wall and the germanium-silicon-carbon epitaxial inner base region and the connecting base region, a negative charge is introduced through an electron or ion implantation process.
3. The germanium-silicon heterojunction npn bipolar transistor according to claim 2, characterized in that, Also includes: A silicon oxide outer wall is formed on the outer side of the base-collector region isolation silicon oxide layer, the polysilicon outer base region, the emitter region-base region isolation silicon oxide layer, and the polysilicon emitter region.
4. The germanium-silicon heterojunction npn bipolar transistor according to claim 3, characterized in that, The upper surfaces of the silicon oxide layer in the field region and the silicon epitaxial current collector region are flush; The upper surfaces of the connecting base region, the germanium-silicon-carbon epitaxial inner base region, and the base region-collector region isolation silicon oxide layer are flush.
5. The germanium-silicon heterojunction npn bipolar transistor according to claim 1, characterized in that, Also includes: The emitter is connected to the polycrystalline silicon emitter region; The base is connected to the outer base region of the polycrystalline silicon. The collector electrode is electrically connected to the buried layer current collection region; The substrate electrode is electrically connected to the substrate.
6. The germanium-silicon heterojunction npn bipolar transistor according to claim 5, characterized in that, The emitter includes an emitter silicide electrode, which is formed on the polycrystalline silicon emitter region; The base includes a base silicide electrode formed on the exposed upper surface of the polycrystalline silicon outer base region.
7. The germanium-silicon heterojunction npn bipolar transistor according to claim 1, characterized in that, The term "heavy doping" refers to an impurity concentration of 10. 19 cm -3 The above refers to light doping, which means an impurity concentration of 10. 16 cm -3 the following.
8. A method for fabricating a germanium-silicon heterojunction npn-type bipolar transistor, characterized in that, include: An npn bipolar transistor basic structure is provided, the npn bipolar transistor basic structure includes a p-type lightly doped silicon substrate, an n-type heavily doped silicon buried collector region formed on the substrate, and an n-type lightly doped silicon epitaxial collector region and a field region silicon oxide layer formed on the buried collector region, wherein the field region silicon oxide layer is located on the side of the silicon epitaxial collector region; The positive charge in the field region silicon oxide layer is reduced by means of process, and the negative charge is introduced at the interface where the field region silicon oxide layer connects with the buried layer current collector region and the silicon epitaxial current collector region by means of process. A base-collector region isolation silicon oxide layer is deposited, and the positive charge in the base-collector region isolation silicon oxide layer is reduced by process means, and a negative charge is introduced at the interface where the base-collector region isolation silicon oxide layer and the silicon epitaxial collector region are connected by process means. A p-type heavily doped outer base region polycrystalline silicon layer, an emitter-base region isolation silicon oxide layer, and a first silicon nitride layer are deposited sequentially. Photolithography is performed on the collector region window. The first silicon nitride layer, the emitter-base region isolation silicon oxide layer and the outer base region polysilicon layer are sequentially etched using photoresist as a mask until the base region-collector region isolation silicon oxide layer is exposed, forming the collector region window. SiC ion implantation is performed through the collector region window to form a SiC region in the area of the silicon epitaxial collector region opposite the collector region window, and then the photoresist is removed. First, a second silicon nitride layer is deposited, and then the silicon nitride is etched anisotropically to form an inner wall of silicon nitride inside the window of the collector region. Using the remaining silicon nitride layer and the inner wall of the silicon nitride as a mask, the exposed base-collector region isolation silicon oxide layer is wet-etched away, and the base-collector region isolation silicon oxide layer is further etched laterally, so that a part of the silicon epitaxial collector region is exposed. Using a p-type in-situ doped germanium-silicon-carbon selective epitaxial growth method, a germanium-silicon-carbon epitaxial inner base region located below the region surrounded by the silicon nitride inner sidewall, a cantilever of the polycrystalline silicon layer in the outer base region, and a connection base region located below the silicon nitride inner sidewall are simultaneously grown. The remaining silicon nitride layer and the inner wall of the silicon nitride are removed by wet etching; A silicon oxide isolation layer is deposited, and the positive charge in the silicon oxide isolation layer is reduced by means of a process, and a negative charge is introduced at the interface where the silicon oxide isolation layer is connected to the germanium silicon carbon epitaxial inner base region and the connecting base region by means of a process. First, an n-type heavily doped first polysilicon layer is deposited, and then the first polysilicon layer is anisotropically dry etched to form the inner sidewall of the emitter region polysilicon. The exposed silicon oxide isolation layer is removed by wet etching using the polycrystalline silicon inner wall as a mask to form an L-shaped silicon oxide inner wall, wherein the bottom of the L-shaped silicon oxide inner wall forms a window area. A second polysilicon layer heavily doped with n-type is deposited, and the second polysilicon layer is combined with the inner sidewall of the emitter polysilicon layer to form an n-type heavily doped emitter polysilicon layer. Photolithography is performed on the polycrystalline silicon emitter region, and the n-type heavily doped emitter region polycrystalline silicon layer and the emitter region-base region isolation silicon oxide layer are sequentially etched using photoresist as a mask to form the n-type heavily doped polycrystalline silicon emitter region. Then the photoresist is removed. Photolithography is performed on the polysilicon outer base region, and the polysilicon layer of the outer base region and the base-collector isolation silicon oxide layer are etched using photoresist as a mask to form a p-type heavily doped polysilicon outer base region. Then the photoresist is removed. Rapid thermal annealing is performed to allow impurities in the polycrystalline silicon emitter region to diffuse into the germanium-silicon-carbon epitaxial inner base region, forming an n-type heavily doped single-crystal emitter region.
9. The method according to claim 8, characterized in that, After depositing the base region-collector region isolation silicon oxide layer, the positive charge in the base region-collector region isolation silicon oxide layer is reduced by an annealing process, and negative charge is introduced at the interface between the base region-collector region isolation silicon oxide layer and the silicon epitaxial collector region by an electron implantation or ion implantation process. After the silicon oxide isolation layer is deposited, the positive charge in the silicon oxide isolation layer is reduced by an annealing process, and negative charge is introduced at the interface where the silicon oxide isolation layer meets the germanium silicon carbon epitaxial inner base region and the connecting base region by an electron or ion implantation process. After the silicon oxide isolation layer is deposited, the positive charge in the silicon oxide isolation layer is reduced by an annealing process, and negative charge is introduced at the interface where the silicon oxide isolation layer meets the germanium-silicon-carbon epitaxial inner base region and the connecting base region by an electron or ion implantation process.
10. The method according to claim 8 or 9, characterized in that, After forming the p-type heavily doped polycrystalline silicon substrate region and then removing the photoresist, and before performing rapid thermal annealing, the method further includes: Deposit a silicon oxide layer on the outer wall; After the rapid thermal annealing, the method further includes: The outer wall silicon oxide layer is etched using anisotropic dry etching to form a silicon oxide outer wall.
11. The method according to claim 10, characterized in that, The method further includes: An emitter, a base, a collector, and a substrate are formed, such that the emitter is connected to the polysilicon emitter region, the base is connected to the polysilicon outer base region, the collector is electrically connected to the buried layer collector region, and the substrate is electrically connected to the substrate.
12. The method according to claim 11, characterized in that, The formation of the emitter and base includes: Emitter silicide electrodes and base silicide electrodes are formed by silicide reaction between refractory metal and the exposed polycrystalline silicon emitter region and polycrystalline silicon base region, which are self-aligned and isolated by the outer wall of the silicon oxide.