An energy-harvesting GFSK-modulated wireless transceiver

Abstract

The application discloses a kind of energy collection GFSK modulation and demodulation wireless transceiver, it is characterized in that, including GFSK demodulator, GFSK modulator, power supply management module, internal control module, radio frequency energy collection module;The GFSK demodulator is connected with transceiving antenna by low-noise amplifier, the GFSK modulator is connected with transceiving antenna by radio frequency power amplifier;The internal control module is connected with GFSK demodulator, GFSK modulator, the GFSK demodulator is used to demodulate received wireless signal, the GFSK modulator is used to modulate the wireless signal that emits;Wherein, the radio frequency energy collection module connects power supply management module, the radio frequency energy collection module is converted into electric energy by energy collection antenna and collects radio frequency energy, and the power supply management module is used to manage the electric energy that radio frequency energy collection module exports and is powered for wireless transceiver.

Description

Technical Field

[0001] This invention relates to the field of wireless information transceiver technology, specifically to a wireless transceiver with energy harvesting GFSK modulation and demodulation. Background Technology

[0002] With the development of smart cities, more and more places and fields require information technology. In low-power wireless data acquisition applications, an external battery is often needed to power the chip. However, the battery capacity and lifespan are limited, requiring periodic battery replacement or the installation of a new acquisition module. But in reality, many nodes are inconvenient to replace or cannot be replaced at all, such as detection nodes embedded inside buildings.

[0003] Existing wireless transceiver chips based on GFSK modulation and demodulation do not integrate wireless power harvesting and require an additional battery for power.

[0004] Therefore, designing a wireless data transceiver chip with long battery life and no need for battery replacement and maintenance has become an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a wireless transceiver that harvests GFSK modulation and demodulation, which collects and stores external radio frequency energy to power the wireless transceiver, thereby improving the flexibility and economy of the Internet of Things network.

[0006] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows:

[0007] A wireless transceiver with energy harvesting GFSK modulation and demodulation includes a GFSK demodulator, a GFSK modulator, a power management module, an internal control module, and a radio frequency energy harvesting module.

[0008] The GFSK demodulator is connected to the transceiver antenna via a low-noise amplifier, and the GFSK modulator is connected to the transceiver antenna via an RF power amplifier.

[0009] The internal control module is connected to a GFSK demodulator and a GFSK modulator. The GFSK demodulator is used to demodulate the received wireless signal, and the GFSK modulator is used to modulate the transmitted wireless signal.

[0010] The radio frequency energy harvesting module is connected to the power supply management module. The radio frequency energy harvesting module collects radio frequency energy through the energy harvesting antenna and converts it into electrical energy. The power supply management module is used to manage the electrical energy output by the radio frequency energy harvesting module to power the wireless transceiver.

[0011] Furthermore, the radio frequency energy harvesting module has an impedance matching unit, a single-ended to differential unit, and an AC boost unit at its radio frequency signal input terminal.

[0012] The impedance matching unit is connected to an external energy harvesting antenna to reduce input signal reflection;

[0013] The single-ended to differential unit connected to the impedance matching unit is used to convert radio signals into AC signals.

[0014] The AC boost unit is connected to a single-ended to differential unit to increase the input voltage.

[0015] Furthermore, the radio frequency energy harvesting module also includes a multi-stage rectifier and a limiting circuit;

[0016] Multiple multi-stage rectifiers are connected in series and then connected to the AC boost unit;

[0017] The output terminals of the AC boost unit and the output terminals of the multiple multi-stage rectifiers are all equipped with limiting circuits.

[0018] The multi-stage rectifier circuit is used to convert AC power into DC power and increase the output voltage.

[0019] Furthermore, the multi-stage rectifier is composed of multiple single-stage rectifier circuits connected in series;

[0020] The single-stage rectifier circuit is provided with a positive input terminal, a negative input terminal, a reference voltage input terminal, and an output terminal connected to the AC boost unit;

[0021] The output terminals of adjacent single-stage rectifier circuits are connected to the reference voltage input terminals.

[0022] Furthermore, the single-stage rectifier circuit includes: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor;

[0023] The input terminal of the reference voltage is connected to the source of the first NMOS transistor and the second NMOS transistor, respectively.

[0024] The positive input terminal is connected to the drain of the first NMOS and the first PMOS transistor, and the gate of the second NMOS and the second PMOS transistor, respectively.

[0025] The negative input terminal is connected to the gate of the first NMOS transistor and the gate of the first PMOS transistor, and the drain of the second NMOS transistor and the second PMOS transistor, respectively.

[0026] The output terminals are respectively connected to the sources of the first PMOS transistor and the second PMOS transistor;

[0027] In this configuration, the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, and the gate of the first NMOS transistor is connected to the gate of the first PMOS transistor.

[0028] The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the second NMOS transistor is connected to the gate of the second PMOS transistor.

[0029] Furthermore, the positive input terminal is provided with a first capacitor, and the negative input terminal is provided with a second capacitor. The first capacitor and the second capacitor are used to block DC and pass AC, effectively filtering interference signals and improving anti-interference capabilities.

[0030] A third capacitor is connected in parallel to the input terminal of the reference voltage, and a fourth capacitor is connected in parallel to the output terminal. The third capacitor is used for filtering the input signal, and the fourth capacitor is used for smoothing the output signal to make the DC voltage output by the rectifier circuit more stable.

[0031] Furthermore, it also includes a passive crystal oscillator module and a clock synthesis module;

[0032] The passive crystal oscillator module is connected to the clock synthesis module to provide a stable, high-precision clock signal.

[0033] The clock synthesis module is connected to the upconversion mixer and the downconversion mixer respectively. The downconversion mixer is located between the GFSK demodulator and the low-noise amplifier, and the upconversion mixer is located between the GFSK modulator and the RF power amplifier.

[0034] Furthermore, the passive crystal oscillation module includes a crystal and a passive crystal oscillation driver, and the clock synthesis module includes a PLL phase-locked loop;

[0035] The passive crystal oscillation drive consists of a third NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor;

[0036] One end of the crystal is connected to the gates of the third NMOS transistor and the third PMOS transistor. The drains of the third NMOS transistor and the third PMOS transistor are connected to the other end of the crystal and the PLL phase-locked loop. The source of the third NMOS transistor is grounded. The source of the third PMOS transistor is connected to the drain of the fourth PMOS transistor. The gate of the fourth PMOS transistor is connected to the bias voltage. The source of the fourth PMOS transistor is connected to the input voltage.

[0037] Furthermore, it also includes a universal bus digital interface, which connects the GFSK demodulator, GFSK modulator, internal control module and external system, and is used for data transmission and exchange.

[0038] Furthermore, a receive data buffer unit is provided between the GFSK demodulator and the general-purpose bus digital interface, and a transmit data buffer unit is provided between the GFSK modulator and the general-purpose bus digital interface.

[0039] By applying the technical solution of this invention, an RF energy harvesting module is added to the wireless transceiver. This allows for the collection and storage of external RF energy to power the transceiver, achieving battery-free sensor data acquisition and wireless data transmission. This reduces the installation difficulty and maintenance frequency of data acquisition nodes in the Internet of Things (IoT) field, improving the flexibility and economy of IoT network deployment. Furthermore, multiple multi-stage rectifier circuits within the RF energy harvesting module amplify the AC signal for use in subsequent circuits.

[0040] Other features and advantages of the invention will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings. Attached Figure Description

[0041] The present invention will now be described in detail with reference to the accompanying drawings, so that the above-mentioned advantages of the present invention will become more apparent.

[0042] Figure 1 This is a schematic diagram of a wireless transceiver for energy harvesting GFSK modulation and demodulation according to the present invention;

[0043] Figure 2 This is a schematic diagram of the radio frequency energy harvesting module of a wireless transceiver with GFSK modulation and demodulation according to the present invention;

[0044] Figure 3 This is a single-stage rectifier circuit diagram of a wireless transceiver for energy harvesting GFSK modulation and demodulation according to the present invention;

[0045] Figure 4 This is a block diagram of the crystal oscillator and frequency synthesis of a GFSK modulated and demodulated wireless transceiver according to the present invention.

[0046] Figure 5 This is a block diagram of the internal control module for GFSK modulation and demodulation of energy harvesting according to the present invention. Detailed Implementation

[0047] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0048] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0049] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0050] like Figure 1-2 As shown, a wireless transceiver with energy harvesting GFSK modulation and demodulation includes a GFSK demodulator, a GFSK modulator, a power management module, an internal control module, and a radio frequency energy harvesting module.

[0051] The GFSK demodulator is connected to the transceiver antenna via a low-noise amplifier, and the GFSK modulator is connected to the transceiver antenna via an RF power amplifier.

[0052] The internal control module is connected to a GFSK demodulator and a GFSK modulator. The GFSK demodulator is used to demodulate the received wireless signal, and the GFSK modulator is used to modulate the transmitted wireless signal.

[0053] The radio frequency energy harvesting module is connected to the power supply management module. The radio frequency energy harvesting module collects radio frequency energy through the energy harvesting antenna and converts it into electrical energy. The power supply management module is used to manage the electrical energy output by the radio frequency energy harvesting module to power the wireless transceiver.

[0054] When a wireless signal needs to be transmitted, the internal control module sends the signal to the GFSK modulator for modulation. After amplification by the RF power amplifier, the signal is sent to the transceiver antenna for transmission. The transceiver antenna receives wireless signals from other transmitters; these signals are amplified by a low-noise amplifier and then sent to the GFSK demodulator for demodulation. The demodulated signal is then transmitted to the internal control module for processing. The RF energy harvesting module collects RF energy and converts it into electrical energy. The power management module manages the output electrical energy to power the wireless transceiver, enabling continuous operation. Through this operating mode, wireless signal transmission and reception can be achieved, and the RF energy harvesting module provides a continuous power supply to the wireless transceiver, thus enabling stable operation over extended periods.

[0055] In this implementation, to achieve radio frequency (RF) energy harvesting and power supply for the wireless transceiver, it is necessary to improve the efficiency of RF energy harvesting and increase the energy conversion rate, while simultaneously reducing the power consumption of the wireless transceiver to minimize energy waste. GFSK modulation and demodulation offer lower power consumption compared to other modulation techniques. This is because GFSK modulation uses a narrower bandwidth and shorter packet length, reducing overall power consumption during data transmission and reception. Furthermore, the simpler demodulation circuitry of GFSK modulation also contributes to reduced power consumption. Therefore, GFSK modulation and demodulation is a superior choice.

[0056] In this embodiment, the radio frequency energy harvesting module is equipped with an impedance matching unit, a single-ended to differential unit, and an AC boost unit at its radio frequency signal input terminal.

[0057] The impedance matching unit is connected to an external energy harvesting antenna to reduce input signal reflection;

[0058] The single-ended to differential unit connected to the impedance matching unit is used to convert radio signals into AC signals.

[0059] The AC boost unit is connected to a single-ended to differential unit to increase the input voltage.

[0060] In an RF energy harvesting module, the impedance matching circuit matches the resistance at the input port to the resistance at the output port to maximize energy transfer efficiency. It adjusts the impedance matching between the input and output to achieve the highest possible energy conversion efficiency, thereby maximizing the harvest of RF energy. The single-ended to differential converter converts the single-ended input RF signal into a differential output AC signal. RF signals are high-frequency AC signals, while differential output signals are two inverse AC signals. The advantages of this differential signal are stronger anti-interference capability, less noise, and improved circuit gain. This is particularly important for RF energy harvesting modules because it improves the reliability and stability of RF signal transmission within the circuit. Furthermore, single-ended input RF signals are not conducive to RF power amplification because they have a smaller amplitude; using differential output signals effectively solves this problem. Therefore, the single-ended to differential converter plays a crucial role in the RF energy harvesting module. The AC boost unit connected after the single-ended to differential converter boosts the converted differential signal. Radio frequency (RF) signals have very small amplitudes, requiring boosting to enhance signal strength and improve signal quality. The general function of an AC boost unit is to match the impedance of differential signals, increasing the signal amplitude to improve energy transmission efficiency. Furthermore, the AC boost unit can also correct the waveform of the RF signal and feed it back to the front-end circuitry for signal processing, thereby further improving the quality of the RF signal. Therefore, the AC boost unit is a crucial module in RF energy harvesting modules, enhancing the strength and quality of RF signals and further improving their transmission performance.

[0061] In this embodiment, the radio frequency energy harvesting module also includes a multi-stage rectifier and a limiting circuit;

[0062] Multiple multi-stage rectifiers are connected in series and then connected to the AC boost unit;

[0063] The output terminals of the AC boost unit and the output terminals of the multiple multi-stage rectifiers are all equipped with limiting circuits.

[0064] The multi-stage rectifier circuit is used to convert AC power into DC power and increase the output voltage.

[0065] In radio frequency (RF) energy harvesting modules, connecting multiple multi-stage rectifier circuits in series can improve the output DC voltage and energy conversion efficiency. Rectifier circuits have strong unidirectional conductivity; by rectifying and filtering the RF signal multiple times, the DC component of the RF signal can be separated from the original signal. Each rectifier circuit processes a different voltage, achieving a smooth rectified voltage. When multiple rectifier circuits are connected in series, the overall voltage value gradually increases, thereby improving the output voltage and energy conversion efficiency of the entire circuit. Therefore, connecting multiple multi-stage rectifier circuits in series in an RF energy harvesting module can significantly improve the efficiency and stability of the entire circuit. Limiting circuits are typically used to protect the rectifier from damage caused by excessively high-amplitude RF signals and to control the signal amplitude range to ensure safe circuit operation.

[0066] In this implementation, the RF energy harvesting module incorporates multiple multi-stage rectifier circuits connected in series and parallel with limiting circuits to improve the overall circuit stability and output voltage quality. This is because in real-world operating environments, circuits are easily affected by noise and interference. These interference signals can cause instability in the output voltage of the rectifier circuits, thus affecting the normal operation of the wireless sensor nodes. In such cases, adding limiting circuits can limit the amplitude of the original signal and keep it within a safe range, preventing the input signal from negatively impacting the rectifier circuit output. Parallel limiting circuits are typically installed at the output of each multi-stage rectifier circuit to eliminate high-amplitude pulses caused by rectification, ensuring a smooth and stable output voltage. When multiple rectifier circuits are connected in series, the overall output voltage gradually increases, requiring limiting processing for each circuit to ensure a smooth and stable output voltage. Therefore, connecting multiple multi-stage rectifier circuits in series and parallel with limiting circuits ensures stable and reliable output voltage, improving the overall circuit efficiency and availability.

[0067] like Figure 3 As shown in this embodiment, the multi-stage rectifier is composed of multiple single-stage rectifier circuits connected in series;

[0068] The single-stage rectifier circuit is provided with a positive input terminal RFP, a negative input terminal RFN, a reference voltage input terminal VREF, and an output terminal VOUT, which are connected to the AC boost unit.

[0069] The output terminals of adjacent single-stage rectifier circuits are connected to the reference voltage input terminals.

[0070] During operation, the AC voltage is first boosted by an AC boost unit, and then rectified by a multi-stage rectifier to convert it into a DC voltage output. The output terminals of adjacent single-stage rectifier circuits are connected to a reference voltage input terminal, thus maintaining the stability of the DC voltage output by the entire multi-stage rectifier.

[0071] The reference voltage in a single-stage rectifier circuit ensures that the positive half-wave output signal remains relatively stable within the positive output range throughout the entire positive half-cycle without excessive distortion. The reference voltage converts the negative value of the input signal into a positive value, forming a complete and stable output signal with the positive portion. Furthermore, the accuracy and stability of the reference voltage have a significant impact on the overall performance of the multi-stage rectifier circuit.

[0072] In this implementation example, a multi-stage rectifier circuit is used instead of a voltage doubler rectifier circuit because the voltage doubler rectifier circuit connects the secondary winding of a transformer to the input terminal of the rectifier circuit to increase the voltage for rectification. This circuit is simple and low-cost, but the output DC voltage fluctuates greatly and has poor stability. A multi-stage current-inducing circuit is a circuit composed of multiple rectifier circuits connected in series. Each rectifier circuit can convert a portion of the AC power into DC power. Through multi-stage rectification, the output DC voltage has better stability and less fluctuation.

[0073] In this embodiment, the single-stage rectifier circuit includes: a first NMOS transistor NM1, a second NMOS transistor NM2, a first PMOS transistor PM1, and a second PMOS transistor PM2;

[0074] The input terminal of the reference voltage is connected to the source of the first NMOS transistor NM1 and the second NMOS transistor NM2, respectively.

[0075] The positive input terminal is connected to the drain of the first NMOS and the first PMOS transistor PM1, and the gate of the second NMOS transistor NM2 and the second PMOS transistor PM2, respectively.

[0076] The negative input terminal is connected to the gate of the first NMOS transistor NM1 and the gate of the first PMOS transistor PM1, and the drain of the second NMOS transistor NM2 and the second PMOS transistor PM2, respectively.

[0077] The output terminals are respectively connected to the sources of the first PMOS transistor PM1 and the second PMOS transistor PM2.

[0078] In this configuration, the drain of the first NMOS transistor NM1 is connected to the drain of the first PMOS transistor PM1, and the gate of the first NMOS transistor NM1 is connected to the gate of the first PMOS transistor PM1.

[0079] The drain of the second NMOS transistor NM2 is connected to the drain of the second PMOS transistor PM2, and the gate of the second NMOS transistor NM2 is connected to the gate of the second PMOS transistor PM2.

[0080] Compared to common rectifier circuits composed of diodes, this single-stage rectifier circuit has the following advantages:

[0081] 1. High rectification efficiency: The single-stage rectifier circuit uses four transistors, which can effectively reduce the voltage drop and power loss of the circuit, and the rectification efficiency is significantly higher than that of the diode rectifier circuit.

[0082] 2. Fast dynamic response: The single-stage rectifier circuit has a very fast response speed and can quickly respond to the input voltage, making it suitable for applications of some high-speed electronic equipment.

[0083] 3. High rectification accuracy: In a single-stage rectifier circuit, because transistors are used for rectification, the rectification accuracy is higher than that of a diode rectifier circuit, which can effectively improve the accuracy and stability of the signal.

[0084] 4. Can operate at high frequencies: Since the single-stage rectifier circuit uses transistors for rectification, it can operate at a high frequency and can be used in some high-frequency equipment and circuits.

[0085] In this embodiment, the positive input terminal is provided with a first capacitor C1, and the negative input terminal is provided with a second capacitor C2. The first capacitor C1 and the second capacitor C2 are used to block DC and pass AC, effectively filtering interference signals and improving anti-interference capabilities.

[0086] A third capacitor C3 is connected in parallel to the input terminal of the reference voltage, and a fourth capacitor C4 is connected in parallel to the output terminal. The third capacitor C3 is used for filtering the input signal, and the fourth capacitor C4 is used for smoothing the output signal to make the DC voltage output by the rectifier circuit more stable.

[0087] In this single-stage rectifier circuit with a capacitor filter, in addition to four field-effect transistors, there are four capacitors used to filter the AC signals in the circuit.

[0088] In this single-stage rectifier circuit with a capacitor filter, in addition to four field-effect transistors, there are four capacitors used to filter the AC signals in the circuit.

[0089] The process and principle of a single-stage rectifier circuit are as follows:

[0090] 1. The reference voltage input terminal is connected to the source of the first NMOS transistor NM1 and the second NMOS transistor NM2. The reference voltage input terminal is the reference voltage for the entire circuit, and changes in the input voltage will affect the operating state of the entire circuit. Here, the reference voltage input terminal is first connected to the source of the first NMOS transistor NM1 and the second NMOS transistor NM2 to realize the input of the circuit's reference voltage.

[0091] 2. When a positive voltage is applied to the positive electrode, the first NMOS transistor NM1 and the second PMOS transistor PM2 are turned on, forming a path through which current can enter from the positive electrode, pass through these two transistors, and reach the output terminal. The negative input terminal is connected to the gates of the first NMOS and the first PMOS transistor PM1, and the drains of the second NMOS and the second PMOS transistor PM2 through the second capacitor C2. When a negative voltage is applied to the negative electrode, the second NMOS transistor NM2 and the first PMOS transistor PM1 are turned on, forming another path through which current can flow from the output terminal, pass through these two transistors, and reach the negative input terminal.

[0092] 3. The output terminal is connected to the sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 respectively. The output terminal is the output port of the circuit and the source of the circuit output signal. Here, the output terminal is connected to the sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 respectively, realizing the output of the circuit output signal.

[0093] 4. A third capacitor C3 is connected in parallel to the reference voltage input terminal, and a fourth capacitor C4 is connected in parallel to the output terminal. To improve the performance of the circuit, a third capacitor C3 is connected in parallel to the reference voltage input terminal, and a fourth capacitor C4 is connected in parallel to the output terminal. Capacitors are commonly used components in circuits, which have energy storage and filtering functions and can effectively improve the stability of the circuit and reduce signal interference.

[0094] When RFP > RFN, NM1 is cut off and PM1 is turned on, and C1 is charged through PM1; when RFP < RFN, NM2 is cut off and PM2 is turned on, and C4 is charged through PM0. Since PM0 and PM1 are unidirectional conduction, the input AC signal RFIN can be unidirectionally charged on C4 with an amplitude of VREF + VPP, and through the smoothing of C4, the input AC signal is finally rectified into DC and the energy storage is completed. The first capacitor C1 and the second capacitor C2 play the role of blocking direct current and passing alternating current in the circuit, effectively filtering out power frequency signals and improving the anti-interference performance of the circuit; the third capacitor C3 and the fourth capacitor C4 are respectively used for filtering the input signal and smoothing the output signal, making the DC voltage output by the rectifier circuit more stable.

[0095] As Figure 4 shown, in this embodiment, it further includes a passive crystal oscillator module and a clock synthesis module;

[0096] The passive crystal oscillator module is connected to the clock synthesis module and is used to provide a stable and high-precision clock signal;

[0097] The clock synthesis module is respectively connected to the up-conversion mixer and the down-conversion mixer. The down-conversion mixer is located between the GFSK demodulator and the low-noise amplifier, and the up-conversion mixer is located between the GFSK modulator and the radio frequency power amplifier.

[0098] The passive crystal oscillator module provides a stable, high-precision clock signal as input to the clock synthesis module. The clock synthesis module processes the input clock signal to generate two signals of different frequencies, which drive the up-conversion and down-conversion mixers. The up-conversion mixer mixes the GFSK-modulated signal with the high-frequency signal to obtain a high-frequency output signal, which drives the RF power amplifier to transmit it. The down-conversion mixer mixes the received signal with the low-frequency signal to obtain an intermediate frequency (IF) signal, which is then demodulated by a GFSK demodulator and amplified by a low-noise amplifier before finally outputting a digital signal. This process enables wireless transmission and reception of digital signals. The passive crystal oscillator module and the clock synthesis module ensure the system's clock synchronization and stability.

[0099] In this embodiment, the passive crystal oscillation module includes a crystal and a passive crystal oscillation driver, and the clock synthesis module includes a PLL phase-locked loop;

[0100] The passive crystal oscillation driver is composed of a third NMOS transistor NM3, a third PMOS transistor PM3, and a fourth PMOS transistor PM4.

[0101] One end of the crystal is connected to the gates of the third NMOS transistor NM3 and the third PMOS transistor PM3. The drains of the third NMOS transistor NM3 and the third PMOS transistor PM3 are connected to the other end of the crystal and the PLL phase-locked loop. The source of the third NMOS transistor NM3 is grounded. The source of the third PMOS transistor PM3 is connected to the drain of the fourth PMOS transistor PM4. The gate of the fourth PMOS transistor PM4 is connected to the bias voltage, and the source of the fourth PMOS transistor PM4 is connected to the input voltage.

[0102] Under the bias voltage, the fourth PMOS transistor PM4 turns on, and its source outputs a high-level signal to the gate of the third PMOS transistor PM3. Upon receiving the high-level signal, the gate of the third PMOS transistor PM3 turns on, and its drain outputs a low-level signal to the gate of the third NMOS transistor NM3. Upon receiving the low-level signal, the gate of the third NMOS transistor NM3 turns on, and its drain is grounded, causing the external crystal to discharge. The crystal charge flows to the drain of the third PMOS transistor PM3, causing PM3 to lose control and turn off. After the crystal discharges, without external interference, the crystal charge begins to accumulate and discharges in reverse, flowing to the drain of the third NMOS transistor NM3, causing NM3 to lose control and turn off. When the crystal charge accumulates to a certain level, the gate of the fourth PMOS transistor PM4 still maintains a high-level signal, and its source continues to output a high-level signal to the gate of the third PMOS transistor PM3. The entire cycle repeats from the second step. This forms a passive crystal oscillator.

[0103] This implementation also includes a Universal Bus Digital Interface (USBD), which connects the GFSK demodulator, GFSK modulator, internal control module, and external systems. The USBD is used for data transmission and exchange. USBD is a universal digital data transmission standard and hardware interface, primarily used to connect transceivers and peripheral devices to achieve data transmission and communication. In RF transceivers, USBD is typically used to control various parameters and configurations of the transceiver and connects to the internal control module in digital signal form. Through USBD, users can control and configure the transceiver, including selecting operating modes, setting center frequency, bandwidth, gain, and adjusting power. These parameter and configuration changes can be controlled by external microcontrollers, FPGAs, or other digital devices, or through the internal control module.

[0104] like Figure 5 As shown in this embodiment, a receive data buffer unit is provided between the GFSK demodulator and the general-purpose bus digital interface, and a transmit data buffer unit is provided between the GFSK modulator and the general-purpose bus digital interface.

[0105] The data to be sent enters the transmit data buffer unit, where CRC check encoding is performed, and a transmit data frame is synthesized. The bitstream is then output to GFSK modulation and transmitted. The received data is GFSK demodulated, the data frame is extracted, CRC check is performed, and the received data is input into the receive data buffer unit.

[0106] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A wireless transceiver for energy harvesting GFSK modulation and demodulation, characterized in that, It includes a GFSK demodulator, a GFSK modulator, a power management module, an internal control module, an RF energy harvesting module, a passive crystal oscillator module, and a clock synthesis module; The GFSK demodulator is connected to the transceiver antenna via a low-noise amplifier, and the GFSK modulator is connected to the transceiver antenna via an RF power amplifier. The internal control module is connected to a GFSK demodulator and a GFSK modulator. The GFSK demodulator is used to demodulate the received wireless signal, and the GFSK modulator is used to modulate the transmitted wireless signal. The passive crystal oscillator module is connected to the clock synthesis module to provide a stable, high-precision clock signal. The clock synthesis module is connected to the upconversion mixer and the downconversion mixer respectively. The downconversion mixer is located between the GFSK demodulator and the low-noise amplifier, and the upconversion mixer is located between the GFSK modulator and the RF power amplifier. The radio frequency energy harvesting module is connected to the power supply management module. The radio frequency energy harvesting module collects radio frequency energy through the energy harvesting antenna and converts it into electrical energy. The power supply management module is used to manage the electrical energy output by the radio frequency energy harvesting module to power the wireless transceiver.

2. The energy harvesting GFSK modulation and demodulation wireless transceiver according to claim 1, characterized in that, The radio frequency energy harvesting module is equipped with an impedance matching unit, a single-ended to differential unit, and an AC boost unit at its radio frequency signal input terminal. The impedance matching unit is connected to an external energy harvesting antenna to reduce input signal reflection; The single-ended to differential unit connected to the impedance matching unit is used to convert radio signals into AC signals. The AC boost unit is connected to a single-ended to differential unit to increase the input voltage.

3. The energy harvesting GFSK modulation and demodulation wireless transceiver according to claim 2, characterized in that, The radio frequency energy harvesting module also includes a multi-stage rectifier and a limiting circuit; Multiple multi-stage rectifiers are connected in series and then connected to the AC boost unit; The output terminals of the AC boost unit and the output terminals of the multiple multi-stage rectifiers are all equipped with limiting circuits. The multi-stage rectifier is used to convert AC power into DC power and increase the output voltage.

4. The energy harvesting GFSK modulation and demodulation wireless transceiver according to claim 3, characterized in that, The multi-stage rectifier is composed of multiple single-stage rectifier circuits connected in series. The single-stage rectifier circuit is provided with a positive input terminal, a negative input terminal, a reference voltage input terminal, and an output terminal connected to the AC boost unit; The output terminals of adjacent single-stage rectifier circuits are connected to the reference voltage input terminals.

5. The energy harvesting GFSK modulated wireless transceiver according to claim 4, characterized in that, The single-stage rectifier circuit includes: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; The input terminal of the reference voltage is connected to the source of the first NMOS transistor and the second NMOS transistor, respectively. The positive input terminal is connected to the drain of the first NMOS and the first PMOS transistor, and the gate of the second NMOS and the second PMOS transistor, respectively. The negative input terminal is connected to the gate of the first NMOS transistor and the gate of the first PMOS transistor, and the drain of the second NMOS transistor and the second PMOS transistor, respectively. The output terminals are respectively connected to the sources of the first PMOS transistor and the second PMOS transistor; In this configuration, the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, and the gate of the first NMOS transistor is connected to the gate of the first PMOS transistor. The drain of the second NMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the second NMOS transistor is connected to the gate of the second PMOS transistor.

6. The energy harvesting GFSK modulated wireless transceiver according to claim 5, characterized in that, The positive input terminal is provided with a first capacitor, and the negative input terminal is provided with a second capacitor. The first capacitor and the second capacitor are used to block DC and pass AC, effectively filtering interference signals and improving anti-interference capabilities. A third capacitor is connected in parallel to the input terminal of the reference voltage, and a fourth capacitor is connected in parallel to the output terminal. The third capacitor is used for filtering the input signal, and the fourth capacitor is used for smoothing the output signal to make the DC voltage output by the rectifier circuit more stable.

7. The energy harvesting GFSK modulation and demodulation wireless transceiver according to claim 1, characterized in that, The passive crystal oscillation module includes a crystal and a passive crystal oscillation driver, and the clock synthesis module includes a PLL phase-locked loop; The passive crystal oscillation drive consists of a third NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; One end of the crystal is connected to the gates of the third NMOS transistor and the third PMOS transistor. The drains of the third NMOS transistor and the third PMOS transistor are connected to the other end of the crystal and the PLL phase-locked loop. The source of the third NMOS transistor is grounded. The source of the third PMOS transistor is connected to the drain of the fourth PMOS transistor. The gate of the fourth PMOS transistor is connected to the bias voltage. The source of the fourth PMOS transistor is connected to the input voltage.

8. The energy harvesting GFSK modulation and demodulation wireless transceiver according to claim 1, characterized in that, It also includes a universal bus digital interface, which connects the GFSK demodulator, GFSK modulator, internal control module and external system, and is used for data transmission and exchange.

9. The energy harvesting GFSK modulation and demodulation wireless transceiver according to claim 8, characterized in that, A receive data buffer unit is provided between the GFSK demodulator and the general-purpose bus digital interface, and a transmit data buffer unit is provided between the GFSK modulator and the general-purpose bus digital interface.

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