Method of manufacturing large-size reconstituted wafer, large-size reconstituted wafer and bonded structure

Abstract

The application belongs to the technical field of semiconductor device processing and manufacturing, and relates to a manufacturing method of a large-size reconstructed wafer, the large-size reconstructed wafer and a bonding structure. The manufacturing method of the large-size reconstructed wafer comprises the following steps: providing a first wafer, cutting the first wafer into a plurality of sub-pieces in the thickness direction; providing a second wafer with a larger size, bonding the plurality of sub-pieces on the surface of a release layer of the second wafer, thinning the sub-pieces to form a target-thickness film layer, and performing planarization treatment on the film layer to ensure the whole-surface flatness; providing a third wafer with a size greater than or equal to that of the second wafer, bonding one side of the film layer of the second wafer with the third wafer; and separating the sub-pieces from the release layer through release treatment and transferring the sub-pieces to the third wafer to finally obtain a high-quality large-size reconstructed wafer. The obtained large-size reconstructed wafer has a performance equivalent to that of a whole-bonding wafer and can be directly used for re-packaging bonding with a single device or a whole wafer.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device processing and manufacturing technology, specifically relating to a method for manufacturing a large-size reconstructed wafer, a large-size reconstructed wafer obtained by the method, and a bonding structure containing the reconstructed wafer. Background Technology

[0002] Currently, the global semiconductor industry has entered a stage of large-scale development, with large-size wafers becoming the mainstream trend due to their higher integration and lower unit manufacturing costs. Limited by the intrinsic properties of materials, silicon, silicon oxide, and silicon photonics can be used to fabricate large-size wafers such as 12 inches; however, compound semiconductor materials such as lithium niobate, indium phosphide, and gallium arsenide are difficult to fabricate into large-size single crystals, resulting in limited size of composite wafers based on these materials, which cannot meet the demand for larger wafers. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention aims to provide a method for manufacturing large-size reconstructed wafers, thereby achieving the fabrication of such wafers. The large-size reconstructed wafers obtained by this invention possess performance comparable to solid-state bonded wafers, with a film surface roughness Ra < 0.5 nm and a reconstructed wafer surface coplanarity < 10 nm. They can be directly used for repackaging and bonding with individual devices or entire wafers; furthermore, the functional layers such as the insulating layer beneath the film remain undamaged, ensuring the usability of the reconstructed wafer.

[0004] To achieve this objective, the present invention adopts the following technical solution:

[0005] A method for manufacturing a large-size reconstructed wafer includes: providing a first wafer having a first size, and cutting the first wafer into multiple sub-wafers along the thickness direction;

[0006] A second wafer is provided, the second wafer having a second size, the second size being larger than the first size; the second wafer includes a release layer having the property of allowing the sub-wafers bonded thereto to detach upon release treatment;

[0007] The plurality of said sub-pieces are bonded to the surface of the release layer of the second wafer;

[0008] The multiple sub-sheets are thinned to the target thickness to form a film layer;

[0009] The film layer is planarized to make the entire surface of the film layer flat.

[0010] A third wafer is provided, the third wafer having a third dimension, the third dimension being greater than or equal to the second dimension;

[0011] The film layer of the second wafer is bonded to the third wafer;

[0012] A release process is performed to detach multiple sub-wafers from the release layer and transfer them to the third wafer, thereby obtaining a large-size reconstructed wafer.

[0013] Preferably, the release process includes exposing the release layer to a non-room temperature environment.

[0014] Preferably, the surface of the release layer is acid-processed to form ion flow channels;

[0015] The release layer contains an ion implantation layer.

[0016] Preferably, the release layer comprises a silicon oxide material layer.

[0017] Preferably, the acid processing includes treating the surface of the release layer with hydrofluoric acid.

[0018] Preferably, the release layer is a thermal stress relief layer;

[0019] The thermal stress relief layer includes a first sub-layer and a second sub-layer. The first sub-layer and the second sub-layer have different coefficients of thermal expansion, and the shear force generated by the difference in thermal expansion coefficients causes the interface to separate.

[0020] Preferably, the release layer is a pyrolytic material layer, which undergoes a thermal decomposition reaction through heat treatment to separate the interfaces.

[0021] Preferably, the pyrolysis material layer is an organic material layer or an inorganic material layer. The organic material layer includes polyimide, polyhydroxy ether, or temporary bonding adhesive, etc., and the inorganic material layer includes SiO2, Ge, Ti, W, Al, TiN, TaN, WN (tungsten nitride), etc.

[0022] Preferably, the heat treatment package increases the ambient temperature or the interface energy, and the increase in interface energy includes laser ablation of the pyrolysis material layer.

[0023] Preferably, the release layer is a low-temperature embrittlement material layer, which is separated at the interface by low-temperature catalysis.

[0024] Preferably, the thinning includes mechanical thinning and / or chemimechanical thinning.

[0025] Preferably, the planarization process includes superatom beam trimming.

[0026] Preferably, the plurality of said sub-wafers are arranged closely together or spaced apart on the surface of the third wafer;

[0027] In the tightly packed arrangement, the interval between adjacent sub-pieces is <50μm;

[0028] The spacing between adjacent sub-pieces in the spacing arrangement is ≥50μm.

[0029] Preferably, after providing the first wafer, a release layer is first prepared on the surface of the first wafer, and then the first wafer is cut into multiple sub-wafers;

[0030] And bonding the release layer side of the plurality of said sub-wafers to the release layer surface of the second wafer.

[0031] Preferably, after the multiple sub-wafers are detached from the release layer and transferred to the third wafer, the residual release layer on the surface of the multiple sub-wafers is removed to obtain a large-size reconstructed wafer.

[0032] Preferably, the film layers are planarized to make the surface roughness Ra of each film layer < 0.5 nm.

[0033] Preferably, after obtaining the large-size reconstructed wafer, the surface of the large-size reconstructed wafer is planarized to make the coplanarity of the large-size reconstructed wafer surface <10nm, for example, 0.5nm, 1nm, 2nm, 5nm, 8nm.

[0034] Preferably, the first wafer comprises a compound semiconductor wafer, or comprises a compound semiconductor layer;

[0035] The compound semiconductor is selected from one or more of lithium niobate, lithium tantalate, indium phosphide, gallium arsenide, gallium antimony, gallium nitride, and silicon carbide.

[0036] Preferably, the non-room temperature environment includes temperatures below 15°C or above 25°C, such as -150°C, -100°C, -50°C, -20°C, or 50°C, 100°C, 200°C, 400°C, 600°C, 1000°C, 1300°C, etc.

[0037] Preferably, the target thickness of the film layer is 50nm-10μm, such as 100nm, 300nm, 500nm, 700nm, 1μm, 3μm, 7μm, or 10μm.

[0038] A large-size reconstructed wafer is fabricated by the method described above.

[0039] A bonding structure includes a structure to be bonded, wherein the bonding surface of the structure to be bonded is bonded to a large-size reconstructed wafer fabricated by the manufacturing method described above, or is bonded to a large-size reconstructed wafer as described above.

[0040] The structure to be bonded includes a chip, a wafer, or a semiconductor device;

[0041] The semiconductor device includes a laser, a detector, a modulator, a resonator, a filter, or a sensor.

[0042] The beneficial effects of this invention are:

[0043] This invention provides a method for manufacturing large-size reconstructed wafers, which reconstructs large-size wafers from small-size sub-wafers, overcoming the intrinsic material limitation of compound semiconductors in fabricating large-size single crystals. Wafer reconstruction is achieved through temporary bonding and debonding of release layers, employing superatom beam trimming technology to avoid lattice damage while maintaining nanoscale flatness, thus ensuring crystal quality. The resulting large-size reconstructed wafer exhibits performance comparable to integrally bonded wafers, with no damage to functional layers, a film surface roughness Ra < 0.5 nm, surface coplanarity < 10 nm, and excellent thickness uniformity. It can be directly used for repackaging and bonding with individual devices or entire wafers. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the manufacturing process of the large-size reconstructed wafer of the present invention;

[0045] In the diagram: 1: First wafer; 11: Sub-wafer; 2: Second wafer; 21: Release layer; 3: Third wafer; 31: Functional layer. Detailed Implementation

[0046] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it.

[0047] like Figure 1 As shown, the large-size reconstructed wafer manufacturing method provided in this embodiment mainly includes the following steps: providing a first wafer 1 and cutting it into multiple sub-wafers 11; providing a second wafer 2 with a release layer 21; bonding the sub-wafers 11 to the second wafer 2; thinning the sub-wafers 11 to form a film layer and performing planarization treatment; providing a third wafer 3 and bonding the film layer side to the third wafer 3; performing a release treatment to transfer the sub-wafers 11 to the third wafer 3 to obtain a large-size reconstructed wafer.

[0048] The method of this embodiment first provides a first wafer 1, which has a first size. The first wafer 1 includes a compound semiconductor wafer, or includes a compound semiconductor layer. The compound semiconductor is selected from one or more of lithium niobate, lithium tantalate, indium phosphide, gallium antimony, gallium arsenide, gallium nitride, and silicon carbide. Because these compound semiconductor materials are limited by their intrinsic properties, it is difficult to achieve high-quality, large-size wafer fabrication. Therefore, the method of this embodiment is needed to achieve large-size reconstruction.

[0049] The first wafer 1 is cut into multiple sub-wafers 11 along its thickness direction. The cutting method can be conventional cutting techniques in the art, such as laser cutting, diamond wheel cutting, or stealth cutting. The size of the sub-wafers 11 after cutting is determined according to the size and arrangement of the second wafer 2 to ensure that the multiple sub-wafers 11 can be completely arranged on the surface of the second wafer 2.

[0050] A second wafer 2 is provided, the second wafer 2 having a second size, the second size being larger than the first size. Preferably, the second wafer 2 is made of a material with good mechanical strength and thermal stability, such as silicon wafer, quartz wafer, or sapphire wafer. The second size is typically 12 inches or larger to meet the fabrication requirements of large-size reconstruction wafers.

[0051] The second wafer 2 includes a release layer 21, which has the property of allowing the sub-wafers 11 bonded thereto to detach after a release treatment. According to different embodiments of the present invention, the release layer 21 can be of various types:

[0052] In a preferred embodiment, the release layer 21 contains an ion implantation layer, and the surface of the release layer 21 is acid-processed to form ion flow channels. Specifically, the release layer 21 includes a silicon oxide material layer, which can be formed on the surface of the second wafer 2 by methods such as thermal oxidation, chemical vapor deposition (CVD) or physical vapor deposition (PVD), and has a thickness ranging from 100 nm to 2 μm.

[0053] The ion-implanted layer is formed by ion implantation into a silicon oxide layer. The implanted ions can be selected from hydrogen ions (H+). + Helium ions (He) + Alternatively, hydrogen-helium co-injection can be used, with an injection energy range of 1 keV to 80 keV and an injection dose range of 1 × 10¹. 3 ions / cm² to 1×10¹ 6 The implantation depth is controlled at 1 / 2 to above the thickness of the silicon oxide layer to form an ion-rich defect layer inside the silicon oxide layer.

[0054] The acid processing includes treating the surface of the release layer with hydrofluoric acid. Specifically, the process involves immersing a silicon oxide layer with an ion-implanted layer in a 0.1% to 30% aqueous solution of hydrofluoric acid for 1 to 100 seconds at a temperature of 10°C to 50°C. The hydrofluoric acid reacts with the silicon oxide, disrupting the ring structure formed by silicon-oxygen bonds and creating channels within the oxide layer that allow ions to flow. These channels are nanoscale microporous structures, providing pathways for the release of ions during subsequent release treatments.

[0055] In another embodiment, the release layer 21 is a thermal stress relief layer. The thermal stress relief layer includes a first sub-layer and a second sub-layer, the first sub-layer and the second sub-layer having different coefficients of thermal expansion, and the shear force generated by the difference in thermal expansion coefficients causes the interface to separate.

[0056] Specifically, the first sublayer can be a silicon oxide layer with a thickness of 50 nm to 500 nm and a coefficient of thermal expansion of approximately 0.5 × 10⁻⁶. -6 / ℃; the second sublayer can be a silicon nitride layer or a metal layer (such as an aluminum layer or a copper layer), with a thickness of 50nm to 500nm and a coefficient of thermal expansion of approximately 2.3×10⁻⁶. -6 / ℃ (silicon nitride) or 23×10 -6 / ℃ (aluminum). Two layers of material are sequentially deposited on the surface of a second wafer 2 using methods such as PECVD, sputtering, or evaporation. When the temperature changes, shear stress is generated at the interface between the two layers due to the difference in thermal expansion coefficients. When the stress exceeds the interfacial bonding strength, the interface separates.

[0057] In another embodiment, the release layer 21 is a pyrolysis material layer. The pyrolysis material layer is formed by methods such as spin coating, spraying, or deposition, and has a thickness of 100 nm to 5 μm. The pyrolysis material layer can be an organic material layer or an inorganic material layer. The organic material layer includes polyimide, polyhydroxy ether, or temporary bonding adhesive, while the inorganic material layer includes SiO2, Ge, Ti, W, Al, TiN, TaN, WN (tungsten nitride), etc. When an organic material is selected as the pyrolysis material layer, thermal decomposition can be achieved by increasing the ambient temperature, such as heat treatment at 200°C to 400°C, thereby separating the interface. When an inorganic material is selected as the pyrolysis material layer, interface separation can be achieved by laser ablation.

[0058] In another embodiment, the release layer 21 is a low-temperature embrittlement material layer. Materials such as modified epoxy resin and polystyrene can be selected. These materials are solid at room temperature and can provide good support. They undergo a brittle transition at low temperatures. When the temperature drops to the transition temperature, such as below -50°C, the material becomes embrittled, the interfacial bonding strength is significantly reduced, and it is easy to separate under external force.

[0059] The plurality of sub-pieces 11 are bonded to the surface of the release layer 21 of the second wafer 2. The bonding method can be direct bonding, including hydrophilic bonding, room temperature bonding, or adhesive bonding. For embodiments using ion implantation-type release layers, hydrophilic bonding is preferred.

[0060] Prior to hydrophilic bonding, the bonding surfaces of sub-wafer 11 and / or the second wafer 2 are subjected to standard cleaning (RCA cleaning or ozone water treatment) to hydroxylate the surfaces and form hydrophilic surfaces. Bonding is performed at room temperature, with appropriate pressure applied (typically 0.1 MPa to 10 MPa) to ensure close contact between the two surfaces, achieving initial bonding through intermolecular forces. Subsequently, a low-temperature annealing at around 200°C can be performed to enhance the bonding strength. This temperature is insufficient to precipitate ion-implanted elements and will not cause interface separation.

[0061] The plurality of sub-sheets 11 are thinned to a target thickness to form a film layer. The thinning process includes mechanical thinning, chemical mechanical thinning, or a combination of mechanical thinning and chemical mechanical thinning.

[0062] Specifically, the thickness of sub-sheet 11 was first reduced from an initial thickness of 350 μm to approximately 10 μm to 50 μm, close to the target thickness, using mechanical polishing. Diamond polishing slurry was used, with the polishing pressure controlled between 10 kPa and 100 kPa and the polishing speed between 100 rpm and 1000 rpm. Subsequently, chemical mechanical polishing (CMP) was used for further thinning, with either alkaline silica gel polishing slurry (pH 9-11) or acidic alumina polishing slurry (pH 2-4) used, and the polishing pressure between 1 kPa and 20 kPa, until the target thickness was achieved.

[0063] The target thickness of the film is 50 nm to 10 μm, depending on the specific application requirements.

[0064] The film layer is planarized to make its entire surface flat. The planarization process includes superatom beam trimming.

[0065] The superatomic beam trimming employs superatomic beam polishing technology. Superatoms are nanoscale particles composed of hundreds to thousands of gas molecules / atoms (such as Ar, He, Kr, NF3, etc.) bound together by van der Waals forces. In ionization collisions and electromagnetic field motion, they can be considered as a single "atom," with a mass and collision cross-section several to thousands of times greater than that of a single atom. The gas source can be argon, helium, or xenon, with argon being preferred.

[0066] The superatomic beam is generated as follows: a working gas is introduced into an ion source, and the gas is ionized by electron bombardment or radio frequency discharge to form plasma; in the plasma, ions and neutral atoms / molecules combine through van der Waals forces to form superatoms; small-mass superatoms and monatomic ions that do not meet the standards are removed by magnetic sieving, so that the proportion of superatoms is >90%, and a single superatom is composed of ≥50 basic particles (atoms and / or molecules).

[0067] When a superatom beam bombards a material surface, it produces a lateral sputtering effect and a localized thermal annealing effect, as well as localized pulsed high temperatures. The process is gentle and does not cause overall damage to the substrate and / or film layers. During the trimming process, the superatom beam energy is controlled between 1 keV and 50 keV, the beam current density is between 1 μA / cm² and 100 μA / cm², and the processing time is between 1 minute and 60 minutes.

[0068] After superatom beam trimming, the surface roughness Ra of the film is <0.5 nm, and the surface coplanarity is <1 nm. The film lattice is undamaged and does not affect the performance of subsequent fabricated devices.

[0069] A third wafer 3 is provided, the third wafer 3 having a third dimension, the third dimension being greater than or equal to the second dimension. The third wafer 3 serves as the final carrier wafer, typically a silicon wafer, and its size is the same as or larger than that of the second wafer to ensure complete support of the transferred film layer. Preferably, the third wafer 3 is a silicon wafer with a surface oxide layer, the surface oxide layer serving as a functional layer 31 that provides insulation.

[0070] The film layer side of the second wafer 2 is bonded to the third wafer 3.

[0071] A release process is performed to detach the plurality of sub-wafers 11 from the release layer 21 and transfer them to the third wafer 3, thereby obtaining a large-size reconstructed wafer 3. The release process includes exposing the release layer to a non-room temperature environment, which includes temperatures below 15°C or above 25°C.

[0072] For ion-implanted release layers: Annealing is performed at a temperature of 400°C for 10 to 120 minutes. Under high temperature, hydrogen or helium ions in the ion-implanted layer gain sufficient energy to move between the silicon oxide lattice layers and precipitate at the temporary bonding interface through the channels formed by the previous acid treatment. Bubbles or cracks are formed at the interface, causing the two temporarily bonded silicon oxide layers to separate and the sub-wafer 11 film layer is transferred to the third wafer 3.

[0073] For the thermal stress relief layer: thermal cycling treatment is performed, with the temperature increasing from room temperature to 150°C to 300°C or decreasing to -50°C to -100°C, utilizing the shear force generated by the difference in thermal expansion coefficients to separate the interface.

[0074] For the pyrolysis material release layer: heat to the pyrolysis temperature of 200℃ to 600℃ to decompose the pyrolysis material and separate the interface, or separate the interface by laser ablation.

[0075] For the low-temperature embrittlement release layer: cool to -50°C to -150°C below the embrittlement temperature, embrittle the material, and then apply mechanical force to separate the interface.

[0076] Because the sub-chip 11 bonded to the third wafer 3 is small, the internal stress generated by its coefficient of thermal expansion after changes in ambient temperature is more easily released than that of the whole wafer, thus preventing fragmentation.

[0077] After the sub-wafer 11 is detached and transferred to the third wafer 3, residual release layer material may remain on the surface of multiple sub-wafers 11. This material can be removed by wet etching with hydrofluoric acid solution (concentration 0.1% to 10%), dry etching with CF4 / CHF3 plasma, or chemical mechanical polishing (CMP) or superatom beam finishing until the surface of the sub-wafer film is exposed.

[0078] After obtaining the large-size reconstructed wafer, the surface of the large-size reconstructed wafer is planarized to make the surface roughness Ra < 0.5 nm and the surface coplanarity < 1 nm. The planarization process uses superatom beam trimming. Because the size of the large-size reconstructed wafer is 12 inches or larger, it is difficult to achieve the expected whole-surface coplanarity using chemical mechanical polishing. However, superatom beam trimming can achieve whole-surface coplanarity trimming. The final large-size reconstructed wafer has performance comparable to that of a solid bonding wafer, with excellent thickness uniformity. It can be directly used for repackaging and bonding with single devices or the entire wafer, and the functional layers 31 such as the insulating layer below the film are undamaged, which can ensure the performance of the reconstructed wafer.

[0079] During the removal of the release layer and the planarization of the surface of the large-size reconstructed wafer, a protective layer needs to be covered on its surface to prevent damage to the functional layer 31 exposed in the middle of the sub-wafer 11 during the process. The protective layer is preferably a photoresist layer.

[0080] Multiple sub-wafers 11 can be arranged in a close-packed or spaced-out manner on the surface of the third wafer 3.

[0081] Close arrangement: The spacing between adjacent sub-chips 11 is <50μm, preferably less than 20μm, and more preferably less than 5μm. This arrangement is suitable for applications requiring large-area continuous film layers, such as large-area optoelectronic integrated devices. Spacing arrangement: The spacing between adjacent sub-chips 11 is ≥50μm, preferably 100μm to 10mm. This arrangement is suitable for applications requiring independent functional units, such as array sensors or discrete device integration. The spacing areas can be filled with insulating material or left empty, depending on subsequent process requirements.

[0082] In another embodiment, a release layer 21 is first prepared on the surface of the first wafer 1, and then the first wafer 1 is cut into a plurality of sub-wafers 11; then the release layer 21 sides of the plurality of sub-wafers 11 are bonded to the surface of the release layer 21 of the second wafer 2.

[0083] Specifically, a silicon oxide release layer 21 with a thickness of 100 nm to 1 μm is prepared on the surface of the first wafer 1 by thermal oxidation or CVD. Ion implantation and acid treatment are then performed to form ion flow channels, with process parameters identical to those of the release layer 21 on the second wafer 2. After dicing, the release layer 21 side of the sub-wafer 11 faces the release layer 21 side of the second wafer 2, forming a temporary bonding structure through hydrophilic bonding. The design of the release layers on both sides ensures more thorough interface separation during debonding, reducing residue.

[0084] After being transferred to the third wafer 3, the residual release layer 21 on the surface of the sub-wafer 11 is removed to obtain a large-size reconstructed wafer with a clean surface.

[0085] The present invention also provides a large-size reconstructed wafer, manufactured by any of the methods described above. The large-size reconstructed wafer has the same size as the third wafer, typically 12 inches or larger. The reconstructed wafer includes a third wafer and a plurality of sub-layer films transferred from a first wafer, the layers being composed of a compound semiconductor material selected from one or more of lithium niobate, lithium tantalate, indium phosphide, gallium antimonide, gallium arsenide, gallium nitride, and silicon carbide.

[0086] The surface roughness Ra of the film layer of the large-size reconstructed wafer is <0.5nm, the surface coplanarity is <10nm, preferably <5nm, more preferably <1nm, and the thickness uniformity is excellent. It can be directly used for repackaging and bonding with individual devices or the entire wafer. The film layer has good lattice integrity and is free from ion bombardment damage or thermal damage.

[0087] This invention also provides a bonding structure, including a structure to be bonded, wherein the bonding surface of the structure to be bonded is bonded to the aforementioned large-size reconstructed wafer.

[0088] The structure to be bonded includes a chip, a wafer, or a semiconductor device. The semiconductor device includes a laser, a detector, a modulator, a resonator, a filter, or a sensor.

[0089] The bonding method can be direct bonding, adhesive bonding, or metal eutectic bonding. Because the large-size reconstructed wafer of this invention has excellent flatness and surface quality, low bonding interface defect density, and high bonding strength, it can meet the requirements of high-reliability packaging.

[0090] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art will be able to make various obvious changes, readjustments, and substitutions without departing from the scope of protection of the present invention. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing large-size reconstructed wafers, characterized in that, include: A first wafer (1) is provided, the first wafer (1) comprising a compound semiconductor wafer, or comprising a compound semiconductor layer; the first wafer (1) has a first size, and the first wafer (1) is cut into a plurality of sub-wafers (11) along the thickness direction. A second wafer (2) is provided, the second wafer (2) having a second size, the second size being larger than the first size; the second wafer (2) includes a release layer (21) having the property of allowing the sub-chip (11) bonded thereto to detach upon release treatment; Multiple sub-pieces (11) are bonded to the surface of the release layer (21) of the second wafer (2); The multiple sub-sheets (11) are thinned to a target thickness to form a film layer, the target thickness being 50 nm-10 μm; The film layers are planarized, and the planarization process includes superatom beam trimming to make the surface roughness Ra of each film layer < 0.5 nm; A third wafer (3) is provided, the third wafer (3) having a third dimension, the third dimension being greater than or equal to the second dimension; The film layer side of the second wafer (2) is bonded to the third wafer (3); A release process is performed to detach multiple sub-pieces (11) from the release layer (21) and transfer them to the third wafer (3) to obtain a large-size reconstructed wafer. After obtaining the large-size reconstructed wafer, the surface of the large-size reconstructed wafer is planarized to make the surface coplanarity of the large-size reconstructed wafer <10nm.

2. The manufacturing method according to claim 1, characterized in that, The release process includes placing the release layer (21) in a non-room temperature environment, which includes below 15°C or above 25°C.

3. The manufacturing method according to claim 1, characterized in that, The release layer (21) contains an ion implantation layer, and the surface of the release layer (21) is acid-processed to form ion flow channels.

4. The manufacturing method according to claim 3, characterized in that, The release layer (21) includes a silicon oxide material layer.

5. The manufacturing method according to claim 3, characterized in that, The acid processing includes treating the surface of the release layer (21) with hydrofluoric acid.

6. The manufacturing method according to claim 1, characterized in that, The release layer (21) is a thermal stress relief layer (21); The thermal stress relief layer (21) includes a first sublayer and a second sublayer, the first sublayer and the second sublayer having different coefficients of thermal expansion, and the shear force generated by the difference in thermal expansion coefficients causes the interface to separate.

7. The manufacturing method according to claim 1, characterized in that, The release layer (21) is a pyrolysis material layer, which undergoes thermal decomposition reaction through heat treatment to separate the interface.

8. The manufacturing method according to claim 1, characterized in that, The release layer (21) is a low-temperature embrittlement material layer, which separates the interface through low-temperature embrittlement.

9. The manufacturing method according to claim 1, characterized in that, The thinning includes mechanical thinning and / or chemical mechanical thinning.

10. The manufacturing method according to claim 1, characterized in that, Multiple sub-wafers (11) are arranged closely or spaced apart on the surface of the third wafer (3); In the close arrangement, the interval between adjacent sub-pieces (11) is <50μm; The spacing between adjacent sub-pieces (11) in the spacing arrangement is ≥50μm.

11. The manufacturing method according to claim 1, characterized in that, Also includes: After providing the first wafer (1), a release layer (21) is first prepared on the surface of the first wafer (1), and then the first wafer (1) is cut into multiple sub-wafers (11). And side-bonding the release layer (21) of the plurality of said sub-pieces (11) to the surface of the release layer (21) of the second wafer (2).

12. The manufacturing method according to claim 11, characterized in that, Also includes: After the multiple sub-pieces (11) are detached from the release layer (21) and transferred to the third wafer (3), the remaining release layer (21) on the surface of the multiple sub-pieces (11) is removed to obtain a large-size reconstructed wafer.

13. The manufacturing method according to claim 1, characterized in that, The compound semiconductor is selected from one or more of lithium niobate, lithium tantalate, indium phosphide, gallium arsenide, gallium antimony, gallium nitride, and silicon carbide.

14. A large-size reconstructed wafer, characterized in that, It is prepared by the manufacturing method according to any one of claims 1-13.

15. A bonding structure, characterized in that, Includes a structure to be bonded, wherein the bonding surface of the structure to be bonded is bonded to a large-size reconstructed wafer prepared by the manufacturing method according to any one of claims 1-13, or bonded to a large-size reconstructed wafer according to claim 14; The structure to be bonded includes a chip, a wafer, or a semiconductor device; The semiconductor device includes a laser, a detector, a modulator, a resonator, a filter, or a sensor.

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