Intelligent electric meter high-precision metering method for two-way settlement and intelligent electric meter

Abstract

The invention discloses an intelligent electric meter high-precision metering method for bidirectional settlement and an intelligent electric meter, and relates to the technical field of electric energy metering, and the method comprises the steps: carrying out the digital / analog heterogeneous shunting of a broadband bidirectional analog electric signal, and obtaining a smooth fundamental wave envelope sequence and a physical jump edge pulse string; determining the width of a shielding window according to the smooth fundamental wave envelope sequence, and performing hardware screening on the physical jump edge pulse string to determine a real physical timestamp; according to a real physical timestamp and a group delay constant, a hardware delay timer is controlled through an event system, and a direct memory access controller is triggered at a delimited moment to capture an active integral snapshot and clear the active integral snapshot; controlling corresponding data to be written into a conventional metering register area or a pollution energy isolation register area according to a difference result of the active integral snapshot and the broadband integral snapshot; according to the scheme, the two-way metering boundary judgment accuracy and the metering stability are improved.

Description

Technical Field

[0001] This invention relates to the field of electricity metering technology, specifically to a high-precision metering method for smart meters and a smart meter for two-way settlement. Background Technology

[0002] Primarily used in residential, industrial and commercial, and substation-level microgrids for grid-connected metering nodes, especially in scenarios involving residential distributed photovoltaic, residential energy storage, charging facilities, and their parallel operation with public low-voltage distribution networks. Bidirectional billing smart meters are typically installed near the main power switch to record purchased electricity, sold electricity, and grid connection power flow status. With the large-scale integration of inverters, bidirectional converters, and charging equipment, the metering object is no longer a single steady-state power frequency quantity, but often accompanied by harmonics, fluctuations, and direction switching. In residential microgrids and photovoltaic-energy storage-charging scenarios, in addition to basic electricity metering, the meter also needs to provide continuous metering data for settlement and operation management. Current mainstream solutions typically rely on voltage sampling, current sampling, analog-to-digital conversion, and microcontroller processing to complete energy metering, and use timing processing to achieve metering sequence control.

[0003] Chinese patent document CN111239482A discloses an electricity metering system and its implementation method. The system disclosed in this document includes a power supply module, a voltage detection module, a current detection module, two 24-bit analog-to-digital converter modules, and a microcontroller processing unit. Voltage and current signals are respectively sent to their corresponding analog-to-digital converter modules to form digital sequences. Subsequently, the system sets large hardware and software filtering time constants to remove zero drift and DC drift caused by factors such as preamplifier temperature drift and analog-to-digital conversion truncation errors. The filtered sequence is then stored in a buffer. In terms of timing processing, this document uses preset voltage and current zero-crossing point detection leads and combines timer capture and comparison functions to compensate for random delays caused by hardware filtering delays, sampling intervals, and program execution time, thereby determining the frequency, phase, and zero-crossing time of the voltage and current.

[0004] The aforementioned existing technologies can acquire voltage, current, and phase information in conventional power frequency metering scenarios, but their processing chain is still based on the path of "sampling-digital filtering-software prediction or compensation-timing capture". When high-frequency harmonics, waveform distortion, and rapid bidirectional power flow switching occur at the grid connection point due to inverters or charging equipment, the large filtering time constant set to ensure amplitude stability will lead to more significant time lag. Zero-crossing prediction and random delay compensation rely on sampling sequences, buffered data, and program execution timing. In terms of mechanism, they respectively pursue amplitude purity and time edge adherence, which can easily lead to boundary inconsistencies under conditions of low power factor, harmonic superposition, and direction reversal. This inconsistency further propagates to the phase determination, power factor calculation, and integration start and end time determination processes, which may result in a mismatch between bidirectional active power statistics and actual power flow boundaries, and cause statistical offsets in purchased power, sold power, and grid connection point metering results at the moment of direction switching.

[0005] Therefore, how to accurately determine the measurement boundary while taking into account the coordination between filtering delay, zero-crossing determination and timing compensation under broadband bidirectional electrical signal conditions containing high-frequency disturbances and direction switching has become a technical problem that needs to be solved in this field. Summary of the Invention

[0006] (a) Technical problems to be solved

[0007] To address the shortcomings of existing technologies, this invention provides a high-precision metering method and smart meter for bidirectional billing. The method involves hardware screening of the physical transition edge pulse train to determine the true physical timestamp. Then, based on the true physical timestamp and the group delay constant, an event system controls a hardware delay timer to trigger a direct memory access controller to capture and clear an active power integral snapshot at a boundary moment. Finally, based on the difference between the active power integral snapshot and the wideband integral snapshot, the corresponding data is written to either the conventional metering register or the pollution energy isolation register. This solution improves the accuracy and stability of bidirectional metering boundary determination and resolves the technical problems described in the background art.

[0008] (II) Technical Solution

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] A high-precision metering method for smart meters oriented towards bidirectional settlement includes metering a wideband bidirectional analog electrical signal based on the smart meter, including: implementing digital / analog heterogeneous splitting of the wideband bidirectional analog electrical signal on the microcontroller pin side, so that the main calculation channel outputs a smooth fundamental envelope sequence and the physical auxiliary channel outputs a physical transition edge pulse train;

[0011] The shielding window width is determined based on the smoothed fundamental envelope sequence, and the physical transition pulse train is screened by hardware to determine the real physical timestamp. Based on the real physical timestamp and the group delay constant, the hardware delay timer is controlled by the event system, and the direct memory access controller is triggered to capture and clear the active power integral snapshot at the boundary time.

[0012] Based on the difference between the active power integral snapshot and the broadband integral snapshot, the corresponding data is written into the conventional metering register or the pollution energy isolation register, respectively.

[0013] Furthermore, the digital / analog heterogeneous splitting includes: feeding the first link of the broadband bidirectional analog electrical signal into an analog-to-digital converter and a high-order IIR low-pass filter path to form a smooth fundamental envelope sequence, and directly feeding the second link of the same broadband bidirectional analog electrical signal into an analog comparator to form a physical transition edge pulse train.

[0014] Furthermore, the physical transition edge pulse train is obtained by polarity reversal detection using an analog comparator with a zero potential reference, and the smoothed fundamental envelope sequence is obtained by filtering the fundamental component in the broadband bidirectional analog electrical signal using a high-order IIR low-pass filter path. Moreover, the smoothed fundamental envelope sequence and the physical transition edge pulse train originate from the same broadband bidirectional analog electrical signal.

[0015] Furthermore, determining the shielding window width based on the smoothed fundamental envelope sequence includes: determining the power flow steepness based on adjacent sampled values ​​of the smoothed fundamental envelope sequence, generating the shielding window width for the current period based on the power flow steepness, and then writing the shielding window width into the event router to limit the allowance range along the physical transition pulse train.

[0016] Furthermore, hardware screening is performed on the physical transition edge pulse train to determine the true physical timestamp. This includes: using the coarse positioning time determined by the smoothed fundamental envelope sequence as the window center, only candidate transition edges falling within the interval corresponding to the width of the shielding window are allowed to pass, and the time corresponding to the first candidate transition edge allowed in the same period is latched as the true physical timestamp. Based on the true physical timestamp and the group delay constant, the event system controls the hardware delay timer, including: the event system receives the edge event corresponding to the true physical timestamp, starts the hardware delay timer, and converts the group delay constant into the waiting threshold of the hardware delay timer to generate the delimiting time.

[0017] Furthermore, at the boundary moment, the direct memory access controller is triggered to capture and clear the active integral snapshot, including: first, latching the current integral value in the multiply-accumulate accumulator to form an active integral snapshot, then the direct memory access controller moves the active integral snapshot, and after moving it, the multiply-accumulate accumulator is cleared to establish the integration starting point of the next cycle.

[0018] Furthermore, the wideband integral snapshot and the active power integral snapshot are obtained using the same integration boundary, and the wideband integral snapshot is obtained by integrating the wideband power sample corresponding to the wideband bidirectional analog electrical signal by the wideband accompanying integral chain. The difference between the active power integral snapshot and the wideband integral snapshot is used to characterize the pollution energy that is distinguishable from the fundamental main metering result.

[0019] Furthermore, based on the difference between the active power integral snapshot and the wideband integral snapshot, the corresponding data is written into the conventional metering register or the pollution energy isolation register, respectively. This includes: generating a pollution hit flag based on the directional relationship between the difference and the active power integral snapshot, and controlling the target address of the direct memory access controller to switch between the conventional metering register and the pollution energy isolation register based on the pollution hit flag.

[0020] Furthermore, the corresponding data written to the pollution energy isolation register is obtained by displacement scaling of the difference result. The displacement level of the displacement scaling is determined according to the excess level of the difference result relative to the pollution threshold. The pollution threshold is jointly calibrated by no-load noise, quantization error and normal harmonic residue, and written to the configuration register during power-on initialization.

[0021] A smart meter for bidirectional billing includes a voltage sampling branch, a current sampling branch, and a microcontroller. The microcontroller contains an analog-to-digital converter, an analog comparator, an event system, a hardware delay timer, a direct memory access controller, a multiply-accumulate unit, a wideband adjoint integral chain, a conventional metering register, and a pollution energy isolation register. The analog-to-digital converter is connected to the voltage and current sampling branches to form the main calculation channel, which outputs a smoothed fundamental envelope sequence and forms an active power integral snapshot. The analog comparator is connected to the current sampling branch to form a physical auxiliary channel, which outputs a physical transition edge pulse train.

[0022] The microcontroller determines the width of the shielding window based on the smooth fundamental envelope sequence and performs hardware filtering on the physical transition pulse train to determine the true physical timestamp;

[0023] The event system controls the hardware delay timer based on the real physical timestamp and group delay constant. At the boundary moment, it triggers the direct memory access controller to capture the active power integral snapshot and clear it. The wideband accompanying integral chain forms a wideband integral snapshot. The direct memory access controller writes the corresponding data into the conventional metering register or the pollution energy isolation register based on the difference between the active power integral snapshot and the wideband integral snapshot.

[0024] (III) Beneficial Effects

[0025] This invention provides a high-precision metering method and a smart meter for two-way settlement, which have the following advantages:

[0026] By performing digital / analog heterogeneous splitting on the broadband bidirectional analog electrical signal at the microcontroller pin side, the smooth fundamental envelope sequence of the main channel output is calculated, while the physical auxiliary channel retains the physical transition edge pulse train. This approach balances fundamental wave purification and phase boundary checks at the source, avoiding processing conflicts caused by simultaneous filtering and zero-crossing determination on a single path. It also provides input for subsequent shielding window generation and boundary control. The shielding window width and physical transition edge pulse train hardware screening are determined based on the smoothed fundamental envelope sequence. This suppresses false flips when high-frequency disturbances are introduced by distributed photovoltaic, energy storage grid connection, and vehicle-to-grid interaction, ensuring that subsequent links obtain a single, reliable, and true physical timestamp, reducing redundant software discrimination.

[0027] By mapping the real physical timestamp and group delay constant in the event system and hardware delay timer, and starting the direct memory access controller at the boundary moment to capture and clear the active integral snapshot, the delayed smooth fundamental envelope sequence is aligned with the physical zero-crossing boundary, avoiding historical sample backtracking and integral boundary drift.

[0028] By controlling the difference between the active power integral snapshot and the broadband integral snapshot to write the corresponding data into the conventional metering register and the pollution energy isolation register respectively, the fundamental wave main metering and pollution energy processing paths are separated. This ensures that different types of energy data for bidirectional settlement flow independently along their predetermined register paths, without being mixed in storage. Ultimately, a closed-loop processing chain is formed, encompassing broadband bidirectional analog electrical signal access, real physical timestamp acquisition, active power integral snapshot delimitation, and classified writing to the register. This enables complete collaborative use of the metering processing chain in scenarios with rapid bidirectional power flow switching and high-frequency pollution. Attached Figure Description

[0029] Figure 1 This is a diagram showing the overall functional architecture of the smart meter metering control board of the present invention.

[0030] Figure 2 This is a schematic diagram of the same-source current splitting and abnormal degradation of the broadband current signal in this invention.

[0031] Figure 3 This is a schematic diagram illustrating the dynamic shielding window generation and real physical timestamp locking of the present invention;

[0032] Figure 4 This is a schematic diagram of hardware timing mapping and integral snapshot delimitation for group delay compensation in this invention;

[0033] Figure 5 This is a schematic diagram illustrating the contamination hit detection and isolation register writing of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] Please see Figures 1-5 This invention provides a high-precision metering method for smart meters oriented towards two-way settlement, comprising:

[0036] This implementation uses the following electricity meter as the unified execution subject: the metering control board in the electricity meter simultaneously receives wideband input electrical signals from the voltage sampling branch and the current sampling branch, wherein the current sampling branch carries the subsequent power flow steepness calculation and zero-crossing boundary tasks, and the voltage sampling branch is used to cooperate with integration.

[0037] Step 1: The wideband input electrical signal, which includes the fundamental frequency, high-frequency pulse width harmonics, and bias disturbances, is split into two types of intermediate results that are time-trackable, amplitude-integrable, and can be aligned in subsequent steps, without increasing the burden on the central processing unit.

[0038] In two-way settlement scenarios, residential-side photovoltaic inverters, energy storage converters, or vehicle-to-grid (V2G) devices continuously introduce high-frequency pulse width harmonics (PWMs) near the grid connection point. If such wideband input signals are completely fed into an analog-to-digital converter (ADC) and handled by a central processing unit (CPU) for filtering, zero-crossing detection, jitter reduction, and delimitation, the CPU must contend with both erroneous flips caused by high-frequency glitches and group delays introduced by digital filtering. The direct consequence is that if amplitude purity is prioritized, the phase timestamp is shifted; if phase proximity is prioritized, high-frequency glitches will trigger zero-crossing detection. Therefore, step one no longer uses a single digital path but instead distributes the same wideband input signal at the chip pins to the main computational channel and the physical auxiliary channel, allowing the two physical domains to perform different tasks, and then passing their respective outputs to subsequent steps.

[0039] To avoid confusion between different objects, the analog signal output from the current sensor and after pre-amplification is uniformly referred to as a wideband current signal. This broadband current signal can be written as:

[0040]

[0041] Among them, wideband current signal The original analog current characterization quantity entering the chip boundary, whose value range is limited by the front-stage limiting network to the intersection of the analog-to-digital converter input range and the analog comparator input range, is used as the common source of the two sub-channels.

[0042] fundamental component : Low-frequency effective components synchronized with the power grid frequency, whose value range is the power frequency neighborhood component in the broadband current signal, used to provide the main energy for subsequent active power integration and power flow direction determination; high-frequency harmonic components : High-frequency pulse width disturbances introduced by inverter switching operations, whose values ​​are superimposed components higher than the fundamental frequency band, are used to explain the source of dense spikes in the physical auxiliary channel and serve as the target for subsequent hardware shielding.

[0043] bias component The slow offset component, formed by Hall zero drift, magnetic bias, or DC injection, has a value range affected by sensor structure and grid connection conditions. It is used to define the abnormal source of analog comparator lockup; time variable. : Continuous time coordinates, whose value range covers the current measurement period, used to unify the waveform position in the analog domain;

[0044] The above decomposition is not for the purpose of reconstructing each component separately in step one, but to clarify what to retain and what to discard in each subsequent sub-channel: the main channel retains the fundamental component and suppresses the high-frequency harmonic components, while the physical auxiliary channel retains the polarity reversal time information without attempting to recover the amplitude.

[0045] Calculate the main channel from the broadband current signal Starting from the input, the signal is fed into the analog-to-digital converter (ADC) via an anti-aliasing network. The ADC outputs a sampled sequence, which is then pushed into the multiply-accumulate path of the central processing unit (CPU). Instead of pursuing full-frequency domain modeling, a high-order IIR low-pass filter of fixed order is used to preserve the fundamental envelope, allowing subsequent active integration to obtain a smooth sequence after removing most high-frequency pulse width disturbances. Its recursive form can be exemplarily written as:

[0046]

[0047] Among them, smooth output sequence : Calculate the main channel at the 1st The filtering result given at each sampling time point, whose value range is constrained by both the input range and the filter coefficients, is used to form the smoothed fundamental envelope sequence for subsequent active integration: Input sampling sequence Analog-to-digital converter in the first The range of values ​​for the discrete samples output at each sampling time point is limited by the quantization bit width of the analog-to-digital converter.

[0048] Feedback coefficient Feedback weights for higher-order IIR low-pass filters, whose values ​​are selected within a stable range that ensures the poles lie within the unit circle; feedforward coefficients. The feedforward weights of a high-order IIR low-pass filter, whose value range matches the target passband and stopband attenuation requirements, are feedback coefficients. and feedforward coefficients The filter order is determined offline by the filter design tool based on the power frequency passband, PWM interference stopband, and required group delay characteristics, stored in the program memory, and loaded into the filter register during the power-on initialization phase. and The feedback coefficients are determined by the selected filter structure and do not change adaptively during operation. Used to determine the recursive memory depth of the filter; feedforward coefficients Used to determine the preservation and suppression of the target frequency band; filter order , Used to limit the recursion length; input sample The main channel analog-to-digital converter operates at a fixed sampling period. get.

[0049] Filter order With feedforward order These represent the discrete depths of the feedback branch and the feedforward branch, respectively, and their values ​​are positive integers used to limit the complexity of the filter structure; sampling number. : The current discrete time-time number, whose value range is a sequence of natural numbers, used to establish the correspondence between the input sampling sequence and the smoothed output sequence;

[0050] Feedback Index With feedforward index These represent the historical term numbers in the recursive summation, with values ​​ranging from 1 to... and arrive This is used to specify the order in which each historical sample participates in the multiplication-addition accumulation;

[0051] The group delay constant of this filter is not guessed online in subsequent steps, but is directly obtained from the coefficient set in step one and written into the register. Its definition is as follows:

[0052]

[0053] Among them, the group delay constant The equivalent time shift introduced by the filter at the fundamental angular frequency, with a non-negative finite range, is used as the delay reference for the hardware timer in step three; phase response. High-order IIR low-pass filter with diagonal frequency The phase change, whose value range is the phase curve corresponding to the filter transfer function, is used to characterize the time shift caused by the filter.

[0054] angular frequency : A continuous frequency domain variable whose value range covers the filter's operating frequency band, used to determine the rate of change of phase with respect to frequency; fundamental angular frequency. The angular frequency corresponding to the fundamental frequency of the power grid is taken from the power frequency neighborhood of the power grid and is used to lock the delay point that needs to be compensated in step three.

[0055] For example, on the metering control board of a residential bidirectional electricity meter, the output of the manganese copper shunt first undergoes amplitude limiting and buffering before entering the analog-to-digital converter via a single trace. During board-level debugging, maintenance personnel can directly observe that the waveform edges in the CPU-side cache are smoothed out, pulse width spikes are no longer densely distributed, but the fundamental wave peak has shifted backward relative to the original input. Step one does not consider this shift a defect but instead registers it as a group delay constant for hardware timing mapping in subsequent steps. Thus, the main computation channel only handles amplitude purging and no longer undertakes zero-crossing triggering tasks, thereby maintaining a stable computation path for the CPU, and subsequent integration objects also obtain a uniform, smoothed fundamental wave envelope sequence.

[0056] Parallel to the main computing channel, wideband current signal The other branch bypasses the analog-to-digital converter and the arithmetic domain of the central processing unit, instead directly coupling to the on-chip analog comparator. The comparator's comparison reference is preferably a zero-potential reference, but a near-zero comparison threshold can also be generated by a bandgap reference and an on-chip analog-to-digital calibration network, as long as its function is always to determine polarity reversal rather than recover amplitude. Its output can be written as:

[0057]

[0058] Among them, the comparison output The physical auxiliary channel provides a binary polarity result, whose value range is limited to two logic states: positive and negative polarity. This is used to compress continuous analog quantities into transition edges that can be directly recognized by the event system; wideband current signal. In this formula, the same original analog source signal is still represented to ensure that the main computation channel and the physical auxiliary channel are completely from the same source at the signal source level.

[0059] Comparison Benchmark The reference potential used by the analog comparator, whose value range is near the sensor zero point, is used to provide the polarity reversal boundary; sign function. The sign determination operator is specifically designed to output a positive polarity state when the independent variable is greater than zero, a negative polarity state when it is less than zero, and to maintain the previous state by a comparator hysteresis structure when the variable is in the threshold neighborhood.

[0060] Among them, the physical auxiliary channel allows high-frequency harmonic components to attach near the polarity reversal to form dense spikes, because step one is only concerned with capturing the moment when the real phase crosses the zero point from the analog domain, while the spike suppression is left to step two to perform dynamic shielding around the power flow steepness.

[0061] For example, at the instant the grid-connected inverter switches from power supply to power absorption, an oscilloscope connected to the analog comparator output can observe a series of narrow pulses clustered near the polarity reversal. These narrow pulses appear chaotic, but they have not undergone the sampling delay of the analog-to-digital converter or the queuing process of the central processing unit, thus preserving the time boundary closest to the original physical process. The direct effect of this processing is that the physical auxiliary channel extracts the physical transition edge pulse train without mathematical phase shift in a manner that consumes almost no computing power, providing an in-situ trigger source for subsequent event routing and hardware shielding, while avoiding piling all the edge determination pressure onto the central processing unit.

[0062] When a persistent bias component exists in a broadband current signal, the analog comparator may remain in a single-sided state for an extended period, resulting in the comparator output no longer flipping. To prevent subsequent steps from misinterpreting this stagnation as a prolonged lack of power flow, step one involves arranging a saturation monitoring register path beside the physical auxiliary channel: if no polarity reversal is detected within the preset fundamental wave observation window, but the smoothed fundamental wave envelope sequence of the main channel still exhibits a valid amplitude, this state is recorded as comparator saturation lock-up, and the zero-crossing determination is temporarily switched to a soft determination path based on the smoothed fundamental wave envelope sequence. Simultaneously, a degradation flag is written to the state register area.

[0063] Thus, steps two and three can still obtain continuous input, only the source is switched from physical transition along the pulse train to degraded time stamps, thereby avoiding chain breakage.

[0064] In terms of structural implementation, the current sampling element can be a manganese-copper shunt, a miniature current transformer, or a Hall effect sampler, as long as it can output a wideband current signal within the controlled range; the analog-to-digital converter can be an on-chip successive approximation structure or an on-chip oversampling structure, as long as it can stably provide the input sampling sequence to the central processing unit; the analog comparator can be an on-chip comparator unit, or an external comparator connected to the event pin, as long as the physical auxiliary channel always bypasses the analog-to-digital converter and the arithmetic domain of the central processing unit. For board-level implementation, it is preferable to shorten the physical auxiliary channel traces and avoid areas with dense digital clock signals, making them closer to the sensor output; for isolated meters, the same source current can be shunted before isolation and then sent to the subsequent stages separately.

[0065] After the above processing, step one finally produces two intermediate results. The first type is a smooth fundamental envelope sequence with pure amplitude and hysteresis, and the second type is a physical transition edge pulse train without mathematical phase shift and high-frequency glitches. If the comparator is saturated and locked, the output degraded time stamp replaces the physical transition edge pulse train.

[0066] The meter includes a voltage sampling branch and a current sampling branch. The voltage sampling branch outputs a wideband voltage signal. The current sampling branch outputs a wideband current signal. Calculate the main channel response to wideband voltage signals. and wideband current signal Synchronous sampling and fundamental low-pass filtering are performed to obtain smoothed voltage sequences. and smooth current sequence And align them one by one according to the sampling time to form active samples. The signal is then fed into a multiply-accumulate unit. In the formula, the wideband voltage signal... Represents the raw analog voltage at the grid connection point, used to provide the voltage factor required for active power calculations; wideband current signal. Represents the raw analog current at the grid connection point, used to provide a bidirectional power flow factor; smooths the voltage sequence. Indicates the first Discrete values ​​of the fundamental voltage at each sampling time; smoothed current sequence Indicates the first Discrete values ​​of the fundamental current at each sampling time; active power samples Indicates the first Instantaneous active discrete quantity at each sampling time; sampling sequence number It is generated by incrementing a uniform sampling clock.

[0067] Among them, continuous level saturation lock-up refers to the continuous level saturation lock-up. Within a half-cycle observation window, the analog comparator output maintained the same logic level and no valid flips were detected, while the smoothed current sequence... The condition is satisfied at least once within the observation window. When this condition is met, the controller sets the lock-up flag, stops using the physical auxiliary channel output, and switches to main channel software zero-crossing detection; when subsequently continuous The comparator flip was detected again after one and a half cycles, and the difference between the comparator flip time and the software zero-crossing time was less than the recovery threshold. At that time, the lockout flag is released and the physical auxiliary channel is restored. In the formula, This indicates the number of consecutive half-cycles required for a lockout determination, used to avoid accidental degradation caused by occasional edge loss during a single half-cycle; This indicates that there is a current threshold, which is determined by the no-load noise calibration value plus a safety margin, and is used to exclude the normal state where there is no current and there is no reversal. This indicates the number of consecutive half-cycles required for recovery confirmation, used to avoid recovery jitter; This represents the recovery threshold, used to constrain the consistency of soft and hard zero crossings before recovery.

[0068] Step 2: Using the smooth fundamental envelope sequence and physical jump-along pulse train generated in Step 1, construct a shielding window that contracts in tandem with the tidal current steepness, and lock in a real physical timestamp from multiple candidate flip pulses that can be directly sent to Step 3.

[0069] The physical transition pulse train output in Step 1 retains the original polarity reversal time boundary, but it also includes narrow pulses generated by the inverter switching chopper. If all these pulses are sent to the central processing unit for comparison one by one, interrupts will accumulate when the polarity is reversed, and the fixed dead time cannot cover both weak and strong disturbance conditions. Therefore, Step 2 does not use a constant shielding width, nor does it postpone the de-jitter task to the software metering thread. Instead, it directly uses the smoothed fundamental envelope sequence obtained in Step 1 to characterize the rate of change of the current half-cycle, and then converts this rate of change into the shielding window width in the event router, determining from the source which reversal pulses are eligible to enter the subsequent timing link. Thus, Step 2 and Step 1 have a clear division of labor: Step 1 is responsible for extracting time information from the analog domain, and Step 2 is responsible for classifying this time information and removing false information.

[0070] The smoothed fundamental envelope sequence is denoted as . The source of the data is the output of the main channel; the physical transition edge pulse train is output by the analog comparator and sent to the capture register via the event router; the degradation time stamp is only enabled when the analog comparator is determined to be saturated and locked in step one. Step two first performs local slope estimation on the smoothed fundamental envelope sequence to obtain the power flow steepness, then calculates the shielding window width based on the power flow steepness, and finally uses the shielding window width to constrain the allowance range of the physical transition edge pulse train, retaining only one real physical timestamp within one and a half cycles. Throughout the process, the central processing unit is only responsible for writing window parameters and reading results, and does not participate in pulse-by-pulse decision-making; pulse-by-pulse decision-making is jointly completed by the event router, the capture register, and the latch trigger.

[0071] Step two involves extracting a quantity representing the current half-cycle rate of change from the smoothed fundamental envelope sequence. Here, a forward probe path is used to continuously read the three most recent sampling points from the direct memory access buffer, and three-point differential analysis is performed within the same sampling period to obtain the power flow steepness. Its expression is:

[0072]

[0073] Among them, tidal steepness : No. The local rate of change at each sampling moment, whose value range covers both positive and negative directions, indicates that the larger the absolute value, the steeper the energy transition near the polarity reversal within the current half-cycle; smooth fundamental envelope sequence. , , These represent the filtered outputs of the current sampling point, the previous sampling point, and the two previous sampling points, respectively, and their value ranges are inherited from the main channel output of the calculation in step one.

[0074] Weighting coefficient With weighting coefficients The two-level weights in the three-point difference method take positive values ​​and preferably satisfy the following conditions: This is used to ensure that the most recently sampled point contributes more to the tidal current steepness, while retaining information from the previous sampling interval, thus preventing single-point spikes from narrowing the shielding window too much; sampling period : Calculate the discrete sampling interval of the main channel, the range of which is determined by the cycle time of the analog-to-digital converter, and use it to restore the discrete difference to the rate of change on the time scale;

[0075] The three-point difference method described above is not the only implementation path. For example, local linear fitting can also be used to obtain the power flow steepness, as long as the output object is still uniformly denoted as power flow steepness. Taking the single-phase current branch of a single-phase bidirectional meter as an example, whenever a new sample is written to the direct memory access buffer, the front probe path retrieves the smoothed fundamental envelope sequence sample from the three most recent addresses; after the calculation is completed, the power flow steepness is written to the window register preparation area, while the physical transition pulse train continues to arrive in another hardware channel.

[0076] In practice, step two no longer relies on a fixed empirical dead zone, but instead allows the shielding strength to be determined by the smooth fundamental envelope sequence itself. Therefore, the width of the shielding window can be adjusted synchronously with changes in the grid connection point's operating conditions. The power flow steepness can be obtained from a small number of samples without disrupting the low-computing-power structure established in step one.

[0077] After obtaining the power flow steepness, step two first maps the power flow steepness to a specific shielding window width, and then sends this shielding window width to the event router. Here, the aforementioned exponential affine form is used, so that the larger the power flow steepness, the more the shielding window width shrinks; the smaller the power flow steepness, the closer the shielding window width is to the baseline value. Its expression is:

[0078]

[0079] Among them, the width of the shielded window The current half-cycle allows the event router to allow candidate flip pulses for a period of time. Its value is positive, and its lower limit is guaranteed not to shrink to 0 by the slip compensation amount; Reference window width. The initial window width used under weak disturbance conditions has a positive value range. It is used to maintain a sufficiently wide release range when the power flow steepness is small, so as to avoid missing the real flip.

[0080] Shrinkage coefficient The compressibility of the power flow steepness on the width of the shielding window is a positive value used to control the exponential contraction rate; the larger the contraction coefficient, the faster the width of the shielding window shrinks as the power flow steepness increases; power flow steepness Continuing the definition from the previous equation, its absolute value is used to eliminate directional differences, making the shielding action sensitive only to the degree of change, without distinguishing between the forward or reverse direction of the power flow itself; slip compensation amount : Minimum time compensation caused by event routers, capture registers, and on-chip interconnect propagation, with a non-negative value range; exponential function The natural exponential mapping operator is used to establish a monotonically decaying relationship between power flow steepness and shielding window width, and to avoid abrupt changes caused by hard inflection points.

[0081] Base window width The shrinkage coefficient is obtained by statistically analyzing the maximum deviation of the actual flip edge relative to the coarse positioning time under pure sinusoidal input conditions, and then written into the configuration register after adding a fixed hardware margin; The factory calibration stage involves offline tuning and solidification based on the false release rate requirements under different disturbance levels; slip compensation amount. The value is measured by the sum of propagation delays between the analog comparator, event router, and capture register, and is used to ensure that the window does not shrink to zero under strong disturbances. The reference window width is... Used to provide a release reference under weak disturbance conditions; contraction coefficient Used to characterize the compressive strength of the tidal current steepness on the window width; slip compensation amount Used to reserve hardware propagation margin.

[0082] In hardware implementation, the window register is preferably configured as a start register and a width register. The central processing unit (CPU) writes the shielding window width only once before the start of the half-cycle, and the event router internally generates the shielding window opening pulse according to the shielding window width. Taking a phase channel of a three-phase four-wire smart meter as an example, the window register is located inside the microcontroller, which is the same as the analog comparator output. The analog comparator output is directly fed to the event router via on-chip metal interconnects. When the power flow steepness suddenly increases, the shielding window width in the window register decreases accordingly, and the event router silently discards the out-of-window flip pulse without sending an interrupt request to the CPU. For microcontrollers without an exponential arithmetic unit, the exponential function can also be discretized into a lookup table, and the CPU can obtain the shielding window width by indexing the power flow steepness interval, as long as the output remains the shielding window width. That's all.

[0083] In use, step two transforms the dejittering process from pulse-level judgment to window-level configuration. Furthermore, exponential affine mapping enables the shielding window width to shrink rapidly in the strong disturbance region and expand smoothly in the weak disturbance region, thus balancing narrow pulse suppression and true flip preservation.

[0084] Once the shielding window width is configured, step two uses adjacent samples with opposite signs from the smoothed fundamental envelope sequence to obtain the coarse positioning time, and uses this coarse positioning time as the center of the shielding window, as shown below:

[0085]

[0086] Among them, coarse positioning time The approximate zero-crossing time obtained by interpolation of adjacent samples with different signs has a range of values ​​within the range of [missing information]. and Between, used as the center of the shielding window; discrete time The time coordinate corresponding to the previous sampling point, whose value range is determined by the sampling time base, is used to provide the left endpoint of the coarse positioning time; sampling period. Inheriting the aforementioned definition, it is used to limit the interpolation interval where the coarse positioning time lies;

[0087] Smooth fundamental envelope sequence With smooth fundamental envelope sequence These represent the filtered outputs at both ends of the interpolation interval, with their value ranges inherited from the definition in step one, used to give the relative position of the coarse positioning time within the current sampling period; absolute value operator : The amplitude positive operator is used to determine the linear interpolation weights by using the amplitude ratio of the two end samples;

[0088] Once the coarse location time is determined, the event router performs a window comparison between the arrival times of all candidate flip pulses and the coarse location time, allowing passage only if the following formula is satisfied:

[0089]

[0090] Among them, candidate arrival times The time when any flip pulse in the pulse train enters the capture register along the physical transition, its value range covers all candidate pulses within the current half-cycle, and is used for window comparison and selection of the actual physical timestamp; coarse positioning time. Inheriting the definition from the previous formula, it is used as the center of the release interval; the width of the shielding window. Inheriting the aforementioned definition, half of it is used to form a symmetrical release boundary;

[0091] When the above formula holds true, the event router allows the earliest arriving candidate arrival time and latches it as a real physical timestamp. If subsequent candidate pulses arriving within the same half-cycle fall into the release interval again, they are suppressed by the latch trigger and no longer output repeatedly. If no candidate pulse in the current half-cycle meets the window condition, step two outputs a degraded timestamp and writes a missed detection flag into the status word. Taking the residential photovoltaic grid-connected feedback operation as an example, two to three clusters of narrow pulses often appear near the zero crossing of the physical transition pulse train. The event router first opens a controlled release interval according to the coarse positioning time. The pulse that first falls into the interval in the first cluster is latched as the real physical timestamp. Even if the remaining pulses arrive later, they will not rewrite the output register. In this way, step three receives a single, de-glitched real physical timestamp.

[0092] As a supplement: Event routers provide coarse location times To shield the center of the window, and only for those that satisfy... Candidate flip pulses are allowed to pass. For multiple candidate flip pulses that meet the window conditions within the same half-cycle, only the first one that arrives is latched, and it has the actual physical timestamp. The latch remains in a latched state for the remainder of the first half of the cycle; when the coarse positioning time of the next half of the cycle enters the update interval, the latch is released and the candidate selection process begins again. Where, the coarse positioning time... This indicates the zero-crossing approximate center obtained by interpolation based on adjacent filtered samples with opposite signs; the arrival time of the candidate flip pulse. Indicates the time of a single toggle edge recorded by the event capture register; mask window width. Indicates the effective release range for the current half-week; actual physical timestamp. This indicates the zero-crossing timescale of the unique output in this half-cycle.

[0093] In practice, step two aligns the continuous information of the smoothed fundamental envelope sequence with the discrete event information of the physical transition pulse train within the same half-cycle, thereby stably extracting a single true physical timestamp from multiple candidate flip pulses. The missed detection bypass and degraded time stamp share the anomaly system of step one, ensuring that step two maintains an unbroken output chain even when the analog comparator malfunctions or candidate pulses are missing. The smoothed fundamental envelope sequence provides the power flow steepness and coarse location time, the physical transition pulse train provides in-situ candidate time boundaries, and the event router performs window-level filtering.

[0094] Furthermore, a continuous mapping relationship is adopted between the shielding window width and the power flow steepness, which can narrow the candidate range when the disturbance increases and maintain the necessary tolerance when the disturbance decreases, thus avoiding the fixed dead zone from becoming unbalanced under different operating conditions.

[0095] Step 3: Convert the actual physical timestamp output in Step 2. The group delay constant solidified in step one A one-to-one mapping is performed in the hardware path to capture active integral snapshots and reset the integration boundaries at the correct time.

[0096] The smoothed fundamental wave envelope sequence obtained in step one It is already suitable for integration, but the sequence has a group delay constant relative to the actual physical flip time. Step two extracts the actual physical timestamp from the physical transition pulse train. However, it does not directly hold a smooth quantity suitable for integration. If the conventional approach is followed, the central processing unit often needs to backtrack some historical samples after an interrupt occurs, or retain a sliding cache in memory before performing the interrupt.

[0097] This approach will re-select the actual physical timestamps from step two. Placing the data back into the software thread queue introduces issues related to cache depth, backtracking indexes, and boundary drift caused by thread preemption. Step three avoids using a backtracking chain that calculates first and then fills in, instead using a peripheral chain that waits first and then retrieves, meaning it accepts the actual physical timestamp. After waiting and group delay constant Consistent hardware duration allows for direct extraction of the result from the current multiply-accumulate at the peripheral level. This smooths the fundamental envelope sequence. Continue updating in the main computing channel, using the actual physical timestamp. The task of simply waiting for the hardware to start is performed; the two are then realigned in step three.

[0098] Among them, the actual physical timestamp Release and latch via step two; group delay constant After the filter coefficients are determined in step one, they are written into the register; the fundamental envelope sequence is smoothed. The active power integral, which participates in the multiply-accumulate unit together with the voltage smoothing sequence, is recorded as the newly added active power integral snapshot in this step. , used to indicate the first The boundary value that is taken by the direct memory access controller at the end of each half-cycle. Step 3: First, set the group delay constant... Discretize the threshold count into a hardware delay timer, and then use the actual physical timestamp. Upon arrival, the event system initiates a hardware delay timer. After the hardware delay timer overflows, another event chain triggers the direct memory access controller to complete the fetching and clearing. Throughout the process, the central processing unit only writes threshold parameters during the initialization phase and does not participate in successive boundary checks during the runtime phase.

[0099] Step three doesn't primarily address the integration itself, but rather the question of how long to wait before truncating. (Group delay constant) The high-order IIR low-pass filter from step one is represented by a time quantity, while the hardware delay timer operates on clock counting. Therefore, a time-to-count mapping is performed first, and its expression is:

[0100]

[0101] Among them, threshold counting : Represents the wait count value written to the hardware delay timer compare register. Its value is a positive integer and is used to equivalently represent the group delay constant at the peripheral level. Group delay constant : This represents the equivalent time shift formed by the high-order IIR low-pass filter at the fundamental angular frequency in step one, and its value range is a non-negative finite value;

[0102] Timer clock cycle This indicates the underlying clock cycle used by the hardware delay timer; its value range is determined by the on-chip clock tree and frequency divider. (Timing clock cycle) Obtained by frequency division from the clock tree of the hardware delay timer; threshold counting. according to Calculate and write to the compare register. The timing clock cycle is used for this calculation. Used to convert continuous time delay into discrete counting; threshold counting This is the direct load value of the hardware delay timer. (Rounding operator) This indicates a rounding-up mapping, used to avoid premature boundary values ​​due to underestimating the threshold count;

[0103] In circuit implementation, threshold counting Preferably, the parameters are written to the comparison register during the parameter loading stage and stored in the same parameter page as the filter coefficient set corresponding to step one. The advantage of this approach is that if the filter order or cutoff frequency is changed, the same set of parameters will be loaded simultaneously to update the group delay constant. and threshold counting This prevents the filter response from changing while the timing wait still uses the old value, thus avoiding a break in the process.

[0104] For example, on a smart meter motherboard using a single-core microcontroller, after power-on, the metering control board first retrieves the filter coefficient set from the read-only memory area, and then, according to the timing clock cycle... Calculate threshold count It is then written to the hardware delay timer; when maintenance personnel subsequently check the register image, they can directly see that the threshold count has been bound to the current filter parameters.

[0105] When used, the group delay constant It no longer remains at the algorithm specification level, but is solidified into a threshold count that can be executed by peripherals. Meanwhile, threshold counting The parameters are loaded together with the filter parameters to ensure that the waiting action in step three is consistent with the filtering action in step one.

[0106] After completing the threshold mapping, step three addresses the question of who initiates the wait and when. Instead of using the method of pushing the CPU interrupt onto the stack and then writing the start bit, this step uses the actual physical timestamp. It directly enters the event system, which then sends the edge event corresponding to the timestamp to the hardware delay timer start terminal.

[0107] For ease of explanation, step three will denot the boundary time at which the waiting period ends as... Their relationship can be written as:

[0108]

[0109] Among them, the boundary time This indicates the time boundary at which the hardware delay timer overflows and triggers subsequent capture actions. Its value range is within the current half-cycle and is used as a snapshot of the active power integral. The moment of capture; the actual physical timestamp This indicates the arrival time of the unique release pulse output in step two, and its value range is within the valid interval near the current zero crossing; threshold count. Inheriting the aforementioned definition, it is used to specify the discrete length of the wait; timing clock period. Inheriting the aforementioned definition, it is used to convert threshold counts back to a time scale.

[0110] On the hardware path, the actual physical timestamp The corresponding edge first enters the event system synchronizer, then the edge latch, and subsequently drives the hardware delay timer counter to increment from zero; when the count value reaches the threshold, it continues counting. At this time, the hardware delay timer generates an overflow event at the compare output. This overflow event does not return to the central processing unit, but continues to be sent to the trigger input of the direct memory access controller through the event system. The actual physical timestamp output in step two. Once formed, it continues until the boundary time. Upon arrival, the entire link operates in a closed loop within the peripheral device.

[0111] For example, in a scenario where residential-side photovoltaic feedback and load absorption alternate, the actual physical timestamp The timing is determined by the effective overriding edge of a phase current comparison branch. This overriding edge is routed to the corresponding phase's hardware delay timer in the on-chip event system. The hardware delay timer starts counting, while the central processing unit continues to execute regular display and communication tasks without interfering with the waiting process. The result observed in the field is that no new software interrupts accumulate after the edge arrives, and the timing wait and metering main loop do not preempt each other.

[0112] When used, the actual physical timestamp This directly transforms the process into a peripheral waiting action, reducing the pollution of boundary moments by software threads; boundary moment. It is generated within the event system and provides a stable and repeatable trigger source for subsequent crawling actions.

[0113] At the boundary moment Upon arrival, the core of step three will shift to determining what to remove, how to zero out the data, and how to continue processing the previous half-cycle after zeroing. The integral value generated from the multiply-accumulate unit will be preferentially used as the candidate energy for the current half-cycle, at the boundary time. The active component snapshot is moved by the direct memory access controller. Written as

[0114]

[0115] Among them, active integral snapshot Indicates the first One and a half cycles at the boundary moment The integrated results that are transported out vary in value range with the load direction and power magnitude, and are used as input objects for power flow polarity verification and subsequent routing in step four.

[0116] Discrete power samples Indicates the first Each sampling moment is an instantaneous active energy sample obtained by multiplying the voltage smoothing sequence and the smoothed fundamental envelope sequence. Its value range covers both positive and negative directions and is used to continuously accumulate energy in the main calculation channel.

[0117] Sampling period This represents the sampling interval for calculating the main channel. Its value range is determined by the cycle time of the analog-to-digital converter and is used to convert discrete power samples into integral quantities.

[0118] Starting Index This indicates the new starting point of integration after the previous half-cycle is cleared. Its value range is non-negative integers, and it is used to give the starting boundary of this integration.

[0119] Termination Index Indicates the time of this boundary determination. The index following the last valid sample has a value greater than the starting index. An integer, used to give the end boundary of this integration;

[0120] In terms of execution, the hardware delay timer overflow event first triggers the read channel of the direct memory access controller to move the current value of the multiply-accumulate accumulator to the half-cycle result register area, and then immediately triggers the write-zero channel to clear the multiply-accumulate accumulator to zero, subsequently updating the starting index of the next accumulation cycle. If the chip provides a dual-channel direct memory access controller, the read channel and the write-zero channel can occupy different channel numbers; if the chip only provides a single-channel direct memory access controller, a chained descriptor approach can be used for read-then-write. In an alternative implementation, the event system can first trigger the shadow register latch, and then the direct memory access controller can move the data from the shadow register, as long as it is maintained at the delimited time. Once the data capture is complete, immediately clear the multiply-accumulate accumulator to zero.

[0121] For example, in the A-phase channel of a three-phase electricity meter, the multiply-accumulate accumulator continuously accumulates the power sample formed by the smoothed voltage sequence of phase A and the smoothed fundamental envelope sequence of phase A. When the hardware delay timer corresponding to phase A overflows, the direct memory access controller first writes the contents of the multiply-accumulate accumulator for that phase into the half-cycle result register, and then writes zero to the same address. Afterward, the samples for the new half-cycle continue to enter the already cleared multiply-accumulate accumulator, and the active power integral snapshot of the previous half-cycle is recorded. Then it remains in the result storage area to await processing in step four.

[0122] When using it, step three compresses the truncation and reset to the same bounded moment. Complete, enabling active integral snapshot It has clear boundaries; at the same time, the direct memory access controller completes the transfer and zeroing at the peripheral level, so that the next half cycle can start seamlessly without relying on the CPU's scheduling timing.

[0123] Furthermore, threshold counting The algorithm delay is translated into a timed wait; the event system translates time events into peripheral triggers; and the direct memory access controller translates the trigger result into an active power snapshot. Because of the clearing action of the multiply-accumulate accumulator, step three is not simply a timing operation, but rather a continuous transformation of time alignment, boundary truncation, and integration restart.

[0124] Finally, step three delivers a well-defined active power integral snapshot to step four. And retain the already cleared multiply-accumulate for the second half of the week, thus truly settling the time and amplitude objects formed in the first two steps into a measurable measurement boundary.

[0125] Step 4: While keeping the output boundary unchanged in Step 3, based on the same periodic polarity relationship between the fundamental energy and the contamination energy, drive the direct memory access controller to complete target address deflection, register area isolation writing, and contamination energy scaling storage.

[0126] Step 3 output active integral snapshot While a clear half-cycle boundary is already established, bidirectional settlement considers not only the net active power but also whether this net active power is accompanied by pollution backflow in the opposite direction to the fundamental frequency. If we take a snapshot of the active power integral... If the billing process is handled uniformly by the software billing thread, the central processing unit needs to read, determine the direction, select the address, and write back sequentially. The peripheral-level boundary established in the previous steps will fall back into the software timing. Therefore, step four rewrites the billing destination as an on-chip bus action: first, the hardware comparison chain core compares the directions of the fundamental energy and the contamination energy; then, the hit result controls the target address pointer of the direct memory access controller; and finally, the written data is restricted to the register area constrained by the memory protection unit.

[0127] Active Integral Snapshot Step 3 at the boundary time The captured fundamental frequency measurement results. To avoid recalculating the frequency domain in step four, this implementation method retains a broadband adjoint integration chain in parallel in the measurement control board. Its integration start and end points are consistent with those in step three, and at the same boundary time. Output wideband integral snapshot Step four: First, obtain the pollution integral snapshot from these two snapshots. Then, based on the active power integral snapshot Pollution points snapshot The combination of symbols forms the hit marker Then hit the mark Directly determine the target address With pollution reduction number When the mark is hit When the value is zero, the data enters the regular bidirectional metering register area; when the flag is hit... At one time, the data enters the dirty electricity penalty register area and undergoes an arithmetic left shift before entering.

[0128] Furthermore, a broadband adjoint integrator chain operating on the same boundary as in step three is utilized. This integrator chain continuously integrates the power sample without fundamental low-pass filtering, and at the same boundary time... Synchronous transfer, therefore wideband integral snapshot With active integral snapshot Naturally, they belong to the same half-cycle. The difference between the two is the pollution integral snapshot. :

[0129]

[0130] Among them, pollution points snapshot The additional energy component of the broadband integral relative to the fundamental main measurement result within the same half-cycle, with values ​​covering both positive and negative directions; broadband integral snapshot. : Wideband adjoint integral chain at the boundary time The total output, whose value range covers both positive and negative directions, is used to provide a total snapshot of the same period, including high-frequency pollution components; active power integral snapshot. The fundamental main measurement result output in step three has a value range covering both positive and negative directions. It is used to provide the main measurement for settlement and as a benchmark for pollution differential.

[0131] Based on this, step four then generates hit markers. :

[0132]

[0133] Among them, the hit marker : Whether the current half-cycle hits the asymmetric contamination condition, its value ranges from zero to one, and is used to directly drive subsequent address deflection and displacement scaling;

[0134] Step operator Threshold determination operator, specifically, outputs one when the independent variable is greater than or equal to zero, and outputs zero when the independent variable is less than zero, used to compress the sign relationship and magnitude threshold relationship into a binary result; Active integral snapshot Pollution points snapshot In product The term "coupling" indicates a directional coupling relationship; when the product is negative, it means that the two directions are opposite; pollution threshold. The minimum magnitude threshold that the pollution integral snapshot must meet before entering the penalty chain. Its value is non-negative and is used to filter out meaningless deflections caused by zero drift and minimal residue.

[0135] For example, when a residential photovoltaic inverter supplies power to the distribution network, the two integral chains on the metering control board output active power integral snapshots respectively. and wideband integral snapshot When the filtering conditions worsen, a difference in opposite directions appears between the two, and the combinational logic immediately writes this difference as a hit flag. The contamination hit bit in the status word is then flipped.

[0136] When using it, step four involves constructing a contaminated integral snapshot using a differential snapshot with the same period. This ensures that the pollution detection is completely consistent with the boundary delineation in step three; simultaneously, it hits the marker. It is given directly by combinational logic, and can be immediately referenced in subsequent bus routing.

[0137] Hit mark After formation, two physical target areas are configured for the direct memory access controller: the starting address of the conventional bidirectional metering register area is denoted as... The address of the dirty electricity punishment storage area is recorded as .

[0138] The direct memory access controller does not modify the target register sequentially by the central processing unit, but rather by the hit flag. Direct-drive address selector forms target address :

[0139]

[0140] Among them, the target address The final on-chip memory address where the half-cycle result is written is limited to the protection page range corresponding to the conventional bidirectional metering register area and the dirty current penalty register area. This is used to convert the hit result into a specific bus landing point; the starting address of the conventional bidirectional metering register area... The default storage starting point for normal settlement results, whose value range is within the regular pages allowed by the memory protection unit; the starting address of the dirty power penalty register area. The starting point of isolated storage after a contamination hit; its value range is within the penalty page separately protected by the memory protection unit; hit flag. Inheriting the aforementioned definition, it is used to control the target address in and Switch between them;

[0141] In hardware implementation, target address This corresponds to the endpoint of a direct memory access write burst. Preferably, the conventional bidirectional metering register area and the dirty power penalty register area are located in different protection pages of the same on-chip memory, both pages are word-aligned, and the width of each register word is consistent with the transport bit width of the direct memory access controller. Hit mark When the value is zero, the target address field in the descriptor remains unchanged. Hit mark For a time, the target address field was rewritten by the hardware as follows: .

[0142] Standard metering storage area address The primary address of the pollution energy isolation storage area The target address is pre-defined by the memory-mapped table during firmware compilation and loaded into the direct memory access controller descriptor and memory protection unit permission table during power-on initialization; Pollution hit markers Select to generate. The starting address of the standard metering register area is specified. Used for writing general bidirectional metering results; address of the pollution energy isolation storage area. Used to write the contamination diversion results; target address This is the actual write address for the current half-week.

[0143] For example, during the half-week of fundamental wave transmission and contamination reinjection, after the delimiting event occurs, the debug port can see a direct memory access write burst moving from the result buffer to the dirty power penalty register instead of entering the regular bidirectional metering register.

[0144] In practice, step four reshapes the settlement destination into an address offset action, separating the results of pollution hits from regular results at the storage layer; simultaneously, the target address... Constrained by the page boundaries of the memory protection unit, subsequent read and write permissions have clear physical boundaries.

[0145] After selecting the target address, step four involves determining the format in which the data is written. This implementation does not write the contamination hit result directly to the dirty electricity penalty register. Instead, it performs an arithmetic left shift before writing, causing a snapshot of the contamination integral. Punishment words are generated based on the hit rate. :

[0146]

[0147] Among them, the word "punishment" Pollution points snapshot The final data word written to the dirty electricity penalty register after being scaled up by a factor of 1, has a value range determined by the contamination integral snapshot. With scaling bits A joint decision was made to store the pollution level, after hardware displacement, in an isolated storage area; pollution integral snapshot. Inherited from the aforementioned definition, it is used as the original object for inputting abbreviations;

[0148] Scaling bits The arithmetic left shift bits used in this half-cycle have a range of non-negative integers and are used to map the contamination hit level to a specific multiplier; preferably, the scaling bits... From the hit mark Pollution points snapshot relative pollution threshold The decision is made jointly by levels beyond; when a marker is hit. When it is zero, the number of bits for scaling is zero. Take zero;

[0149] In terms of the order of operations, the direct memory access controller first reads the contamination integral snapshot from the result buffer. Or active integral snapshot Then, the word to be written is formed by displacement units, and then written according to the target address. Write to the appropriate protected page. If the target address... If the target address falls within the dirty power penalty register, the memory protection unit only grants write permissions to the direct memory access controller and the digest generation unit, while keeping the normal read / write path of the central processing unit closed; If the data falls within the standard bidirectional metering register area, it is written according to the standard permission table. After the write is complete, the digest generation unit records the write address, the written word, and the delimitation time. Perform a sequential scan, generate an additional digest word and store it immediately after the result word, then the state machine clears the hit mark for this half-cycle. With the temporary displacement parameters, proceed to the next half-cycle waiting. For example, after a pollution condition is hit in a certain half-cycle, the debugging interface will show a new scaled result word in the dirty current penalty register area, followed by a summary word, while the regular bidirectional metering register area remains empty for this half-cycle.

[0150] The digest generation unit uses the SM3 digest algorithm to digest the target address. Write words Boundary Time and half-cycle serial number The concatenated message is digested to obtain the digest word. and the abstract word The data is stored in the corresponding register area immediately adjacent to the written word. Where, the digest word... Used to verify that the contents of the storage area have not changed before reporting; half-week sequence number It is given by a half-cycle counter that increments automatically after each delimitation.

[0151] When in use, step four translates the pollution attribution results into visible data word placement and displacement methods, rather than remaining at the level of abstract settlement judgment; at the same time, the write permissions of the dirty power penalty register area are controlled separately by the memory protection unit, so that the pollution results are separated from the normal results in the physical storage structure.

[0152] Taking a smart meter installed at the user's grid connection point as an example, the smart meter includes a casing, a metering control board, a power supply circuit, a communication interface, a display unit, a voltage sampling branch, a current sampling branch, and a microcontroller. The metering control board is located inside the casing, with the voltage and current sampling branches connected to external lines to acquire wideband bidirectional analog electrical signals. The microcontroller is located on the metering control board and integrates an analog-to-digital converter, an analog comparator, an event system, a hardware delay timer, a direct memory access controller, a multiply-accumulate unit, a wideband accompanying integral chain, a conventional metering register area, and a pollution energy isolation register area.

[0153] In terms of connectivity, the output of the current sampling branch is connected to both the analog-to-digital converter and the analog comparator, forming a digital / analog heterogeneous shunt at the microcontroller pin side; the output of the voltage sampling branch is connected to the analog-to-digital converter, forming the main computation channel together with the current sampling branch; the analog comparator and the current sampling branch form the physical auxiliary channel. The main computation channel performs high-order IIR low-pass filtering on the sampled signal, outputting a smoothed fundamental envelope sequence, and forming an active integral snapshot within the multiply-accumulate accumulator; the physical auxiliary channel outputs a physical transition edge pulse train.

[0154] The microcontroller determines the shielding window width based on the smoothed fundamental envelope sequence and performs hardware filtering on the physical transition pulse train to determine the true physical timestamp. The event system starts a hardware delay timer based on the true physical timestamp and the group delay constant, triggering the direct memory access controller to capture and clear the active power integral snapshot at the boundary moment. The wideband accompanying integral chain forms a wideband integral snapshot with the same integration boundary as the active power integral snapshot. The direct memory access controller writes the corresponding data into the conventional metering register or the pollution energy isolation register based on the difference between the active power integral snapshot and the wideband integral snapshot.

[0155] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0156] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0157] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0158] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0159] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A high-precision metering method for smart meters oriented towards two-way settlement, including: The method for measuring wideband bidirectional analog electrical signals based on smart meters is characterized by further comprising: Digital / analog heterogeneous splitting is implemented on the microcontroller pin side for wideband bidirectional analog electrical signals, so that the main calculation channel outputs a smooth fundamental envelope sequence and the physical auxiliary channel outputs a physical transition pulse train. The shielding window width is determined based on the smoothed fundamental envelope sequence, and the physical transition pulse train is screened by hardware to determine the real physical timestamp. Based on the real physical timestamp and the group delay constant, the hardware delay timer is controlled by the event system, and the direct memory access controller is triggered to capture and clear the active power integral snapshot at the boundary time. Based on the difference between the active power integral snapshot and the broadband integral snapshot, the corresponding data is written into the conventional metering register or the pollution energy isolation register, respectively.

2. The high-precision metering method for smart meters oriented towards two-way settlement according to claim 1, characterized in that: The digital / analog heterogeneous splitting includes: sending the first link of the broadband bidirectional analog electrical signal into an analog-to-digital converter and a high-order IIR low-pass filter path to form a smooth fundamental envelope sequence, and sending the second link of the same broadband bidirectional analog electrical signal directly into an analog comparator to form a physical transition edge pulse train.

3. The high-precision metering method for smart meters oriented towards two-way settlement according to claim 2, characterized in that: The physical transition edge pulse train is obtained by polarity reversal detection using an analog comparator with a zero potential reference. The smoothed fundamental envelope sequence is obtained by filtering the fundamental component in the broadband bidirectional analog electrical signal using a high-order IIR low-pass filter path. The smoothed fundamental envelope sequence and the physical transition edge pulse train originate from the same broadband bidirectional analog electrical signal.

4. The high-precision metering method for smart meters oriented towards two-way settlement according to claim 3, characterized in that: Determining the shielding window width based on the smoothed fundamental envelope sequence includes: determining the power flow steepness based on adjacent sampled values ​​of the smoothed fundamental envelope sequence, generating the shielding window width for the current period based on the power flow steepness, and then writing the shielding window width into the event router to limit the allowance range of the physical transition along the pulse train.

5. The high-precision metering method for smart meters oriented towards two-way settlement according to claim 4, characterized in that: Hardware screening is performed on the physical transition edge pulse train to determine the true physical timestamp, including: using the coarse positioning time determined by the smooth fundamental envelope sequence as the window center, only allowing candidate flip edges that fall within the interval corresponding to the width of the shielding window, and locking the time corresponding to the first candidate flip edge allowed in the same period as the true physical timestamp.

6. The high-precision metering method for smart meters oriented towards two-way settlement according to claim 5, characterized in that: Based on the actual physical timestamp and the group delay constant, the event system controls the hardware delay timer, including: the event system receiving the edge event corresponding to the actual physical timestamp, starting the hardware delay timer to start timing, and converting the group delay constant into the waiting threshold of the hardware delay timer to generate the delimited moment.

7. The high-precision metering method for smart meters oriented towards two-way settlement according to claim 6, characterized in that: At the boundary moment, the direct memory access controller is triggered to capture and clear the active integration snapshot, including: first, latching the current integration value in the multiply-accumulate accumulator to form an active integration snapshot, then the direct memory access controller moves the active integration snapshot, and after moving it, the multiply-accumulate accumulator is cleared to establish the integration starting point of the next cycle.

8. The high-precision metering method for smart meters oriented towards two-way settlement according to claim 7, characterized in that: The wideband integral snapshot and the active power integral snapshot are obtained using the same integration boundary. The wideband integral snapshot is obtained by integrating the wideband power sample corresponding to the wideband bidirectional analog electrical signal by the wideband adjoint integral chain. The difference between the active power integral snapshot and the wideband integral snapshot is used to characterize the pollution energy that is distinguishable from the fundamental main metering result.

9. The high-precision metering method for smart meters oriented towards two-way settlement according to claim 8, characterized in that: Based on the difference between the active power integral snapshot and the wideband integral snapshot, the corresponding data is written into the conventional metering register or the pollution energy isolation register, respectively. This includes: generating a pollution hit flag based on the directional relationship between the difference and the active power integral snapshot, and controlling the target address of the direct memory access controller to switch between the conventional metering register and the pollution energy isolation register based on the pollution hit flag. The corresponding data written to the pollution energy isolation register is obtained by displacement scaling of the difference result. The displacement scaling level is determined according to the excess level of the difference result relative to the pollution threshold. The pollution threshold is jointly calibrated by no-load noise, quantization error and normal harmonic residue, and written to the configuration register during power-on initialization.

10. A smart meter for two-way billing, comprising a voltage sampling branch, a current sampling branch, and a microcontroller, characterized in that, The microcontroller contains an analog-to-digital converter, an analog comparator, an event system, a hardware delay timer, a direct memory access controller, a multiply-accumulate unit, a wideband adjoint integral chain, a conventional metering register, and a pollution energy isolation register. The analog-to-digital converter is connected to the voltage sampling branch and the current sampling branch to form the main calculation channel, which outputs a smooth fundamental envelope sequence and forms an active power integral snapshot. The analog comparator is connected to the current sampling branch to form a physical auxiliary channel, which outputs a physical transition edge pulse train. The microcontroller determines the width of the shielding window based on the smooth fundamental envelope sequence and performs hardware filtering on the physical transition pulse train to determine the true physical timestamp; The event system controls the hardware delay timer based on the real physical timestamp and group delay constant. At the boundary moment, it triggers the direct memory access controller to capture the active power integral snapshot and clear it. The wideband accompanying integral chain forms a wideband integral snapshot. The direct memory access controller writes the corresponding data into the conventional metering register or the pollution energy isolation register based on the difference between the active power integral snapshot and the wideband integral snapshot.

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