Temperature control method and system of integrated circuit

Abstract

The invention relates to the technical field of data acquisition control, and discloses a temperature control method and system for an integrated circuit, and the method comprises the steps: obtaining the real-time temperature of the surface of a chip, a heterogeneous core identifier, a physical coordinate, and a heat dissipation path parameter; correlating the correction data to generate a temperature distribution map and a feature matrix, identifying a hot spot region and sequencing the core needing to be intervened; a high-load core is judged and migrated to a low-temperature high-heat-dissipation area, and the working frequency of the core is adjusted to guarantee clock synchronization; and tracking temperature change to calculate a global variance, and optimizing load distribution if the global variance exceeds a threshold value to obtain a final temperature control scheme. According to the method, accurate dynamic temperature control of the integrated circuit can be realized, and the requirement of data acquisition on the stability of a high-performance chip is met.

Description

Technical Field

[0001] This invention relates to the field of data acquisition and control technology, and in particular to a temperature control method and system for integrated circuits. Background Technology

[0002] Currently, in the field of data acquisition and control, with the continuous improvement of integrated circuit integration and the widespread application of heterogeneous core architecture, chip temperature control, as a core link to ensure the stable operation of high-performance computing, is directly related to the service life and computing throughput of integrated circuits.

[0003] Current integrated circuit temperature control methods in the industry mainly rely on global uniform frequency reduction or coarse-grained task migration. Examples include triggering large-scale frequency reduction with a fixed threshold, randomly migrating tasks to idle cores according to preset rules, or ignoring differences in core heat dissipation paths for uniform load distribution. However, this approach is clearly insufficient in complex operating environments. Global frequency reduction wastes a large amount of computing resources from idle cores, and coarse-grained migration does not consider differences in core heat dissipation capabilities, easily leading to the formation of new hotspots. Furthermore, the lack of precise identification and coordinated control of local hotspots makes it difficult to balance temperature uniformity and computing performance. Especially in high-load heterogeneous core scenarios, local cores are prone to triggering thermal saturation protection and may also transmit interference through the clock tree, causing overall performance fluctuations.

[0004] In summary, existing technologies are insufficient to achieve precise dynamic temperature control of integrated circuits, and cannot meet the requirements of data acquisition for high-performance chip stability. Summary of the Invention

[0005] This invention provides a temperature control method and system for integrated circuits to achieve precise dynamic temperature control of integrated circuits and meet the requirements of data acquisition for high-performance chip stability.

[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a temperature control method for an integrated circuit, comprising: Acquire real-time temperature data, heterogeneous core identifiers, physical coordinates of heterogeneous cores, and heat dissipation path parameters for each region on the chip surface; The real-time temperature data is correlated with the physical coordinates, and the correlated temperature data is corrected by combining the heat dissipation path parameters to generate a dynamic temperature distribution map. The feature matrix of the temperature distribution is extracted based on the map. Calculate the full-field temperature gradient vector based on the feature matrix, and extract the connected regions whose gradient magnitude exceeds the preset thermal anomaly threshold as hotspot regions. Monitor the real-time core temperature of the hotspot area, calculate the deviation between the real-time core temperature and the preset heat saturation threshold, sort the cores corresponding to the hotspot area according to the deviation value, and obtain a core identification list that needs intervention; By combining the core identifier list with the load rate of the heterogeneous cores monitored in real time, if the load rate exceeds a preset load judgment threshold, it is determined to be a high-load core. The region with a temperature lower than a preset low temperature threshold and a heat dissipation capacity higher than a preset heat dissipation capacity threshold is selected as the target region. The tasks of the high-load core are then migrated to the target region to adjust the core layout. Monitor the clock synchronization deviation of each core under the adjusted core layout. If the clock synchronization deviation exceeds the preset timing deviation threshold, adjust the operating frequency of the corresponding core to obtain stable operating parameters. The chip surface temperature changes under the stable operating parameters are tracked, and the variance of the global temperature is calculated. If the variance exceeds the preset temperature variance threshold, the load distribution of the heterogeneous cores is optimized to obtain the final temperature control scheme.

[0007] In a second aspect, the present invention provides an integrated circuit temperature control system, comprising: The data acquisition module is used to acquire real-time temperature data of various regions on the chip surface, heterogeneous core identifiers, physical coordinates of heterogeneous cores, and heat dissipation path parameters. The matrix generation module is used to associate the real-time temperature data with the physical coordinates, and to correct the associated temperature data by combining the heat dissipation path parameters, thereby generating a dynamic temperature distribution map, and extracting the feature matrix of the temperature distribution based on the map. The hotspot identification module is used to calculate the full-field temperature gradient vector based on the feature matrix and extract connected regions whose gradient magnitude exceeds a preset thermal anomaly threshold as hotspot regions. The list generation module is used to monitor the real-time core temperature of the hot spot area, calculate the deviation value between the real-time core temperature and the preset heat saturation threshold, sort the cores corresponding to the hot spot area according to the deviation value, and obtain a list of core identifiers that need intervention. The load determination module is used to combine the core identifier list with the load rate of the heterogeneous cores monitored in real time. If the load rate exceeds the preset load determination threshold, it is determined to be a high-load core. The core adjustment module is used to select areas with temperatures below a preset low temperature threshold and heat dissipation capacity above a preset heat dissipation capacity threshold as target areas, and migrate the tasks of the high-load core to the target areas to obtain an adjusted core layout. The frequency adjustment module is used to monitor the clock synchronization deviation value of each core under the adjusted core layout. If the clock synchronization deviation value exceeds the preset timing deviation threshold, the operating frequency of the corresponding core is adjusted to obtain stable operating parameters. The load optimization module is used to track the chip surface temperature change under the stable operating parameters and calculate the global temperature variance. If the variance exceeds the preset temperature variance threshold, the load distribution of the heterogeneous cores is optimized to obtain the final temperature control scheme.

[0008] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention obtains real-time temperature data of the chip surface, physical coordinates of the heterogeneous core and heat dissipation path parameters, associates temperature with spatial position and combines thermal resistance correction, generates dynamic temperature distribution map and extracts feature matrix, calculates temperature gradient vector to identify hot spot areas, breaks through the limitation of traditional coarse-grained temperature monitoring that cannot accurately locate local hot spots, explores the spatial distribution and heat dissipation difference characteristics of chip temperature, eliminates temperature misjudgment interference caused by heat dissipation path differences, provides high-precision basic data support for temperature control, effectively improves the identification accuracy of local hot spot areas, and solves the problem of global frequency reduction and waste of computing resources.

[0009] (2) The present invention sorts the cores that need intervention by temperature deviation, determines the high load cores by load rate, screens the low temperature and high heat dissipation area migration tasks, monitors the clock synchronization deviation and adjusts the core working frequency, breaks through the limitations of traditional single task migration or fixed frequency reduction, accurately captures the load characteristics and heat dissipation capacity differences of heterogeneous cores, provides multi-dimensional basis for temperature control, significantly improves the balance accuracy of temperature and performance under complex working conditions, and makes up for the defects of traditional methods that are prone to causing new hot spots or performance fluctuations.

[0010] (3) This invention tracks the chip temperature change under stable operating parameters, calculates the global temperature variance, optimizes the heterogeneous core load distribution when the threshold is exceeded, breaks through the limitations of traditional lack of dynamic feedback and load coordination, provides a basis for precise dynamic temperature control of integrated circuits, solves the problems of uneven heat distribution and local heat saturation, takes into account both temperature stability and computing throughput, and meets the dual requirements of high-performance chips for stability and performance. Attached Figure Description

[0011] Figure 1 This is a schematic flowchart of a temperature control method for an integrated circuit provided in the first embodiment of the present invention; Figure 2 This is a schematic diagram of an integrated circuit temperature control system provided in the second embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] Reference Figure 1 The first embodiment of the present invention provides a temperature control method for an integrated circuit, comprising the following steps: S11, acquire real-time temperature data of each area on the chip surface, heterogeneous core identifier, physical coordinates of the heterogeneous core and heat dissipation path parameters; S12, associate the real-time temperature data with the physical coordinates, and correct the associated temperature data in combination with the heat dissipation path parameters to generate a dynamic temperature distribution map, and extract the feature matrix of the temperature distribution based on the map; S13, calculate the full-field temperature gradient vector based on the feature matrix, and extract the connected regions whose gradient magnitude exceeds the preset thermal anomaly threshold as hotspot regions; S14, monitor the real-time core temperature of the hotspot area, calculate the deviation between the real-time core temperature and the preset heat saturation threshold, sort the cores corresponding to the hotspot area according to the deviation value, and obtain a core identification list that needs intervention; S15, combining the core identifier list with the real-time monitored load rate of heterogeneous cores, if the load rate exceeds the preset load judgment threshold, it is judged as a high load core. S16, select areas with temperatures below a preset low temperature threshold and heat dissipation capacity above a preset heat dissipation capacity threshold as target areas, migrate the tasks of the high-load core to the target areas, and obtain an adjusted core layout. S17, monitor the clock synchronization deviation value of each core under the adjusted core layout. If the clock synchronization deviation value exceeds the preset timing deviation threshold, adjust the working frequency of the corresponding core to obtain stable operating parameters. S18, track the chip surface temperature change under the stable operating parameters and calculate the global temperature variance. If the variance exceeds the preset temperature variance threshold, optimize the load distribution of heterogeneous cores to obtain the final temperature control scheme.

[0014] In step S11, real-time temperature data of each region on the chip surface, heterogeneous core identifiers, physical coordinates of the heterogeneous cores, and heat dissipation path parameters are acquired, including: Real-time temperature data of various areas on the chip surface is collected through a distributed sensor network. Retrieve the preset heterogeneous core identifier and its corresponding physical coordinates; Obtain the heat dissipation path parameters that are fixed during the chip design stage. The heat dissipation path parameters include thermal resistance values ​​and heat conduction path distribution.

[0015] It should be noted that, firstly, real-time temperature data of various areas on the chip surface is collected through a distributed sensor network. A distributed acquisition network is constructed using miniature thermistor sensors, arranged in a grid uniformly according to the chip's physical layout. In areas with high heat generation, the grid spacing can be reduced to achieve a denser arrangement, ensuring spatial accuracy of temperature acquisition. The sampling frequency is set based on the effective response range of the chip's dynamic temperature changes. According to measured statistics of the thermal time constant of silicon-based materials and the thermal impedance characteristics of the package, due to the "low-pass filtering" physical effect of material thermal conduction, high-frequency power transients are smoothed by thermal capacitance. The effective components of rapid temperature fluctuations are mainly concentrated in the 0-10Hz range. Therefore, based on the Nyquist sampling theorem and with a certain margin, the basic sampling frequency is set to 100Hz, which can both fully capture real-time temperature changes and avoid redundant data caused by high-frequency sampling. Those skilled in the art will understand that this sampling frequency can be adjusted within the range of 50Hz to 200Hz depending on the severity of chip load fluctuations.

[0016] Secondly, when retrieving the preset heterogeneous core identifiers and their corresponding physical coordinates, the heterogeneous core identifiers and physical coordinates are pre-calibrated based on the chip's physical layout and stored in the chip's local control memory unit in the form of a structured data table. The data table includes key fields such as a unique identifier code and two-dimensional physical coordinates with the chip's geometric center as the origin. Before the chip leaves the factory, the coordinate data undergoes secondary calibration based on the packaging process to improve coordinate matching accuracy. The retrieval process is completed through the chip's dedicated control bus, controlling the read latency to within 1μs to meet the real-time requirements of temperature control. After reading, the data undergoes uniqueness verification to ensure that each identifier has a corresponding unique physical coordinate, avoiding data corruption. For example, the physical coordinates corresponding to identifier C3 are quickly retrieved from the local control memory unit as (2.5mm, 3.0mm), and the physical coordinates corresponding to identifier C11 are (-4.0mm, -2.0mm). After uniqueness verification, all identifiers and coordinates correspond one-to-one, without duplication or corruption, and can be directly used for subsequent correlation analysis of temperature data and spatial location.

[0017] Next, the heat dissipation path parameters fixed during the chip design stage are obtained. These parameters include thermal resistance values ​​and heat conduction path distribution values. These parameters are calibrated using professional thermal simulation software during the chip design stage and then stored in the chip's firmware storage area. The thermal resistance values ​​cover various thermal resistance data, such as the volume thermal resistance of each layer of chip materials and the interface thermal resistance between different materials. The heat conduction path distribution is stored in the form of a topology diagram, clearly marking the main conduction paths of heat from each heat-generating unit to the heat dissipation end.

[0018] Data is retrieved via the chip's dedicated firmware read interface, directly preserving the original physical dimensions of thermal resistance (K / W). This facilitates subsequent calculations combining it with temperature data for accurate physical corrections. Simultaneously, the topology of the heat conduction path distribution is converted into a digital path matrix, adaptable to subsequent data processing logic. For example, the bulk thermal resistance of the silicon layer in the computation area retrieved from the chip firmware storage is 1.2 K / W, and the interface thermal resistance between silicon and the bottom heatsink is 0.8 K / W. This raw thermal resistance data, along with the converted path matrix, clearly characterizes the thermal conductivity relationships between different regions.

[0019] In step S12, the process of associating the real-time temperature data with the physical coordinates, and correcting the associated temperature data by combining the heat dissipation path parameters, generates a dynamic temperature distribution map. The feature matrix of the temperature distribution is then extracted based on the map, including: By associating the real-time temperature data with the physical coordinates, raw temperature data with spatial location information is generated. Based on the thermal resistance value in the heat dissipation path parameters, the original temperature data is corrected to obtain corrected temperature data that reflects the difference in heat dissipation. Spatial interpolation is performed on the corrected temperature data to generate a continuous dynamic temperature field, which is then transformed into a dynamic temperature distribution map. Extract the temperature peak, gradient change, and hotspot distribution information from the temperature distribution map, construct a temperature distribution feature matrix to associate the real-time temperature data with the physical coordinates, and correct the associated temperature data by combining the heat dissipation path parameters to generate a dynamic temperature distribution map. Extract the temperature distribution feature matrix from the map, including: By associating the real-time temperature data with the physical coordinates, raw temperature data with spatial location information is generated. Based on the thermal resistance value in the heat dissipation path parameters, the original temperature data is corrected to obtain corrected temperature data that reflects the difference in heat dissipation. Spatial interpolation is performed on the corrected temperature data to generate a continuous dynamic temperature field, which is then transformed into a dynamic temperature distribution map. Extract the temperature peaks, gradient changes, and hotspot distribution information from the temperature distribution map to construct a feature matrix of the temperature distribution.

[0020] It should be noted that, firstly, real-time temperature data is associated with physical coordinates. Based on the deployment mapping relationship of the sensor network, each temperature sensor has a unique identifier code. This code is pre-bound to two-dimensional coordinates in the chip's physical layout (with the chip's geometric center as the origin) and stored in a local configuration table. The association process matches the sensor identifier with the coordinate information in the configuration table, mapping each real-time acquired temperature data point to its corresponding spatial location, forming a "temperature-coordinate" binary data entry. Simultaneously, invalid entries with failed coordinate matching or missing temperature data are discarded to ensure the integrity of the original data.

[0021] For example, a sensor collects a real-time temperature of 85℃, and its identifier code matches the physical coordinates (2.5mm, 3.0mm). The generated original temperature data entry after association is (85℃, 2.5mm, 3.0mm), which clearly marks the spatial location attribute of the temperature.

[0022] Next, the original temperature data is corrected based on the thermal resistance value in the heat dissipation path parameters. In the real physical environment of a chip, the relationship between local temperature and thermal resistance is not a simple linear one. An increase in thermal resistance not only leads to a decrease in basic heat conduction efficiency but also triggers a local "temperature-power positive feedback effect," where local high temperatures cause an exponential increase in transistor leakage current, resulting in additional secondary heat accumulation. Therefore, the correction logic abandons a simple fixed linear proportional coefficient and adopts a nonlinear thermal resistance correction model based on the "thermal-electric coupling effect."

[0023] Specifically, the system sets a reference thermal resistance for the chip (e.g., 1.0 K / W). When the actual thermal resistance of the region is greater than the reference thermal resistance, the temperature is corrected upwards to reflect thermal congestion; when it is less than the reference thermal resistance, it is corrected downwards to reflect heat dissipation advantages. The specific temperature correction amount is calculated using the following formula: in, The corrected temperature; The actual thermal resistance of the region is obtained directly from the heat dissipation path parameters fixed during the chip design stage, and the unit is K / W; The reference thermal resistance is determined by the chip's global average thermal resistance and can be calibrated by measuring the chip's average temperature rise under uniform power consumption. A typical value is 1.0 K / W. This is the basic heat flux mapping coefficient. It represents the change in heat flux caused by a unit thermal resistance difference without positive feedback, in W; this coefficient is preset based on the typical power consumption density and thermal capacity characteristics of the chip, for example, estimated based on the ratio of the chip's rated power consumption to average thermal resistance, with a typical range of 0.3 to 0.8 W; Temperature-leakage current coupling coefficient, in °C -1It can be calibrated through offline experiments. One calibration method is to measure the static power consumption (or leakage current) I at different temperature points under constant voltage conditions. l Fit ln(I) l The relationship between temperature and the slope is... Typical values ​​are between 0.01 and 0.05℃. -1 between; The actual raw temperature collected, in °C. The ambient reference temperature is usually taken as the base temperature of the chip's operating environment (such as 25°C), which can be monitored in real time by the temperature sensor on the board or set to a fixed value.

[0024] Subsequently, spatial interpolation is performed on the corrected temperature data to generate a continuous dynamic temperature field. When transforming this into a dynamic temperature distribution map, inverse distance-weighted interpolation (IDW) is employed. This technique estimates the temperature value by calculating the distance weights between the interpolation point and surrounding known data points; the closer the distance, the greater the weight, resulting in an interpolation result that more closely matches the actual temperature distribution. The number of neighborhood points for interpolation is set to 8, meaning each interpolation point references 8 of its nearest corrected temperature data points. This number is empirical; for scenarios requiring high interpolation accuracy, it can be increased to 10, while for scenarios requiring high real-time performance, it can be reduced to 6. The time update cycle of the dynamic temperature field is consistent with the temperature sampling frequency (100Hz) to ensure that the temperature field reflects chip temperature changes in real time.

[0025] Then, the continuous temperature field is transformed into a dynamic spectrum using 3D visualization technology. The horizontal and vertical axes represent the chip's physical coordinates, and the vertical axis represents the temperature value. For example, there are temperature gaps between the corrected discrete temperature data points. After IDW interpolation, the gaps are transformed into continuous temperature estimates, smoothly transitioning from 85.024℃ in the core region to 64.984℃ in the edge region. The transformed dynamic spectrum visually presents the temperature distribution gradient on the chip surface.

[0026] Finally, the temperature peak, gradient change and hot spot distribution information of the temperature distribution map are extracted to construct the temperature distribution feature matrix. The dimension of the feature matrix is ​​determined according to the temperature sampling grid of the chip. The number of rows is equal to the total number of sampling grids, and the number of columns is fixed at 3, which correspond to the three key features of temperature peak, gradient change and hot spot distribution.

[0027] It should be noted that the temperature peak is the highest temperature value within each sampling grid; the gradient change is the average of the temperature difference between the current grid and the adjacent grids, reflecting the degree of drastic local temperature change; the hotspot distribution is represented in binary form, and when the grid temperature peak exceeds the preset hotspot candidate threshold (the basic threshold is set to 80℃, which can be adjusted according to the chip's tolerance temperature range of 75℃ to 85℃), it is marked as 1, otherwise it is marked as 0.

[0028] It's worth noting that the hotspot candidate threshold was not set by guesswork, but rather determined based on the temperature decay characteristics of carrier mobility in silicon-based chips and the thermal stress fatigue boundary. When the local temperature of a silicon-based chip reaches 80°C, carrier mobility begins to decay significantly non-linearly, leading to increased gate delay and potentially triggering timing violations. This temperature also marks the inflection point where interlayer thermal stress in the packaging material rises sharply. Therefore, setting 80°C as the base threshold allows for early marking and intervention before this region evolves into a destructive hotspot. In practical applications, for high-performance computing chips with advanced packaging and high heat resistance, this threshold can be increased to 85°C; for low-power mobile chips that are extremely sensitive to power consumption and leakage current, the threshold needs to be lowered to 75°C.

[0029] For example, if the peak temperature of a certain sampling grid is 87℃ and the average temperature difference with the adjacent grid is 5℃ / mm, and it exceeds the hotspot candidate threshold, the corresponding row data in the feature matrix is ​​[87℃, 5℃ / mm, 1]. The entire feature matrix fully integrates the core information of temperature distribution, providing data support for subsequent hotspot identification.

[0030] In step S13, the full-field temperature gradient vector is calculated based on the feature matrix, and connected regions whose gradient magnitude exceeds a preset thermal anomaly threshold are extracted as hotspot regions, including: Calculate the full-field temperature gradient vector based on the aforementioned feature matrix; The gradient magnitude is calculated based on the full-field temperature gradient vector. Discrete points whose gradient magnitude exceeds a preset thermal anomaly threshold are extracted. Connectivity analysis is performed on the discrete points to form independent connected regions. The independent connected regions are spatially matched with the preset chip physical layout to determine hotspot regions.

[0031] It should be noted that, firstly, the overall temperature gradient vector is calculated based on the temperature distribution feature matrix. When the magnitude of the temperature gradient vector reflects the severity of local temperature changes, the two-dimensional temperature gradient components at each sampling point on the chip surface are calculated using the temperature gradient change information stored in the feature matrix and the chip's spatial coordinate information. These components represent the rate of temperature change in the x-axis and y-axis directions, respectively. The components in these two directions are then combined to form the overall temperature gradient vector. The magnitude of the gradient vector is obtained by performing a modulo operation on the two-dimensional components. Its value directly represents the severity of local temperature changes; a larger magnitude indicates a more pronounced temperature change. To ensure the intuitiveness and consistency of the data in subsequent physical threshold determination, the original physical dimensions (°C / mm) of the temperature gradient magnitude are directly retained without normalization. For example, if the x-axis gradient component at a sampling point is 4°C / mm and the y-axis gradient component is 3°C / mm, the magnitude of the synthesized gradient vector is 5°C / mm. This physical value is directly used as a feature in subsequent analysis, clearly reflecting the severity of temperature changes at that point.

[0032] When extracting discrete points whose gradient magnitude exceeds a preset thermal anomaly threshold, and performing connected component analysis to form independent connected regions, the thermal anomaly threshold is set based on the temperature gradient magnitude distribution range during normal chip operation. During normal chip operation, the temperature gradient magnitude in areas without thermal anomalies is mainly concentrated between 0-5℃ / mm, therefore the basic threshold is set to 5℃ / mm. For highly integrated heterogeneous chips with higher heat density, the threshold can be increased to 6℃ / mm, while for ordinary low-power integrated circuits it can be decreased to 4℃ / mm. Those skilled in the art know that this threshold can be flexibly adjusted according to the chip's process node and power consumption characteristics. After extracting all discrete sampling points whose magnitude exceeds this threshold, the eight-neighborhood connectivity analysis method is used to aggregate these discrete points, grouping adjacent anomalous discrete points into the same region, ultimately forming multiple independent connected regions, each representing a potential thermal anomaly region. For example, if 20 discrete points on the chip surface have gradient magnitudes exceeding the basic threshold of 5℃ / mm, after eight-neighborhood connectivity analysis, these points are aggregated into three independent connected regions, each containing a different number of discrete points: 12, 5, and 3, respectively.

[0033] Spatial matching of independent connected regions with the chip physical layout is performed to determine hotspot areas. The two-dimensional coordinates of the independent connected regions and the chip physical layout use the same coordinate system, with the chip's geometric center as the origin. Before matching, an affine transformation calibration based on reference markers is performed. This involves extracting the coordinates of the Fiducial Marks reserved on the chip physical layout and the coordinates of the physical mounting reference points of the sensor network array, calculating a transformation matrix including translation and minor rotations, and thus calibrating and correcting the coordinates of the connected regions. This step effectively eliminates minor coordinate deviations caused by sensor mounting drift and manufacturing tolerances, ensuring absolute matching accuracy of hotspot locations on the silicon wafer.

[0034] The matching process maps the coordinate range of connected regions to the physical layout, clarifying the specific location, coverage area, and surrounding device distribution of each connected region in the actual physical layout of the chip. If the mapped connected region corresponds to the main heat-generating area of ​​the chip and its coverage area reaches the preset minimum hot spot area, then the connected region is officially identified as the hot spot area of ​​the chip. It should be noted that this minimum hot spot area (base value 0.5 mm²) is not arbitrarily set, but is determined based on the characteristic spatial scale of thermal coupling effects in integrated circuit design and the physical area of ​​the minimum power control domain. When the area of ​​the heat-generating region is extremely small, due to the extremely high lateral thermal conductivity of silicon-based materials, the heat will be quickly distributed without causing deep, continuous thermal damage; only when the accumulated area reaches a certain scale—for example, the cluster area of ​​an ALU logic cluster in a standard heterogeneous computing core is typically around 0.5 mm²—will it exceed the material's own heat dissipation limit, triggering local thermal saturation.

[0035] Therefore, setting the base value to 0.5 mm² can effectively filter out harmless transient micro-hot spots. In practical applications, for big core architectures, this threshold can be increased to 1.0 mm²; for high-density little core architectures, it can be decreased to 0.2 mm².

[0036] In step S14, the real-time core temperature of the hotspot area is monitored, and the deviation between the real-time core temperature and a preset heat saturation threshold is calculated. The cores corresponding to the hotspot area are sorted according to the deviation value to obtain a core identifier list that requires intervention, including: Monitor the real-time core temperature of the hotspot area, calculate the deviation between the real-time core temperature and a preset heat saturation threshold, and sort the cores corresponding to the hotspot area according to the deviation value to obtain a list of core identifiers requiring intervention, including: Monitor the real-time temperature of the core corresponding to the hot spot area, calculate the difference between the real-time temperature of the core and the preset heat saturation threshold, and obtain the temperature deviation value of each core. The temperature deviation values ​​are assigned sorting weights from largest to smallest to generate a sequence to be processed. Identify the cores in the sequence to be processed whose temperature deviation values ​​exceed a preset critical deviation threshold, and combine them to form a core identifier list that requires intervention.

[0037] It should be noted that, firstly, the real-time temperature of the hot spot area corresponding to the marker relies on a distributed network of miniature thermistor sensors deployed on the chip surface to complete the temperature monitoring. The sampling frequency is kept consistent with the previous temperature acquisition at 100Hz. The heterogeneous markers of the hot spot area are determined by spatial mapping of the chip physical layout, and each marker corresponds to a unique temperature acquisition channel.

[0038] Subsequently, when establishing the correspondence, it is stored in the form of structured key-value pairs, with the key being a heterogeneous identifier and the value being the temperature data collected in real time. At the same time, data validity verification is carried out to remove abnormal data that has exceeded the sampling timeout or whose values ​​exceed the normal operating temperature range of the chip, ensuring that each identifier matches the valid temperature data.

[0039] For example, the heterogeneous identifiers C3 and C5 in the hotspot area correspond to dedicated temperature acquisition channels. The real-time acquired temperatures are 89℃ and 86℃, respectively. The established key-value pair is {C3:89℃, C5:86℃}. After verification, there is no abnormal data, and it can be directly used for subsequent deviation calculation.

[0040] Next, the difference between the real-time temperature of the identifier and the preset thermal saturation threshold is calculated to obtain the temperature deviation value for each identifier. The thermal saturation threshold is set based on the chip's process node, leakage current temperature sensitivity, and heat resistance characteristics. From the perspective of semiconductor physics, thermal saturation means that the local temperature of the chip is approaching the thermal runaway boundary. At this point, the static leakage power consumption of the transistor will increase exponentially, while the carrier mobility will drop sharply, which can easily cause severe timing delays or even hardware-level crashes. During normal chip operation, the reasonable range of this physical critical point is concentrated between 80-90℃, so the basic threshold is set at 85℃. For chips with advanced integration processes such as 7nm, the threshold can be raised to 90℃, while for chips with low-power processes, it can be lowered to 80℃. Those skilled in the art know that this threshold can be flexibly adjusted within the range of 75-95℃ according to the chip's design power consumption. The temperature deviation value is obtained by subtracting the thermal saturation threshold from the real-time temperature of the identifier. A positive value indicates that the temperature exceeds the threshold, and a negative value indicates that it is within the safe range. After calculation, the deviation value is retained to one decimal place to ensure data accuracy. For example, if the heat saturation threshold is set to 85℃, and the real-time temperature of C3 is 89℃, the calculated deviation value is 4.0℃. If the real-time temperature of C5 is 86℃, the deviation value is 1.0℃. The deviation values ​​of both labels are positive, indicating that the temperature has exceeded the heat saturation threshold.

[0041] Subsequently, sorting weights are assigned according to the temperature deviation values ​​from largest to smallest. When generating the sequence to be processed, the sorting weights are linearly positively correlated with the temperature deviation values; the larger the deviation value, the higher the corresponding weight value. The basic weight coefficient is set to 0.2, meaning that for every 1°C increase in deviation value, the weight value increases by 0.2. This coefficient can be adjusted within the range of 0.1-0.3 according to the priority requirements of temperature control. After assigning weights to each identifier, the heterogeneous identifiers are strictly sorted in descending order of weight values ​​to generate the sequence to be processed. Only identifiers with positive deviation values ​​are retained in the sequence; identifiers with negative deviation values ​​are directly discarded and do not need to be included in the subsequent processing.

[0042] For example, if the deviation value of identifier C3 is 4.0℃ and the corresponding weight value is 0.8, and the deviation value of identifier C5 is 1.0℃ and the corresponding weight value is 0.2, after sorting them from high to low weight, the generated sequence to be processed is [C3, C5], and there are no identifiers that need to be removed.

[0043] Finally, identifiers in the sequence to be processed whose temperature deviation values ​​exceed a preset critical deviation threshold are identified and combined to form a list of identifiers requiring intervention. The critical deviation threshold is set based on the chip's thermal protection trigger threshold. The critical deviation range for the chip to approach the thermal protection mechanism is 3-5℃, so the basic threshold is set to 3℃. For chips with high heat resistance, the threshold can be increased to 5℃, while for chips using ordinary processes, it can be decreased to 2℃. Those skilled in the art know that this threshold can be adjusted within the range of 2-5℃ according to the chip's thermal protection parameters. Then, all identifiers in the sequence to be processed are traversed, and identifiers whose deviation values ​​exceed the critical deviation threshold are filtered out. These identifiers are combined according to the original sequence's sorting order to form a list of identifiers requiring intervention. Identifiers whose deviation values ​​do not exceed the threshold are not included for the time being, and are only continuously monitored in real time. For example, if the critical deviation threshold is set to 3℃, identifier C3 in the sequence to be processed has a deviation value of 4.0℃, which exceeds the threshold, while identifier C5 has a deviation value of 1.0℃, which does not exceed the threshold. Therefore, the combined list of identifiers requiring intervention is [C3], and subsequent temperature control intervention operations are only performed on this identifier.

[0044] In step S15, combining the core identifier list with the real-time monitored load rate of heterogeneous cores, if the load rate exceeds a preset load determination threshold, it is determined to be a high-load core, including: The load status of each core in the core identifier list is monitored in real time, and the load rate of the core is calculated. If the load rate exceeds the preset load determination threshold, then the core is confirmed as a high-load core.

[0045] It should be noted that, firstly, the load status of each identifier in the real-time monitoring identifier list relies on the on-chip power monitoring unit and instruction throughput acquisition module integrated into the chip to complete the load status monitoring. The two modules work together, and the sampling frequency is set to 50Hz, which can accurately capture real-time changes in load without consuming too many chip resources due to high-frequency sampling.

[0046] The load rate is calculated by dividing the actual computing power usage of the identifier by its maximum computing power capacity. The result is presented as a percentage. To avoid calculation errors caused by instantaneous load fluctuations, a moving average is applied to five consecutive sampling points to smooth the data before determining the final load rate. Abnormal sampling data where the computing power usage exceeds the maximum capacity is also removed to ensure the validity of the calculation result. For example, if the maximum computing power capacity of identifier C3 is 100 MIPS, and the instruction throughput collected from five consecutive sampling points is 83, 86, 85, 84, and 87 MIPS respectively, a moving average is obtained at 85 MIPS, resulting in a load rate of 85%. With no abnormal data, the result can be directly used for subsequent judgment.

[0047] If the load rate exceeds the preset load judgment threshold, the identified core is confirmed as a high-load core. The load judgment threshold is set based on the load distribution range during normal chip operation. Under normal operating conditions, the chip has no high-load normal operation area, and the load rate is mainly concentrated between 0% and 70%. Therefore, the basic threshold is set to 70%. For heterogeneous chips designed for high computing power scenarios, the threshold can be increased to 80% due to their stronger computing power capacity. For chips used in low-power applications, the threshold can be lowered to 60% to avoid overheating issues caused by excessive load. This threshold can be flexibly adjusted within the range of 60% to 80% according to the chip's design computing power and actual application scenarios. During judgment, the smoothed load rate is directly compared with the threshold. If the load rate exceeds the threshold, the task running on that core is directly confirmed as a high-load core; otherwise, it is determined as a normal-load core. For example, if the load judgment threshold is set to 70%, and the load rate of identifier C3 is 85%, exceeding the threshold, the task running on that core is confirmed as a high-load core. The load rate of another identifier, C5, is calculated to be 65%, which does not reach the threshold and is not determined as a high-load core.

[0048] In step S16, regions with temperatures below a preset low-temperature threshold and heat dissipation capabilities above a preset heat dissipation capability threshold are selected as target regions. The tasks of the high-load cores are then migrated to these target regions to adjust the core layout, including: Collect real-time temperature and heat dissipation parameters of each core in non-hotspot areas of the chip; Cores whose real-time temperature is lower than a preset low-temperature threshold and whose heat dissipation capacity parameter is higher than a preset heat dissipation capacity threshold are selected to form a target core set; Establish a remapping relationship between the high-load cores and the cores in the target core set, execute scheduling instructions, and adjust the core layout.

[0049] It should be noted that, firstly, when collecting real-time temperature and heat dissipation parameters of each marker in the non-hotspot areas of the chip, the real-time temperature is collected using a distributed network of miniature thermistor sensors on the chip surface. The sampling frequency remains consistent with the previous temperature monitoring at 100Hz. Data collection is only performed on markers in the identified non-hotspot areas to avoid invalid sampling and resource consumption. The heat dissipation parameters are retrieved from the firmware storage area fixed during the chip design phase, including core heat dissipation indicators such as thermal conductivity and reciprocal of thermal resistance for each area. Real-time data from the on-chip thermal flow monitoring module is also used for supplementation and correction.

[0050] After data acquisition, the heat dissipation parameters are processed using minimum-maximum normalization, mapping them to the [0,1] interval. Specifically, the effective thermal conductivity (W / K) is selected as the quantification index, and normalization boundaries are set: the lowest thermal conductivity at the chip edge relying solely on natural convection (e.g., 0 W / K) is used as the lower limit, and the theoretical maximum thermal conductivity of the active heat dissipation path directly connected to the heat sink in the core area (e.g., 10.0 W / K) is used as the upper limit. The minimum-maximum normalization method ensures that a larger value indicates better heat dissipation conditions in that area. Temperature data retains actual measured values, while abnormal sampled values ​​exceeding the chip's normal operating temperature range are simultaneously removed to ensure data validity.

[0051] For example, the real-time temperatures of the non-hotspot areas C11 and C14 on the acquisition chip were 68℃ and 70℃, respectively. The effective thermal conductivity values ​​retrieved and corrected from the firmware storage were 9.0 W / K and 8.5 W / K, respectively. Substituting these values ​​into the formula, the normalized value for C11 was (9.0 - 0) / 10.0 = 0.9, and the normalized value for C14 was (8.5 - 0) / 10.0 = 0.85. All data showed no anomalies. These high heat dissipation scores indicate that this area is suitable for supporting high-load cores and can be directly used for subsequent screening.

[0052] Secondly, when selecting identifiers whose real-time temperature is lower than the preset low-temperature threshold and whose heat dissipation capacity parameter is higher than the preset heat dissipation capacity threshold to form a target identifier set, the low-temperature threshold is set based on the suitable temperature range for non-hotspot areas of the chip to bear high-load cores. During normal chip operation, the temperature at which non-hotspot areas can effectively bear high loads without rapid heat accumulation is mainly concentrated between 60-70℃, so the basic threshold is set to 70℃. For heterogeneous chips with high computing power requirements, the threshold can be increased to 75℃ due to their stronger computing power capacity; for chips in low-power application scenarios, the threshold can be decreased to 65℃ to further improve thermal safety margin. Those skilled in the art know that this threshold can be flexibly adjusted within the range of 65-75℃ according to the application scenario of the chip. The heat dissipation capacity threshold is set based on the normalized heat dissipation capacity parameter distribution. Areas that can effectively bear high-load cores must have high heat dissipation capacity, so the basic threshold is set to 0.8. High-computing-power scenarios have higher heat dissipation requirements, so the threshold can be increased to 0.85; ordinary computing scenarios can be decreased to 0.75, and this threshold can be adjusted within the range of 0.75-0.85. During the screening process, two conditions must be met simultaneously: the temperature must be below the low-temperature threshold and the heat dissipation capacity parameter must be above the heat dissipation capacity threshold. The identifiers that meet the conditions are sorted from high to low according to the heat dissipation capacity parameter to form a target identifier set.

[0053] For example, if the low temperature threshold is set to 70℃ and the heat dissipation capacity threshold is set to 0.8, the temperature of identifier C11 is 68℃ and the heat dissipation parameter is 0.9, and the temperature of identifier C14 is 70℃ and the heat dissipation parameter is 0.85, all of which meet the screening conditions. The target identifier set formed by sorting by heat dissipation parameter is [C11, C14].

[0054] Finally, a remapping relationship is established between high-load cores and the target core set. Scheduling instructions are executed, and when adjusting the core layout, the remapping relationship is constructed based on a precise match between the computing power requirements of high-load cores and the computing power capacity of target cores. Matching methods include one-to-one, many-to-one, and one-to-many collaborative mapping: a single high-computing-power, high-load core corresponds to a single target core with sufficient computing power; multiple low-computing-power, high-load cores are merged and mapped to the same target core; when the computing power capacity of a single target core is insufficient to meet the overall computing power requirements of a high-load core, the system adopts a one-to-many mapping method, splitting the tasks of the high-load core and allocating them proportionally and weighted according to the available remaining computing power and heat dissipation capacity of multiple cores in the target set, with multi-node collaborative processing.

[0055] After matching is completed, a structured remapping table is generated, which contains key information such as high-load core ID, original running identifier, target identifier, and computing power allocation ratio.

[0056] For example, a high-load core's total computing power requirement is 120 MIPS, but the available computing power of a single node on the target cores C11 and C14 cannot meet this requirement independently. The system then splits the task and maps it to cores C11 and C14 for collaborative execution according to the ratio of their available computing power (e.g., 60% and 40%). After matching is completed, a remapping table is generated and scheduling instructions are issued. After verifying successful task migration, the remapping results of other high-load cores are combined to form a complete adjusted core layout.

[0057] In step S17, the clock synchronization deviation value of each core under the adjusted core layout is monitored. If the clock synchronization deviation value exceeds a preset timing deviation threshold, the operating frequency of the corresponding core is adjusted to obtain stable operating parameters, including: Read the rising edge timestamps of the clock signals of each core under the adjusted core layout; The deviation between the rising edge timestamp and the global clock reference is calculated to obtain the clock synchronization deviation value of each core; If the clock synchronization deviation value exceeds the preset timing deviation threshold, then a frequency reduction operation is performed on the corresponding core. The clock synchronization deviation value is continuously monitored until it falls below the timing deviation threshold, at which point the current operating frequency is determined to be a stable operating parameter.

[0058] It should be noted that, firstly, when reading the rising edge timestamp of each identifier clock signal under the core layout adjustment, the data reading is completed by relying on the high-precision clock signal acquisition module integrated in the chip. This module works synchronously with the chip's global clock crystal oscillator, with a sampling frequency set to 1GHz and an acquisition accuracy of nanosecond level, which can accurately capture the rising edge time of the clock signal.

[0059] It's worth noting that the reading process only targets identifiers with running tasks under the adjusted core layout, avoiding invalid data collection from idle identifiers. Simultaneously, the timestamps of the read data are calibrated to eliminate minor errors caused by module transmission delays, ensuring that all identifier timestamps are based on the same time base. The data is temporarily stored in time series format after reading for subsequent deviation calculations. For example, the rising edge timestamps of the clock signals for identifiers C11 and C14 in the adjusted layout are read as system base times T0+12.7 nanoseconds and T0+12.2 nanoseconds, respectively. After calibration, there is no time base deviation, and the data can be directly used for subsequent calculations.

[0060] Subsequently, the clock synchronization deviation value for each identifier is obtained by calculating the deviation between the rising edge timestamp and the global clock reference. The global clock reference is provided by the chip's high-precision crystal oscillator module, providing a unified time reference for the clock signals of all identifiers. The deviation value is calculated by the absolute value of the difference between the rising edge timestamp of each identifier and the global clock reference, and the result is rounded to one decimal place to ensure accuracy. To avoid misjudgment caused by instantaneous clock fluctuations, a moving average is applied to the deviation values ​​calculated from three consecutive sampling points to obtain the final clock synchronization deviation value after smoothing.

[0061] If the clock synchronization deviation exceeds the preset timing deviation threshold, a frequency decrement operation will be performed on the corresponding identifier. The timing deviation threshold is set based on the chip's timing margin range. During normal chip operation, a clock synchronization deviation within 0-0.5 nanoseconds can ensure timing stability without performance jitter. Therefore, the basic threshold is set to 0.5 nanoseconds. For heterogeneous chips with high computing power requirements, the threshold can be increased to 0.8 nanoseconds due to the larger timing margin. For chips in low-power application scenarios, the threshold can be decreased to 0.3 nanoseconds to improve timing stability. As those skilled in the art know, this threshold can be flexibly adjusted within the range of 0.3-0.8 nanoseconds according to the chip's process node and computing requirements.

[0062] The frequency reduction uses a stepped adjustment method, with a basic reduction step size set at 0.3 GHz. After each adjustment, the current frequency is maintained, and the adjusted frequency is not lower than the chip's minimum operating frequency to avoid excessive frequency reduction affecting computing performance. For example, if the timing deviation threshold is set to 0.5 nanoseconds, and the deviation value of indicator C11 is 0.7 nanoseconds, exceeding the threshold, a frequency reduction operation is performed on it, reducing it from 2.4 GHz to 2.1 GHz. The deviation value of indicator C14 is 0.2 nanoseconds, which does not exceed the threshold, and its original frequency remains unchanged.

[0063] Finally, continuously monitor the clock synchronization deviation value until it falls below the timing deviation threshold. Once the current operating frequency is determined to be a stable operating parameter, use the same monitoring frequency of 100Hz as before to continuously track the clock synchronization deviation value of the marker. After each frequency decrement operation on the marker, observe the deviation stability for at least 50 milliseconds to avoid misjudging the adjustment effect due to instantaneous fluctuations. When the deviation value remains consistently below the timing deviation threshold and remains stable, determine the current operating frequency of the marker as a stable operating parameter. Simultaneously, record the power supply voltage, power consumption, and other related parameters at this frequency to form a complete stable operating parameter set. Store the parameter set in the chip's local configuration storage area for subsequent task scheduling and parameter retrieval.

[0064] For example, after the frequency of the identifier C11 is reduced to 2.1 GHz, it is continuously monitored. After 200 milliseconds, its clock synchronization deviation value is stably reduced to 0.3 nanoseconds, which is lower than the threshold of 0.5 nanoseconds. Therefore, 2.1 GHz is determined to be the stable operating parameter of the identifier. At the same time, the corresponding power supply voltage of 1.025V and power consumption of 0.6W are recorded to form a complete parameter set and stored in the configuration area.

[0065] In step S18, the chip surface temperature change is tracked under the stable operating parameters, and the variance of the global temperature is calculated. If the variance exceeds a preset temperature variance threshold, the load distribution of the heterogeneous cores is optimized to obtain the final temperature control scheme, including: Track the real-time temperature of each core on the chip surface under the stable operating parameters, and construct a time series of temperature evolution; Calculate the global temperature variance based on the time series; If the global temperature variance exceeds a preset temperature variance threshold, then cores with temperatures higher than a preset high-heat determination threshold are extracted from the time series as high-heat cores. The static power consumption data and leakage current parameters of the high-heat core are collected to construct asymmetric power consumption characteristics; Based on the asymmetric power consumption characteristics, the frequency configuration and load distribution of each core are adjusted to generate a load distribution sequence between cores; The load distribution sequence is input into a preset thermal simulation model to calculate the predicted junction temperature. If the predicted junction temperature is lower than the preset safe junction temperature threshold, the final temperature control scheme is determined. If the predicted junction temperature is higher than or equal to the preset safe junction temperature threshold, the core frequency configuration and load distribution ratio are iteratively adjusted according to the preset step size until the predicted junction temperature is lower than the preset safe junction temperature threshold, and the corresponding scheme is determined as the final temperature control scheme.

[0066] It should be noted that, firstly, when tracking the real-time temperature of each marker on the chip surface under stable operating parameters, the temperature is collected by relying on the distributed micro thermistor sensor network deployed on the chip surface when constructing the time series of temperature evolution. The sampling frequency is kept at 100Hz, consistent with the previous monitoring. Full data collection is carried out for all markers that are in stable operating state and bound to tasks. Abnormal sampling points with temperature values ​​exceeding the normal operating range of the chip are removed to ensure the validity of the data.

[0067] The collected temperature data is arranged in order by timestamp, constructing an independent temperature data sequence for each identifier. A 5-second sliding time window is set, integrating all temperature data within the window to form a time series of temperature evolution. The sequence retains key information such as temperature values, collection timestamps, and identifier physical coordinates, intuitively reflecting the temperature change trend of each identifier over time. For example, the real-time temperatures of identifiers C11, C3, and C14 within the 5-second window are 77℃, 71℃, 76℃; 77.2℃, 71.5℃, 76.3℃; and 76.8℃, 71.2℃, 76.1℃, respectively. After being sorted by timestamp, a corresponding temperature evolution time series is constructed for each identifier, clearly presenting the small fluctuations in temperature.

[0068] Subsequently, when calculating the global temperature variance based on the time series, the temperature values ​​of all identifiers at the same time node are first extracted, the average temperature of the chip surface at that time node is calculated, and then the squared deviation of each identifier temperature from the average temperature is calculated one by one. The arithmetic mean of all the squared deviations is used to obtain the temperature variance of a single time node. Finally, the variances of all single time nodes within the sliding time window are averaged again to obtain the global temperature variance of the chip surface.

[0069] For example, based on the temperature evolution time series of each identifier within a 5-second time window, the temperature variances of each single time node are calculated to be 6.2℃², 6.8℃², and 6.5℃², respectively. After averaging, the global temperature variance is 6.5℃², which can be directly used for subsequent threshold determination.

[0070] If the global temperature variance exceeds the preset temperature variance threshold, static power consumption data of the high-heat marker is extracted to construct an asymmetric power consumption feature. The temperature variance threshold is set based on the temperature distribution uniformity requirements during normal chip operation. Under stable operating conditions, the global temperature variance is mainly concentrated between 0-5℃², at which point the temperature distribution uniformity is good; therefore, the basic threshold is set to 5℃². For highly integrated heterogeneous chips with higher heat density, the threshold can be increased to 6℃². For ordinary low-power integrated circuits, to improve temperature uniformity, the threshold can be decreased to 4℃². As those skilled in the art know, this threshold can be flexibly adjusted within the range of 4℃² to 6℃² according to the chip's process node and application scenario. The high-heat indicator refers to an indicator whose temperature value is continuously higher than the heat saturation threshold. Its static power consumption data is retrieved from the on-chip power monitoring unit integrated in the chip, including core indicators such as leakage current value and static power consumption value. After retrieval, the power consumption data is normalized to the [0,1] interval by minimum and maximum. Then, a polynomial curve fitting method is used, with the physical coordinates of the indicator as the horizontal axis and the normalized static power consumption value as the vertical axis, to fit the power consumption distribution curve on the chip surface. This curve is the asymmetric power consumption feature, which intuitively reflects the power consumption difference of different areas of the indicator.

[0071] For example, the calculated global temperature variance of 6.5℃² exceeds the basic threshold of 5℃². The static power consumption values ​​of C5 and C2 are extracted as 0.8W and 0.75W respectively. After normalization, the corresponding values ​​are 0.8 and 0.75. The fitted power consumption distribution curve shows that the power consumption of the central region of the chip is significantly higher than that of the edge region, forming a typical asymmetric power consumption characteristic.

[0072] Next, based on the asymmetric power consumption characteristics, the frequency configuration and load distribution of each identifier are adjusted. When generating the load allocation sequence between identifiers, the principle of frequency reduction in high-power areas and frequency preservation in low-power areas is followed. For identifiers with higher power consumption values ​​in the asymmetric power consumption characteristics, a step-wise frequency reduction operation is performed, with a basic frequency reduction step size set at 0.2GHz. After each frequency reduction, it is ensured that the identifier frequency is not lower than the chip's minimum operating frequency. Identifiers with lower power consumption values ​​maintain their current stable operating frequency. Some identifiers with strong heat dissipation capabilities can be slightly increased in frequency, with an increase step size not exceeding 0.1GHz. After the frequency configuration adjustment is completed, combined with the computing power capacity and heat dissipation capacity of each identifier, high-load cores are migrated from high-power identifiers to low-power, high-heat-dissipation identifiers. The task and identifier are accurately matched according to computing power requirements. Finally, the frequency configuration, load ratio, physical coordinates, and bound task ID of all identifiers are integrated and sorted in order from left to right and from top to bottom according to the physical coordinates on the chip surface to generate the load allocation sequence between identifiers. The sequence clearly defines the operating parameters and task allocation rules of each identifier.

[0073] For example, based on the asymmetric power consumption characteristics, the high-power identifier C5 is reduced from 2.1GHz to 1.9GHz and the identifier C2 is reduced from 2.0GHz to 1.8GHz. The high-load cores carried by these two identifiers are migrated to identifiers C11 and C14 respectively. The load allocation sequence generated after sorting by physical coordinates includes the frequency configuration, load ratio and bound tasks of each identifier, clearly defining the operation and load rules of all identifiers.

[0074] Then, the load distribution sequence is input into the preset thermal simulation model to calculate the predicted junction temperature. If the predicted junction temperature is lower than the preset safe junction temperature threshold, the final temperature control scheme is determined. The thermal simulation model is constructed using a finite element analysis architecture. The training set contains 500+ sets of chip temperature monitoring samples under different frequencies, loads, and power consumptions, which are divided into training and validation sets in an 8:2 ratio. The model uses ReLU as the activation function and mean squared error as the loss function. The initial learning rate is set to 0.01, and it decreases by 0.1 every 20 iterations until it reaches 0.001. The loss value is monitored in real time during training. The iteration stops when the loss fluctuation is less than 0.001 for 10 consecutive rounds. The trained model can accurately predict the chip junction temperature under different operating parameters.

[0075] It should be noted that the safe junction temperature threshold is set based on the chip's process node and thermal characteristics. The basic safe junction temperature threshold for 7nm advanced process chips is set at 90℃, which can be adjusted to 95℃ for 14nm process chips, and lowered to 85℃ for 28nm process chips. Those skilled in the art will understand that this threshold can be adjusted within the range of 85℃ to 95℃ according to the chip's process specifications. The load distribution sequence is input into the trained thermal simulation model, and the model outputs the predicted junction temperature value for each identifier. If the predicted junction temperature value for all identifiers is lower than the safe junction temperature threshold, then the load distribution sequence is determined as the final temperature control scheme; if there are identifiers with junction temperatures exceeding the threshold, the frequency configuration and load distribution are readjusted until the junction temperatures of all identifiers meet the requirements.

[0076] For example, the generated load distribution sequence is input into the thermal simulation model, and the predicted junction temperature of the identifier C5 is 78.6℃, the predicted junction temperature of C2 is 77.8℃, and the junction temperatures of the other identifiers are all below 80℃. All values ​​are below the safe junction temperature threshold of 90℃. Therefore, this load distribution sequence is determined as the final temperature control scheme for the chip.

[0077] In summary, this invention discloses a temperature control method for integrated circuits, including acquiring real-time chip surface temperature, heterogeneous core identifiers and physical coordinates, and heat dissipation path parameters; correlating and correcting the data to generate a temperature distribution map and feature matrix, identifying hotspot areas and prioritizing cores requiring intervention; determining high-load cores and migrating them to low-temperature, high-heat-dissipation areas, adjusting the core operating frequency to ensure clock synchronization; tracking temperature changes to calculate global variance, and optimizing load allocation if a threshold is exceeded to obtain the final temperature control scheme. This achieves precise dynamic temperature control of integrated circuits, meeting the data acquisition requirements for high-performance chip stability.

[0078] Reference Figure 2 The second embodiment of the present invention provides a temperature control system for an integrated circuit, comprising: The data acquisition module is used to acquire real-time temperature data of various regions on the chip surface, heterogeneous core identifiers, physical coordinates of heterogeneous cores, and heat dissipation path parameters. The matrix generation module is used to associate the real-time temperature data with the physical coordinates, and to correct the associated temperature data by combining the heat dissipation path parameters, thereby generating a dynamic temperature distribution map, and extracting the feature matrix of the temperature distribution based on the map. The hotspot identification module is used to calculate the full-field temperature gradient vector based on the feature matrix and extract connected regions whose gradient magnitude exceeds a preset thermal anomaly threshold as hotspot regions. The list generation module is used to monitor the real-time core temperature of the hot spot area, calculate the deviation value between the real-time core temperature and the preset heat saturation threshold, sort the cores corresponding to the hot spot area according to the deviation value, and obtain a list of core identifiers that need intervention. The load determination module is used to combine the core identifier list with the load rate of the heterogeneous cores monitored in real time. If the load rate exceeds the preset load determination threshold, it is determined to be a high-load core. The core adjustment module is used to select areas with temperatures below a preset low temperature threshold and heat dissipation capacity above a preset heat dissipation capacity threshold as target areas, and migrate the tasks of the high-load core to the target areas to obtain an adjusted core layout. The frequency adjustment module is used to monitor the clock synchronization deviation value of each core under the adjusted core layout. If the clock synchronization deviation value exceeds the preset timing deviation threshold, the operating frequency of the corresponding core is adjusted to obtain stable operating parameters. The load optimization module is used to track the chip surface temperature change under the stable operating parameters and calculate the global temperature variance. If the variance exceeds the preset temperature variance threshold, the load distribution of the heterogeneous cores is optimized to obtain the final temperature control scheme.

[0079] It should be noted that the integrated circuit temperature control system provided in this embodiment of the invention is used to execute all the process steps of the integrated circuit temperature control method of the above embodiment. The working principle and beneficial effect of the two are one-to-one, so they will not be described again.

[0080] It should be noted that the system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the system embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0081] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A temperature control method for an integrated circuit, characterized in that, include: Acquire real-time temperature data, heterogeneous core identifiers, physical coordinates of heterogeneous cores, and heat dissipation path parameters for each region on the chip surface; The real-time temperature data is correlated with the physical coordinates, and the correlated temperature data is corrected by combining the heat dissipation path parameters to generate a dynamic temperature distribution map. The feature matrix of the temperature distribution is extracted based on the map. Calculate the full-field temperature gradient vector based on the feature matrix, and extract the connected regions whose gradient magnitude exceeds the preset thermal anomaly threshold as hotspot regions. Monitor the real-time core temperature of the hotspot area, calculate the deviation between the real-time core temperature and the preset heat saturation threshold, sort the cores corresponding to the hotspot area according to the deviation value, and obtain a core identification list that needs intervention; By combining the core identifier list with the load rate of the heterogeneous cores monitored in real time, if the load rate exceeds a preset load judgment threshold, it is determined to be a high-load core. The region with a temperature lower than a preset low temperature threshold and a heat dissipation capacity higher than a preset heat dissipation capacity threshold is selected as the target region. The tasks of the high-load core are then migrated to the target region to adjust the core layout. Monitor the clock synchronization deviation of each core under the adjusted core layout. If the clock synchronization deviation exceeds the preset timing deviation threshold, adjust the operating frequency of the corresponding core to obtain stable operating parameters. The chip surface temperature changes under the stable operating parameters are tracked, and the variance of the global temperature is calculated. If the variance exceeds the preset temperature variance threshold, the load distribution of the heterogeneous cores is optimized to obtain the final temperature control scheme.

2. The temperature control method for integrated circuits according to claim 1, characterized in that, The acquisition of real-time temperature data, heterogeneous core identifiers, physical coordinates of heterogeneous cores, and heat dissipation path parameters for each region of the chip surface includes: Real-time temperature data of various areas on the chip surface is collected through a distributed sensor network. Retrieve the preset heterogeneous core identifier and its corresponding physical coordinates; Obtain the heat dissipation path parameters that are fixed during the chip design stage. The heat dissipation path parameters include thermal resistance values ​​and heat conduction path distribution.

3. The temperature control method for integrated circuits according to claim 1, characterized in that, The process involves associating the real-time temperature data with the physical coordinates, and correcting the associated temperature data using the heat dissipation path parameters to generate a dynamic temperature distribution map. Based on this map, a feature matrix of the temperature distribution is extracted, including: By associating the real-time temperature data with the physical coordinates, raw temperature data with spatial location information is generated. Based on the thermal resistance value in the heat dissipation path parameters, the original temperature data is corrected to obtain corrected temperature data that reflects the difference in heat dissipation. Spatial interpolation is performed on the corrected temperature data to generate a continuous dynamic temperature field, which is then transformed into a dynamic temperature distribution map. Extract the temperature peaks, gradient changes, and hotspot distribution information from the temperature distribution map to construct a feature matrix of the temperature distribution.

4. The temperature control method for integrated circuits according to claim 1, characterized in that, The step of calculating the full-field temperature gradient vector based on the feature matrix and extracting connected regions whose gradient magnitude exceeds a preset thermal anomaly threshold as hotspot regions includes: Calculate the full-field temperature gradient vector based on the aforementioned feature matrix; The gradient magnitude is calculated based on the full-field temperature gradient vector. Discrete points whose gradient magnitude exceeds a preset thermal anomaly threshold are extracted. Connectivity analysis is performed on the discrete points to form independent connected regions. The independent connected regions are spatially matched with the preset chip physical layout to determine hotspot regions.

5. The temperature control method for integrated circuits according to claim 1, characterized in that, The process involves monitoring the real-time core temperature of the hotspot area, calculating the deviation between the real-time core temperature and a preset heat saturation threshold, and sorting the cores corresponding to the hotspot area according to the deviation value to obtain a list of core identifiers requiring intervention, including: Monitor the real-time temperature of the core corresponding to the hot spot area, calculate the difference between the real-time temperature of the core and the preset heat saturation threshold, and obtain the temperature deviation value of each core. The temperature deviation values ​​are assigned sorting weights from largest to smallest to generate a sequence to be processed. Identify the cores in the sequence to be processed whose temperature deviation values ​​exceed a preset critical deviation threshold, and combine them to form a core identifier list that requires intervention.

6. The temperature control method for integrated circuits according to claim 1, characterized in that, The process involves combining the core identifier list with the real-time monitored load rate of heterogeneous cores. If the load rate exceeds a preset load determination threshold, the core is identified as a high-load core, including: The load status of each core in the core identifier list is monitored in real time, and the load rate of the core is calculated. If the load rate exceeds the preset load determination threshold, then the core is confirmed as a high-load core.

7. The temperature control method for integrated circuits according to claim 1, characterized in that, The region whose screening temperature is lower than a preset low-temperature threshold and whose heat dissipation capacity is higher than a preset heat dissipation capacity threshold is selected as the target region. The tasks of the high-load core are migrated to the target region to adjust the core layout, including: Collect real-time temperature and heat dissipation parameters of each core in non-hotspot areas of the chip; Cores whose real-time temperature is lower than a preset low-temperature threshold and whose heat dissipation capacity parameter is higher than a preset heat dissipation capacity threshold are selected to form a target core set; Establish a remapping relationship between the high-load cores and the cores in the target core set, execute scheduling instructions, and adjust the core layout.

8. The temperature control method for integrated circuits according to claim 1, characterized in that, The monitoring of clock synchronization deviation values ​​for each core under the adjusted core layout, if the clock synchronization deviation value exceeds a preset timing deviation threshold, adjusts the operating frequency of the corresponding core to obtain stable operating parameters, including: Read the rising edge timestamps of the clock signals of each core under the adjusted core layout; The deviation between the rising edge timestamp and the global clock reference is calculated to obtain the clock synchronization deviation value of each core; If the clock synchronization deviation value exceeds the preset timing deviation threshold, then a frequency reduction operation is performed on the corresponding core. The clock synchronization deviation value is continuously monitored until it falls below the timing deviation threshold, at which point the current operating frequency is determined to be a stable operating parameter.

9. The temperature control method for integrated circuits according to claim 1, characterized in that, The process involves tracking the chip surface temperature change under stable operating parameters and calculating the global temperature variance. If the variance exceeds a preset temperature variance threshold, the load distribution of heterogeneous cores is optimized to obtain the final temperature control scheme, including: Track the real-time temperature of each core on the chip surface under the stable operating parameters, and construct a time series of temperature evolution; Calculate the global temperature variance based on the time series; If the global temperature variance exceeds a preset temperature variance threshold, then cores with temperatures higher than a preset high-heat determination threshold are extracted from the time series as high-heat cores. The static power consumption data and leakage current parameters of the high-heat core are collected to construct asymmetric power consumption characteristics; Based on the asymmetric power consumption characteristics, the frequency configuration and load distribution of each core are adjusted to generate a load distribution sequence between cores; The load distribution sequence is input into a preset thermal simulation model to calculate the predicted junction temperature. If the predicted junction temperature is lower than the preset safe junction temperature threshold, the final temperature control scheme is determined. If the predicted junction temperature is higher than or equal to the preset safe junction temperature threshold, the core frequency configuration and load distribution ratio are iteratively adjusted according to the preset step size until the predicted junction temperature is lower than the preset safe junction temperature threshold, and the corresponding scheme is determined as the final temperature control scheme.

10. A temperature control system for an integrated circuit, characterized in that, include: The data acquisition module is used to acquire real-time temperature data of various regions on the chip surface, heterogeneous core identifiers, physical coordinates of heterogeneous cores, and heat dissipation path parameters. The matrix generation module is used to associate the real-time temperature data with the physical coordinates, and to correct the associated temperature data by combining the heat dissipation path parameters, thereby generating a dynamic temperature distribution map, and extracting the feature matrix of the temperature distribution based on the map. The hotspot identification module is used to calculate the full-field temperature gradient vector based on the feature matrix and extract connected regions whose gradient magnitude exceeds a preset thermal anomaly threshold as hotspot regions. The list generation module is used to monitor the real-time core temperature of the hot spot area, calculate the deviation value between the real-time core temperature and the preset heat saturation threshold, sort the cores corresponding to the hot spot area according to the deviation value, and obtain a list of core identifiers that need intervention. The load determination module is used to combine the core identifier list with the load rate of the heterogeneous cores monitored in real time. If the load rate exceeds the preset load determination threshold, it is determined to be a high-load core. The core adjustment module is used to select areas with temperatures below a preset low temperature threshold and heat dissipation capacity above a preset heat dissipation capacity threshold as target areas, and migrate the tasks of the high-load core to the target areas to obtain an adjusted core layout. The frequency adjustment module is used to monitor the clock synchronization deviation value of each core under the adjusted core layout. If the clock synchronization deviation value exceeds the preset timing deviation threshold, the operating frequency of the corresponding core is adjusted to obtain stable operating parameters. The load optimization module is used to track the chip surface temperature change under the stable operating parameters and calculate the global temperature variance. If the variance exceeds the preset temperature variance threshold, the load distribution of the heterogeneous cores is optimized to obtain the final temperature control scheme.

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