Three-dimensional stacked chip, temperature control method, and electronic device

Abstract

The application provides a three-dimensional stacked chip, a temperature control method and an electronic device. The chip comprises a logic die and a storage die stacked on the logic die; a first temperature sensor and a hierarchical temperature controller disposed in the logic die, the temperature controller being configured to control the first temperature sensor to collect first temperature data of the logic die; a second temperature sensor disposed in each layer of the storage die, and a temperature output pin shared by the storage dies, the temperature output pin being configured to output second temperature data of the storage die, the second temperature data being determined based on temperature collected by the second temperature sensor; and a temperature fusion controller connected with the temperature controller and the temperature output pin, and configured to perform scene classification based on the first temperature data and the second temperature data, and perform global temperature collaborative control or local area temperature control based on a scene classification result. Through the application, temperature collaborative control of the three-dimensional stacked chip can be realized.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a three-dimensional stacked chip, a temperature control method, and an electronic device. Background Technology

[0002] With the continuous development of integrated circuit technology, the requirements for chip performance and functionality are becoming increasingly stringent, and chip area is also constantly increasing.

[0003] In a system-on-a-chip (SoC) employing a three-dimensional stacked memory architecture, there are typically logic sections and stacked memory sections. Since the three-dimensional stacked memory and logic sections each have their own thermal distribution characteristics, to ensure the entire chip can operate stably and at high performance for extended periods, it is necessary to collect thermal information from each part of the chip appropriately and formulate corresponding thermal control schemes based on the collected temperature information to meet the temperature control requirements of different high-performance application scenarios. Summary of the Invention

[0004] This application provides a three-dimensional stacked chip, a temperature control method, and an electronic device, which can realize the fusion collection and coordinated control of temperature information of logic dies and storage dies.

[0005] The technical solution of this application embodiment is implemented as follows: This application provides a three-dimensional stacked chip, the three-dimensional stacked chip comprising: Logic die and at least one layer of memory die stacked on the logic die; Multiple first temperature sensors and multiple temperature controllers arranged in a hierarchical manner are deployed in the logic die. The multiple temperature controllers are used to control the multiple first temperature sensors to collect first temperature data of the logic die. At least one second temperature sensor is deployed in each layer of the memory die, and a temperature output pin is shared by the at least one layer of memory dies. The temperature output pin is used to output second temperature data of the at least one layer of memory dies, which is determined based on the temperature collected by the at least one second temperature sensor. A temperature fusion controller is connected to the temperature controller and the temperature output pin, respectively, and is used to classify the scene based on the first temperature data and the second temperature data, and to perform global temperature collaborative control or local area temperature control based on the scene classification result.

[0006] This application provides a temperature control method applied to a three-dimensional stacked chip. The three-dimensional stacked chip includes a logic die, at least one layer of memory dies stacked on the logic die, and a temperature fusion controller. The logic die has multiple first temperature sensors and multiple temperature controllers arranged in a hierarchical manner. Each layer of memory dies has at least one second temperature sensor. The at least one layer of memory dies has a shared temperature output pin. The method includes: The multiple temperature controllers control the multiple first temperature sensors to collect data, thereby obtaining the first temperature data of the logic die. Based on the temperature collected by the at least one second temperature sensor, the second temperature data of the at least one layer of storage die is output through the temperature output pin; The temperature fusion controller performs scene classification based on the first temperature data and the second temperature data, and performs global temperature collaborative control or local area temperature control based on the scene classification results.

[0007] In the above scheme, the plurality of temperature controllers include a central temperature controller and at least one level protocol controller. The step of controlling the plurality of first temperature sensors to collect data to obtain the first temperature data of the logic die through the plurality of temperature controllers includes: sending temperature control information to the at least one level protocol controller through the central temperature controller; controlling the first temperature sensors to collect the temperature of the logic die based on the temperature control information through the at least one level protocol controller, and uploading the collected temperature to the central temperature controller level by level; and collecting the temperature data uploaded level by level through the central temperature controller to obtain the first temperature data.

[0008] In the above scheme, the at least one level protocol controller includes a first-level protocol controller, an intermediate-level protocol controller, and a last-level protocol controller. The deployment location of the first-level protocol controller corresponds to the functional partition of the logic die. The step of controlling the first temperature sensor to collect the temperature of the logic die based on the temperature control information through the at least one level protocol controller, and then uploading the collected temperature level by level to the central temperature controller, includes: receiving the temperature control information through the first-level protocol controller and cooperating with the intermediate-level protocol controller to broadcast the temperature control information level by level downwards; configuring a control signal based on the temperature control information through the last-level protocol controller and sending the control signal to the first temperature sensor corresponding to the last-level protocol controller; and performing temperature acquisition at the temperature detection point corresponding to the first temperature sensor in the logic die based on the received control signal through the first temperature sensor, obtaining the temperature of the temperature detection point, and returning the temperature of the temperature detection point to the last-level protocol controller, so as to transmit the collected temperature level by level upwards.

[0009] In the above scheme, the temperature output pin includes two general-purpose pins. The step of outputting the second temperature data of the at least one layer of memory die through the temperature output pin based on the temperature collected by the at least one second temperature sensor includes: determining the highest temperature in the at least one layer of memory die based on the temperature collected by the second temperature sensor; mapping the highest temperature based on a preset temperature mapping relationship to obtain a discrete level state; wherein the temperature mapping relationship indicates the correspondence between the temperature range to which the temperature of the memory die falls and the discrete level state; and outputting the discrete level state outward through the two general-purpose pins, the discrete level state being used as the second temperature data.

[0010] In the above scheme, the step of performing global temperature collaborative control or local area temperature control based on the scene classification result includes: when the scene classification result is a global temperature control scenario, performing collaborative temperature control for the logic die and the at least one layer of storage die; and when the scene classification result is a local temperature control scenario, performing temperature control for a local area of ​​the logic die.

[0011] In the above scheme, the first temperature data includes the temperatures of multiple temperature detection points in the logic die. The scene classification based on the first temperature data and the second temperature data includes: when the temperature of a target number of the temperature detection points exceeds the corresponding first temperature threshold, or when the temperature classification represented by the second temperature data reaches the overheating classification state, the scene classification result is determined as the global temperature control scene; when the global temperature control scene is not triggered, and the temperature of at least some of the temperature detection points located in the same local area exceeds the second temperature threshold, the scene classification result is determined as the local temperature control scene.

[0012] In the above scheme, the second temperature data is used to characterize the unified temperature classification of the at least one layer of memory dies. The execution of coordinated temperature control for the logic die and the at least one layer of memory dies includes: determining the target refresh rate increase corresponding to the at least one layer of memory dies based on the unified temperature classification characterized by the second temperature data, and increasing the refresh frequency of the at least one layer of memory dies according to the target refresh rate increase; triggering the clock gating mechanism of the logic die, and dynamically inserting idle cycles into the working cycle of the logic die through the clock gating mechanism.

[0013] In the above scheme, the step of performing temperature control on a local area of ​​the logic die includes: determining the local area of ​​the logic die that triggers the local temperature control scenario based on the first temperature data, and performing buck control or frequency modulation control on the local area.

[0014] This application provides an electronic device, which includes a processor, wherein the processor includes a three-dimensional stacked chip provided in this application.

[0015] The embodiments of this application have the following beneficial effects: Multiple temperature controllers are deployed in a hierarchical manner within the logic die. These controllers control multiple first temperature sensors for data acquisition, and this hierarchical approach improves the efficiency of obtaining the first temperature data from the logic die. A temperature output pin, shared by at least one layer of storage dies, outputs second temperature data determined based on the temperature collected by at least one second temperature sensor, thus establishing a channel for outputting the temperature data from at least one layer of storage dies. A temperature fusion controller is connected to both the temperature controllers and the temperature output pin. Based on the first and second temperature data, it performs scene classification, fusing the temperature conditions of the logic die and at least one layer of storage dies, and performs global temperature coordination control or local area temperature control based on the scene classification results. This method of combining first and second temperature data to classify and execute corresponding temperature control achieves precise adjustment of the internal heat dissipation of the 3D stacked chip, maintaining the temperature stability of the 3D stacked chip. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the physical structure of the three-dimensional stacked chip provided in the embodiments of this application; Figure 2 This is a schematic diagram of the internal module structure of the three-dimensional stacked chip provided in the embodiments of this application; Figure 3 This is a schematic diagram of the architecture of the temperature controller in the logic die provided in the embodiments of this application; Figure 4 This is a schematic diagram of the hierarchical network structure of the multi-level protocol controller provided in the embodiments of this application; Figure 5 This is a schematic flowchart of the temperature control method provided in the embodiments of this application; Figure 6 This is a schematic diagram of the multi-level broadcast process of temperature control information provided in the embodiments of this application; Figure 7 This is a schematic diagram of the thermal information fusion control process provided in the embodiments of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0019] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0020] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0021] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0022] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0023] 1) 3D Stacked Chip: This refers to an integrated circuit where multiple dies are stacked vertically and interconnected using technologies such as through-silicon vias (TSVs) or micro-bumps. A 3D stacked chip can include a bottom layer of logic dies and an upper layer of memory dies. It is an integrated circuit product formed by vertically stacking and connecting logic dies and memory dies. 2) Logic Die (LD): A silicon wafer containing the main computing units, processing nodes, and logic control functions.

[0024] 3) Memory Die (MD): A silicon die containing data storage units that is highly sensitive to changes in the external temperature environment.

[0025] 4) First temperature sensor: A sensing electronic component deployed in the logic die to collect real-time temperature parameters of the logic operation area.

[0026] 5) Second temperature sensor: A sensing electronic component deployed in the storage die to collect real-time temperature parameters of the storage medium area.

[0027] With advancements in semiconductor technology, 3D stacked chips are widely used due to their advantages of high bandwidth and low latency. (See also...) Figure 1 , Figure 1 This is a schematic diagram of the physical structure of the three-dimensional stacked chip provided in an embodiment of this application. For example... Figure 1 As shown, the three-dimensional stacked chip 10 includes a bottom logic die (LD) 110 and one or more memory dies (MD) 120 stacked vertically above the logic die 110. The three-dimensional stacked chip 10 utilizes interconnect technologies such as through-silicon vias (TSVs) or microbumps in the vertical direction to achieve physical fixation and signal interaction between the logic die 110 and the memory die 120. However, this vertical stacking structure presents a significant heat dissipation challenge. The bottom logic die 110 is typically the primary source of power consumption and heat generation, and the large amount of heat generated is directly transferred upwards to the temperature-sensitive top memory die 120. High temperatures can exacerbate leakage current in memory cell capacitors, shortening data retention time. Traditional temperature control schemes often isolate the logic die 110 and the memory die 120, preventing them from sensing each other's true temperature status and hindering global thermal coordination, which can easily lead to a sharp drop in overall chip performance or data loss.

[0028] To address the aforementioned issues, embodiments of this application provide a three-dimensional stacked chip, a temperature control method, and an electronic device. Figure 2 This is a schematic diagram of the internal module structure of the three-dimensional stacked chip provided in an embodiment of this application. For example... Figure 2 As shown, the three-dimensional stacked chip 10 includes a logic die 110, at least one layer of memory dies 120 stacked on the logic die 110, a temperature fusion controller 130, a plurality of first temperature sensors 112 deployed in the logic die 110, a plurality of hierarchically arranged temperature controllers 111, at least one second temperature sensor 121 deployed in each layer of memory dies 120, and a temperature output pin 122 shared by at least one layer of memory dies 120. The temperature fusion controller 130 can be deployed inside or outside the logic die 110. The plurality of temperature controllers 111 are used to control the plurality of first temperature sensors 112 to acquire first temperature data of the logic die 110. The temperature output pin 122 is used to output second temperature data of at least one layer of memory dies 120, the second temperature data being determined based on the temperature acquired by at least one second temperature sensor 121. The temperature fusion controller 130 is connected to multiple temperature controllers 111 and temperature output pins 122 respectively. It is used to classify the scene based on the first temperature data and the second temperature data, and to perform global temperature collaborative control or local area temperature control based on the scene classification results.

[0029] Here, the 3D stacked chip 10 refers to a system-on-chip (SOC) that vertically stacks different functional layers using a 3D bonding process. The logic die 110 serves as the core logic processing part of this SOC, integrating functional modules such as arithmetic units and interface control. The storage die 120 refers to a semiconductor substrate that provides data read / write and temporary storage capabilities, such as a die for Dynamic Random Access Memory (DRAM). Hierarchical configuration refers to deploying multiple controllers according to a hierarchical network topology, forming a control architecture that includes a top-level master control unit and at least one lower-level intermediate or execution unit, to achieve hierarchical instruction delivery and hierarchical data aggregation.

[0030] In terms of hardware physical layout, the logic die 110 has a large area and a wide distribution of heat-generating modules. The multiple temperature controllers 111 deployed inside adopt a hierarchical network topology structure, which are connected to the first temperature sensor 112 in different areas. This design is used to avoid bus congestion caused by a single master node acquiring a large amount of data.

[0031] For at least one layer of memory die 120, the signal transmission mechanism of the temperature output pin 122 is adaptively matched according to the number of physically stacked layers. In some embodiments, when the at least one layer of memory die 120 contains only one layer of memory die, after at least one second temperature sensor 121 inside the single-layer memory die acquires the temperature, it directly transmits the second temperature data to the bottom logic die 110 through the temperature output pin 122 solidified on the edge of the single-layer memory die.

[0032] In some embodiments, when at least one layer of memory die 120 comprises two or more vertically stacked memory dies, each memory die layer has at least one second temperature sensor 121 deployed within it. These multi-layer memory dies share the same temperature output pin 122 at the physical level through three-dimensional electrical connection structures such as through-silicon vias (TSVs) or microbumps. In this multi-layer stacked structure, the temperature data collected by each layer is compared and logically converged within the memory structure, and then output to the outside via the shared temperature output pin 122, representing the second temperature data of the overall memory region status.

[0033] In some embodiments, the first temperature data characterizes the real-time heating state of each temperature detection point inside the logic die 110. The first temperature data can be an actual continuous absolute temperature value (e.g., a Celsius scalar), the rate of temperature change (i.e., temperature gradient) of each temperature detection point per unit time, or the raw digital quantization code based on the output of an analog-to-digital converter (ADC).

[0034] In some embodiments, the second temperature data characterizes the overall thermal state of the at least one layer of memory die 120. The second temperature data is determined based on the temperature collected by at least one second temperature sensor 121, and the determination process may include data aggregation and format conversion steps. When multiple second temperature sensors 121 exist (including multiple sensors on the same layer or multiple sensors on multiple layers), the built-in comparison logic circuit aggregates the collected multiple temperatures, for example, extracting the highest temperature value as a safety control benchmark, or calculating the average temperature value as an overall state benchmark; subsequently, the aggregated temperature value is converted into an output data format. In terms of implementation, the second temperature data can be a discrete level state code characterizing a temperature range, or it can be duty cycle data of a pulse width modulation (PWM) signal, or it can be a continuously changing analog voltage signal, etc.

[0035] In some embodiments, global temperature coordination control refers to a coordinated response mechanism that simultaneously issues allocation commands to both the upper and lower layers of the chip (logic die 110 and at least one layer of storage die 120). For example, it can simultaneously reduce the operating frequency of the logic side and the read / write bandwidth of the storage side, triggering chip-level thermal throttling to block the vicious cycle of heat conduction at the three-dimensional bonding layer. Local area temperature control refers to an independent adjustment mechanism that targets only specific heat-generating modules in the logic die 110, and this adjustment does not affect the storage die 120 or other non-heat-generating modules in the logic die 110. For example, it can perform dynamic voltage and frequency scaling (DVFS) bucking on a core computing unit where heat accumulation occurs, or control the task scheduler to migrate computing tasks from high-temperature nodes to low-temperature nodes.

[0036] In some embodiments, the temperature fusion controller 130 receives first temperature data reported by the logic die 110 via an internal data bus; simultaneously, it reads second temperature data output from the temperature output pin 122. The temperature fusion controller 130 invokes a built-in heat distribution evaluation model with spatial weights to logically merge and weight the acquired first and second temperature data, outputting a comprehensive heat load index. When the comparison determines that the comprehensive heat load index exceeds a preset global limit, the temperature fusion controller 130 classifies the scenario as a global temperature control scenario and executes global temperature collaborative control. When the comparison determines that the comprehensive heat load index does not exceed the global limit, but the temperature of individual logic nodes exceeds a local limit based on the first temperature data, the temperature fusion controller 130 classifies the scenario as a local temperature control scenario and executes local area temperature control.

[0037] In some embodiments, the hierarchical hardware acquisition architecture deployed within the logic die 110 is not limited to temperature acquisition. This multi-level convergence mechanism is also applicable to the collection of other physical characteristic parameters within the three-dimensional stacked chip 10. For example, the first temperature sensor 112 can be replaced with or configured in parallel with a voltage sensor and a current sensor to acquire dynamic power supply fluctuation data in real time; or it can be used to acquire process deviation characteristic parameters, thereby providing comprehensive decision support for the global power management module.

[0038] In some embodiments, Figure 3 This is a schematic diagram of the architecture of a temperature controller in a logic die provided in an embodiment of this application. See also... Figure 3 The multiple temperature controllers 111 include a central temperature controller 310 and at least one level protocol controller 320. The central temperature controller 310 is used to send temperature control information to the at least one level protocol controller 320 and collect the temperature data uploaded level by level to obtain the first temperature data; the at least one level protocol controller 320 is used to control the first temperature sensor 112 to collect the temperature of the logic die 110 based on the temperature control information, and upload the collected temperature data to the central temperature controller 310 level by level.

[0039] Here, the temperature central controller refers to the top-level main control logic unit in the hardware architecture responsible for generating and issuing global instructions and ultimately aggregating underlying data. The protocol controller refers to the intermediate-level hardware unit deployed at the intermediate node of the data transmission bus link, responsible for receiving instructions from higher levels and completing protocol parsing and local data transmission and reception scheduling. Temperature control information refers to hardware configuration instructions that include control parameters such as sensor operating mode and sampling period.

[0040] In some embodiments, the temperature central controller 310 generates temperature control information including sampling frequency and acquisition channel configuration according to the current operating mode of the chip, and sends the temperature control information to the downstream protocol controller 320 through the internal configuration bus. At least one level protocol controller 320 receives and parses the temperature control information, converts the temperature control information into the corresponding electrical control level or pulse enable signal, and drives the connected first temperature sensor 112 to start analog temperature signal detection. Finally, at least one level protocol controller 320 reads the temperature acquisition result returned by the first temperature sensor 112, performs digital formatting and encapsulation, and transmits the acquired temperature up the hierarchical link to the temperature central controller 310 according to the preset bus timing and transmission protocol. The temperature central controller 310 completes the final data assembly in the receiving buffer, thereby obtaining the first temperature data reflecting the global heat distribution of the logic die 110.

[0041] In some embodiments, the number of protocol controller levels is configured based on the total number of first temperature sensors 112 deployed in the logic die 110. When the total number of first temperature sensors 112 deployed is less than a preset threshold, a single-level protocol controller is configured to form a star topology network. When the total number of first temperature sensors 112 deployed is greater than or equal to the preset threshold, multiple levels of cascaded protocol controllers are configured to construct a tree-like communication network. The hierarchical relay transmission mechanism shortens the physical length of a single trace and reduces the resistance-capacitance delay of signal transmission. Furthermore, the master-slave hierarchical communication architecture can also be extended to the hierarchical design of clock tree synchronization control or reset signal distribution within the logic die 110.

[0042] For example, see Figure 3 Assuming the logic die 110 is divided into multiple physical partitions, and a primary protocol controller 320 is configured below the temperature central controller 310 (containing a total of...) Each independent protocol controller (310, 312, 312) forms a two-layer control architecture. Temperature control information has a unified sampling period. Each protocol controller manages the first temperature sensor 112 corresponding to its physical zone. During one temperature acquisition cycle, the central temperature controller 310 sends... Each protocol controller sends temperature control information in parallel. Each protocol controller drives the connected first temperature sensor 112 to synchronously acquire data and generate a regional temperature matrix representing the corresponding physical zone. Assume the... Each protocol controller collects the regional temperature matrix. and the regional temperature matrix The temperature data is uploaded step by step to the upper bus. The central temperature controller 310 collects the uploaded temperatures to obtain the first temperature data. The data collection and spatial reconstruction process can be achieved through matrix splicing and fusion formula (1).

[0043] Formula (1); in, This represents the first temperature data obtained after final aggregation, which is represented in the data structure as a global temperature distribution matrix. This represents the total number of protocol controllers at the current aggregation level; Representing the The regional temperature matrix uploaded by each protocol controller; The representative corresponds to the first The position mapping matrix of each protocol controller in the global physical space distribution of the logic die 110 is used to restore a one-dimensional vector to a two-dimensional planar coordinate system; This represents the assembly and fusion operations of matrix elements.

[0044] Assuming configuration parameters are set This indicates the existence of two protocol controllers, one managing the left-side and the other the right-side processing cores. The regional temperature matrix uploaded by the first protocol controller is... The second protocol controller uploads the regional temperature matrix as follows: After receiving the temperature data uploaded level by level, the central temperature controller 310 combines it with the pre-configured location mapping matrix. and The matrix assembly and fusion operation is performed. After calculation and reconstruction, the first temperature data representing the global heating state of the logic die 110 is finally obtained. By employing a hierarchical distribution and matrix aggregation approach, the spatial temperature characteristics of the logic die 110 were extracted under the condition of fixed concurrent bandwidth.

[0045] This embodiment configures multiple temperature controllers, including a central temperature controller and at least one level protocol controller. The central temperature controller sends temperature control information to the at least one level protocol controller, which then controls the first temperature sensor to collect the temperature of the logic die based on the temperature control information. This hierarchical hardware architecture enables distributed issuance of control commands, optimizing the communication load of single-point controllers. Simultaneously, the at least one level protocol controller uploads the collected temperatures level by level to the central temperature controller, which then aggregates the uploaded temperatures to obtain the first temperature data. This level-by-level upload and aggregation data transmission mechanism improves the concurrent transmission efficiency of a large amount of distributed node data and ensures the timeliness of the first temperature data generation.

[0046] In some embodiments, at least one level protocol controller 320 includes a first-level protocol controller, an intermediate-level protocol controller, and a last-level protocol controller. The first-level protocol controller is deployed in a location corresponding to the functional partition of the logic die 110, and is used to receive temperature control information and cooperate with the intermediate-level protocol controller to broadcast the temperature control information down level by level. The last-level protocol controller is used to configure control signals based on the temperature control information and send the control signals to the first temperature sensor 112 corresponding to the last-level protocol controller. The first temperature sensor 112 is used to perform temperature acquisition at the temperature detection point corresponding to the first temperature sensor 112 in the logic die 110 based on the received control signals, obtain the temperature of the temperature detection point, and return the temperature of the temperature detection point to the last-level protocol controller so as to pass the acquired temperature up level by level.

[0047] Here, functional partitioning refers to physically isolated areas within the logic die 110 based on computational attributes, such as arithmetic unit areas or storage interface areas. Broadcast mode refers to a communication mode where a single communication node simultaneously sends the same data packet to all lower-level nodes at the same level in the network topology. Control signals refer to low-level electrical drive signals natively supported by physical sensors, generated after hardware instruction parsing and translation, such as high / low level or timing pulse signals. Temperature detection points refer to specific physical spatial coordinates within the logic die 110 used for real-time detection of thermal status; for example, temperature detection points can be located near transistor clusters with high-frequency switching. Intermediate-level protocol controllers refer to data relay nodes between the first-level protocol controller and the last-level protocol controller. The number of intermediate-level protocol controllers is not limited to a single level; they can be flexibly configured into two-, three-, or more-level relay cascade structures based on the internal wiring distance of the logic die 110 and the size of the control nodes. Intermediate-level protocol controllers may include at least one second-level protocol controller.

[0048] In terms of the number of correspondences in the hardware hierarchy architecture, the temperature control network adopts a one-to-many tree topology design: one temperature central controller 310 corresponds to at least one (usually multiple) first-level protocol controllers; each first-level protocol controller corresponds to at least one intermediate-level protocol controller; in the case where the intermediate-level protocol controllers have a multi-level cascaded structure, the next-level intermediate-level protocol controller corresponds to at least one next-level intermediate-level protocol controller; the last intermediate-level protocol controller corresponds to at least one last-level protocol controller; each last-level protocol controller corresponds to at least one (usually multiple) first temperature sensor 112, thereby forming a fan-out control network covering the entire domain of the logic die 110.

[0049] In some embodiments, the first-level protocol controller receives temperature control information, copies the temperature control information into multiple parallel data streams, and synchronously sends them to all intermediate-level protocol controllers within the same functional partition using a broadcast channel. The intermediate-level protocol controllers execute the same parallel transmission process. In the presence of multiple intermediate-level protocol controllers, the temperature control information is broadcast downwards layer by layer among the intermediate-level protocol controllers until it reaches the last-level protocol controller. The last-level protocol controller performs instruction translation, extracts the sampling frequency and enable parameters from the temperature control information, generates a control signal matching the hardware interface protocol, and sends the control signal to the first temperature sensor 112 via a direct-connect pin. Finally, after receiving the control signal, the first temperature sensor 112 performs analog temperature measurement on the temperature detection point, converts the measurement result into a digital format of the temperature at the temperature detection point, and outputs it to the receiving port of the last-level protocol controller. Each level of protocol controller transmits the temperature of the temperature detection point upwards through a polling reading mechanism.

[0050] In some embodiments, the multi-level broadcast architecture based on functional partition deployment is not only applied to the distribution and aggregation of temperature control information, but also to the periodic rotation and distribution of internal security keys within the logic die 110. The first-level protocol controller, acting as a proxy node for the security management unit in the physical partition, rapidly transmits the encrypted global rotation command and synchronization clock signal downwards to all intermediate and final-level protocol controllers via broadcast. The final-level protocol controller translates the received security commands into control signals to trigger the underlying encryption engine, and after completing the key update, propagates the status identifier upwards level by level. This expansion scheme ensures the timeliness of hardware status synchronization at the underlying unit level of the logic die 110.

[0051] For example, Figure 4 This is a schematic diagram of the hierarchical network structure of the multi-level protocol controller provided in an embodiment of this application. See also... Figure 4 Multiple temperature controllers 111 are constructed in a fan-out architecture consisting of a central temperature controller 310 and multi-level protocol controllers. In terms of physical deployment, the first-level protocol controller comprises n+1 nodes, from first-level protocol controller 0 to first-level protocol controller n, each corresponding to a different functional partition of the logic die 110. Taking first-level protocol controller 0 as an example, first-level protocol controller 0 connects downwards to multiple protocol controllers at the next lower level (i.e., Figure 4 The second-level protocol controllers 00 to 0n are located within this architecture. When constructing a deeply cascaded architecture adapted to large-area dies, Figure 4 The second-level protocol controller can act as an intermediate-level protocol controller, continuing to cascade other intermediate-level protocol controllers down to the last-level protocol controller, which in turn connects to the first temperature sensor 112 at the bottom layer (e.g., corresponding to...). Figure 4 Temperature sensors 00 to nn are used in the network structure. In structures with fewer network layers... Figure 4 The second-level protocol controller in the protocol controller can also be used directly as the last-level protocol controller.

[0052] based on Figure 4 In the network topology shown, when the first-level protocol controller (such as the first-level protocol controller 0) receives the temperature control information, it uses the broadcast channel to synchronously send the temperature control information to all connected intermediate nodes (such as the second-level protocol controllers 00 to 0n), and so on, broadcasting downwards level by level.

[0053] In this embodiment, the deployment location of the first-level protocol controller corresponds to the functional partition of the logic die, realizing the independent division and management of the hardware state of local areas. The first-level protocol controller and the intermediate-level protocol controller cooperate to send temperature control information down level by level in a broadcast manner, eliminating the time delay of multi-level serial transmission and accelerating the transmission efficiency of control commands to the bottom-level nodes. The last-level protocol controller configures control signals based on temperature control information and sends them to the first temperature sensor, completing the accurate translation of macro-level commands to the bottom-level electrical drive signals. The first temperature sensor performs temperature acquisition on the temperature detection point based on the control signal and returns the temperature of the temperature detection point to the last-level protocol controller, which is used as the acquired temperature to be transmitted up level by level, thus constructing a closed-loop data acquisition and reporting channel with high timeliness.

[0054] In some embodiments, the temperature output pin 122 includes two general-purpose pins. At least one layer of memory die 120 is used to determine the highest temperature in the at least one layer of memory die 120 based on the temperature collected by the second temperature sensor 121, and to map the highest temperature based on a preset temperature mapping relationship to obtain a discrete level state; wherein, the temperature mapping relationship indicates the correspondence between the temperature range of the memory die 120 and the discrete level state; the two general-purpose pins are used to output the discrete level state externally, and the discrete level state is used as second temperature data.

[0055] Here, a general-purpose pin refers to a standardized physical contact reserved on the edge of a semiconductor package or die for transmitting basic high and low level signals. A preset temperature mapping relationship refers to the corresponding conversion rules, fixed in the logic gate circuits during the hardware design phase, that divide continuously changing analog temperature values ​​into multiple discrete intervals. Discrete level states refer to the electrical output states of an analog quantity range characterized by a combination of binary digital signals of a finite number of bits (e.g., 00, 01, etc.).

[0056] In some embodiments, temperature information collected by multiple second temperature sensors 121 deployed inside a single-layer memory die is acquired and aggregated at the first level. In the presence of multi-layer stacked memory dies, the aggregated temperatures of all stacked memory dies are compared, and the highest temperature among all memory dies is extracted. Then, the highest temperature is compared with multiple preset temperature ranges in a preset temperature mapping relationship to determine the actual temperature range within which the highest temperature falls. Finally, the temperature range within which the highest temperature falls is converted into a corresponding two-bit binary logic level state, and this two-bit binary logic level state is synchronously output to the outside through two shared general-purpose pins, forming a discrete level state and transmitting it as the second temperature data.

[0057] In some embodiments, the mechanism for aggregating extreme value data within the memory die and outputting it via a small number of pin mappings is not only applied to the acquisition and transmission of temperature data. The many-to-one data aggregation and state mapping mechanism is also applicable to early warning of power supply integrity within the memory die. For example, temperature sensors can be replaced with distributed voltage sag sensors. When a large-scale transient read / write operation occurs in the memory array, causing a sharp drop in the local power supply voltage, the comparison logic filters out the lowest transient voltage value and maps it to a discrete level state representing the voltage danger level based on the voltage mapping relationship. This value is then output to the logic die side via general-purpose pins, thereby providing a trigger signal with extremely low latency for the dynamic voltage compensation mechanism across the die.

[0058] For example, suppose at least one layer of memory die 120 comprises four vertically stacked layers of dynamic random access memory dies, each layer having a plurality of second temperature sensors 121 distributedly deployed. Two general-purpose pins are labeled Temp pad[1:0] on the hardware circuitry. The fixed temperature mapping is set as follows: When the highest temperature At that time, the corresponding discrete level state is binary logic level 00, when the highest temperature At that time, the corresponding discrete level state is binary logic level 01, when the highest temperature At that time, the corresponding discrete level state is binary logic level 10, when the highest temperature When the time is specified, the corresponding discrete level state is binary logic level 11.

[0059] Within a certain period, the maximum combined internal temperatures of the four memory dies were respectively , , as well as At least one layer of memory die 120 performs the maximum value operation, and the calculation process is as follows: Determine the highest temperature in at least one layer of storage die 120. for Subsequently, interval determination is performed based on the temperature mapping relationship. Because... The interval that meets the conditions The logic unit maps the highest temperature to the corresponding binary logic level 10. Subsequently, two general-purpose pins output discrete level states 10. The discrete level states 10 are transmitted as second temperature data to the temperature fusion controller 130 on the logic die 110 side, indicating that the storage layer has now reached the corresponding heating level.

[0060] In this embodiment, at least one layer of the memory die determines the highest temperature based on the temperature collected by the second temperature sensor, ensuring that any local extreme heating conditions in the memory array can be captured, avoiding the physical risk of local overheating being masked by the averaging algorithm; the highest temperature is mapped to a discrete level state based on a preset temperature mapping relationship, abstracting complex analog temperature changes in a range-level manner, eliminating the electrical interference problem of transmitting high-frequency analog signals across the three-dimensional bonding layer; two general-purpose pins output the discrete level state as the second temperature data, which, while meeting the requirements of full-domain heating state detection, minimizes the number of physical pins occupied by the three-dimensional stacked chip, reducing the complexity of three-dimensional packaging wiring and hardware implementation costs.

[0061] In some embodiments, when the scenario classification result is a global temperature control scenario, the temperature fusion controller 130 is further configured to perform coordinated temperature control for the logic die 110 and at least one layer of storage die 120; when the scenario classification result is a local temperature control scenario, the temperature fusion controller 130 is further configured to perform temperature control for a local area of ​​the logic die 110.

[0062] Here, global temperature control refers to a working state where both the logic die 110 and at least one layer of storage die 120 require temperature regulation after comprehensive evaluation. Coordinated temperature control refers to control actions that simultaneously change the operating parameters of the logic die 110 and at least one layer of storage die 120. Local temperature control refers to a working state where a specific spatial area within the logic die 110 requires temperature regulation. Local area temperature control refers to control actions that only change the operating parameters of the corresponding spatial area within the logic die 110, without changing the operating parameters of other areas within the logic die 110 or the at least one layer of storage die 120.

[0063] In some embodiments, the temperature fusion controller 130 reads the scene classification result and determines whether the scene classification result indicates a global temperature control scene or a local temperature control scene. If the scene classification result indicates a global temperature control scene, the temperature fusion controller 130 generates a global coordinated adjustment command and sends it to the control interface of at least one layer of storage die 120 and the clock control module of the logic die 110 to synchronously adjust the operating states of different dies. If the scene classification result indicates a local temperature control scene, the temperature fusion controller 130 obtains the physical address corresponding to the local area that triggers the local temperature control scene, generates a local adjustment command, and sends the local adjustment command to the controller corresponding to that physical address to independently execute temperature control for the local area of ​​the logic die 110.

[0064] In some embodiments, the dual-dimensional control mechanism that distinguishes between global collaborative and local independent control is not only applicable to temperature management tasks. The dual-dimensional control mechanism is also applicable to the dynamic voltage regulation task of the three-dimensional stacked chip 10. When a drop in the overall power supply network voltage is detected and a global voltage control scenario is triggered, collaborative voltage compensation is performed for the logic die 110 and at least one layer of memory dies 120; when a voltage fluctuation is detected only in a local area of ​​the logic die 110 and a local voltage control scenario is triggered, independent voltage regulation is performed only for that local area. This extended mechanism ensures the stability of the power supply network for the logic die 110 and at least one layer of memory dies 120.

[0065] In this embodiment, when the scenario classification result is a global temperature control scenario, the temperature fusion controller performs coordinated temperature control for the logic die and at least one layer of storage die, realizing heat linkage adjustment between different die layers and avoiding heat transfer across layers in the three-dimensional bonding structure; when the scenario classification result is a local temperature control scenario, the temperature fusion controller performs temperature control for a local area of ​​the logic die, realizing targeted adjustment only for local heat sources, avoiding unnecessary impact of global adjustment on the overall operating parameters of the logic die, and balancing temperature control and the operating performance of the logic die.

[0066] In some embodiments, the first temperature data includes the temperatures of multiple temperature detection points in the logic die 110. The temperature fusion controller 130 is further configured to determine the scene classification result as a global temperature control scene when the temperature of a target number of temperature detection points exceeds the corresponding first temperature threshold, or when the temperature classification represented by the second temperature data reaches an overheating classification state. The temperature fusion controller 130 is further configured to determine the scene classification result as a local temperature control scene when the global temperature control scene is not triggered and the temperature of at least some temperature detection points located in the same local area exceeds the second temperature threshold.

[0067] Here, the target quantity refers to a pre-set statistical benchmark value of physical nodes used to determine the overall heat generation scale of the logic die 110. The first temperature threshold refers to a temperature comparison benchmark set for each temperature detection point to trigger global linkage. Overheating classification state refers to a level state that is pre-defined as endangering the safety of the physical stack structure among the discrete states mapped by the second temperature data. The second temperature threshold refers to a temperature comparison benchmark set for a specific local area to trigger independent adjustment. The first temperature threshold and the second temperature threshold are set differently according to the physical heat generation characteristics of different functional areas in the logic die 110, and their values ​​can be equal or unequal. Temperature classification refers to dividing a continuous temperature value range into a finite number of discrete logic level states represented by specific codes or level states through a preset mapping relationship.

[0068] In some embodiments, the temperature fusion controller 130 traverses the first temperature data, extracts the temperature of multiple temperature detection points, and compares the temperature of each temperature detection point with its corresponding first temperature threshold, counting the cumulative number of detection points exceeding the first temperature threshold. Simultaneously, it parses the second temperature data to obtain the temperature classification of at least one layer of storage die 120. Next, the temperature fusion controller 130 performs a logical OR judgment: if the cumulative number of detection points is greater than or equal to the target number, or if the temperature classification is in an overheating state, a global judgment condition is triggered, and the scene classification result is directly determined as a global temperature control scene. Finally, if the global judgment condition is not met, the temperature fusion controller 130 divides the multiple temperature detection points into multiple local regions according to physical coordinates; if, in any local region, the number of temperature detection points exceeding the second temperature threshold satisfies the local judgment rule, the scene classification result is determined as a local temperature control scene.

[0069] In some embodiments, the dual threshold determination mechanism based on quantity statistics and graded status is not only applicable to temperature scenario classification. The dual threshold determination mechanism is also applicable to the classification and response to voltage descent scenarios within the three-dimensional stacked chip 10. When the voltage of a target number of nodes is lower than a first voltage threshold, or when the storage layer voltage reaches a severe descent level, it is determined to be a global voltage control scenario and overall compensation is initiated. When a global voltage control scenario is not triggered, but the voltage of some nodes in the same local area is lower than a second voltage threshold, it is determined to be a local voltage control scenario and local power supply network compensation is initiated. This extended scheme improves the accuracy of the coordinated management of global and local power supply in the chip.

[0070] For example, suppose a total of 10 temperature sensing points are deployed in the logic die 110, and the hardware preset target number is 8. A first temperature threshold is set for these 10 temperature sensing points. for The set second temperature threshold for Simultaneously, at least one layer of storage die 120 outputs second temperature data representing four temperature levels (00, 01, 10, 11), with the hardware configuration defining 10 and 11 as the overheating level state set. .

[0071] During the first detection cycle, the temperatures of eight temperature detection points on the logic die 110 were obtained. The temperature of the remaining two temperature detection points Simultaneously, the second temperature data was read as 01. Cumulative number of detection points. .because The number equals the target number (8), satisfying the global trigger condition, even if the second temperature data 01 does not fall into the overheating classification state set. The temperature fusion controller 130 still determines the scene classification result as a global temperature control scene.

[0072] During the second testing cycle, only two temperature detection points on the logic die 110 reached the required temperature. (Does not meet global conditions), the rest are Meanwhile, the second temperature data is updated to 10. This is because the second temperature data falls within the overheating classification state set. If the global triggering conditions are met, the temperature fusion controller 130 will determine the scene classification result as a global temperature control scene.

[0073] In the third detection cycle, the temperatures of two temperature detection points within a certain arithmetic unit (as a local area) in logic die 110 are... , (because The first temperature threshold was not exceeded. And the second temperature data is 01 (not in the set). Within the local area, the global temperature control scenario was not triggered. However, due to the temperature differences between the two temperature detection points in the same local area (…), the global temperature control scenario was not triggered. The temperature exceeded the second temperature threshold. ( The temperature fusion controller 130 determines the scene classification result as a local temperature control scene.

[0074] In this embodiment, when the temperature at a target number of temperature detection points exceeds a first temperature threshold, or when the temperature classification represented by the second temperature data reaches an overheating level, the scenario classification result is determined as a global temperature control scenario. This establishes a global priority response mechanism for large-scale overheating of logic dies or severe overheating of storage dies, ensuring the physical safety of the 3D stacked chips under extreme conditions. When a global temperature control scenario is not triggered and the temperature at some temperature detection points in a local area exceeds the second temperature threshold, it is determined as a local temperature control scenario, achieving refined local heat identification. This decoupled classification rule between global and local conditions achieves an orderly combination of global priority and precise local control.

[0075] In some embodiments, the second temperature data is used to characterize the unified temperature classification of at least one layer of storage dies 120. The temperature fusion controller 130 is further configured to, when the scenario classification result is a global temperature control scenario, determine the target refresh rate increase corresponding to at least one layer of storage dies 120 based on the unified temperature classification characterized by the second temperature data, and increase the refresh frequency of at least one layer of storage dies 120 according to the target refresh rate increase; the temperature fusion controller 130 is further configured to, when the scenario classification result is a global temperature control scenario, trigger the clock gating mechanism of the logic die 110, and dynamically insert idle cycles into the working cycle of the logic die 110 through the clock gating mechanism.

[0076] Here, "unified temperature grading" refers to a logic level state that establishes a unique correspondence with the discrete level states (such as combinations of high and low levels output through general-purpose pins) corresponding to the second temperature data. This is used to abstract the discrete level states of at least one layer of memory die hardware (120 layers) into different levels of heat dissipation severity at the system level. "Target refresh rate increase" refers to the percentage increase in frequency superimposed on the base refresh cycle to offset the physical impact of increased charge leakage from memory cell capacitors under high-temperature conditions. "Clock gating" refers to a technique that uses hardware logic circuits to dynamically block the clock signal transmission tree, controlling specific flip-flops to stop toggling and thus reducing dynamic power consumption. "Idle cycle" refers to a non-working time segment introduced in the processor pipeline or bus clock sequence by pausing clock pulses. The idle cycle is not a fixed length but dynamically adjusts with temperature changes. The duration of the idle cycle is positively correlated with the temperature of the logic die and at least one layer of memory die; the higher the temperature, the longer the inserted idle cycle.

[0077] In some embodiments, firstly, a mapping table is pre-built and stored in the configuration register inside the temperature fusion controller 130. This mapping table defines the binding correspondence between multiple levels of unified temperature classification and different target refresh rate increases. Secondly, the temperature fusion controller 130 receives second temperature data transmitted from physical pins and directly parses the discrete level states reflected in the second temperature data into the corresponding unified temperature classification. Then, the temperature fusion controller 130 uses the parsed unified temperature classification as an index to query the pre-built mapping table to determine the target refresh rate increase that perfectly matches the current state. Finally, the temperature fusion controller 130 issues a configuration command to at least one layer of memory die 120 to accelerate the refresh operation of the memory array with the target refresh rate increase; simultaneously, it issues a global enable signal to the clock generation network of the logic die 110 to trigger the clock gating mechanism, and calculates the corresponding idle cycle insertion ratio by substituting the specific temperature value of the first temperature data into a preset duty cycle calculation model. It then controls the logic die 110 to insert the corresponding idle cycle in the working cycle according to the insertion ratio until the global overheating scenario is resolved and the normal refresh frequency and continuous working cycle are restored.

[0078] In some embodiments, the collaborative control mechanism, in which one party adjusts data refresh characteristics and the other party dynamically gates and pauses, is applicable not only to global temperature control scenarios. This cross-level collaborative control mechanism is also applicable to transient voltage drop recovery tasks within the three-dimensional stacked chip 10. When a severe undershoot of the global supply voltage is detected and triggers a global voltage alarm, at least one layer of storage die 120 temporarily increases the refresh or read / write latency to reduce instantaneous current draw; simultaneously, the logic die 110 triggers a clock gating mechanism to insert an idle cycle, cutting off the dynamic current flipping of the logic gates. This extended solution, by jointly suppressing transient current demands, helps the power supply network restore the voltage to within safe tolerances in a very short time.

[0079] For example, suppose that at least one layer of storage die 120 outputs second temperature data through two general-purpose pins, which represents four discrete level states (i.e., binary 00, 01, 10, and 11). The temperature fusion controller 130 abstracts and resolves these four discrete level states into four unified temperature levels: normal operation level, slight heating level, overheating level 1 state, and overheating level 2 state. Based on this, the temperature fusion controller 130 pre-builds a mapping table, binding the overheating level 1 state to a 1.5-fold increase in the base refresh rate (i.e., a target refresh rate increase of 1.5), and binding the overheating level 2 state to a 2.0-fold increase in the base refresh rate (i.e., a target refresh rate increase of 2.0).

[0080] When the three-dimensional stacked chip 10 triggers a global temperature control scenario during operation, if the second temperature data received by the temperature fusion controller 130 is 11, the temperature fusion controller 130 first resolves the discrete level state 11 into a unified temperature classification of the overheating secondary state. Subsequently, based on the overheating secondary state, the temperature fusion controller 130 queries the pre-built mapping table to determine that the current corresponding target refresh rate increase is the upper limit of 2.0 times. The temperature fusion controller 130 generates a storage-side control command, directly increasing the refresh frequency of at least one layer of storage die 120 to twice that of the normal state. The significantly increased refresh operation frequently replenishes the leakage charge of the fragile capacitors under extremely high temperatures, preventing the risk of data loss.

[0081] Meanwhile, for logic die 110, the temperature fusion controller 130 triggers a clock gating mechanism to... Substituting the positive correlation adjustment rule, the idle period insertion ratio is calculated as follows: Temperature fusion controller 130 control logic die 110 according to The proportional insertion of idle cycles (i.e., setting 6 working cycles and inserting 4 idle cycles in a continuous 10 total clock cycles) reduces the heat dissipation on the logic side from the physical source.

[0082] After a specified period of coordinated cooling, in another test, the representative temperature in the first temperature data dropped to [a certain value]. Furthermore, the second temperature data changes to 10. At this time, the temperature fusion controller 130 re-executes the judgment: interpreting 10 as an overheating level one state, and by querying the mapping table again, determines that the target refresh rate increase has changed to 1.5 times, and accordingly, simultaneously reduces the refresh rate multiple of at least one layer of memory die 120. Simultaneously, the temperature fusion controller 130 will... Substituting the positive correlation adjustment rule, the idle period insertion ratio is calculated as follows: The temperature fusion controller 130 adjusts the clock gating mechanism based on this result, and the control logic die 110 follows... The idle cycle insertion ratio is dynamically and adaptively reduced (i.e., setting 8 working cycles and inserting 2 idle cycles in 10 consecutive total clock cycles). When the temperature has completely dropped and the global temperature control scenario is lifted, the temperature fusion controller 130 resumes the basic refresh rate and continuous working cycle.

[0083] In this embodiment, the target refresh rate is determined based on a unified temperature grading system, and the refresh frequency of at least one layer of memory die is increased. This accurately compensates for leakage losses of memory capacitors under different high temperature levels, ensuring the physical integrity of the stored data. In a global temperature control scenario, the clock gating mechanism of the logic die is triggered and idle cycles are dynamically inserted. By blocking invalid transistor flips, the peak power consumption of the logic die is directly suppressed. The combination of frequency compensation on the memory side and cycle suspension on the logic side not only effectively prevents the malignant conduction and accumulation of heat in the three-dimensional bonding layer, but also achieves rapid and proactive degradation of the entire chip's thermal load without directly shutting down the chip power supply.

[0084] In some embodiments, the temperature fusion controller 130 is further configured to determine the local area of ​​the logic die 110 that triggers the local temperature control scenario based on the first temperature data when the scenario classification result is a local temperature control scenario, and to perform buck control or frequency modulation control on the local area.

[0085] Here, "local area" refers to a hardware sub-block within the logic die 110, defined by physical space coordinates or functional module boundaries, and possessing an independent power supply domain or independent clock domain. Buck control refers to the hardware adjustment action of reducing the operating power supply voltage of the target hardware module by adjusting the output voltage parameters of the power management module. Frequency modulation control refers to the hardware adjustment action of reducing the operating clock frequency of the target hardware module by configuring the frequency division and multiplication coefficients of the clock generation circuit.

[0086] In some embodiments, the temperature fusion controller 130 parses the first temperature data, extracts the target temperature detection point whose temperature value exceeds a preset local threshold, and obtains the hardware topology coordinates of the target temperature detection point within the logic die 110. The temperature fusion controller 130 compares the hardware topology coordinates with the region mapping table of the logic die 110 to determine the power supply domain or clock domain to which the target temperature detection point belongs, and locks the determined power supply domain or clock domain as the local area that triggers the local temperature control scenario. Finally, the temperature fusion controller 130 sends adjustment parameters to the independent power management unit or independent phase-locked loop circuit bound to the local area, executes a preset step-down control or frequency modulation control, while keeping the voltage and frequency parameters of the remaining areas of the logic die 110 that have not triggered alarms unchanged.

[0087] In some embodiments, the local control mechanism for independent power supply domains or independent clock domains is not only applicable to physical cooling tasks involving localized heat generation. The local independent adjustment mechanism is also applicable to dynamic power budget allocation tasks for local areas within the logic die 110. When a transient instruction density overload is detected in a local area within the logic die 110, causing its actual current draw to exceed the allocated limit, local frequency modulation control for that local area is triggered, limiting its instruction issue rate, even if the actual temperature does not exceed the limit. This extended scheme avoids voltage noise interference caused by single-point power overload on the overall power tree distribution of the logic die 110.

[0088] For example, assume that the logic die 110 is divided into a tensor operation area and a general-purpose computing area, each with an independent power supply domain. The temperature fusion controller 130 acquires first temperature data, wherein the first temperature data indicates that the temperature reported by the temperature detection point in the tensor operation area is... The temperature reported by the temperature detection points within the general computing area is Assume the hardware's preset local control trigger threshold is... The global control trigger threshold is .because Exceeded But not exceeding The temperature fusion controller 130 determines the scene classification result as a local temperature control scene.

[0089] Subsequently, the temperature fusion controller 130, based on the first temperature data... The corresponding physical coordinates determine the local region triggering the local temperature control scenario as the tensor computation region. The temperature fusion controller 130 performs buck control on the tensor computation region. Assume the hardware buck adjustment rule is: whenever the temperature exceeds the local control trigger threshold... Lower the operating voltage The temperature fusion controller 130 performs logic operations and determines the temperature exceedance amount. minus ,equal Based on this calculation, the voltage drop is 4 times... ,equal Assume the current operating voltage of the tensor computation region is... The temperature fusion controller 130 sends a configuration command to the independent power management unit corresponding to the tensor computation area, adjusting the operating voltage of the tensor computation area to... minus That is, set as During the process of performing local voltage reduction control on the tensor computation area, the operating voltage of the general computing area remains at [value missing]. constant.

[0090] In this embodiment, when the scenario classification result is a local temperature control scenario, the local area that triggers the local temperature control scenario is determined based on the first temperature data, thereby achieving precise physical spatial positioning of the heat source inside the chip; the local area is subjected to buck control or frequency modulation control, which directly reduces the dynamic power consumption and heat generation of the specific heat-generating module from a physical level; this directional isolation and adjustment mechanism that targets only abnormal heat-generating nodes eliminates local hot spots while maintaining the high-speed operation of other non-heat-generating areas inside the logic die, thus maximizing the protection of the overall computing performance of the three-dimensional stacked chip without loss.

[0091] In some embodiments, see Figure 5 , Figure 5 This is a schematic flowchart of the temperature control method provided in this application embodiment. The temperature control method provided in this application embodiment is applied to the three-dimensional stacked chip 10 in the above embodiment. The three-dimensional stacked chip includes a logic die, at least one layer of memory die stacked on the logic die, and a temperature fusion controller. The logic die is equipped with a plurality of first temperature sensors and a plurality of temperature controllers arranged in a hierarchical manner. Each layer of memory die is equipped with at least one second temperature sensor. At least one layer of memory die is provided with a shared temperature output pin.

[0092] In step 101, multiple temperature controllers control multiple first temperature sensors to collect data and obtain the first temperature data of the logic die.

[0093] In step 102, based on the temperature collected by at least one second temperature sensor, the second temperature data of at least one layer of storage die is output through the temperature output pin.

[0094] In step 103, the temperature fusion controller performs scene classification based on the first temperature data and the second temperature data, and performs global temperature collaborative control or local area temperature control based on the scene classification results.

[0095] In some embodiments, the multiple temperature controllers include a central temperature controller and at least one level protocol controller. The multiple temperature controllers control multiple first temperature sensors to collect data to obtain the first temperature data of the logic die. This can be achieved by: sending temperature control information to the at least one level protocol controller through the central temperature controller; controlling the first temperature sensors to collect the temperature of the logic die based on the temperature control information through the at least one level protocol controller, and uploading the collected temperatures to the central temperature controller level by level; and collecting the temperature data uploaded level by level through the central temperature controller to obtain the first temperature data.

[0096] In some embodiments, at least one level of protocol controller includes a first-level protocol controller, an intermediate-level protocol controller, and a last-level protocol controller, wherein the deployment location of the first-level protocol controller corresponds to the functional partition of the logic die. The at least one-level protocol controller controls a first temperature sensor to collect the temperature of the logic die based on temperature control information, and uploads the collected temperature level by level to the central temperature controller. This can be achieved in the following ways: the first-level protocol controller receives temperature control information and, in cooperation with the intermediate-level protocol controller, broadcasts the temperature control information down level by level; the last-level protocol controller configures a control signal based on the temperature control information and sends the control signal to the first temperature sensor corresponding to the last-level protocol controller; the first temperature sensor, based on the received control signal, performs temperature acquisition at the temperature detection point corresponding to the first temperature sensor in the logic die, obtains the temperature of the temperature detection point, and returns the temperature of the temperature detection point to the last-level protocol controller, so as to transmit the collected temperature level by level upwards.

[0097] In some embodiments, the temperature output pin includes two general-purpose pins. Based on the temperature collected by at least one second temperature sensor, the temperature output pin outputs second temperature data of at least one layer of storage die. This can be achieved by: determining the highest temperature in at least one layer of storage die based on the temperature collected by the second temperature sensor; mapping the highest temperature based on a preset temperature mapping relationship to obtain discrete level states; wherein, the temperature mapping relationship indicates the correspondence between the temperature range of the storage die and the discrete level states; and outputting the discrete level states to the outside through the two general-purpose pins, the discrete level states being used as the second temperature data.

[0098] In some embodiments, global temperature collaborative control or local area temperature control based on the scenario classification result can be implemented in the following ways: when the scenario classification result is a global temperature control scenario, collaborative temperature control is performed on the logic die and at least one layer of storage die; when the scenario classification result is a local temperature control scenario, temperature control is performed on a local area of ​​the logic die.

[0099] In some embodiments, the first temperature data includes the temperatures of multiple temperature detection points in the logic die. Scene classification based on the first temperature data and the second temperature data can be achieved in the following ways: when the temperature of a target number of temperature detection points exceeds the corresponding first temperature threshold, or when the temperature classification represented by the second temperature data reaches the overheating classification state, the scene classification result is determined as a global temperature control scene; when the global temperature control scene is not triggered, and the temperature of at least some temperature detection points located in the same local area exceeds the second temperature threshold, the scene classification result is determined as a local temperature control scene.

[0100] In some embodiments, the second temperature data is used to characterize the unified temperature classification of at least one layer of memory dies. Coordinated temperature control for logic dies and at least one layer of memory dies can be implemented in the following ways: determining the target refresh rate increase for at least one layer of memory dies based on the unified temperature classification characterized by the second temperature data, and increasing the refresh frequency of at least one layer of memory dies according to the target refresh rate increase; triggering the clock gating mechanism of the logic dies, and dynamically inserting idle cycles into the working cycle of the logic dies through the clock gating mechanism.

[0101] In some embodiments, temperature control of a local area of ​​a logic die can be implemented by determining the local area of ​​the logic die that triggers the local temperature control scenario based on first temperature data, and performing buck control or frequency modulation control on the local area.

[0102] This application provides an electronic device, which includes a processor, wherein the processor includes a three-dimensional stacked chip 10 of any of the foregoing embodiments.

[0103] Based on the temperature control method defined in steps 101 to 103 above, precise adjustment of the internal heat generation of the 3D stacked chip is achieved at the technical level, and the temperature stability of the 3D stacked chip is maintained. First, multiple first temperature sensors are controlled by multiple temperature controllers set in a hierarchical manner to collect data, and the temperature control information is sent down level by level using a broadcast method, realizing efficient acquisition of the first temperature data of the logic die, and providing a comprehensive data foundation for subsequent control.

[0104] Secondly, by determining the highest temperature in at least one layer of the memory die and mapping it to discrete temperature levels based on a preset temperature mapping relationship, the second temperature data is finally output via a temperature output pin. This method ensures that the critical thermal state of the memory die can be accurately fed back in a low-resource-consumption manner.

[0105] Finally, the temperature fusion controller classifies scenarios based on the acquired first and second temperature data. When the scenario classification result is a global temperature control scenario, coordinated temperature control is performed on the logic die and at least one layer of storage die; when the scenario classification result is a local temperature control scenario, temperature control is performed only on a local area of ​​the logic die. This closed-loop adjustment mechanism, which performs differentiated control based on different scenario classification results, can accurately match the actual heat source and severity level, avoiding performance impact on unnecessary areas, thereby objectively achieving precise adjustment and temperature stability of the entire 3D stacked chip.

[0106] The following will describe an exemplary application of the embodiments of this application in a real-world application scenario.

[0107] With the continuous development of VLSI technology, the performance and functional requirements for high-performance computing chips are becoming increasingly demanding, and chip area is also constantly increasing. For example, in artificial intelligence (AI) chips, the demand for big data and computing power is enormous, and the demand for multi-core parallelism is also constantly increasing, resulting in a large amount of heat being generated inside the chip. If heat information is not effectively and timely collected, the chip's thermal information cannot be effectively controlled, which will greatly affect the stability and lifespan of the AI ​​chip, and may lead to chip failure or even damage.

[0108] Currently, in the field of chip thermal control, the common practice is to embed relevant temperature sensors within the chip as data acquisition devices to perceive internal thermal information in real time. In System-on-Chip (SOC) architectures employing three-dimensional (3D) stacked dynamic random access memory (DRAM) architectures (corresponding to the 3D stacked chip in the above embodiments), the 3D stacked DRAM portion (corresponding to at least one layer of memory die in the above embodiments) and the SOC logic portion (corresponding to the logic die in the above embodiments) have independent thermal information acquisition architectures. Furthermore, the SOC implementation requires 3D bonding of these two parts. Therefore, the SOC needs to collect thermal information from both parts and provide a reasonable thermal control scheme to ensure that the SOC can maintain a stable and high-performance operating state for extended periods. To cope with different high-performance application scenarios, the design of thermal control schemes for SOCs based on 3D stacked DRAM architectures has become more complex, and higher demands are placed on the timeliness and accuracy of thermal information collection.

[0109] This application addresses the shortcomings of existing technologies by proposing a temperature control method for three-dimensional stacked chips. See also... Figure 1 The three-dimensional stacked chip 10 is divided into two parts: an on-chip integrated chip logic part (corresponding to the logic die 110 in the above embodiment) and a three-dimensional stacked dynamic random access memory part (corresponding to at least one layer of memory die 120 in the above embodiment).

[0110] All temperature information from the logic section of the on-chip integrated chip is collected and transmitted through the temperature controllers inside the on-chip integrated chip (corresponding to the multiple temperature controllers 111 in the above embodiments). The temperature controllers consist of a central temperature controller (corresponding to the central temperature controller 310 in the above embodiments), a first-level protocol controller (corresponding to the first-level protocol controller 321 in the above embodiments), a second-level protocol controller (not limited to two-level protocol controllers, but can have multiple-level protocol controllers, corresponding to the intermediate-level protocol controller 322 in the above embodiments), and a temperature sensor (corresponding to the first temperature sensor 112 in the above embodiments).

[0111] The number of controller levels depends on the area of ​​the on-chip integrated circuit (IC) logic die, the distribution density of temperature detection points (corresponding to the temperature detection points in the above embodiments), and the response speed requirements for heat control. For small IC logic dies (50 or fewer temperature detection points), a central temperature controller combined with a single-level protocol controller can be used. For medium to large dies (50 to 200 temperature detection points), a two-level protocol controller is used. For very large dies (more than 200 temperature detection points, such as high-performance AI chips), a three-level or higher protocol controller can be used. More levels enable distributed data collection, avoid overloading a single controller, and ensure smooth heat information transmission.

[0112] Regarding the number of deployments, the number of Level 1 protocol controllers corresponds to the functional partitions of the logic die. One Level 1 protocol controller is deployed for each functional partition (e.g., arithmetic unit area, storage interface area) to ensure that heat information from each partition is collected independently without interference. The number of Level 2 and higher protocol controllers matches the coverage area and number of temperature detection points of the corresponding Level 1 controller. One Level 1 controller can correspond to multiple Level 2 controllers (e.g., one Level 1 protocol controller covers 2 to 4 Level 2 protocol controllers). Each Level 2 controller is responsible for collecting data from temperature sensors in a local area (e.g., one Level 2 protocol controller corresponds to 10 to 20 temperature sensors). The constraint of the above configuration is that the number of controllers at each level must match the physical wiring resources of the chip to prevent excessive controllers from causing wiring congestion, while ensuring sufficient information transmission bandwidth for each level controller.

[0113] The functions of the temperature central controller include sending global thermal control commands, summarizing all heat information, deciding on thermal scenario classification and temperature control strategies, and controlling the entire on-chip integrated chip logic die and three-dimensional stacked dynamic random access memory.

[0114] The function of the first-level protocol controller is to relay and conduct information. It receives instructions from the central temperature controller and forwards them to the lower-level controllers. It also collects heat information from the lower-level controllers and uploads it to the central temperature controller. The first-level protocol controller corresponds to a functional area (e.g., the computing unit area).

[0115] The functions of the second-level and above protocol controllers are to receive instructions from the upper-level controller, control the temperature sensors in the corresponding area, collect temperature data and upload it. The second-level and above protocol controllers correspond to a local area (such as a specific module in the computing unit area).

[0116] The specific control and interaction process is as follows: The central temperature controller is primarily responsible for sending temperature control information (corresponding to the temperature control information in the above embodiment) to the first-level protocol controller and collecting the temperature information collected by the first-level protocol controller. The central temperature controller can broadcast the temperature control information to all first-level protocol controllers or send the temperature control information individually to a specific first-level protocol controller.

[0117] The first-level protocol controller receives temperature control information from the central temperature controller and transmits it to the second-level protocol controller. The first-level protocol controller can broadcast the temperature control information to all second-level protocol controllers or send it individually to a specific second-level protocol controller.

[0118] The core function of temperature control information is to achieve hierarchical transmission of thermal control commands and unified scheduling of temperature acquisition. First, command transmission: It accurately transmits global or local thermal control commands (such as temperature sensor configuration commands and temperature acquisition frequency adjustment commands) issued by the central temperature controller to the second-level protocol controller, ensuring that lower-level controllers understand the operational requirements and synchronously execute heat information acquisition and control operations. Second, scheduling and coordination: It transmits the coordination and scheduling information of the central temperature controller, enabling the second-level protocol controller to maintain synchronized operation with other controllers at all levels (including those at the same level and those at higher and lower levels), avoiding chaotic temperature acquisition and conflicting control commands, and ensuring the orderly operation of the temperature acquisition architecture of the entire on-chip integrated chip logic section. Third, feedback support: It provides the command basis for the second-level protocol controller to upload temperature data (i.e., the acquired local area temperature information), ensuring that the second-level protocol controller understands the timing, format, and path of data upload, helping the central temperature controller quickly summarize the heat information of the entire chip, and providing data support for thermal scenario classification (e.g., corresponding to the global temperature control scenario or local temperature control scenario in the above embodiments) and temperature control strategy decisions.

[0119] The second-level protocol controller receives the temperature control information from the first-level protocol controller and then transmits the temperature control information from the first-level protocol controller to the subsequent... ( Level 1 protocol controller. The Level 2 protocol controller can broadcast this temperature control information to all Level 1 controllers. Level 1 protocol controller. Here, the second-level protocol controller is a fixed intermediate level, while the third-level protocol controller is a fixed intermediate level. The protocol controller is a variable subsequent layer ( (Any integer greater than or equal to 2). That is, the second-level protocol controller belongs to the... A type of protocol controller (when) (At that time, the two overlapped), but the first The level-two protocol controller can include not only the second level, but also the third, fourth, and so on, to adapt to the temperature acquisition requirements of chips of different sizes. Furthermore, the second-level protocol controller can also send the temperature control information independently to a specific third-level controller. Level 1 protocol controller. The Level 2 protocol controller collects data from the Level 1 protocol controller. The first-level protocol controller acquires the temperature information and uploads it to the first-level protocol controller.

[0120] The temperature sensor is based on the first The control signal issued by the first-level protocol controller (corresponding to the last-level protocol controller 323 in the above embodiment) is used to acquire the temperature of the temperature detection point and return the temperature information to the first-level protocol controller. The first-level protocol controller completes the acquisition of temperature information. Among them, this first-level... The level protocol controller can broadcast control signals to the level 1 controller. The primary protocol controller is responsible for all temperature sensors within its range. A first-level protocol controller... The level protocol controller is not fixedly connected to a single temperature sensor, but rather corresponds to multiple temperature sensors, forming a one-to-many connection. As the level closest to the temperature sensor, the first-level protocol controller receives temperature control information from the higher-level controller (e.g., the second-level protocol controller) and converts this information into a specific electrical signal (i.e., the control signal) that the temperature sensor can recognize and execute. This conversion process is essentially a command translation and parameter configuration process, including functions such as starting or stopping information acquisition, configuring acquisition parameters, and calibrating the acquisition results. Temperature control information belongs to the higher-level commands and is a macroscopic command transmitted between various protocol controllers (e.g., from the central temperature controller to the first-level protocol controller, from the first level to the second level, and from the second level to the third level). (Instructions transmitted by the level protocol controller). Control signals are execution signals and are the first level. The specific electrical signals (e.g., high / low levels, pulse signals) translated by the level protocol controller are concrete physical signals that can be directly recognized and executed by the temperature sensor. The protocol controller is configured and generated based on the received temperature control information.

[0121] See Figure 6 , Figure 6 This is a schematic diagram of the multi-level broadcast process of temperature control information provided in an embodiment of this application. To visually illustrate the transmission process of temperature control information in the aforementioned multi-level protocol controller architecture, as shown... Figure 6 As shown, the multi-level protocol controllers adopt a cascading broadcast mechanism, which specifically includes: first-level broadcast, second-level broadcast, and nth-level broadcast that extends downwards along the hardware link.

[0122] In the first-level broadcast phase, after receiving temperature control information from the central temperature controller, the first-level protocol controller synchronously and in parallel transmits this temperature control information to all second-level protocol controllers connected to the same functional partition via the broadcast channel. Subsequently, in the second-level broadcast phase, upon receiving the temperature control information, the second-level protocol controllers execute the same parallel transmission process, broadcasting the temperature control information to subsequent levels of protocol controllers. For example... Figure 6 The combination of unidirectional and dashed arrows indicates the transmission path. This instruction transmission process cascades down the hardware topology layer by layer until it reaches the nth-level protocol controller, which is the final level. Finally, in the nth-level broadcast phase, after completing the instruction translation, the nth-level protocol controller broadcasts the generated physical control signals in parallel to all temperature sensors within its area of ​​responsibility, triggering the underlying temperature acquisition actions. Figure 6 The multi-level broadcast delivery process shown effectively avoids the accumulation of transmission time in the unicast polling mode and accelerates the transmission efficiency of heat control commands to the underlying physical nodes.

[0123] The above architecture design enables the acquisition of large amounts of temperature information within a single on-chip integrated circuit. A central temperature controller and a hierarchically configured multi-level protocol controllers are used to transmit temperature control information and collect temperature data. Broadcasting accelerates the rapid transmission of temperature control information to each level of the protocol controller, saving transmission time. By configuring multiple protocol controllers at various levels, independent collection and precise control of temperature information in localized areas of the chip are achieved.

[0124] The following describes the heat control method for the three-dimensional stacked dynamic random access memory section.

[0125] The thermal control information for the three-dimensional stacked dynamic random access memory (DRAM) portion (corresponding to at least one layer of memory die 120 in the above embodiment) is obtained by acquiring the temperature of the DRAM chips through a temperature sensor (Sensor, corresponding to the second temperature sensor 121 in the above embodiment) deployed inside the DRAM die. Information is transmitted externally via two physical pins (Pad, corresponding to the two general-purpose pins in the above embodiment). These two general-purpose pins output binary logic level states 00, 01, 10, or 11 (corresponding to discrete level states in the above embodiment). The preset mapping relationship between this discrete level state and the internal temperature range of the DRAM die (corresponding to the temperature mapping relationship in the above embodiment) is shown in Table 1 below: Table 1

[0126] Each dynamic random access memory die will deploy multiple temperature sensors, rather than just one, based on its physical size and heat distribution characteristics, in order to meet the requirements for accuracy and grading of temperature acquisition.

[0127] In terms of specific implementation, firstly, the temperature information inside a single dynamic random access memory die is summarized. Then, all stacked dynamic random access memory dies are bonded to the logic part of the on-chip integrated chip through a three-dimensional bonding process, sharing two general-purpose pins as temperature information output interfaces (corresponding to temperature output pin 122 in the above embodiment).

[0128] Figure 7 This is a schematic diagram of the thermal information fusion control process provided in an embodiment of this application. The thermal information fusion control process of the on-chip integrated chip is as follows. Figure 7 As shown, the temperature fusion controller 130 collects graded temperature information from the storage die (corresponding to the second temperature data in the above embodiments, i.e., 00, 01, 10, and 11 mentioned above) and temperature information from the logic die temperature sensor (corresponding to the first temperature data in the above embodiments, transmitting actual temperature values, such as 88°C and 92°C, not binary data). Based on the temperature strategy scheme selected by the chip, the temperature fusion controller performs thermal scene classification 701 (corresponding to scene classification in the above embodiments).

[0129] The results of this thermal scene classification 701 include the following two scenarios: The first scenario is a global overheating scenario (corresponding to the global temperature control scenario in the above embodiments). The determination condition for this global overheating scenario is: the temperature of each part of the logic die exceeds a certain first temperature threshold, or the temperature of the dynamic random access memory (DRAM) die reaches a temperature-graded overheating state. Specifically, the determination condition for this global overheating scenario is a logical OR relationship of "the temperature of each part of the logic die exceeds a certain first temperature threshold or the temperature of the DRAM die reaches a graded overheating state". On the logic die side, as long as the sensor temperature of most core areas and key heat-generating areas (such as the arithmetic unit area) exceeds the first temperature threshold, it can be determined as global overheating; it is not necessary for all sensors to exceed the first temperature threshold.

[0130] For example, a logic die has 10 sensors. If 8 exceed a threshold (e.g., 90°C) and 2 do not (e.g., 80°C), combining this with the core area temperature provides a more reliable indicator and can be considered a global overheating situation. The first temperature thresholds for the temperature sensors deployed in different parts of the logic die (i.e., the on-chip integrated logic section) are not all the same; instead, they are differentiated based on the heat dissipation characteristics of the deployed areas. On the storage die side, the classification of overheating refers to the 10 (…) temperature sensors corresponding to two general-purpose pins. ) and 11 ( These two levels. Multiple stacked dynamic random access memory (DRAM) dies output temperature level information through two shared general-purpose pins. The core principle is to take the highest temperature level. That is, if any one of the stacked DRAM dies reaches an overheated state (10 or 11), the overall output binary level corresponds to the overheated level and is considered as the DRAM die reaching an overheated state.

[0131] When a scenario is determined to be a global overheating scenario, such as Figure 7 As shown in the global overheating branch, cross-layer cooperative temperature control 703 is executed (corresponding to the cooperative temperature control in the above embodiment). This cooperative temperature control includes: In the Dynamic Random Access Memory (DRAM) layer (corresponding to at least one memory die 120 in the above embodiments), the refresh rate is increased (up to 2 times), and capacitor leakage is compensated according to the corresponding data level. The increase in DRAM refresh rate varies depending on the temperature level. When multiple memory dies have different temperature levels, the refresh rate is not increased according to each individual temperature level, but rather all DRAM dies are uniformly increased according to the level corresponding to the highest temperature level. In a global overheating scenario, the overall chip thermal load has reached a point requiring emergency temperature control. Even if only the logic die overheats, heat will be conducted to the DRAM layer through the three-dimensional bonding layer, causing the DRAM die temperature to rise accordingly. Increasing the DRAM refresh rate in advance can prevent the DRAM die from overheating as well. When the global overheating scenario is resolved, the default refresh rate is restored.

[0132] At the logic layer (corresponding to the logic die 110 in the above embodiment), idle cycles (clock gating) are inserted to reduce peak power consumption. The idle cycle is not of fixed duration but dynamically adjusted according to temperature changes. Its duration is positively correlated with chip temperature (including logic die temperature and dynamic random access memory die temperature); the higher the temperature, the longer the idle cycle; the lower the temperature, the shorter the idle cycle, until the global overheating scenario is resolved and normal operation resumes. The proportion of inserted idle cycles is determined during the chip design phase based on the chip's analog power consumption.

[0133] The second type is the local overheating scenario (corresponding to the local temperature control scenario in the above embodiments). The determination condition for this local overheating scenario is that the temperature of a certain part of the logic die exceeds a certain second temperature threshold. The core of this local overheating scenario is that the temperature of a certain local area exceeds the limit, rather than a single sensor exceeding the limit. That is, as long as the sensor temperature corresponding to a certain local area (e.g., a functional area of ​​the logic die) exceeds the second temperature threshold, it is determined to be local overheating. The second temperature threshold of the sensor in this local overheating scenario is not necessarily equal to the first temperature threshold of the global overheating scenario. Global overheating and local overheating can coexist. When they coexist, temperature control is performed according to the principle of global priority. Local overheating only includes the logic die and does not consider dynamic random access memory (DRAM). When the temperature of DRAM reaches a temperature-graded overheating state, it is considered global overheating.

[0134] When the scenario is determined to be a localized overheating scenario, such as Figure 7As shown by the local overheating branch, an adaptive adjustment working strategy 702 (corresponding to the temperature control of the local area in the above embodiments) can be adopted, and measures to reduce local overheating can be taken, such as voltage reduction and frequency modulation schemes. The adaptive adjustment strategy includes frequency reduction or test voltage reduction. When the global overheating scenario is not triggered, the normal working state is executed; when the global overheating scenario is triggered, linkage control is executed.

[0135] The embodiment of the present application proposes a fusion thermal control design method for a three-dimensional stacked dynamic random access memory architecture. Based on this fusion thermal control design method for a three-dimensional stacked dynamic random access memory architecture, the requirement for collecting a large amount of temperature information in the on-chip integrated chip of the three-dimensional stacked dynamic random access memory architecture can be met. The temperature control information is sent and the temperature data is collected through multiple protocol controllers set hierarchically, and the rapid transmission of temperature control information to each level of protocol controllers is accelerated through broadcast, saving transmission time. By configuring multiple protocol controllers at each level, the independent collection and precise control of local area temperature information are achieved. The heat information of the logic chip and the hierarchical heat control information of the three-dimensional stacked dynamic random access memory are fused by the temperature fusion controller, and the heat control of the entire chip is achieved by using the scenario classification method, realizing the flexible control of local and global heat scenarios, and ensuring that the entire chip can effectively and quickly reach the temperature control target of the entire chip under a high-density working scenario.

[0136] This design scheme is not limited to temperature information collection and can be extended to the implementation of chip voltage information collection, current information collection, process information collection and other schemes.

[0137] In summary, through the embodiment of the present application, a three-dimensional fusion thermal management hardware architecture spanning the logic die and at least one storage die is constructed. At the data collection level, on the logic die side, through the hierarchically set temperature controller and broadcast communication mechanism, the efficient concurrent collection and low-latency transmission of a large amount of first temperature data are achieved; on the storage die side, through multi-layer data aggregation and discrete level state mapping, while greatly saving the physical pin resources of the three-dimensional package, the cross-layer feedback of highly reliable second temperature data is achieved. At the control decision level, the temperature fusion controller establishes a scenario classification mechanism with global and local decoupling based on the overall analysis of the first temperature data and the second temperature data. At the execution response level, this architecture can execute linkage control when the global heat load is overloaded to block the vicious conduction of heat across layers and ensure the physical integrity of the stored data; at the same time, it can execute precise spatial isolation control when local heat accumulation occurs to maintain the high-speed operation of the non-heating area. The above-mentioned software and hardware collaborative fusion control scheme perfectly balances the physical thermal safety and overall operation performance of the three-dimensional stacked chip in an extremely high computing power scenario, and significantly improves the operation stability and service life of the high-density packaging architecture.

[0138] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A three-dimensional stacked chip, characterized in that, The three-dimensional stacked chip includes: Logic die and at least one layer of memory die stacked on the logic die; Multiple first temperature sensors and multiple temperature controllers arranged in a hierarchical manner are deployed in the logic die. The multiple temperature controllers are used to control the multiple first temperature sensors to collect first temperature data of the logic die. At least one second temperature sensor is deployed in each layer of the memory die, and a temperature output pin is shared by the at least one layer of memory dies. The temperature output pin is used to output second temperature data of the at least one layer of memory dies, which is determined based on the temperature collected by the at least one second temperature sensor. A temperature fusion controller is connected to the temperature controller and the temperature output pin, respectively, and is used to classify the scene based on the first temperature data and the second temperature data, and to perform global temperature collaborative control or local area temperature control based on the scene classification result.

2. The three-dimensional stacked chip according to claim 1, characterized in that, The plurality of temperature controllers includes a central temperature controller and at least one level protocol controller, wherein... The temperature central controller is used to send temperature control information to the at least one level protocol controller and collect the temperature data uploaded level by level to obtain the first temperature data. The at least one-level protocol controller is used to control the first temperature sensor to collect the temperature of the logic die based on the temperature control information, and to upload the collected temperature to the temperature central controller level by level.

3. The three-dimensional stacked chip according to claim 2, characterized in that, The at least one level of protocol controller includes a first-level protocol controller, intermediate-level protocol controllers, and a final-level protocol controller, wherein, The deployment location of the first-level protocol controller corresponds to the functional partition of the logic die. It is used to receive the temperature control information and cooperate with the intermediate-level protocol controller to send the temperature control information down level by level in a broadcast manner. The last-level protocol controller is configured to configure a control signal based on the temperature control information and send the control signal to the first temperature sensor corresponding to the last-level protocol controller. The first temperature sensor is used to perform temperature acquisition on the temperature detection point corresponding to the first temperature sensor in the logic die based on the received control signal, obtain the temperature of the temperature detection point, and return the temperature of the temperature detection point to the last-level protocol controller, so as to pass the acquired temperature upwards level by level.

4. The three-dimensional stacked chip according to claim 1, characterized in that, The temperature output pin includes two general-purpose pins, wherein, The at least one layer of memory die is used to determine the highest temperature in the at least one layer of memory die based on the temperature collected by the second temperature sensor, and to map the highest temperature based on a preset temperature mapping relationship to obtain discrete level states; wherein, the temperature mapping relationship indicates the correspondence between the temperature range in which the temperature of the memory die falls and the discrete level states; The two general-purpose pins are used to output the discrete level state, which is used as the second temperature data.

5. The three-dimensional stacked chip according to claim 1, characterized in that, In the case where the scenario classification result is a global temperature control scenario, the temperature fusion controller is also used to perform coordinated temperature control for the logic die and the at least one layer of storage die; In the case where the scenario classification result is a local temperature control scenario, the temperature fusion controller is also used to perform temperature control for a local area of ​​the logic die.

6. The three-dimensional stacked chip according to claim 5, characterized in that, The first temperature data includes the temperatures of multiple temperature detection points in the logic die. The temperature fusion controller is further configured to determine the scene classification result as the global temperature control scene when the temperature of the target number of temperature detection points exceeds the corresponding first temperature threshold, or when the temperature classification represented by the second temperature data reaches the overheating classification state. The temperature fusion controller is further configured to determine the scene classification result as the local temperature control scene when the global temperature control scene is not triggered and the temperature of at least some of the temperature detection points located in the same local area exceeds the second temperature threshold.

7. The three-dimensional stacked chip according to claim 5, characterized in that, The second temperature data is used to characterize the uniform temperature gradation of the at least one layer of memory die. The temperature fusion controller is further configured to, when the scenario classification result is a global temperature control scenario, determine the target refresh improvement magnitude corresponding to the at least one layer of storage die based on the unified temperature classification characterized by the second temperature data, and increase the refresh frequency of the at least one layer of storage die according to the target refresh improvement magnitude. The temperature fusion controller is also used to trigger the clock gating mechanism of the logic die when the scenario classification result is a global temperature control scenario, and to dynamically insert idle cycles into the working cycle of the logic die through the clock gating mechanism.

8. The three-dimensional stacked chip according to claim 5, characterized in that, The temperature fusion controller is further configured to, when the scenario classification result is a local temperature control scenario, determine the local area of ​​the logic die that triggers the local temperature control scenario based on the first temperature data, and perform buck control or frequency modulation control on the local area.

9. A temperature control method, characterized in that, This invention relates to a 3D stacked chip, comprising a logic die, at least one layer of memory dies stacked on the logic die, and a temperature fusion controller. The logic die has multiple first temperature sensors and multiple hierarchically configured temperature controllers deployed therein. Each layer of memory dies has at least one second temperature sensor deployed therein. The at least one layer of memory dies has a shared temperature output pin. The method includes: The multiple temperature controllers control the multiple first temperature sensors to collect data, thereby obtaining the first temperature data of the logic die. Based on the temperature collected by the at least one second temperature sensor, the second temperature data of the at least one layer of storage die is output through the temperature output pin; The temperature fusion controller performs scene classification based on the first temperature data and the second temperature data, and performs global temperature collaborative control or local area temperature control based on the scene classification results.

10. An electronic device, characterized in that, The electronic device includes a processor, wherein the processor includes a three-dimensional stacked chip as described in any one of claims 1 to 8.

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