A multifunctional vehicle-mounted TSN testing device and its testing method

Abstract

This invention belongs to the field of automotive testing technology and discloses a multifunctional automotive TSN testing device and its testing method. The testing method includes: enabling all test ports to share the same time base; generating inbound and outbound timestamps for all incoming and outbound frames in a unified time domain; forming a port-level time-aware scheduling matrix; deeply binding the Layer 3 packet payload to a designated physical port and outputting test traffic through the timestamp injection unit of each port; recording the inbound and outbound timestamps of abnormal frames under the same time base; generating TSN consistency verification results based on the inbound and outbound timestamps; and performing cross-protocol delay consistency verification between automotive Ethernet and CAN / LIN. This invention achieves TSN function verification and cross-protocol delay consistency testing under a unified time base, improving the overall testing accuracy and consistency analysis capability in a multi-protocol automotive network environment.

Description

Technical Field

[0001] This invention relates to the field of vehicle-mounted testing technology, specifically to a multifunctional vehicle-mounted TSN testing device and its testing method, electronic equipment, and storage medium. Background Technology

[0002] Developing in-vehicle TSN testing equipment is a critical infrastructure for ensuring safety, improving efficiency, and promoting industry collaboration in the era of intelligent vehicles. It serves multiple stakeholders, including automakers, component suppliers, and testing and certification bodies, helping the industry smoothly transition from a "traditional distributed architecture" to a "centralized high-performance network," possessing long-term strategic value and market prospects. For example: 1) It can support the upgrading of vehicle intelligence and connectivity, and in autonomous driving and advanced driver assistance systems (ADAS) scenarios: TSN provides highly reliable, low-latency network communication, ensuring real-time data synchronization between sensors (cameras, radar, lidar) and control units. The testing equipment can verify whether the TSN network performance meets stringent safety requirements. 2) It can ensure the reliability and security of in-vehicle networks: Functional safety (ISO 26262): TSN testing equipment can simulate extreme network conditions (such as latency, jitter, congestion) to verify the stability of the network under fault scenarios, complying with automotive functional safety standards; Network security: The testing equipment can detect the anti-interference capability and data integrity of the TSN network, preventing the loss of critical data or operational failure due to network attacks. 3) Reduced R&D and verification costs: TSN design flaws can be identified in advance through dedicated testing equipment during laboratory and real vehicle testing phases, avoiding high costs for later rectification;

[0003] Achieving standardized testing processes: Providing unified testing methods and tools to help automakers, suppliers, and testing institutions efficiently complete compliance verification and shorten development cycles. 4) Promoting industry standards and ecosystem development: TSN involves the IEEE 802.1 series of standards. Testing equipment can promote the standardized application of TSN in the automotive industry and facilitate collaboration across the industry chain (chips, software, and vehicles); providing automakers, component suppliers, and testing institutions with key tools to accelerate the process of TSN technology from R&D to mass production.

[0004] However, existing TSN testing equipment typically has the following problems: the time base of each test port is independent, making it difficult to ensure the consistency of cross-port measurements; timestamp recording is mostly done at the software layer, resulting in jitter errors; cross-protocol (such as Ethernet and CAN / LIN) tests lack a unified time base; interference injection is usually a preset mode, lacking a closed-loop feedback mechanism, etc.

[0005] Therefore, there is a need for a comprehensive test device that can achieve high-precision port-level measurement and has cross-protocol consistency testing capabilities. Summary of the Invention

[0006] To overcome the shortcomings of the prior art, the purpose of this invention is to provide a multifunctional vehicle-mounted TSN testing device and its testing method and electronic equipment, establish a complete testing process under a unified time domain, realize cross-protocol consistency verification, and improve the overall testing accuracy and consistency analysis capability in a multi-protocol vehicle-mounted network environment.

[0007] To address the aforementioned problems, the first aspect of this invention discloses a multifunctional vehicle-mounted TSN testing device, which includes the following:

[0008] A multi-port physical interface module is used to enable physical signal access to the vehicle network;

[0009] The FPGA-based data path module includes an integrated unit for encoding, decoding and MAC processing of data from each port, and a processing channel located at the data link layer. The processing channel is used to perform traffic mirroring, frame modification and frame injection operations, and to record the time information of inbound and outbound data frames from each port.

[0010] The unified time synchronization module is used to share a unified time synchronization protocol among various ports and to complete global time synchronization.

[0011] The timestamp injection unit is set at the MAC inlet and outlet of each port and is used to insert and extract frame timestamps;

[0012] The TSN control logic module is used to implement Qav credit base traffic shaping, Qbv time-aware traffic shaping, Qbu frame preemption, Qci per-stream filtering and policing, and Qcb frame duplication and elimination.

[0013] The traffic generation and control module includes a Linux control subsystem, a second- or third-layer packet generation engine, and an open API interface. The API interface is used to bind the generated packet payload to a specified physical port and send it through the timestamp injection unit of the corresponding port.

[0014] Error frame injection module, used to generate CRC tampered or corrupted frames to simulate network anomalies;

[0015] An FPGA hardware interface is used to extend support for conversion testing between CAN / LIN interfaces and automotive Ethernet.

[0016] Optionally, the multi-functional vehicle-mounted TSN testing equipment further includes an adaptive interference injection control module, which is connected to the error frame injection module. When the port-level time offset vector exceeds a first preset threshold, interference frame injection is automatically triggered to form a time closed-loop verification mechanism.

[0017] A second aspect of this invention discloses a testing method for a multifunctional vehicle-mounted TSN testing device, comprising the following steps:

[0018] In the test equipment, a reference clock signal is generated based on a high-precision oscillator and a phase-locked loop. A unified synchronization domain for all ports is established through the IEEE 802.1AS protocol, and the test equipment is set as the time master node so that all test ports share the same time reference.

[0019] Establish a multi-port data path based on a switching structure, and embed timestamp injection units at the MAC inlet and MAC outlet of each port respectively, so that all incoming and outgoing frames generate inbound and outbound timestamps in a unified time domain;

[0020] Based on the unified time domain, Qav credit shaping, Qbv time-aware scheduling, Qbu frame preemption, Qci per-stream filtering supervision, and Qcb frame duplication and elimination are configured for each port to form a port-level time-aware scheduling matrix.

[0021] The Linux control subsystem calls the traffic generation engine to deeply bind the third-layer packet payload to the specified physical port, and outputs test traffic through the timestamp injection unit 240 of each port;

[0022] Perform CRC tampering or corrupted frame injection, and record the inbound and outbound timestamps of the abnormal frames under the same time base;

[0023] Based on the inbound and outbound timestamps, a TSN consistency verification result is generated; the TSN consistency verification result includes port-level transmission latency, scheduling window deviation, preemption trigger time deviation, and frame replication consistency difference.

[0024] Switch some ports to CAN or LIN hardware mode and perform cross-protocol latency consistency verification between vehicle Ethernet and CAN / LIN under the unified time domain.

[0025] Optionally, the port-level transmission delay includes a media access control layer processing delay segment, a scheduling waiting delay segment, a frame preemption insertion delay segment, and a forwarding propagation delay segment.

[0026] Optional, also includes:

[0027] Based on the scheduling window deviation, preemption trigger time deviation, and frame replication consistency difference, a port-level time offset vector is generated. When the port-level time offset vector exceeds a first preset threshold, interference frame injection is automatically triggered, and the timestamp is re-recorded to form a closed-loop verification.

[0028] Optionally, the first preset threshold includes at least two graded thresholds, and different levels of interference injection strategies are triggered when the port-level time offset vector is in different graded threshold ranges.

[0029] Optional, also includes:

[0030] When the port-level time offset vector exceeds the second preset threshold, a calibration frame is generated and a loop structure is formed in the internal data path. The port-level time offset is corrected by comparing the inbound timestamp and outbound timestamp of the calibration frame.

[0031] Optionally, the step of performing cross-protocol delay consistency verification between vehicle Ethernet and CAN / LIN in the unified time domain includes: obtaining the timestamps of Ethernet and CAN / LIN in the unified time domain, and performing time granularity mapping processing on the timestamps according to the scheduling time granularity of the target protocol to calculate the end-to-end time difference, and generating a cross-protocol delay consistency result based on the time difference.

[0032] A third aspect of the present invention discloses an electronic device comprising: a memory storing executable program code; a processor coupled to the memory; the processor calling the executable program code stored in the memory to execute the test method of the multifunctional vehicle-mounted TSN test device disclosed in the second aspect of the present invention.

[0033] A fourth aspect of the present invention discloses a computer-readable storage medium storing a computer program, wherein the computer program causes a computer to execute the test method of the multifunctional vehicle-mounted TSN test device disclosed in the first aspect of the present invention.

[0034] Compared with the prior art, the beneficial effects of the embodiments of the present invention are as follows:

[0035] The test equipment of this invention establishes a multi-port physical interface module and an FPGA data path module. All ports share the board-level master clock, avoiding local time drift between ports. The MAC entry and exit points are embedded through a timestamp injection unit, directly recording the inbound / outbound time at the hardware layer, avoiding software statistical errors. Based on a unified time synchronization module, a unified synchronization domain is established to achieve time consistency across all ports. At the same time, through error frame injection and traffic generation and control modules, a complete test link of "generation-disturbance-recording-analysis" is realized, providing an integrated, unified time domain, and multi-protocol extended vehicle TSN test platform.

[0036] Furthermore, the testing method of the present invention obtains the timestamps of Ethernet and CAN / LIN in a unified time domain, and calculates the end-to-end time difference after performing time granularity mapping processing on the timestamps according to the scheduling time granularity of the target protocol. This achieves normalization processing of time resolution of different protocols, avoids error amplification caused by direct comparison, and improves the accuracy and reliability of cross-protocol delay consistency judgment. Attached Figure Description

[0037] Figure 1 This is a flowchart illustrating a testing method for a multifunctional vehicle-mounted TSN testing device according to an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of the structure of a multifunctional vehicle-mounted TSN testing device provided in an embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram of the structure of an electronic device disclosed in an embodiment of the present invention. Detailed Implementation

[0040] This specific embodiment is merely an explanation of the embodiments of the present invention and is not intended to limit the embodiments of the present invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but as long as they are within the scope of the claims of the embodiments of the present invention, they are protected by patent law.

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the embodiments of the present invention.

[0042] The term "comprising" and any variations thereof in the specification and claims of this application are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to such process, method, product or device.

[0043] In embodiments of the present invention, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in embodiments of the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0044] The following is a description of the English abbreviations and related terms used in the text:

[0045] TSN (Time-Sensitive Networking) refers to a deterministic Ethernet communication technology system built on the IEEE 802.1 standard family, used to achieve time-deterministic data transmission with low latency, low jitter, and high reliability.

[0046] IEEE (Institute of Electrical and Electronics Engineers): The international standards organization that develops standards related to Ethernet and TSN.

[0047] IEEE 802.1AS (Timing and Synchronization for Time-Sensitive Applications): A timing and synchronization standard for time-sensitive applications, used to establish a unified time synchronization domain in a network to achieve high-precision time synchronization between devices.

[0048] Qav (IEEE 802.1Qav, Credit-Based Shaper): A credit-based traffic shaping mechanism used for bandwidth shaping and rate control of real-time service traffic.

[0049] Qbv (IEEE 802.1Qbv, Time-Aware Shaper): A time-aware shaping scheduling mechanism that uses a gating scheduler to achieve deterministic transmission control based on time windows.

[0050] Qbu (IEEE 802.1Qbu, Frame Preemption): A frame preemption mechanism used to allow high-priority frames to interrupt the transmission of low-priority frames, thereby reducing latency for critical services.

[0051] Qci (IEEE 802.1Qci, Per-Stream Filtering and Policing): A per-stream filtering and policing mechanism used to filter and police individual service flows.

[0052] Qcb (IEEE 802.1Qcb, Frame Replication and Elimination for Reliability): A frame replication and elimination mechanism that improves communication reliability through multipath redundant transmission and duplicate frame elimination.

[0053] PLL (Phase-Locked Loop): A phase-locked loop circuit used to multiply and phase-lock the reference clock to generate a stable system master clock signal.

[0054] FPGA (Field-Programmable Gate Array): A programmable hardware device that allows for the reconfiguration of data paths and control logic through logic configuration.

[0055] MAC (Media Access Control): The Media Access Control layer is a sublayer of the data link layer, responsible for frame encapsulation, address identification, and link access control.

[0056] PHY (Physical Layer Transceiver): A physical layer transceiver used to implement physical layer signal encoding, decoding, and electrical interface conversion.

[0057] IP core (Intellectual Property Core): An intellectual property core refers to a reusable hardware functional module unit.

[0058] CRC (Cyclic Redundancy Check): Used to detect errors in data frames during transmission.

[0059] Linux (Linux Operating System): The Linux operating system is used to implement control and management functions in test equipment.

[0060] API (Application Programming Interface): An application programming interface used to enable calls and interactions between software control modules and underlying hardware modules.

[0061] L2 (Layer 2): The second layer, namely the data link layer.

[0062] L3 (Layer 3): The third layer, also known as the network layer.

[0063] IP (Internet Protocol): The Internet Protocol is a network layer protocol used to define the addressing and routing mechanisms for datagrams.

[0064] UDP (User Datagram Protocol): A connectionless data transmission protocol at the transport layer.

[0065] CAN (Controller Area Network): A serial communication protocol widely used in automotive electronic systems.

[0066] LIN (Local Interconnect Network): A low-cost in-vehicle serial communication protocol.

[0067] 100BASE-T1 (100 Megabit per second Baseband over Single Twisted Pair): A 100Mbps automotive Ethernet physical layer standard based on a single twisted pair.

[0068] 1000BASE-T1 (1000 Megabit per second Baseband over Single TwistedPair): A 1000Mbps automotive Ethernet physical layer standard based on a single pair of twisted-pair cables.

[0069] This invention establishes a multi-port data path under a unified time synchronization domain and embeds a timestamp injection unit 240 at the MAC inlet and outlet. Combined with TSN scheduling configuration, traffic generation, abnormal frame injection, and cross-protocol switching steps, it realizes TSN function verification and cross-protocol latency consistency testing under a unified time reference. This makes the testing process structured and repeatable, and improves the overall testing accuracy and consistency analysis capability in a multi-protocol vehicle network environment.

[0070] Example 1

[0071] Please refer to Figure 1-3 As shown, a test method for a multi-functional vehicle-mounted TSN test device, such as... Figure 1 As shown, it includes the following steps:

[0072] Step S110: In the test equipment, a reference clock signal is generated based on a high-precision oscillator and a phase-locked loop. A unified synchronization domain for all ports is established through the IEEE 802.1AS protocol, and the test equipment is set as the time master node so that all test ports share the same time reference.

[0073] In this step, a high-stability crystal oscillator can be set on the motherboard of the test equipment as the reference clock source for the entire system. The reference clock is multiplied and phase-locked by a phase-locked loop (PLL) circuit to generate the system master clock signal.

[0074] Then, the master clock signal is input to the FPGA-based data path module 220; serving as the unified time base for the internal time counters of each timestamp injection unit 240; and provided to the TSN control logic module 250. By adopting a low-jitter phase-locked loop structure and a controlled temperature rise circuit design, the effects of phase noise and temperature drift are reduced, thereby ensuring the stability of time counting and thus forming a unique master clock source for the entire device at the hardware level.

[0075] In practical implementation, the present invention adopts a switch structure to independently design the test ports. Each test port has an embedded MAC address switching IP core and communicates with the corresponding PHY chip to realize 100 / 1000BASE-T1 port control. All ports share the same IEEE 802.1AS protocol stack and use a board-level high-precision clock circuit as a unified master clock source.

[0076] The test ports are designed with an independent architecture using a switch structure. Specifically, a multi-port data switching path is built within the FPGA; each test port embeds an independent MAC address switching IP core; each MAC IP core is directly connected to a corresponding PHY chip; and the PHY chip is used to enable the 100 / 1000BASE-T1 physical layer interface. Under this structure, each port has independent transmit and receive capabilities, but shares a unified time base and a unified synchronization protocol stack.

[0077] In the above implementation process, by combining a board-level high-precision oscillator with a phase-locked loop circuit and the IEEE 802.1AS synchronization mechanism, the test equipment is made to operate as a time master, which can achieve nanosecond-level time synchronization accuracy and improve the accuracy of TSN testing.

[0078] Step S120: Establish a multi-port data path based on the switching structure, and embed a timestamp injection unit 240 into the MAC inlet and MAC outlet of each port respectively, so that all incoming and outgoing frames generate inbound timestamps and outbound timestamps in a unified time domain.

[0079] In this embodiment, a multi-port data path based on a switching structure is constructed within the FPGA-based data path module 220, specifically including:

[0080] Each physical port is assigned an independent MAC processing subunit, and these subunits are interconnected via an internal switching matrix. This switching matrix supports port-to-port forwarding, mirroring, replication, and loopback path construction. All port data operates under a unified internal clock. The multi-port data path based on this switching structure differs from a simple serial data path, enabling: independent port processing, internal traffic redirection, and calibrated loopback path construction.

[0081] A timestamp injection unit 240 is embedded in the MAC inlet and MAC outlet of each port. Specifically, it includes: setting an inbound timestamp submodule of the timestamp injection unit 240 on the MAC inlet side of each port; when the physical layer PHY completes frame reception and submits data to the MAC layer; when the MAC receiving state machine recognizes the start-of-frame character; calling the internal time counter of the timestamp injection unit 240; recording the time count value provided by the current unified time synchronization module 230; and appending the time count value as an inbound timestamp to the internal metadata area of ​​the data frame, thereby realizing accurate time recording at the moment the frame arrives.

[0082] On the MAC egress side of each port, an outbound timestamp submodule of timestamp injection unit 240 is also set. When the frame is ready to be sent after being processed by the switching path, when the MAC sending state machine triggers the frame sending, the same time counter is called; the current time count value is recorded; and the time value is appended to the frame sending record as an outbound timestamp, thereby realizing the time recording at the moment of frame sending.

[0083] In this embodiment, the time difference comparison between inbound and outbound frames is realized through the port-level timestamp insertion and extraction interface, which can accurately decompose the delays of the MAC layer, PHY layer and scheduling layer, and improve the traceability of delay measurement.

[0084] Step S130: Based on the unified time domain, configure Qav credit shaping, Qbv time-aware scheduling, Qbu frame preemption, Qci per-stream filtering supervision, and Qcb frame duplication and elimination for each port to form a port-level time-aware scheduling matrix.

[0085] Specifically, in the TSN control logic module 250, Qav credit shaping parameters are configured for each port; a Qbv gating schedule table based on a unified time base is constructed; Qbu frame preemption logic is enabled; Qci per-flow filtering rules are set; and Qcb frame duplication and elimination strategies are configured, thereby forming a port-level time-aware scheduling matrix.

[0086] In this embodiment, the present invention supports TSN functional modules such as Qav credit shaping, Qbv time-aware scheduling, Qbu frame preemption, Qci per-stream filtering supervision, and Qcb frame duplication and elimination. It verifies deterministic scheduling based on a unified time axis, compares multi-port parallel scheduling behavior, tests the isolation between real-time and non-real-time streams, verifies the reliability of redundancy mechanisms, and performs quantitative analysis of time-aware scheduling performance, enabling the test equipment to have complete TSN protocol consistency testing capabilities.

[0087] Step S140: The traffic generation engine is invoked through the Linux control subsystem to deeply bind the third-layer packet payload to the specified physical port, and the test traffic is output through the timestamp injection unit 240 of each port;

[0088] In this embodiment, a Linux control subsystem is set in the traffic generation and control module 260, which can be used to: provide a user configuration interface; receive port selection instructions; receive L2 / L3 packet construction parameters; and call the third-layer packet generation engine through an open API interface, etc.

[0089] The Layer 3 packet generation engine performs the following operations: constructs IP header fields; fills in UDP or other transport layer payloads; generates a complete L3 packet; encapsulates the L3 packet into an Ethernet frame format; and writes it to the internal data path buffer. During the generation process, the packet may contain: a variable-length payload; a specified flow identifier; and configurable priority tags, etc.

[0090] In this embodiment, "deep binding" is not a simple port selection, but rather allocates an independent transmission queue for a specified port at the data path layer; directly maps the generated data frames to the MAC processing unit corresponding to that port; binds them to the timestamp injection unit 240 corresponding to that port; and inherits the TSN scheduling strategy of that port, thereby achieving the goal of not using the general switching broadcast path, not going through the port reselection mechanism, and not sharing the transmission timer. After the third-layer data packets are scheduled by the port-specific transmission queue, they enter the MAC processing unit of the corresponding port, and an outbound timestamp is generated at the MAC egress side through the timestamp injection unit 240, forming: L3 load → port-specific transmission queue → port MAC processing unit → timestamp injection unit 240, and then outputs test traffic through the timestamp injection units 240 of each port.

[0091] The test traffic is output through the timestamp injection unit 240 of each port, specifically including: when a data frame enters the transmission path of the target port: triggering the generation of outbound timestamp on the MAC egress side; calling the internal time counter of the timestamp injection unit 240; generating an outbound timestamp based on a unified time domain; appending the timestamp to the internal record structure; and sending the frame to the corresponding physical layer PHY output.

[0092] In step S140, the traffic generation parameters are received through the Linux control subsystem; the third-layer packet generation engine is called to construct test packets; the generated data packets are mapped to the sending queue corresponding to the specified physical port; the TSN scheduling policy of the port is inherited; and the outbound timestamp is generated and the test traffic is output through the timestamp injection unit 240.

[0093] In practical implementation, this invention deeply binds the L3 and above data packet payload definition with the hardware port, and calls the port's internal timestamp injection unit 240 through the open API interface to realize real-time detection and correction of inbound / outbound data packet time difference.

[0094] Step S150: Perform CRC tampering or corrupted frame injection, and record the inbound and outbound timestamps of the abnormal frame under the same time base;

[0095] In this step, CRC tampering or corrupted frame injection is performed by constructing abnormal frame generation logic in the error frame injection module 270. Specifically, this includes: generating a standard Ethernet data frame inside the FPGA-based data path module 220; after the frame is generated, tampering with the Cyclic Redundancy Check (CRC) field at the end of the frame; or inserting an intentionally corrupted bit sequence into the MAC layer processing channel; or constructing a frame structure with abnormal frame length or invalid fields. The above operations are performed at the MAC / PHY boundary, so that the abnormal frame maintains the integrity of physical layer transmission, but is identified as an error frame during link layer verification.

[0096] Among them, abnormal frame injection can be carried out through active transmission injection, by specifying the target physical port through the traffic generation and control module 260; the constructed abnormal frame is written into the dedicated transmission queue of the corresponding port; and the port's MAC processing unit schedules the transmission.

[0097] Since the timestamp injection units 240 of each port are all bound to the time base provided by the unified time synchronization module 230, the following are achieved: an inbound timestamp is generated when an abnormal frame enters the MAC entry point; an outbound timestamp is generated when an abnormal frame is sent from the MAC exit point; the timestamps are generated based on the unified time counter; and the abnormal frame time record is compared with the normal frame time record.

[0098] By recording the inbound and outbound timestamps of abnormal frames, we can analyze: whether the abnormal frame was discarded by the switching structure; where the abnormal frame was filtered; the changes in the processing delay of abnormal frames; the response time of the TSN scheduling mechanism to abnormal traffic; the effective time of QCI per-flow filtering supervision, thereby realizing the verification of CRC abnormal handling capabilities; verification of per-flow supervision rules; verification of abnormal response of frame preemption mechanism; analysis of abnormal frame propagation path; and quantification of abnormal behavior in a unified time domain.

[0099] Step S160: Based on the inbound and outbound timestamps, generate TSN consistency verification results; the TSN consistency verification results include port-level transmission latency, scheduling window deviation, preemption trigger time deviation, and frame replication consistency difference.

[0100] Specifically, the port-level transmission delay includes a media access control layer processing delay segment, a scheduling waiting delay segment, a frame preemption insertion delay segment, and a forwarding and propagation delay segment.

[0101] In this embodiment, the port-level transmission delay is further subdivided into the medium access control layer processing delay segment, the scheduling waiting delay segment, the frame preemption insertion delay segment, and the forwarding propagation delay segment. This enables segmented statistics and analysis of port-level delay, which is beneficial for accurately locating the source of delay and improving the ability to identify TSN scheduling anomalies or preemption anomalies, thereby enhancing the precision of fault analysis.

[0102] Specifically, in the FPGA-based data path module 220, the port-level transmission delay is calculated by combining the inbound and outbound timestamps recorded by the timestamp injection unit 240.

[0103] The media access control layer processing delay segment, which is the time required for a data frame to be received from the MAC inlet to complete MAC layer parsing and processing, includes: frame header parsing time, check field checking time, and priority identification time. This delay segment is measured by setting an internal time stamp at the MAC inlet processing node.

[0104] The scheduling waiting delay segment refers to the waiting time from when a data frame enters the transmission queue until the scheduling window opens, including: Qav credit recovery waiting time and Qbv gating closing waiting time.

[0105] The frame preemption insertion delay segment refers to the additional delay caused when a high-priority frame is inserted into the transmission process of the current low-priority frame when the Qbu frame preemption mechanism is triggered. This includes the preemption trigger response time and the recovery time of the interrupted frame.

[0106] Forwarding and propagation delay refers to the delay experienced by a data frame from the MAC output to the physical layer output, including: MAC to PHY interface delay, PHY encoding delay, and physical layer propagation delay.

[0107] In step S160, the port-level transmission delay is calculated based on the inbound and outbound timestamps; the port-level transmission delay is decomposed into MAC layer (media access control layer) processing delay segment, scheduling waiting delay segment, frame preemption insertion delay segment, and forwarding propagation delay segment;

[0108] Specifically, the scheduling window deviation is calculated based on the preset scheduling window time (the scheduling window deviation is the actual transmission timestamp minus the preset scheduling window time), the preemption trigger time deviation is calculated based on the preemption trigger theoretical time (the preemption trigger time deviation is the preemption trigger timestamp minus the theoretical trigger time), and the frame replication consistency difference is calculated based on the outbound timestamps of multiple ports (the frame replication consistency difference is the absolute value of the difference between the outbound timestamps of the two ports), thus obtaining the TSN consistency verification result.

[0109] Optionally, the method of the present invention further includes:

[0110] Step S1601: Based on the scheduling window deviation, preemption trigger time deviation, and frame replication consistency difference, a port-level time offset vector is generated. When the port-level time offset vector exceeds a first preset threshold, interference frame injection is automatically triggered, and the timestamp is re-recorded to form a closed-loop verification.

[0111] In the Linux control subsystem, a time offset vector model is established for each port, where ΔW represents the scheduling window deviation, ΔP represents the preemption trigger time deviation, and ΔR represents the frame replication consistency difference; then the port-level time offset vector can be expressed as: port-level time offset vector V=[ΔW,ΔP,ΔR].

[0112] In practical implementation, a first preset threshold can be set for each port. This first preset threshold can be a vector magnitude threshold, an independent threshold for any component of the port-level time offset vector, or a weighted total offset threshold for all components of the port-level time offset vector. When the time offset vector of a port exceeds the first preset threshold, it is determined that the current port has a time anomaly.

[0113] When a time anomaly is detected at the current port, a preset interference frame is generated by the traffic generation and control module 260; the interference frame can be a high-priority burst flow or a CRC anomaly frame, etc. This triggering process is completed automatically by the system without manual intervention.

[0114] After the interference frame is injected, the port-level timestamp injection unit 240 continues to generate inbound and outbound timestamps, and recalculates: scheduling window deviation, preemption trigger time deviation, and frame replication consistency difference; and constructs a new port-level time offset vector.

[0115] In the above implementation process, a port-level time offset vector is constructed based on the scheduling window deviation, preemption trigger time deviation, and frame replication consistency difference. The port-level time offset vector is compared with a first preset threshold. When it exceeds the first preset threshold, an interference frame is automatically generated by the traffic generation and control module 260. The inbound and outbound timestamps are re-recorded by the port-level timestamp injection unit 240.

[0116] Based on the re-recorded timestamps to form closed-loop verification results, by comparing the changes in offset vectors before and after the interference, we can determine: TSN scheduling robustness, preemption response stability, redundancy replication consistency stability, and network time stability under abnormal loads.

[0117] The first preset threshold includes at least two graded thresholds. When the port-level time offset vector is in different graded threshold ranges, different levels of interference injection strategies are triggered respectively.

[0118] In practice, the first preset threshold can be classified into three levels: first-level threshold T1 (mildly abnormal threshold), second-level threshold T2 (moderately abnormal threshold), and third-level threshold T3 (severely abnormal threshold).

[0119] When the port-level time offset vector is in different graded threshold ranges, different levels of interference injection strategies are triggered respectively; wherein, the different levels of interference injection strategies include different injection frequencies, frame lengths, frame priorities or abnormal frame ratios.

[0120] For example, the first-level threshold T1 (minor anomaly threshold), the second-level threshold T2 (moderate anomaly threshold), and the third-level threshold T3 (severe anomaly threshold) are set as thresholds for the magnitude of the port-level time offset vector, specifically 200ns, 500ns, and 1000ns, respectively. If the port-level time offset vector V=[ΔW,ΔP,ΔR]=[120,80,60], then the magnitude of the port-level time offset vector is 156ns, which is less than the first-level threshold of 200ns, and no interference is triggered. If the port-level time offset vector V=[ΔW,ΔP,ΔR]=[300,200,100], then the magnitude of the port-level time offset vector is 374ns, which is greater than the first-level threshold but less than the third-level threshold T3, thus triggering the first-level interference strategy. For example, the first-level interference strategy injects an interference frame with a duration of 1 ms, an injection frequency of 1 kHz, and a frame length of 128 bytes.

[0121] In this example, by setting a graded threshold, frequent false triggering of high-intensity interference can be avoided, stress test intensity can be adaptively adjusted, and the accuracy of TSN consistency verification can be improved.

[0122] Optionally, the method of the present invention further includes:

[0123] Step S1602: When the port-level time offset vector exceeds the second preset threshold, a calibration frame is generated and a loop structure is formed in the internal data path. The port-level time offset is corrected by comparing the inbound timestamp and outbound timestamp of the calibration frame.

[0124] In this embodiment, when the port-level time offset vector exceeds the second preset threshold, instead of just performing stress verification, a time correction mechanism is activated to determine that the system time base has experienced a structural offset and requires internal calibration.

[0125] For example, if the first preset threshold is 500 ns, the second preset threshold is 2000 ns. The second preset threshold is much larger than the first preset threshold. The second preset threshold can be set to 3 to 5 times the first preset threshold.

[0126] In this step, when the port-level time offset vector exceeds the second preset threshold, the Linux control subsystem generates a calibration frame; the calibration frame includes a fixed frame length (e.g., 64 bytes).

[0127] Fixed priority (highest priority queue); preset unique identifier field; CRC tampering disabled; the calibration frame does not carry service data and is only used for time measurement.

[0128] In step S1602, when the port-level time offset vector exceeds a second preset threshold, a calibration frame is generated; a loopback forwarding path is established within the multi-port data path; the outbound and inbound timestamps of the calibration frame are recorded through the port-level timestamp injection unit 240; the internal loopback delay is calculated based on the inbound and outbound timestamps; the internal loopback delay is compared with a preset theoretical delay; and the port-level time offset is compensated and corrected based on the comparison result.

[0129] For example, if the preset theoretical delay is 800ns, and the internal loopback delay calculated by the inbound and outbound timestamps is 950ns, then the overall port time is calculated to be 150ns behind. Then, the port-level time offset is compensated and corrected (for example, by using timestamp compensation correction and introducing a compensation register in the timestamp injection unit 240) to restore the loopback delay to 800ns.

[0130] Step S170: Switch some ports to CAN or LIN hardware mode, and perform cross-protocol latency consistency verification between vehicle Ethernet and CAN / LIN under the unified time domain.

[0131] In this step, some ports are switched to CAN or LIN hardware mode; timestamps are generated for Ethernet frames, CAN frames, or LIN frames under a unified time domain; the time difference between frames of different protocols is calculated; the time difference is compared with the preset cross-protocol theoretical delay; and a cross-protocol delay consistency verification result is generated.

[0132] In practical implementation, the multi-port physical interface module 210 of the test equipment supports a multiplexed hardware structure: some ports operate in vehicle Ethernet mode by default; through the hardware multiplexing control circuit, it can be switched to CAN controller mode or LIN controller mode.

[0133] Specifically, the switching methods include: disabling Ethernet MAC; enabling CAN or LIN controllers; maintaining a unified board-level master clock; and ensuring that the timestamp injection unit 240 still uses a unified time counter. In this case, all protocols share the same board-level master clock and are therefore still in a unified time domain. The timestamps of different protocol frames can be directly compared without time conversion.

[0134] When performing cross-protocol delay consistency verification between vehicle Ethernet and CAN / LIN, a test frame can be sent to the Ethernet port, and a synchronization trigger frame can be sent to the CAN or LIN port at the same time. Record the Ethernet outbound timestamp, the CAN transmission completion timestamp, and the LIN response timestamp. Calculate the cross-protocol delay difference. Due to the same master clock and the same timestamp injection mechanism, nanosecond-level comparisons can be performed directly. Under the same time domain, the actual delay difference between vehicle Ethernet and CAN / LIN can be directly compared.

[0135] In practical implementation, this invention is based on the FPGA data path structure to achieve port mode reconfigurability, supports hardware-level conversion between vehicle Ethernet and CAN / LIN interfaces, and builds a unified test platform to replace the soft gateway test method.

[0136] In the above implementation process, a hardware-level CAN / LIN to Ethernet conversion structure is adopted to avoid the jitter and uncontrollable delay caused by the operating system scheduling of traditional software gateways, thereby improving the test determinism.

[0137] The cross-protocol latency consistency verification between the vehicle Ethernet and CAN / LIN under the unified time domain includes:

[0138] Step S1701: Obtain the timestamps of Ethernet and CAN / LIN under the unified time domain, and perform time granularity mapping processing on the timestamps according to the scheduling time granularity of the target protocol to calculate the end-to-end time difference, and generate cross-protocol delay consistency results based on the time difference.

[0139] In practical implementation, under a unified board-level master clock: Ethernet TSN time granularity is usually 8ns / 16ns, CAN controller scheduling granularity is usually 1 bit time, and LIN scheduling granularity is usually 1 time slot. Although the timestamp source is the same, the internal scheduling resolution of the protocol is different, so time granularity mapping must be performed.

[0140] The Ethernet frame outbound timestamp, CAN frame transmission completion timestamp, and LIN response timestamp are obtained under a unified time domain, with the time unit being unified in ns. Then, the Ethernet frame outbound timestamp, CAN frame transmission completion timestamp, and LIN response timestamp are respectively processed by time granularity mapping to obtain the end-to-end difference.

[0141] For example, the end-to-end time difference is 1880ns. If the theoretical design delay is 2000ns, the deviation is 120ns. If the preset cross-protocol allowable deviation threshold is 500ns, and the deviation is less than the preset cross-protocol allowable deviation threshold, then the cross-protocol delay consistency result is considered to be in good consistency.

[0142] In this step, the timestamps of Ethernet and CAN / LIN are obtained in a unified time domain. The timestamps are quantized and mapped according to the scheduling time granularity of the target protocol. The end-to-end time difference is calculated based on the mapped timestamps. The difference between the end-to-end time difference and the theoretical design delay is compared with a preset cross-protocol allowable deviation threshold to generate a cross-protocol delay consistency result. This can eliminate the difference in protocol scheduling resolution, thereby avoiding false deviations caused by direct comparison and improving the accuracy of cross-protocol consistency verification.

[0143] Example 2

[0144] This invention discloses a multifunctional vehicle-mounted TSN testing device, such as... Figure 2 As shown, Figure 2 It is a multi-functional vehicle-mounted TSN testing device, which includes the following:

[0145] The multi-port physical interface module 210 is used to realize the physical signal access of the vehicle network;

[0146] The FPGA-based data path module 220 includes an integrated unit for encoding, decoding and MAC processing of data from each port, and a processing channel set in the data link layer. The processing channel is used to perform traffic mirroring, frame modification and frame injection operations, and to record the time information of inbound and outbound data frames from each port.

[0147] The unified time synchronization module 230 is used to share a unified time synchronization protocol among various ports and complete global time synchronization;

[0148] The timestamp injection unit 240 is set at the MAC inlet and outlet of each port and is used to insert and extract frame timestamps.

[0149] TSN control logic module 250 is used to implement Qav credit base traffic shaping, Qbv time-aware traffic shaping, Qbu frame preemption, Qci per-stream filtering and policing, and Qcb frame duplication and elimination.

[0150] The traffic generation and control module 260 includes a Linux control subsystem, a second- or third-layer packet generation engine, and an open API interface. The API interface is used to bind the generated packet payload to a specified physical port and send it through the timestamp injection unit of the corresponding port.

[0151] Error frame injection module 270 is used to generate CRC tampered or corrupted frames to simulate network anomalies;

[0152] The FPGA hardware interface 280 is used to extend support for conversion testing between CAN / LIN interfaces and automotive Ethernet.

[0153] Optionally, the test equipment further includes an adaptive interference injection control module, which is connected to the error frame injection module. When the port-level time offset vector exceeds a first preset threshold, interference frame injection is automatically triggered to form a time closed-loop verification mechanism.

[0154] In the above implementation process, by setting up a multi-port physical interface module 210, an FPGA-based data path module 220, a unified time synchronization module 230, and a timestamp injection unit 240 embedded in the MAC inlet and outlet of each port, each port can achieve frame-level time acquisition and data processing in a unified time domain. At the same time, combined with the TSN control logic module 250, the traffic generation and control module 260, and the error frame injection module 270, an integrated test architecture for traffic generation, anomaly simulation, time recording, and consistency analysis is realized. This improves the time accuracy, functional coverage, and test reliability of vehicle TSN network testing, and supports extended conversion testing between vehicle Ethernet and CAN / LIN interfaces, enhancing the comprehensive applicability of the test equipment.

[0155] Furthermore, by setting an adaptive interference injection control module, interference frame injection is automatically triggered when the port-level time offset vector exceeds the first preset threshold, realizing an automatic response mechanism based on the time offset result. This enables the test equipment to actively apply pressure and re-record time information when an anomaly is detected, thereby forming a time closed-loop verification structure and improving the accuracy and automation of time consistency verification.

[0156] In practical implementation, the hardware structure and function table shown in Table 1 can be adopted.

[0157] Table 1: Hardware Structure and Function Table

[0158]

[0159] In practice, the software implementation can adopt the software implementation table shown in Table 2.

[0160] Table 2: Software Implementation Table

[0161]

[0162] Example 3

[0163] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of an electronic device disclosed in an embodiment of the present invention. For example... Figure 3 As shown, the electronic device may include:

[0164] Memory 310 storing executable program code;

[0165] Processor 320 coupled to memory 310;

[0166] The processor 320 calls the executable program code stored in the memory 310 to execute some or all of the steps in the test method of a multi-functional vehicle-mounted TSN test device in Embodiment 1.

[0167] This invention discloses a computer-readable storage medium storing a computer program that causes a computer to perform some or all of the steps in the testing method of a multifunctional vehicle-mounted TSN testing device according to Embodiment 1.

[0168] This invention also discloses a computer program product, wherein when the computer program product is run on a computer, the computer executes some or all of the steps in the test method of a multifunctional vehicle-mounted TSN test device in Embodiment 1.

[0169] This invention also discloses an application publishing platform, which is used to publish computer program products. When the computer program products are run on a computer, the computer executes some or all of the steps in the testing method of a multifunctional vehicle-mounted TSN testing device in Embodiment 1.

[0170] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0171] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they can be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0172] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0173] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-accessible memory. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several requests to cause a computer device (which can be a personal computer, server, or network device, specifically a processor in the computer device) to execute some or all of the steps of the methods described in the various embodiments of the present invention.

[0174] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0175] Those skilled in the art will understand that some or all of the steps in the various methods of the embodiments described can be implemented by a program instructing related hardware. This program can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-Erasable Programmable Read-Only Memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium capable of carrying or storing data.

[0176] The above provides a detailed description of the testing method, apparatus, electronic device, and storage medium of a multifunctional vehicle-mounted TSN testing device disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A multifunctional vehicle-mounted TSN testing device, characterized in that, include: A multi-port physical interface module is used to enable physical signal access to the vehicle network; The FPGA-based data path module includes an integrated unit for encoding, decoding and MAC processing of data from each port, and a processing channel located at the data link layer. The processing channel is used to perform traffic mirroring, frame modification and frame injection operations, and to record the time information of inbound and outbound data frames from each port. The unified time synchronization module is used to share a unified time synchronization protocol among various ports and to complete global time synchronization. The timestamp injection unit is set at the MAC inlet and outlet of each port and is used to insert and extract frame timestamps; The TSN control logic module is used to implement Qav credit base traffic shaping, Qbv time-aware traffic shaping, Qbu frame preemption, Qci per-stream filtering and policing, and Qcb frame duplication and elimination. The traffic generation and control module includes a Linux control subsystem, a second- or third-layer packet generation engine, and an open API interface. The API interface is used to bind the generated packet payload to a specified physical port and send it through the timestamp injection unit of the corresponding port. Error frame injection module, used to generate CRC tampered or corrupted frames to simulate network anomalies; An FPGA hardware interface is used to extend support for conversion testing between CAN / LIN interfaces and automotive Ethernet.

2. The multifunctional vehicle-mounted TSN testing equipment according to claim 1, characterized in that, It also includes an adaptive interference injection control module, which is connected to the error frame injection module. When the port-level time offset vector exceeds a first preset threshold, it automatically triggers interference frame injection to form a time closed-loop verification mechanism.

3. A testing method for the testing equipment as described in claim 1, characterized in that, Includes the following steps: In the test equipment, a reference clock signal is generated based on a high-precision oscillator and a phase-locked loop. A unified synchronization domain for all ports is established through the IEEE 802.1AS protocol, and the test equipment is set as the time master node so that all test ports share the same time reference. Establish a multi-port data path based on a switching structure, and embed timestamp injection units at the MAC inlet and MAC outlet of each port respectively, so that all incoming and outgoing frames generate inbound and outbound timestamps in a unified time domain; Based on the unified time domain, Qav credit shaping, Qbv time-aware scheduling, Qbu frame preemption, Qci per-stream filtering supervision, and Qcb frame duplication and elimination are configured for each port to form a port-level time-aware scheduling matrix. The Linux control subsystem calls the traffic generation engine to deeply bind the third-layer packet payload to the specified physical port, and outputs test traffic through the timestamp injection unit of each port; Perform CRC tampering or corrupted frame injection, and record the inbound and outbound timestamps of the abnormal frames under the same time base; Based on the inbound and outbound timestamps, a TSN consistency verification result is generated; The TSN consistency verification results include port-level transmission latency, scheduling window deviation, preemption trigger time deviation, and frame replication consistency difference. Switch some ports to CAN or LIN hardware mode and perform cross-protocol latency consistency verification between vehicle Ethernet and CAN / LIN under the unified time domain.

4. The test method according to claim 3, characterized in that, The port-level transmission delay includes a media access control layer processing delay segment, a scheduling waiting delay segment, a frame preemption insertion delay segment, and a forwarding and propagation delay segment.

5. The test method according to claim 4, characterized in that, Also includes: Based on the scheduling window deviation, preemption trigger time deviation, and frame replication consistency difference, a port-level time offset vector is generated. When the port-level time offset vector exceeds a first preset threshold, interference frame injection is automatically triggered, and the timestamp is re-recorded to form a closed-loop verification.

6. The test method according to claim 5, characterized in that, The first preset threshold includes at least two graded thresholds. When the port-level time offset vector is in different graded threshold ranges, different levels of interference injection strategies are triggered respectively.

7. The test method according to claim 5, characterized in that, Also includes: When the port-level time offset vector exceeds the second preset threshold, a calibration frame is generated and a loop structure is formed in the internal data path. The port-level time offset is corrected by comparing the inbound timestamp and outbound timestamp of the calibration frame.

8. The test method according to claim 3, characterized in that, The step of performing cross-protocol delay consistency verification between vehicle Ethernet and CAN / LIN in the unified time domain includes: obtaining the timestamps of Ethernet and CAN / LIN in the unified time domain, and performing time granularity mapping processing on the timestamps according to the scheduling time granularity of the target protocol to calculate the end-to-end time difference, and generating a cross-protocol delay consistency result based on the time difference.

9. An electronic device, characterized in that, It includes: a memory storing executable program code; a processor coupled to the memory; the processor calling the executable program code stored in the memory to execute the test method of the multifunctional vehicle-mounted TSN test device according to any one of claims 3-8.

10. A computer-readable storage medium, characterized in that, It stores a computer program, wherein the computer program causes a computer to execute the test method of the multifunctional vehicle-mounted TSN test device according to any one of claims 3-8.

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