Short-wave infrared pixel reading circuit and control method thereof

Abstract

The invention provides a short wave infrared pixel readout circuit and a control method thereof, the short wave infrared pixel readout circuit converts an optical signal into a light current based on a photoelectric conversion module, and provides a preset transconductance gain through a symmetric differential amplification structure in a charge integration amplification module, so as to amplify the light current based on the preset transconductance gain; charge integration is carried out on the light current to obtain integral voltage; and performing reset sampling and signal sampling on the integral voltage through the correlated double-sampling module to obtain a sampling voltage. The short-wave infrared pixel reading circuit provided by the invention adopts a symmetrical differential amplification input structure, has a relatively high common-mode rejection ratio and a relatively good anti-interference capability, and improves the anti-interference capability in an amplification process under the condition of not increasing power consumption; the correlated double sampling modules are concentrated in the reading circuit, signals are not transmitted for multiple times between pixels and a column-level circuit, the processing pressure of the column-level circuit is reduced, the number of circuit switches is small, time sequence control is simple, and the pixel area is reduced.

Description

Technical Field

[0001] This invention relates to the field of photoelectric imaging detector technology, and in particular to a short-wave infrared pixel readout circuit and its control method. Background Technology

[0002] Short-wave infrared imaging technology, due to its unique advantages, is widely used in fields such as night vision, remote sensing, industrial inspection, and spectral analysis. Unlike mid- and long-wave infrared imaging, which relies on the thermal radiation of objects themselves, short-wave infrared imaging has significant advantages over visible light imaging, especially in low-light environments where it can obtain high-contrast images and possesses strong smoke penetration capabilities, making it crucial for target detection in special environments. The pixel readout circuit is a key component connecting the front-end photosensitive detector and the back-end signal processing system; its performance directly determines the core indicators of the entire imaging system, such as signal-to-noise ratio, dynamic range, frame rate, and power consumption.

[0003] Currently, among existing readout circuit structures, the capacitive feedback transimpedance amplifier pixel structure is widely used for short-wave infrared weak light signal readout due to its high injection efficiency and precise bias control capability. However, existing readout circuits based on capacitive feedback transimpedance amplifiers still have significant shortcomings in pursuing high performance indicators. Specifically, in terms of noise suppression, traditional correlated double sampling techniques are mostly implemented in column-level circuits; although this architecture simplifies pixel design, it requires weak signals to be transmitted over long lines, easily introducing crosstalk and parasitic noise, which severely restricts the improvement of signal-to-noise ratio; at the same time, complex column-level timing control also increases power consumption and limits frame rate. In the design of the core amplification unit, in order to meet the requirements of small pixel area and low power consumption, the gain of traditional amplifier structures is often limited, making it difficult to effectively suppress its own low-frequency noise and offset voltage. As the requirements of application scenarios for imaging systems continue to increase, existing technologies often sacrifice one or several performance aspects to improve other indicators. Summary of the Invention

[0004] This invention provides a short-wave infrared pixel readout circuit and its control method to solve the technical problems of high noise, high frame rate and high power consumption in the above-mentioned pixel readout circuit.

[0005] In a first aspect, the present invention provides a short-wave infrared pixel readout circuit, comprising:

[0006] A photoelectric conversion module is used to convert optical signals into photocurrent; A charge integration amplification module, connected to the photoelectric conversion module, provides a preset transconductance gain based on a symmetrical differential amplification structure to amplify the photocurrent based on the preset transconductance gain, and performs charge integration on the photocurrent to obtain the integrated voltage; The related dual sampling module, which is connected to the charge integration amplification module, performs reset sampling and signal sampling on the integrated voltage to output a sampling voltage characterizing the intensity of the optical signal.

[0007] In one embodiment of the present invention, the charge integration amplification module includes an integration unit and an amplification unit. The amplification unit provides a preset transconductance gain based on the symmetrical differential amplification structure and amplifies the photocurrent based on the preset transconductance gain. The integration unit is coupled between the input terminals of the amplification unit and the input terminal of the amplification unit, and the integration unit performs charge integration on the photocurrent.

[0008] In one embodiment of the present invention, the integration unit includes a first PMOS transistor and a first capacitor. The drain of the first PMOS transistor is connected to a first terminal of the first capacitor, the source of the first PMOS transistor is connected to a second terminal of the first capacitor, the first terminal of the first capacitor is connected to the negative input terminal of the amplification unit, and the second terminal of the first capacitor is also connected to the output terminal of the amplification unit. The gate of the first PMOS transistor is connected to a first reset signal.

[0009] In one embodiment of the present invention, the charge integration amplification module further includes a second PMOS transistor and a second capacitor. The amplification unit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The source of the second PMOS transistor is connected to the negative input terminal of the amplification unit, and the drain of the second PMOS transistor is connected to the positive input terminal of the amplification unit. The source of the third PMOS transistor is connected to the power supply voltage. The drain of the S-channel MOSFET is connected to the source of the fourth PMOS transistor, the source of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, the drain of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor, the gate of the sixth PMOS transistor is connected to the gate of the seventh PMOS transistor, the drain of the fifth PMOS transistor is connected to the source of the seventh PMOS transistor, the drain of the sixth PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the sixth PMOS transistor is also connected to the gate of the third PMOS transistor, and the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor. The drain of the seventh PMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the seventh PMOS transistor is also grounded through the second capacitor. The source of the first NMOS transistor is connected to the drain of the third NMOS transistor, the source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fourth PMOS transistor is connected to the gate of the third NMOS transistor, the gate of the fifth PMOS transistor is connected to the gate of the fourth NMOS transistor, and the source of the third NMOS transistor is connected to the source of the fourth NMOS transistor. The drain of the fifth NMOS transistor is grounded, the source of the fifth NMOS transistor is grounded, the gate of the fourth PMOS transistor is the positive input terminal of the amplification unit, the gate of the fifth PMOS transistor is the negative input terminal of the amplification unit, the drain of the seventh PMOS transistor is the output terminal of the amplification unit, the gate of the sixth PMOS transistor is the first bias input terminal of the amplification unit, the gate of the first NMOS transistor is the second bias input terminal of the amplification unit, the gate of the second PMOS transistor is connected to the first reset signal, and the gate of the fifth NMOS transistor is the third bias input terminal of the amplification unit.

[0010] In one embodiment of the present invention, the photoelectric conversion module includes a photodiode, the cathode of the photodiode is connected to the power supply voltage, and the anode of the photodiode is the output terminal of the photoelectric conversion module.

[0011] In one embodiment of the present invention, the correlated dual sampling module includes an eighth PMOS transistor, a ninth PMOS transistor, a sixth NMOS transistor, a third capacitor, and a fourth capacitor. The drain of the eighth PMOS transistor is connected to the source of the sixth NMOS transistor, the source of the eighth PMOS transistor is connected to the drain of the sixth NMOS transistor, the source of the eighth PMOS transistor is connected to the first terminal of the third capacitor, the first terminal of the third capacitor is grounded after passing through the fourth capacitor, the source of the ninth PMOS transistor is connected to a reference voltage, and the drain of the ninth PMOS transistor is connected to the second terminal of the third capacitor. The gate of the eighth PMOS transistor is connected to a second reset signal, the gate of the sixth NMOS transistor is connected to a third reset signal, the gate of the ninth PMOS transistor is connected to a fourth reset signal, and the second terminal of the third capacitor is the output terminal of the correlated dual sampling module. The second reset signal is inversely related to the third reset signal.

[0012] Secondly, the present invention provides a control method for a short-wave infrared pixel readout circuit, comprising: Convert optical signals into photocurrent; The photocurrent is amplified based on a preset transconductance gain, and the photocurrent is simultaneously integrated by charge integration to obtain the integrated voltage. The integrated voltage is reset and sampled, and the sampled voltage is obtained.

[0013] In one embodiment of the present invention, before converting the optical signal into photocurrent, the method further includes: acquiring a reset signal; and performing a reset process on the short-wave infrared pixel readout circuit based on the reset signal.

[0014] The beneficial effects of this invention are as follows: This invention provides a short-wave infrared pixel readout circuit and its control method. The short-wave infrared pixel readout circuit converts optical signals into photocurrents based on a photoelectric conversion module. A preset transconductance gain is provided through a symmetrical differential amplification structure in the charge integration amplification module to amplify the photocurrent based on the preset transconductance gain. The photocurrent is then integrated by charge integration to obtain an integrated voltage. A related dual sampling module performs reset sampling and signal sampling on the integrated voltage to obtain a sampled voltage. The short-wave infrared pixel readout circuit provided by this invention adopts a symmetrical differential amplification input structure, which has a high common-mode rejection ratio and good anti-interference capability. It improves the anti-interference capability of the amplification process without increasing power consumption. The related dual sampling module is concentrated within the readout circuit, avoiding multiple signal transmissions between the pixel and column-level circuits, reducing the processing pressure on the column-level circuits, which is beneficial for improving the system frame rate. It also has low noise, and the fewer switches in the related dual sampling module simplify timing control, resulting in a smaller pixel area and increased chip integration. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0016] In the attached diagram: Figure 1 This is a block diagram of the short-wave infrared pixel readout circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the specific structure of the short-wave infrared pixel readout circuit provided in the embodiment of the present invention; Figure 3 This is a schematic diagram of the specific structure of the amplification unit provided in the embodiment of the present invention; Figure 4 This is a schematic diagram of the operating timing of the shortwave infrared pixel readout circuit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the amplitude-frequency curve and phase-frequency curve of the amplification unit provided in the embodiment of the present invention; Figure 6 This is a schematic diagram of the noise curve of the amplification unit provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the output characteristic curve of the short-wave infrared pixel readout circuit provided in an embodiment of the present invention.

[0017] Figure reference numerals: 110 - photoelectric conversion module; 120 - charge integration amplification module; 130 - correlation dual sampling module; I A - Photocurrent; Vg - Integrating voltage; Vc - Sampling voltage; VC C - Power supply voltage; RST1 - First reset signal; RST2 - Second reset signal; RST3 - Third reset signal; RST4 - Fourth reset signal; V REF - Reference voltage; V CM1 - First bias voltage; V CM2 - Second bias voltage; V CM3 -Third bias voltage; V CM4 - Fourth bias voltage. Detailed Implementation

[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0019] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0021] Short-wave infrared imaging technology, due to its unique advantages, is widely used in fields such as night vision, remote sensing, industrial inspection, and spectral analysis. Unlike mid- and long-wave infrared imaging, which relies on the thermal radiation of objects themselves, short-wave infrared imaging has significant advantages over visible light imaging, especially in low-light environments where it can obtain high-contrast images and possesses strong smoke penetration capabilities, making it crucial for target detection in special environments. The pixel readout circuit is a key component connecting the front-end photosensitive detector and the back-end signal processing system; its performance directly determines the core indicators of the entire imaging system, such as signal-to-noise ratio, dynamic range, frame rate, and power consumption.

[0022] Among various readout circuit structures, the capacitive feedback transimpedance amplifier pixel structure is suitable for weak light signal detection scenarios such as short-wavelength infrared (SWIR) due to its high injection efficiency, excellent linearity, and precise control over the detector bias voltage. The core principle of the capacitive feedback transimpedance amplifier is to maintain the photodiode cathode voltage at a fixed reference value using an operational amplifier, and then integrate the photocurrent using a feedback capacitor to convert the charge into a voltage signal output.

[0023] However, existing short-wave infrared readout circuits based on capacitive feedback transimpedance amplifiers face numerous irreconcilable contradictions and challenges in pursuing key performance indicators such as low noise, high frame rate, small pixel area, and low power consumption. Regarding noise suppression, traditional correlated double sampling techniques often employ column-level circuits. While this sampling structure simplifies pixel design, it necessitates long-distance signal transmission between the pixel and the column-level circuit, introducing additional crosstalk and parasitic capacitance noise, resulting in noise superposition and severely limiting the improvement of the signal-to-noise ratio. Simultaneously, the column-level sampling circuit requires complex timing control and signal multiplexing, increasing system power consumption and becoming a bottleneck for improving the imaging frame rate.

[0024] Secondly, in the design of the core amplification unit, traditional operational amplifier structures (such as simple common-source amplifiers) often have limited gain. Under low-power constraints, they are difficult to effectively suppress their own low-frequency noise and offset voltage, resulting in high equivalent input noise for the entire readout circuit. Although some designs use more complex amplifier structures to improve gain, this usually comes at the cost of a significant increase in transistor count and quiescent power consumption, which contradicts the pixel-level design requirements of high integration and low power consumption.

[0025] Furthermore, as application scenarios place increasingly higher demands on the dynamic range of imaging systems, achieving a comprehensive performance improvement within a limited pixel area has become a core design challenge. Existing technologies often sacrifice one or a few performance metrics to improve others, lacking a systematic and innovative architecture that can synergistically optimize noise, area, power consumption, and speed.

[0026] To solve the above problems, such as Figure 1 As shown, the present invention provides a short-wave infrared pixel readout circuit, comprising: Photoelectric conversion module 110 is used to convert optical signals into photocurrent I. A ; The charge integration amplifier module 120, connected to the photoelectric conversion module 110, provides a preset transconductance gain based on a symmetrical differential amplification structure, so as to control the photocurrent I based on the preset transconductance gain. A Amplification was performed, and the photocurrent I was... A By performing charge integration, the integrated voltage Vg is obtained; The related dual sampling module 130 is connected to the charge integration amplifier module 120 to perform reset sampling and signal sampling on the integrated voltage Vg, so as to output the sampling voltage Vc that characterizes the intensity of the optical signal.

[0027] In detail, such as Figure 2As shown, the charge integration amplification module 120 includes an integration unit 121 and an amplification unit 122. The amplification unit 122 provides a preset transconductance gain based on a symmetrical differential amplification structure, and amplifies the photocurrent based on the preset transconductance gain. The integration unit 121 is coupled between the input and output terminals of the amplification unit 122. The integration unit 121 amplifies the photocurrent I... A Perform charge integration.

[0028] More in detail, such as Figure 2 As shown, the integration unit 121 includes a first PMOS transistor PM1 and a first capacitor C1. The drain of the first PMOS transistor PM1 is connected to the first terminal of the first capacitor C1, and the source of the first PMOS transistor PM1 is connected to the second terminal of the first capacitor C1. The first terminal of the first capacitor C1 is connected to the negative input terminal of the amplification unit 122, and the second terminal of the first capacitor C1 is connected to the output terminal of the amplification unit 122. The gate of the first PMOS transistor PM1 is connected to the first reset signal RST1.

[0029] More in detail, such as Figure 2 As shown, the charge integration amplifier module 120 also includes a second PMOS transistor PM2 and a second capacitor C2, as... Figure 3As shown, the amplification unit 122 includes a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM5. The source of the second PMOS transistor PM2 is connected to the negative input terminal of the amplification unit 122, and the drain of the second PMOS transistor PM2 is connected to the positive input terminal of the amplification unit 122. The source of the third PMOS transistor PM3 is connected to the power supply voltage VCC. The drain of the third PMOS transistor PM3 is connected to the source of the fourth PMOS transistor PM4. The source of the fourth PMOS transistor PM4 is connected to the source of the fifth PMOS transistor PM5. The drain of the fourth PMOS transistor PM4 is connected to the source of the sixth PMOS transistor PM6. The gate of the sixth PMOS transistor PM6 is connected to the gate of the seventh PMOS transistor PM7. The drain of the fifth PMOS transistor PM5 is connected to the source of the seventh PMOS transistor PM7. The drain of the sixth PMOS transistor PM6 is connected to the first N... The drain of MOSFET NM1 is connected to the drain of the sixth PMOS transistor PM6, which is also connected to the gate of the third PMOS transistor PM3. The gate of the first NMOS transistor NM1 is connected to the gate of the second NMOS transistor NM2. The drain of the seventh PMOS transistor PM7 is connected to the drain of the second NMOS transistor NM2, and the drain of the seventh PMOS transistor PM7 is also grounded through the second capacitor C2. The source of the first NMOS transistor NM1 is connected to the drain of the third NMOS transistor NM3, and the source of the second NMOS transistor NM2 is connected to the drain of the fourth NMOS transistor NM4. The gate of the fourth PMOS transistor PM4 is connected to the gate of the third NMOS transistor NM3, the gate of the fifth PMOS transistor PM5 is connected to the gate of the fourth NMOS transistor NM4, the source of the third NMOS transistor NM3 is connected to the source of the fourth NMOS transistor NM4, the source of the third NMOS transistor NM3 is connected to the drain of the fifth NMOS transistor NM5, and the source of the fifth NMOS transistor NM5 is grounded. The gate of the fourth PMOS transistor PM4 is the non-inverting input of amplifier unit 122, and the non-inverting input of amplifier unit 122 is connected to the first bias voltage V. CM1 The gate of the fifth PMOS transistor PM5 is the negative input terminal of the amplifier unit 122, which is connected to the first terminal of the first capacitor C1. The drain of the seventh PMOS transistor PM7 is the output terminal of the amplifier unit 122, which is connected to the second terminal of the first capacitor C1. The gate of the sixth PMOS transistor PM6 is the first bias input terminal of the amplifier unit 122, which is connected to the second bias voltage V. CM2 The gate of the first NMOS transistor NM1 is the second bias input terminal of the amplifier unit 122, and the second bias input terminal of the amplifier unit 122 is connected to the third bias voltage V. CM3The gate of the second PMOS transistor PM2 is connected to the first reset signal RST1, and the gate of the fifth NMOS transistor NM5 is the third bias input terminal of the amplifier unit 122. The third bias input terminal of the amplifier unit 122 is connected to the fourth bias voltage V. CM4 .

[0030] More in detail, such as Figure 2 As shown, the photoelectric conversion module 110 includes a photodiode D1. The cathode of photodiode D1 is connected to the power supply voltage VCC, and the anode of photodiode D1 is the output terminal of the photoelectric conversion module 110. The output terminal of the photoelectric conversion module 110 is connected to the negative phase input terminal of the amplification unit 122, and the output terminal of the photoelectric conversion module 110 outputs a photocurrent I. A .

[0031] More in detail, such as Figure 2 As shown, the related dual sampling module 130 includes an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a sixth NMOS transistor NM6, a third capacitor C3, and a fourth capacitor C4. The drain of the eighth PMOS transistor PM8 is connected to the source of the sixth NMOS transistor NM6, and the source of the eighth PMOS transistor PM8 is connected to the drain of the sixth NMOS transistor NM6. The source of the eighth PMOS transistor PM8 is connected to the first terminal of the third capacitor C3, and the first terminal of the third capacitor C3 is grounded through the fourth capacitor C4. The source of the ninth PMOS transistor PM9 is connected to the reference voltage V. REF The drain of the ninth PMOS transistor PM9 is connected to the second terminal of the third capacitor C3. The gate of the eighth PMOS transistor PM8 is connected to the second reset signal RST2. The gate of the sixth NMOS transistor NM6 is connected to the third reset signal RST3. The gate of the ninth PMOS transistor PM9 is connected to the fourth reset signal RST4. The drain of the eighth PMOS transistor PM8 is the input terminal of the correlated dual sampling module 130. The second terminal of the third capacitor C3 is the output terminal of the correlated dual sampling module 130. The second reset signal RST2 and the third reset signal RST3 are out of phase.

[0032] It should also be mentioned that the short-wave infrared pixel readout circuit also includes an output module, such as... Figure 2 As shown, the output module includes a buffer buf. The input of the buffer buf is connected to the output of the correlated dual sampling module 130. The output of the buffer buf transmits the sampled voltage Vc to the subsequent circuit.

[0033] Please refer to Figures 1 to 7 As shown, the working principle of the short-wave infrared pixel readout circuit provided by the present invention is as follows: like Figure 1 As shown, the photoelectric conversion module 110 receives the optical signal and converts it into a photocurrent I. AThe input terminal of the charge integration amplifier module 120 is connected to the output terminal of the photoelectric conversion module 110. Based on the symmetrical differential amplification structure in the amplifier unit 122, a preset transconductance gain is provided. Based on the preset transconductance gain, the photocurrent I... A Amplification processing, the photocurrent I is processed by the integration unit 121. A Charge integration is performed to obtain the integrated voltage Vg; the input terminal of the related dual sampling module 130 is connected to the output terminal of the charge integration amplification module 120. When the circuit is reset, the voltage in the reset state is sampled, and when the circuit is sampled, the voltage in the sampling state is sampled to obtain the sampling voltage Vc.

[0034] like Figure 3 As shown, the input terminal of amplifier unit 122 simultaneously incorporates the transconductance (gm) of both the NMOS and PMOS transistors. Without increasing the additional bias current, the equivalent transconductance is boosted to a preset transconductance gain (gm1 + gm2), where gm1 is the transconductance of the NMOS transistor and gm2 is the transconductance of the PMOS transistor. The voltage gain Av of amplifier unit 122 is -(gm1 + gm2)Rout, where Rout is the equivalent resistance of amplifier unit 122. The high-gain amplifier unit 122 provides lower equivalent input thermal noise and can operate at lower supply voltages (e.g., 3V), thereby reducing power consumption. The second capacitor C2 provides frequency compensation for amplifier unit 122, thus improving stability.

[0035] First, a reset operation is performed on the short-wave infrared pixel readout circuit. The first reset signal RST1, the second reset signal RST2, and the fourth reset signal RST4 are at low level, and the third reset signal RST3 is at high level. The first PMOS transistor PM1, the second PMOS transistor PM2, the eighth PMOS transistor PM8, the ninth PMOS transistor PM9, and the sixth NMOS transistor NM6 are all turned on, thus realizing the reset operation. For example... Figure 4 As shown, at time t1, the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned off first. At this time, the voltage across the first capacitor C1 is equal to the first bias voltage V. CM1 The voltage across the first terminal of the third capacitor C3 is equal to the first bias voltage V. CM1 The voltage across the second terminal of the third capacitor C3 is equal to the reference voltage V. REF At time t2, the ninth PMOS transistor PM9 is turned off, and the voltage across the first capacitor C1 decreases. At time t3, the eighth PMOS transistor PM8 and the sixth NMOS transistor NM6 are turned off, and the voltage across the first terminal of the third capacitor C3 decreases. A The voltage drop difference ▲V compared to time t2 means that the voltage across the second terminal of the first capacitor C1 is equal to the voltage across the first terminal of the third capacitor C3. A The voltage V at the second terminal of the third capacitor C3 B Equal to reference voltage VREF The difference between the voltage difference ▲V and the voltage difference. A significant voltage difference is formed across the third capacitor C3. This voltage difference is the reset noise of the first capacitor C1, and the sampled voltage Vc is output through the buffer buf, and this process is repeated.

[0036] like Figure 5 As shown, the amplitude-frequency curve and phase-frequency curve of the amplifier unit 122 are displayed. The black curve represents the amplitude-frequency curve, with the horizontal axis representing frequency and the vertical axis representing the gain of the amplifier unit 122. The red curve represents the phase-frequency curve, with the horizontal axis representing frequency and the vertical axis representing the phase margin of the amplifier unit 122. Figure 5 It can be seen that as the frequency increases, the gain and phase margin decrease. For example... Figure 6 As shown, the horizontal axis represents frequency, and the vertical axis represents the noise of amplifier unit 122. The noise of amplifier unit 122 decreases as the frequency increases. Figure 7 As shown, the output characteristic curve of the charge integration amplifier module 120 is shown. The horizontal axis represents time, and the vertical axis represents the voltage across the first capacitor C1. It can be seen that the larger the photocurrent, the greater the change in voltage across the first capacitor C1.

[0037] The present invention also provides a control method for a pixel readout circuit, which is applied to the short-wave infrared pixel readout circuit as described above, including: Convert optical signals into photocurrent I A ; Based on the preset transconductance gain, the photocurrent I A Amplification is performed, and the photocurrent I is simultaneously... A By performing charge integration, the integrated voltage Vg is obtained; The integral voltage Vg is reset and sampled to obtain the sampled voltage Vc.

[0038] In detail, in converting the optical signal into photocurrent I... A Previously, it also included: acquiring a reset signal; and resetting the short-wave infrared pixel readout circuit based on the reset signal. Specifically, this involved converting the optical signal into photocurrent I... A Previously, the first reset signal RST1, the second reset signal RST2, and the fourth reset signal RST4 were obtained as low level, and the third reset signal RST3 was obtained as high level. Based on the four reset signals, the first PMOS transistor PM1, the second PMOS transistor PM2, the eighth PMOS transistor PM8, the ninth PMOS transistor PM9, and the sixth NMOS transistor NM6 were turned on to realize the reset operation of the short-wave infrared pixel readout circuit.

[0039] This invention provides a short-wave infrared pixel readout circuit and its control method. The short-wave infrared pixel readout circuit converts optical signals into photocurrents using a photoelectric conversion module. A preset transconductance gain is provided through a symmetrical differential amplification structure in a charge integration amplification module to amplify the photocurrent based on this gain. The photocurrent is then integrated to obtain an integrated voltage. A related dual sampling module performs reset sampling and signal sampling on the integrated voltage to obtain a sampled voltage. The short-wave infrared pixel readout circuit provided by this invention employs a symmetrical differential amplification input structure, which has a high common-mode rejection ratio and good anti-interference capability, improving the anti-interference capability of the amplification process without increasing power consumption. The related dual sampling module is concentrated within the readout circuit, avoiding multiple signal transmissions between the pixel and column-level circuits, reducing the processing pressure on the column-level circuits, which is beneficial for improving the system frame rate. It also features low noise, and the fewer switches in the related dual sampling module simplify timing control, resulting in a smaller pixel area and increased chip integration.

[0040] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A short-wave infrared pixel readout circuit, characterized in that, include: A photoelectric conversion module is used to convert optical signals into photocurrent; A charge integration amplification module, connected to the photoelectric conversion module, provides a preset transconductance gain based on a symmetrical differential amplification structure to amplify the photocurrent based on the preset transconductance gain, and performs charge integration on the photocurrent to obtain the integrated voltage; The related dual sampling module, which is connected to the charge integration amplification module, performs reset sampling and signal sampling on the integrated voltage to output a sampling voltage characterizing the intensity of the optical signal.

2. The short-wave infrared pixel readout circuit according to claim 1, characterized in that, The charge integration amplification module includes an integration unit and an amplification unit. The amplification unit provides a preset transconductance gain based on the symmetrical differential amplification structure and amplifies the photocurrent based on the preset transconductance gain. The integration unit is coupled between the input terminals of the amplification unit and the input terminal of the amplification unit, and the integration unit performs charge integration on the photocurrent.

3. The short-wave infrared pixel readout circuit according to claim 2, characterized in that, The integration unit includes a first PMOS transistor and a first capacitor. The drain of the first PMOS transistor is connected to the first terminal of the first capacitor, and the source of the first PMOS transistor is connected to the second terminal of the first capacitor. The first terminal of the first capacitor is connected to the negative input terminal of the amplification unit, and the second terminal of the first capacitor is also connected to the output terminal of the amplification unit. The gate of the first PMOS transistor is connected to a first reset signal.

4. The short-wave infrared pixel readout circuit according to claim 2, characterized in that, The charge integration amplification module further includes a second PMOS transistor and a second capacitor. The amplification unit includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The source of the second PMOS transistor is connected to the negative input terminal of the amplification unit, and the drain of the second PMOS transistor is connected to the positive input terminal of the amplification unit. The source of the third PMOS transistor is connected to the power supply voltage, and the drain of the third PMOS transistor is connected to the... The source of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor, the drain of the fourth PMOS transistor is connected to the source of the sixth PMOS transistor, the gate of the sixth PMOS transistor is connected to the gate of the seventh PMOS transistor, the drain of the fifth PMOS transistor is connected to the source of the seventh PMOS transistor, the drain of the sixth PMOS transistor is connected to the drain of the first NMOS transistor, the drain of the sixth PMOS transistor is also connected to the gate of the third PMOS transistor, and the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor. The drain of the MOS transistor is connected to the drain of the second NMOS transistor. The drain of the seventh PMOS transistor is also grounded via the second capacitor. The source of the first NMOS transistor is connected to the drain of the third NMOS transistor. The source of the second NMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the fourth PMOS transistor is connected to the gate of the third NMOS transistor. The gate of the fifth PMOS transistor is connected to the gate of the fourth NMOS transistor. The source of the third NMOS transistor is connected to the source of the fourth NMOS transistor. The source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor. The source of the fifth NMOS transistor is grounded. The gate of the fourth PMOS transistor is the positive input terminal of the amplification unit, the gate of the fifth PMOS transistor is the negative input terminal of the amplification unit, the drain of the seventh PMOS transistor is the output terminal of the amplification unit, the gate of the sixth PMOS transistor is the first bias input terminal of the amplification unit, the gate of the first NMOS transistor is the second bias input terminal of the amplification unit, the gate of the second PMOS transistor is connected to the first reset signal, and the gate of the fifth NMOS transistor is the third bias input terminal of the amplification unit.

5. The short-wave infrared pixel readout circuit according to claim 1, characterized in that, The photoelectric conversion module includes a photodiode, the cathode of which is connected to the power supply voltage, and the anode of which is the output terminal of the photoelectric conversion module.

6. The short-wave infrared pixel readout circuit according to claim 1, characterized in that, The correlated dual sampling module includes an eighth PMOS transistor, a ninth PMOS transistor, a sixth NMOS transistor, a third capacitor, and a fourth capacitor. The drain of the eighth PMOS transistor is connected to the source of the sixth NMOS transistor, and the source of the eighth PMOS transistor is connected to the drain of the sixth NMOS transistor. The source of the eighth PMOS transistor is connected to the first terminal of the third capacitor, and the first terminal of the third capacitor is grounded after passing through the fourth capacitor. The source of the ninth PMOS transistor is connected to a reference voltage, and the drain of the ninth PMOS transistor is connected to the second terminal of the third capacitor. The gate of the eighth PMOS transistor is connected to a second reset signal, the gate of the sixth NMOS transistor is connected to a third reset signal, and the gate of the ninth PMOS transistor is connected to a fourth reset signal. The second terminal of the third capacitor is the output terminal of the correlated dual sampling module, and the second reset signal is inverted from the third reset signal.

7. A control method for a short-wave infrared pixel readout circuit, characterized in that, include: Convert optical signals into photocurrent; The photocurrent is amplified based on a preset transconductance gain, and the photocurrent is simultaneously integrated by charge integration to obtain the integrated voltage. The integrated voltage is reset and sampled, and the sampled voltage is obtained.

8. The control method for the short-wave infrared pixel readout circuit according to claim 7, characterized in that, Before converting the optical signal into a photocurrent, the process also includes: Obtain the reset signal; The short-wave infrared pixel readout circuit is reset based on the reset signal.

Images