Waveform data management method, system, and computer-readable storage medium

Abstract

The application relates to the technical field of simulation test, and discloses a waveform data management method, a system and a computer readable storage medium. The method comprises the following steps: storing waveform data generated in a simulation test process into a main memory file in real time; when the storage space of the main memory file is full, switching a standby memory file to a next main memory file to continue receiving the waveform data generated in the simulation test process in real time; synchronously transferring all the waveform data in the main memory file with the full storage space to a solid state disk, and switching the main memory file to a standby memory file available after the data transfer. The method can guarantee uninterrupted waveform data receiving and no frame loss in long-time simulation.

Description

Technical Field

[0001] This application relates to the field of simulation testing technology, and in particular to a waveform data management method, system, and computer-readable storage medium. Background Technology

[0002] In integrated circuit (IC) simulation testing, waveform data is generated in real time at rates up to 32 GB / s, such as... Figure 1 As shown, traditional storage paths rely on the PCIe bus to write data directly to the hard drive, which is limited by the hard drive's write bandwidth and is far lower than the emulator's output rate. If this direct write mode is adopted, data backlog will inevitably occur, ultimately leading to the loss of waveforms in critical timing segments, thus compromising the integrity and traceability of the test results.

[0003] Furthermore, traditional storage methods selectively save waveform data, storing only critical paths and signals, retaining representative waveforms, and discarding the rest. This selective saving is causing a data black hole crisis in IC simulation and verification, increasing the cost of analyzing IC design defects and bugs. Summary of the Invention

[0004] In view of this, embodiments of this application provide a waveform data management method, system, and computer-readable storage medium, which can effectively solve the technical problems of data backlog and loss of waveforms in key timing segments caused by traditional storage paths.

[0005] In a first aspect, embodiments of this application provide a waveform data management method, including: The waveform data generated during the simulation test is stored in the main memory file in real time. When the main memory file is full, a backup memory file is switched to the next main memory file to continue receiving waveform data generated in real time during the simulation test. Simultaneously, all waveform data in the main memory file, whose storage space is full, is transferred to the solid-state drive, and after the data transfer, the main memory file is switched to a usable backup memory file.

[0006] Secondly, embodiments of this application provide a waveform data management system, including: The first module is used to store the waveform data generated during the simulation test into the main memory file in real time. The second module is used to switch a backup memory file to the next main memory file when the storage space of the main memory file is full, so as to continue to receive waveform data generated in real time during the simulation test. The third module is used to synchronously transfer all waveform data from the main memory file whose storage space is full to the solid-state drive, and after the data transfer, switch the main memory file to a usable backup memory file.

[0007] Thirdly, this application also provides a terminal device, including a processor and a memory, wherein the memory stores a computer program, and the processor is used to execute the computer program to perform the following steps: The waveform data generated during the simulation test is stored in the main memory file in real time. When the main memory file is full, a backup memory file is switched to the next main memory file to continue receiving waveform data generated in real time during the simulation test. Simultaneously, all waveform data in the main memory file, whose storage space is full, is transferred to the solid-state drive, and after the data transfer, the main memory file is switched to a usable backup memory file.

[0008] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps: The waveform data generated during the simulation test is stored in the main memory file in real time. When the main memory file is full, a backup memory file is switched to the next main memory file to continue receiving waveform data generated in real time during the simulation test. Simultaneously, all waveform data in the main memory file, whose storage space is full, is transferred to the solid-state drive, and after the data transfer, the main memory file is switched to a usable backup memory file.

[0009] The embodiments of this application have the following beneficial effects: First, waveform data is stored in the main memory file, giving full play to the bandwidth advantage of ≥300 GB / s memory, completely avoiding the hard disk write bottleneck, and realizing full, lossless, and continuous capture of waveform data.

[0010] Secondly, by triggering a transfer when the storage space is full, the timing is controlled and overflow is avoided; after the transfer, the memory file is reused immediately, forming a low-overhead closed loop, ensuring that waveform reception is uninterrupted and frames are not lost during long-term simulation. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This diagram illustrates a traditional waveform data management method. Figure 2 This illustration shows a first schematic diagram of a waveform data management method according to an embodiment of this application; Figure 3 A second schematic diagram of the waveform data management method according to an embodiment of this application is shown; Figure 4 A third schematic diagram of the waveform data management method according to an embodiment of this application is shown; Figure 5 A fourth schematic diagram of the waveform data management method according to an embodiment of this application is shown; Figure 6 A fifth schematic diagram of the waveform data management method according to an embodiment of this application is shown; Figure 7 A structural block diagram of the waveform data management method according to an embodiment of this application is shown. Detailed Implementation

[0013] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0014] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0015] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0016] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in a generally used dictionary) shall be interpreted as having the same meaning as in the context of the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0017] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0018] The waveform data management method, system, and computer-readable storage medium will be described below with reference to some specific embodiments.

[0019] The waveform data management method proposed in this application should be applicable to integrated circuit (IC) simulation and testing systems, where an integrated circuit simulation and testing system refers to a hardware and software platform for performing integrated circuit design verification. In some embodiments, the integrated circuit simulation and testing system includes memory and a solid-state drive (SSD), with the memory connected to the integrated circuit simulator via a PCIe interface and also connected to the SSD; further optionally, it also includes a display for displaying waveform data.

[0020] For example, this memory can be implemented using a memory such as dynamic random access memory. In this application, using Ramfs (RAM File System) technology, a main memory file and a spare memory file are created in memory. The main memory file refers to the selected memory file used for real-time data storage, and its state is occupied; while the spare memory file refers to the unselected memory file that is allowed to write data, and its state is available.

[0021] The hard drive refers to a solid-state drive (SSD), a non-volatile storage medium primarily used in this embodiment for long-term storage of waveform data. It is worth noting that the maximum data access speed of a hard drive is no more than 550MB / s, while the data access speed of RAM can reach 300GB / s.

[0022] The PCIe interface has high transmission efficiency, avoids switching between user space and kernel space, and greatly increases the speed of writing files to SSD hard drives.

[0023] Figure 2 A first schematic diagram of a waveform data management method according to an embodiment of this application is shown. Exemplarily, the waveform data management method includes the following steps: Step S202: The waveform data generated during the simulation test is stored in the main memory file in real time.

[0024] Main memory files are high-speed temporary files created in memory modules (such as dynamic random access memory) using memory file system technology. They are used to receive waveform data streams in real time to achieve high-speed temporary storage.

[0025] Waveform data refers to a sequence of digital signal values ​​sampled at discrete time points with fixed or variable time steps, used to record the state evolution trajectory of the integrated circuit under test during the simulation process.

[0026] Optionally, waveform data generated during simulation testing can be stored in the main memory file in real time via a DDR5 channel. The DDR5 channel is configured as an eight-channel-4800, with a theoretical bandwidth (unidirectional) of 307.2 GB / s and an actual usable bandwidth of approximately 280 GB / s. DDR5 refers to a fifth-generation double data rate synchronous dynamic random access memory (DRAM) characterized by high bandwidth, low latency, and high energy efficiency. This application uses the DDR5 data transmission channel to store waveform data generated during simulation testing in real time into the main memory file. Alternatively, other types of memory can also be used in this application; the aforementioned type is merely an example.

[0027] Step S204: When the main memory file is full, switch a backup memory file to the next main memory file to continue receiving waveform data generated in real time during the simulation test.

[0028] Among them, "storage space is full" means that the current size of the waveform data written to the main memory file is 100%.

[0029] Step S206: Simultaneously transfer all waveform data from the main memory file whose storage space is full to the solid-state drive, and switch the main memory file to a usable backup memory file after the data transfer.

[0030] Among them, the backup memory file refers to a memory file that is pre-created through the memory file system and is isomorphic to the main memory file as a backup. It is mainly used to seamlessly take over waveform data reception when the main file is full.

[0031] In one example, reference Figure 3 First, a backup memory file is created. When the storage space of the main memory file is full, the system quickly switches to the backup memory file to receive waveform data. For a full main memory file, a separate thread is started to synchronously write the waveform data to a solid-state drive (such as an SSD file). After the data in the main memory file is completely transferred, it can be switched to another backup memory file by clearing the data or allowing data overwriting. By repeating the above process, waveform data can be received and saved continuously.

[0032] Because the bandwidth rate of writing from the main memory file to the SSD hard disk file is much lower than the bandwidth rate of transferring waveform data to the main memory file via PCIe, the main memory file will always be full.

[0033] In another example, refer to Figure 4 Using Parallel write technology, multiple memory files are created as backup memory files. When the main memory file is full, an available backup memory file is switched to become the next main memory file to continue receiving waveform data. Simultaneously, an independent thread is started to write the waveform data from the full main memory file to the SSD hard disk file. Synchronization here means that while the next main memory file is receiving data, the previous main memory file, which is already full, is also performing data transfer operations.

[0034] When the next main memory file is full, another available backup memory file is switched to, and another independent thread is started simultaneously to write the waveform data from the next main memory file that is full to another SSD hard disk file. This process is repeated, and each main memory file that is full is started simultaneously with an independent thread to write the waveform data to multiple SSD hard disk files in parallel, which can multiply the writing speed to the SSD.

[0035] Specifically, when the storage space of multiple main memory files is full, multiple independent threads are invoked to transfer all waveform data from the multiple main memory files to the solid-state drive in parallel. That is, each independent thread corresponds to one main memory file and is used to perform the corresponding data transfer operation.

[0036] For example, when module-level integrated circuit simulation generates 1GB / s waveform data, an SSD with a bandwidth of 500MB / s will have two main memory files being transferred simultaneously. When system-level integrated circuit simulation generates 32GB / s data, there will be 64 main memory files being transferred simultaneously.

[0037] As an alternative solution, this involves determining how many backup memory files need to be created to match the rate at which the parallel writing speed to the SSD hard disk files can be matched with the rate at which the main memory file receives waveform data.

[0038] In one embodiment, multiple available backup memory files are linked together to obtain a dynamic memory pool; the number of files in all backup memory files in the dynamic memory pool is monitored in real time, and the number of backup memory files in the dynamic memory pool is dynamically adjusted based on the number of files.

[0039] The dynamic memory pool refers to a scalable memory resource set consisting of N spare memory files linked by a circular doubly linked list, for example, N∈[2, 20].

[0040] Specifically, refer to Figure 5 The system uses memory pool technology to dynamically allocate the SSD write speed. Multiple backup memory files are linked together in a circular linked list to form a dynamic memory pool. When the main memory file is full, a backup memory file is taken from the dynamic memory pool and used as the next main memory file to continue receiving waveform data. After the original main memory file has finished writing the waveform data to the SSD hard disk file, it is put into the dynamic memory pool as a new backup memory file.

[0041] Optionally, when the main memory file is full, an available spare memory file is retrieved from the dynamic memory pool and used as the next main memory file to continue receiving waveform data generated in real time during the simulation test.

[0042] In one embodiment, if the number of files is less than a first threshold, a first preset number of spare memory files are dynamically added to the dynamic memory pool; if the number of files is greater than a second threshold, a second preset number of spare memory files are dynamically destroyed in the dynamic memory pool.

[0043] The first quantity threshold refers to the lower limit of the number of backup memory files.

[0044] The first preset quantity refers to the number of new spare memory files added each time dynamic expansion occurs.

[0045] The second quantity threshold refers to the upper limit of the number of backup memory files.

[0046] The second preset quantity refers to the number of spare memory files reduced each time the capacity is dynamically reduced.

[0047] Specifically, another independent thread (different from the independent thread that writes waveform files to hard disk files) is started to monitor the number of spare files in the memory pool in real time. When the monitoring finds that the number of spare files is less than the first threshold (e.g., 2), it means that the writing speed to the SSD hard disk files is insufficient and the number of spare files written in parallel needs to be increased. Then, a first preset number (e.g., 10) of spare memory files are created and put into the dynamic memory pool.

[0048] When monitoring detects that the number of backup files exceeds the second threshold (e.g., 20), it indicates that the rate of writing files to the SSD has a significant margin to meet the rate of waveform data generation for integrated circuit simulation verification. Therefore, the second preset number (e.g., 10) of backup memory files are destroyed to release memory. This allows for dynamic adjustment of the number of backup memory files in the dynamic memory pool, adapting to different levels of integrated circuit simulation verification scale.

[0049] When dealing with waveform data of terabytes or more at the level of an integrated circuit simulation and verification system, in order to quickly locate and load a specific waveform data stored on the hard drive and display it, as an optional solution, this application also proposes a waveform data index construction method and a fast search method.

[0050] In one embodiment, the method for constructing an index further includes: Based on the timestamp of each waveform file stored on the solid-state drive, each waveform file is named to obtain an ID identifier for each waveform file; a first-level index is built for each waveform file according to the time order of each ID identifier; for each waveform file, a second-level index is built based on the sequence number of the clock cycle corresponding to each byte inside the waveform file.

[0051] The timestamp refers to the starting simulation time of the waveform data recorded in the waveform file.

[0052] Time order refers to the order in which waveform files are arranged in ascending order according to their timestamp values.

[0053] Clock cycle refers to the smallest time step unit in integrated circuit simulation, which is determined by the clock precision configured in the simulator.

[0054] Specifically, a secondary index is built from the set of waveform data files stored on the SSD hard drive: First-level index: Each waveform file stored on the solid-state drive is named and a unique identifier is generated. For example, whenever a waveform data segment is transferred from the main memory file, the starting simulation time corresponding to that waveform data is automatically read, converted into a string of numbers, and used as the complete filename of the waveform file. Furthermore, an ordered list is created, arranging the identifiers of all generated waveform files in ascending order according to the time sequence they represent.

[0055] Secondary index: The waveform data inside the waveform file is converted into binary format, and the waveform data is continuously sorted according to the principle that one byte in the binary waveform data corresponds to one clock cycle. A secondary index is built based on the clock cycle number corresponding to each segment of waveform data.

[0056] In one embodiment, for a fast lookup method, the method further includes: In response to a waveform data lookup request, the system locates the corresponding target waveform file in the primary index based on the timestamp information carried in the waveform data lookup request and maps the target waveform file to a memory block. Based on the clock cycle number information carried in the waveform data lookup request, the system calculates the address offset of the target waveform data to be searched. Based on the address offset, the system moves the access pointer to the storage address of the target waveform data in the memory block through random addressing, and then reads the target waveform data for display.

[0057] The target waveform file refers to one or more waveform files whose recorded time periods cover the target time range, selected by file-level time-series indexing.

[0058] Target waveform data refers to the signal state information at a specific moment that a user wants to view when debugging integrated circuit simulation.

[0059] Address offset refers to the number of bytes within the target waveform file that the waveform data to be searched is located from the beginning of the file.

[0060] A memory block refers to a contiguous area formed by loading the entire target waveform file into the memory space used by the process running the waveform viewing program through memory mapping.

[0061] Specifically, refer to Figure 6 When searching for waveform data (such as target waveform data), the system first retrieves the target waveform file in the first-level index using the timestamp information carried in the request. Then, it uses mmap memory mapping technology to map the entire target waveform file into a memory block. Finally, it uses the clock sequence information of the second-level index to calculate the address offset of the target waveform data. For example, when searching for waveform data with clock sequence number 1001, the data address offset is 1001 bytes.

[0062] By using random addressing within a memory block, the access pointer is directly moved to the address of the target waveform data, thereby accessing the target waveform data for display.

[0063] Since the entire waveform file is mapped into memory blocks, the waveform data of the immediate preceding and following clocks can be directly accessed within the currently displayed waveform, avoiding the waiting time of multiple lookups and loading, achieving a smooth display effect at the millisecond level. See the following comparison table for details:

[0064] Figure 7 A structural block diagram of a waveform data management system according to an embodiment of this application is shown. Exemplarily, the waveform data management system 700 includes: The first module 702 is used to store the waveform data generated during the simulation test into the main memory file in real time. The second module 704 is used to switch a backup memory file to the next main memory file when the main memory file is full, so as to continue receiving waveform data generated in real time during the simulation test. The third module 706 is used to synchronously transfer all waveform data from the main memory file, which is full, to the solid-state drive, and after the data transfer, switch the main memory file to a usable backup memory file.

[0065] It is understood that the system in this embodiment corresponds to the waveform data management method in the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0066] This application also provides a terminal device, exemplary of which includes a processor and a memory, wherein the memory stores a computer program, and the processor executes the computer program to enable the terminal device to perform the functions of the waveform data management method described above or the various modules in the waveform data management system described above.

[0067] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Network Processor (NP), Digital Signal Processor (DSP), Application-Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0068] Memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable Programmable Read-Only Memory (EEPROM). Memory is used to store computer programs, and the processor can execute these programs upon receiving execution instructions.

[0069] This application also provides a computer-readable storage medium for storing the computer program used in the aforementioned terminal device. For example, the computer-readable storage medium may include, but is not limited to, various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0070] In the several embodiments provided in this application, it should be understood that the disclosed systems and methods can also be implemented in other ways. The system embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0071] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0072] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0073] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A waveform data management method, characterized in that, An integrated circuit simulation and testing system, comprising memory and a solid-state drive, wherein a main memory file and at least one backup memory file are created in the memory, the method comprising: The waveform data generated during the simulation test is stored in the main memory file in real time. When the main memory file is full, a backup memory file is switched to the next main memory file to continue receiving waveform data generated in real time during the simulation test. Simultaneously, all waveform data in the main memory file whose storage space is full is transferred to the solid-state drive, and after the data transfer, the main memory file is switched to a usable backup memory file; Based on the timestamp of each waveform file stored on the solid-state drive, each waveform file is named to obtain the ID identifier of each waveform file; A first-level index is constructed for each waveform file according to the time sequence of each ID identifier; For each waveform file, a secondary index is constructed based on the sequence number of the clock cycle corresponding to each byte within the waveform file. In response to a waveform data lookup request, based on the timestamp information carried in the waveform data lookup request, the corresponding target waveform file is found in the first-level index, and the target waveform file is mapped to a memory block using mmap memory mapping technology; Based on the clock cycle number information carried in the waveform data lookup request, calculate the address offset of the target waveform data to be searched. Based on the address offset, the access pointer is moved to the storage address of the target waveform data in the memory block by random addressing, and then the target waveform data is read and displayed.

2. The method according to claim 1, characterized in that, The method further includes: When the storage space of multiple main memory files is full, multiple independent threads are invoked to transfer all waveform data from the multiple main memory files to the solid-state drive in parallel. Each independent thread corresponds to one main memory file.

3. The method according to claim 1, characterized in that, The method further includes: Multiple available backup memory files are linked together to obtain a dynamic memory pool; The number of all spare memory files in the dynamic memory pool is monitored in real time, and the number of spare memory files in the dynamic memory pool is dynamically adjusted based on the number of files.

4. The method according to claim 3, characterized in that, The step of dynamically adjusting the number of spare memory files in the dynamic memory pool based on the number of files includes: If the number of files is less than a first quantity threshold, a first preset number of spare memory files are dynamically added to the dynamic memory pool; If the number of files exceeds the second threshold, a second preset number of spare memory files are dynamically destroyed in the dynamic memory pool.

5. The method according to claim 3, characterized in that, The step of switching the backup memory file to the next main memory file and continuing to receive waveform data generated in real time during the simulation test includes: An available spare memory file is retrieved from the dynamic memory pool and used as the next main memory file to continue receiving waveform data generated in real time during the simulation test.

6. A waveform data management system, characterized in that, The system includes: The first module is used to store the waveform data generated during the simulation test into the main memory file in real time. The second module is used to switch a backup memory file to the next main memory file when the storage space of the main memory file is full, so as to continue to receive waveform data generated in real time during the simulation test. The third module is used to synchronously transfer all waveform data in the main memory file whose storage space is full to the solid-state drive, and after the data transfer, switch the main memory file to a usable backup memory file; Based on the timestamp of each waveform file stored on the solid-state drive, each waveform file is named to obtain the ID identifier of each waveform file; A first-level index is constructed for each waveform file according to the time sequence of each ID identifier; For each waveform file, a secondary index is constructed based on the sequence number of the clock cycle corresponding to each byte within the waveform file. In response to a waveform data lookup request, based on the timestamp information carried in the waveform data lookup request, the corresponding target waveform file is found in the first-level index, and the target waveform file is mapped to a memory block using mmap memory mapping technology; Based on the clock cycle number information carried in the waveform data lookup request, calculate the address offset of the target waveform data to be searched. Based on the address offset, the access pointer is moved to the storage address of the target waveform data in the memory block by random addressing, and then the target waveform data is read and displayed.

7. A terminal device, characterized in that, The terminal device includes a processor and a memory, the memory storing a computer program, and the processor executing the computer program to implement the waveform data management method according to any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed on a processor, implements the waveform data management method according to any one of claims 1-5.

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