A SATA controller low power management device and method

Abstract

The application discloses a kind of SATA controller low-power consumption management device and method, it is related to SATA solid state disk technical field, integrated in SoC chip, including SATA physical layer unit, SATA control unit, crystal oscillator clock unit, clock gating unit, phase-locked loop unit, power consumption management unit, configuration register unit.Integrated SATA physical layer and SATA control unit as independent power supply domain, when DEVSLP signal is effective, cut off its power supply, while cooperate to close phase-locked loop, crystal oscillator clock and other clock units and CPU and so on cut-off power consumption source, make SoC chip enter lowest power consumption state.Enter and exit process of DEVSLP low-power consumption mode by software and hardware collaborative operation, avoid data loss and command exception.

Description

Technical Field

[0001] This invention relates to the field of SATA solid-state drive technology, and more specifically to a low-power management device and method for a SATA controller. Background Technology

[0002] With the rapid development of mobile terminals such as laptops, tablets, and portable devices, the widespread deployment of large-scale data center storage servers, and the application upgrades in scenarios such as industrial control, automotive systems, and IoT devices, increasingly stringent requirements are being placed on the power consumption of storage devices. For mobile terminals, longer battery life is one of the core requirements, which necessitates that SATA solid-state drives (SSDs) significantly reduce power consumption under idle or light load conditions. For data center storage servers, due to the deployment of a large number of hard drives, the total power consumption is extremely high. Reducing the power consumption of each SATA device, especially standby power consumption, can significantly reduce electricity costs and heat dissipation costs, aligning with the development trend of green computing. In addition, scenarios such as industrial control, automotive systems, and IoT devices are extremely sensitive to the power consumption and stability of storage devices. Low-power SATA designs help reduce system heat dissipation, improve device stability, and extend device lifespan.

[0003] The SATA 3.2 protocol introduced the Device Sleep (DEVSLP) function: DEVSLP is a sideband signal, active high, requiring both the host and device sides to support this function for low-power operation. When this signal is high, the device enters an ultra-low power mode, further reducing standby power consumption and supporting a "near-zero power" state. SATA's low-power design requirements are driven by mobility, data center energy efficiency, protocol evolution, SSD technology, and market demand. Through hardware and protocol optimization, it significantly reduces overall system power consumption while meeting storage performance requirements, adapting to the needs of all scenarios from portable devices to data centers. With the widespread adoption of PCIe / NVMe interfaces, SATA's low-power design philosophy has been inherited and developed, further driving the energy efficiency evolution of storage technology. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a low-power management device and method for a SATA controller, enabling the SoC chip to enter the lowest power consumption state, while improving the flexibility of entering and exiting the low-power mode, and meeting the low-power requirements of multiple scenarios.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] In a first aspect, a low-power management device for a SATA controller, integrated into a SoC chip, includes a SATA physical layer unit, a SATA control unit, a crystal clock unit, a clock gating unit, a phase-locked loop unit, a power management unit, and a configuration register unit, wherein:

[0007] The SATA physical layer unit is used to implement the SATA physical layer protocol functions;

[0008] The SATA control unit is connected to the SATA physical layer unit and is physically integrated by sharing an independent power domain E1. It is used to implement the link layer, transport layer and command layer functions above the physical layer of the SATA protocol.

[0009] The crystal clock unit is used to receive the ref_clk clock signal input to the SoC chip and input it to the phase-locked loop unit and the clock gating unit;

[0010] The clock gating unit is used to turn on and off the ref_clk clock signal input to the SATA physical layer unit, and its control signal comes from the configuration register of the configuration register unit.

[0011] The phase-locked loop unit is used to multiply the ref_clk clock input from the crystal oscillator clock unit to different frequencies required by each unit of the SoC.

[0012] The power management unit is used to receive the deep sleep signal DEVSLP sent by the host and perform debouncing processing, control the opening and closing of each power domain of the SoC chip, the opening and closing of the phase-locked loop unit and the crystal clock unit when entering and exiting low power mode, and the closing of the input clock of the SATA physical layer unit; when the deep sleep signal DEVSLP is high, the power management unit is also used to cut off the power of the independent power domain E1 to achieve low power control.

[0013] The configuration register unit is used to receive the configuration values ​​of each register from the CPU and transmit them to the clock gating unit, the crystal clock unit, the power management unit, the SATA physical layer unit, and the SATA control unit. At the same time, it receives the status information of the above units and stores it in the corresponding registers.

[0014] Furthermore, the SATA physical layer unit is connected to the host SATA interface via the SATA_IF interface.

[0015] Furthermore, the ref_clk clock signal is input to the SATA physical layer unit as a reference clock required for the operation of the SATA physical layer unit. The opening and closing of the reference clock is controlled by the clock gating unit according to the low power control requirements.

[0016] Furthermore, the SoC chip also includes a CPU, DDR, and on-chip cache. The SATA control unit is also used to interact with the CPU, DDR, and on-chip cache at the command layer to respectively implement SATA command parsing, DMA command transmission, and IO data read / write functions.

[0017] Secondly, a low-power management method for a SATA controller, applied in the low-power management device for a SATA controller as described in the first aspect, the method comprising:

[0018] The host pulls the DEVSLP deep sleep signal high, enabling the device to enter the DEVSLP low-power state.

[0019] When the CPU receives a DEVSLP high interrupt, it stops receiving SATA commands, discards unexecuted SATA commands, processes and waits for the currently executing SATA commands to complete.

[0020] The CPU performs preparatory work before power failure, including data being flashed to flash memory, table entries being updated, register backups being made, and firmware variable backups being made.

[0021] After completing the preparations before the power outage, the CPU configures the devslp_start register of the power management unit to a high level, starts the power management unit to enable the DEVSLP low-power process, and the CPU enters the interrupt waiting state.

[0022] The power management unit determines whether the current DEVSLP signal is high. If it is low, it means that it is not necessary to enter the DEVSLP state at present, the low-power process ends, and the CPU receives the DEVSLP interrupt to exit the low-power process.

[0023] If the current DEVSLP signal is high, the low-power process is started. The power management unit outputs control signals to turn off the clock of the CPU and SATA physical layer units and reset them, turn on the isolation control signals of each power domain to isolate each power domain, turn off the power of each power domain of the SoC chip, turn off the phase-locked loop unit and the crystal clock unit, and the device enters the DEVSLP low-power state.

[0024] Furthermore, it also includes: when the host needs the device to exit low-power mode, it pulls down the deep sleep signal DEVSLP. After the power management component detects the change in the deep sleep signal DEVSLP, it immediately exits its own DEVSLP low-power state and sequentially starts the crystal clock unit and the phase-locked loop unit to restore the clock supply. Subsequently, the power management component turns on the power of each power domain, turns off the isolation control signal of each power domain, restores the normal connection of each power domain, starts the clock of the CPU and SATA physical layer unit, and resets the relevant modules to restore each module to normal operation. The CPU wakes up from the interrupt waiting state, reads the previously backed-up register data and firmware variables, restores the normal operating state of the system, and simultaneously resumes receiving and executing SATA commands, and the device returns to normal operating mode.

[0025] The beneficial effects of this invention are:

[0026] (1) The present invention integrates the SATA physical layer and the SATA control unit as an independent power domain. When the DEVSLP signal is valid, the power management unit directly cuts off the power of the power domain. At the same time, it shuts down the phase-locked loop, the crystal clock and other clock units and the CPU and other core modules, thereby cutting off the power source to the greatest extent and truly enabling the SoC chip to enter the lowest power consumption state, significantly reducing the power consumption of the SATA controller.

[0027] (2) The entry and exit process of DEVSLP low power mode is realized through the coordinated operation of software and hardware. Before entering low power mode, the CPU completes data backup, command processing and other preparation work to avoid data loss and command abnormality. The power management unit is responsible for the overall control of the power supply and clock of each unit component, and can dynamically adjust the low power process according to the DEVSLP signal level. When exiting, the system can quickly resume normal operation, which improves the flexibility and reliability of low power control. Attached Figure Description

[0028] Figure 1 This is a schematic diagram showing the connection relationship of each unit in the low-power management device of the SATA controller of the present invention;

[0029] Figure 2 This is a schematic diagram of the DEVSLP low-power mode entry process of the present invention;

[0030] Figure 3 This is a schematic diagram of the DEVSLP low-power mode exit process of the present invention. Detailed Implementation

[0031] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] See Figures 1-3 The present invention provides a technical solution:

[0033] Example 1: A low-power management device for a SATA controller, such as Figure 1 As shown, integrated into the SoC chip, it includes a SATA physical layer unit, a SATA control unit, a crystal clock unit, a clock gating unit, a phase-locked loop unit, a power management unit, and a configuration register unit, wherein:

[0034] The SATA physical layer unit is used to implement the SATA physical layer protocol functions. The SATA physical layer unit connects to the host's SATA interface via the SATA_IF interface to achieve signal interaction with the host. Internally, it connects to the SATA control unit to complete data transmission between the physical layer and the upper protocol layer.

[0035] The SATA control unit is connected to the SATA physical layer unit and is physically integrated through a shared independent power domain E1. It is used to implement the link layer, transport layer, and command layer functions above the SATA protocol physical layer. Furthermore, the SoC chip also includes a CPU, DDR, and on-chip cache. The SATA control unit is also used to interact with the CPU, DDR, and on-chip cache at the command layer, respectively implementing SATA command parsing, DMA command transmission, and IO data read / write functions. Simultaneously, the SATA control unit also interacts bidirectionally with the configuration register unit. On the one hand, it obtains the register values ​​of relevant CPU configuration signals from the configuration register unit; on the other hand, it feeds back its own controller status results to the configuration register unit, facilitating real-time monitoring of the controller's operating status by the CPU, such as idle, busy, or error status.

[0036] The SATA control unit and the SATA physical layer unit are physically integrated by sharing an independent power domain E1. The core advantage of this design is that when the DEVSLP signal is high, the power management unit can directly cut off the power to both of them, causing the two core components to stop working at the same time, thereby minimizing the power consumption of the SATA controller and ensuring that the chip enters the lowest power consumption state.

[0037] The crystal clock unit receives the ref_clk clock signal input to the SoC chip and inputs it to the phase-locked loop unit and clock gating unit, providing basic clock support for the operation of the entire SoC chip and its various units. In low-power mode, the crystal clock unit can be turned off according to the control instructions of the power management unit, further reducing the power consumption of the clock module.

[0038] The clock gating unit is used to turn on and off the ref_clk clock signal input to the SATA physical layer unit, and its control signal comes from the configuration register of the configuration register unit.

[0039] The ref_clk clock signal is input to the SATA physical layer unit as a reference clock required for the SATA physical layer unit to operate. The activation and deactivation of the reference clock are controlled by the clock gating unit according to low-power control requirements. When entering low-power mode, the clock gating unit deactivates the clock according to the control signal, causing the SATA physical layer unit to stop clock supply and enter a low-power state; when exiting low-power mode, the clock gating unit activates the clock, allowing the SATA physical layer unit to resume normal operation.

[0040] The phase-locked loop unit is used to multiply the ref_clk clock input from the crystal oscillator clock unit to different frequencies required by each unit of the SoC. In low-power mode, the power management component can control the phase-locked loop component to shut down, stop the clock multiplication operation, and reduce the power consumption of the phase-locked loop module.

[0041] The power management unit receives the deep sleep signal DEVSLP sent by the host and performs debouncing to avoid low-power control malfunctions caused by signal jitter. It also controls the on / off of various power domains of the SoC chip, the on / off of the phase-locked loop unit and crystal clock unit when entering and exiting low-power mode, and the shutdown of the SATA physical layer unit input clock. When the deep sleep signal DEVSLP is high, the power management unit also cuts off the power to the independent power domain E1 to achieve low-power control.

[0042] The configuration register unit is used to receive the configuration values ​​of each register from the CPU and transmit them to the clock gating unit, the crystal clock unit, the power management unit, the SATA physical layer unit, and the SATA control unit. At the same time, it receives the status information of the above units and stores it in the corresponding registers.

[0043] Example 2: A low-power management method for a SATA controller, applied in the aforementioned low-power management device for a SATA controller, such as... Figure 2 As shown, the method includes:

[0044] The host pulls the DEVSLP deep sleep signal high to enable the device to enter the DEVSLP low-power state; the DEVSLP deep sleep signal is a high active signal and requires both the host and the device to support the DEVSLP function to be effective.

[0045] When the CPU receives a DEVSLP high interrupt, it stops receiving SATA commands, discards unexecuted SATA commands, processes and waits for the currently executing SATA commands to complete, in order to avoid data loss or command execution errors.

[0046] The CPU performs preparatory work before power failure, including data flashing to flash memory, table updates, SATA register backup, DDR register backup, and firmware variable backup, to ensure that data is not lost after power failure and subsequent recovery work can proceed normally.

[0047] After completing the preparations before the power outage, the CPU configures the devslp_start register of the power management unit to a high level, starts the power management unit to enable the DEVSLP low-power process, and the CPU enters the interrupt waiting state, pausing its own work to reduce power consumption.

[0048] The power management unit determines whether the current DEVSLP signal is high. If it is low, it means that it is not necessary to enter the DEVSLP state at present, the low-power process ends, and the CPU receives the DEVSLP interrupt to exit the low-power process.

[0049] If the current DEVSLP signal is high, the low-power process is started. The power management unit outputs control signals to turn off the clock of the CPU and SATA physical layer units and reset them, turn on the isolation control signals of each power domain to isolate each power domain, turn off the power of each power domain of the SoC chip, turn off the phase-locked loop unit and the crystal clock unit, and the device enters the DEVSLP low-power state.

[0050] In this embodiment, the DEVSLP low-power mode exit process is as follows: Figure 3 As shown, the process includes: when the host needs the device to exit low-power mode, it pulls the deep sleep signal DEVSLP low. After the power management unit detects the change in the deep sleep signal DEVSLP, it immediately exits its own DEVSLP low-power state and sequentially starts the crystal clock unit and the phase-locked loop unit to restore the clock supply. Subsequently, the power management component turns on the power of each power domain, turns off the isolation control signal of each power domain, restores the normal connection of each power domain, starts the clock of the CPU and SATA physical layer unit, and resets the relevant modules to restore each module to normal operation. The CPU wakes up from the interrupt waiting state, reads the previously backed-up register data and firmware variables, restores the normal operating state of the system, and simultaneously resumes receiving and executing SATA commands, and the device returns to normal operating mode.

[0051] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A low-power management device for a SATA controller, characterized in that, Integrated into the SoC chip, it includes a SATA physical layer unit, a SATA control unit, a crystal clock unit, a clock gating unit, a phase-locked loop unit, a power management unit, and a configuration register unit, among which: The SATA physical layer unit is used to implement the SATA physical layer protocol functions; The SATA control unit is connected to the SATA physical layer unit and is physically integrated by sharing an independent power domain E1. It is used to implement the link layer, transport layer and command layer functions above the physical layer of the SATA protocol. The crystal clock unit is used to receive the ref_clk clock signal input to the SoC chip and input it to the phase-locked loop unit and the clock gating unit; The clock gating unit is used to turn on and off the ref_clk clock signal input to the SATA physical layer unit, and its control signal comes from the configuration register of the configuration register unit. The phase-locked loop unit is used to multiply the ref_clk clock input from the crystal oscillator clock unit to different frequencies required by each unit of the SoC. The power management unit is used to receive the deep sleep signal DEVSLP sent by the host and perform debouncing processing, control the opening and closing of each power domain of the SoC chip, the opening and closing of the phase-locked loop unit and the crystal clock unit when entering and exiting low power mode, and the closing of the input clock of the SATA physical layer unit; when the deep sleep signal DEVSLP is high, the power management unit is also used to cut off the power of the independent power domain E1 to achieve low power control. The configuration register unit is used to receive the configuration values ​​of each register from the CPU and transmit them to the clock gating unit, the crystal clock unit, the power management unit, the SATA physical layer unit, and the SATA control unit. At the same time, it receives the status information of the above units and stores it in the corresponding registers.

2. The low-power management device for a SATA controller according to claim 1, characterized in that: The SATA physical layer unit is connected to the host SATA interface via the SATA_IF interface.

3. The low-power management device for a SATA controller according to claim 1, characterized in that: The ref_clk clock signal is input to the SATA physical layer unit as a reference clock required for the operation of the SATA physical layer unit. The opening and closing of the reference clock is controlled by the clock gating unit according to the low power control requirements.

4. The low-power management device for a SATA controller according to claim 1, characterized in that: The SoC chip also includes a CPU, DDR, and on-chip cache. The SATA control unit is also used to interact with the CPU, DDR, and on-chip cache at the command layer to realize the parsing of SATA commands, the transmission of DMA commands, and the reading and writing of IO data, respectively.

5. A low-power management method for a SATA controller, characterized in that: Applied in the low-power management device for a SATA controller as described in any one of claims 1 to 4, the method includes: The host pulls the DEVSLP deep sleep signal high, enabling the device to enter the DEVSLP low-power state. When the CPU receives a DEVSLP high interrupt, it stops receiving SATA commands, discards unexecuted SATA commands, processes and waits for the currently executing SATA commands to complete. The CPU performs preparatory work before power failure, including data being flashed to flash memory, table entries being updated, register backups being made, and firmware variable backups being made. After completing the preparations before the power outage, the CPU configures the devslp_start register of the power management unit to a high level, starts the power management unit to enable the DEVSLP low-power process, and the CPU enters the interrupt waiting state. The power management unit determines whether the current DEVSLP signal is high. If it is low, it means that it is not necessary to enter the DEVSLP state at present, the low-power process ends, and the CPU receives the DEVSLP interrupt to exit the low-power process. If the current DEVSLP signal is high, the low-power process is started. The power management unit outputs control signals to turn off the clock of the CPU and SATA physical layer units and reset them, turn on the isolation control signals of each power domain to isolate each power domain, turn off the power of each power domain of the SoC chip, turn off the phase-locked loop unit and the crystal clock unit, and the device enters the DEVSLP low-power state.

6. The low-power management method for a SATA controller according to claim 5, characterized in that: Also includes: When the host needs the device to exit low power mode, it pulls the deep sleep signal DEVSLP low. After the power management component detects the change in the deep sleep signal DEVSLP, it immediately exits its own DEVSLP low power state and sequentially starts the crystal clock unit and phase-locked loop unit to restore the clock supply. Subsequently, the power management component turns on the power of each power domain, turns off the isolation control signal of each power domain, restores the normal connection of each power domain, starts the clock of the CPU and SATA physical layer unit, and resets the relevant modules to restore each module to normal operation. The CPU wakes up from the interrupt waiting state, reads the previously backed-up register data and firmware variables, restores the normal working state of the system, and resumes receiving and executing SATA commands, and the device resumes normal working mode.

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