A communication device, method, electronic device, storage medium, and program

Abstract

Embodiments of the present application disclose a communication device, method, electronic equipment, storage medium and program. The communication device is integrated in a processor and is configured to receive a current instruction and determine an instruction type of the current instruction; in a case where the instruction type of the current instruction is determined to be a non-aligned instruction, send the current instruction to a lower module for a subsequent instruction processing flow; in a case where the instruction type of the current instruction is determined to be an aligned instruction, obtain an instruction execution result of a preceding target associated instruction of the current instruction, and in a case where the instruction execution results of the preceding target associated instruction of the current instruction are all determined to be execution completed, execute an aligned instruction processing flow of the current instruction. The technical scheme of the embodiments of the present application can efficiently ensure that the instructions are completed in order, reduce the delay of instruction in-order processing, and thus improve the overall communication performance.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of communication technologies, and in particular, to a communication device, method, electronic device, storage medium, and program. Background Art

[0002] Processing instructions in order is the core foundation for ensuring the integrity of communication data and the accuracy of semantics. In data communication, if instructions or data are not processed in the established order, the information restored at the receiving end may deviate severely, resulting in system misjudgment or functional abnormalities. For example, in serial transmission, data is sent bit by bit, and the receiving end must strictly reorganize the bit stream in the sending order; otherwise, the meaning of a "word" will change, just like misspelling "hello" as "olleh". Therefore, in communication scenarios, how to implement the instruction order-preserving function is particularly important.

[0003] Currently, when performing order-preserving processing on instructions in the existing communication field, an approach of adding extra software instructions is often adopted. For example, when the previous instruction is a write data instruction, to ensure that the content carried by the write instruction reaches its destination, an extra read data instruction needs to be added after the write instruction. The read data instruction reads the written data from the destination address corresponding to the write data to ensure that after the data is successfully written, other instructions are then executed in sequence.

[0004] In the process of implementing the present invention, the inventors found that the existing technology has the following defects: in practical applications, it may involve adding extra software instructions for order-preserving processing multiple times. And each extra software instruction added may need to serially execute a series of operations correspondingly, so a relatively large delay will be generated, thus seriously affecting the overall communication performance. Summary of the Invention

[0005] Embodiments of the present invention provide a communication device, method, electronic device, storage medium, and program, which can efficiently ensure that instructions are completed in order, reduce the delay of instruction order-preserving processing, and further improve the overall communication performance.

[0006] According to one aspect of the present invention, a communication device is provided. The communication device is integrated in a processor and is used for: Receiving a current instruction and determining the instruction type of the current instruction; When it is determined that the instruction type of the current instruction is a non-aligned instruction, sending the current instruction to a lower-level module for subsequent instruction processing procedures; When it is determined that the instruction type of the current instruction is an aligned instruction, obtaining the instruction execution result of the previous target-related instruction of the current instruction, and when it is determined that the instruction execution results of the previous target-related instructions of the current instruction are all executed and completed, performing the aligned instruction processing procedure of the current instruction.

[0007] According to another aspect of the present invention, a communication method is provided, applied to the communication apparatus described in the first aspect, the method comprising: Receive the current instruction and determine the instruction type of the current instruction; If it is determined that the instruction type of the current instruction is an unaligned instruction, the current instruction is sent to the next-level module for subsequent instruction processing. If the instruction type of the current instruction is determined to be an alignment instruction, the execution result of the preceding target associated instruction of the current instruction is obtained, and if the execution result of the preceding target associated instruction of the current instruction is determined to be completed, the alignment instruction processing flow of the current instruction is executed.

[0008] According to another aspect of the present invention, an electronic device is provided, the electronic device including at least one processor, the processor including the communication device described in the first aspect.

[0009] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the communication method described in any embodiment of the present invention.

[0010] According to another aspect of the present invention, a computer program product is also provided, comprising a computer program that, when executed by a processor, implements the communication method described in any embodiment of the present invention.

[0011] This invention addresses the problems of high latency and low performance in existing instruction order preservation methods by configuring a communication device within the processor. This device receives the current instruction and determines its type. If the instruction type is determined to be an unaligned instruction, it sends the instruction to a lower-level module for subsequent instruction processing. If the instruction type is determined to be an aligned instruction, it obtains the execution results of the preceding target related instructions. If the execution results of all preceding target related instructions are confirmed to be complete, it executes the aligned instruction processing flow. This solves the problems of high latency and low performance in existing instruction order preservation methods, efficiently ensuring that instructions are completed in order, reducing the latency of instruction order preservation processing, and thus improving overall communication performance.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the structure of a communication device provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the structure of a communication device provided in Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure of a communication device provided in Embodiment 3 of the present invention; Figure 4 This is a schematic diagram of the internal structure of a second judgment module provided in Embodiment 3 of the present invention; Figure 5 This is a schematic diagram of the structure of an instruction response counter provided in Embodiment 3 of the present invention; Figure 6 This is a schematic diagram of the overall working process of a communication device provided in Embodiment 3 of the present invention; Figure 7 This is a schematic diagram of the operation flow of the sending end in a typical RDMA data transfer process in existing technology; Figure 8 This is a schematic diagram of the receiving end's operation flow in a typical RDMA data transfer process in existing technology; Figure 9 This is a flowchart of RDMA data processing at the receiving end of an integrated communication device in a GDR process provided by an embodiment of the present invention; Figure 10 This is a flowchart illustrating the interaction between various programs and network cards in the existing GDR process. Figure 11 This is a flowchart illustrating the interaction between various programs and network cards in a GDR (Global Dedicated Line) configured with a communication device, provided by an embodiment of the present invention. Figure 12 This is a flowchart of RDMA data processing at the receiving end of an integrated communication device in a GDA process provided by an embodiment of the present invention; Figure 13 This is a flowchart of a communication method provided in Embodiment 4 of the present invention; Figure 14 This is a schematic diagram of the structure of an electronic device provided in Embodiment 5 of the present invention. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0016] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0017] Example 1 Figure 1 This is a schematic diagram of the structure of a communication device provided in Embodiment 1 of the present invention, as shown below. Figure 1 As shown, Embodiment 1 of the present invention provides a communication device 10. Optionally, the communication device 10 can be integrated into a processor and is used for: receiving a current instruction and determining the instruction type of the current instruction; if the instruction type of the current instruction is determined to be a non-aligned instruction, sending the current instruction to a lower-level module for subsequent instruction processing; if the instruction type of the current instruction is determined to be an aligned instruction, obtaining the instruction execution results of the preceding target associated instructions of the current instruction, and if the instruction execution results of the preceding target associated instructions of the current instruction are all completed, executing the aligned instruction processing flow of the current instruction.

[0018] The current instruction can be any instruction that the processor needs to process, such as a read instruction, a write instruction, or any other type of instruction. This embodiment of the invention does not limit the type of the current instruction. Unaligned instructions can be instructions that do not require processing. Aligned instructions can be instructions that require processing. Alignment processing can be understood as executing the specific instruction operation of the alignment instruction after all preceding instructions have been completed in sequence. The preceding target-associated instruction can be an instruction issued before the current instruction.

[0019] In this embodiment of the invention, the communication device 10 can be a hardware module for processing instructions. This hardware module can be integrated inside a processor, specifically within a GPU (Graphics Processing Unit) or NPU (Neural Network Processing Unit) or other device-level processors. Accordingly, for a processor integrating the communication device 10, all instructions requiring processor processing can be received and processed through the communication device 10. During instruction processing, the communication device 10 can receive each instruction and determine its instruction type in real time for each received instruction. If the communication device 10 determines that the instruction type is an unaligned instruction, indicating that the instruction does not require alignment processing, it can directly send the instruction to the next-level module for subsequent instruction processing. It is understood that different instructions will result in different types of instructions being sent to the next-level module. If the communication device 10 determines that the instruction type of the current instruction is an alignment instruction, indicating that the current instruction needs alignment processing, the communication device 10 can obtain the instruction execution results of the preceding target related instructions of the current instruction and determine whether the instruction execution results of the preceding target related instructions of the current instruction are all completed. If it is determined that the instruction execution results of the preceding target related instructions of the current instruction are all completed, it indicates that the preceding target related instructions have been completed in sequence, and subsequent instructions can continue to be processed. At this time, the communication device 10 can execute the alignment instruction processing flow according to the instruction content of the alignment instruction itself.

[0020] Optionally, alignment instructions can be write instructions, read instructions, or atomic operation instructions, and can be a single instruction or a set of multiple instructions. Correspondingly, the destination address of the alignment instruction can be configured within the module that processes the alignment instruction (i.e., the communication device), or it can be configured in the address space of a lower-level module of the module that processes the alignment instruction. If the destination address of the alignment instruction is configured within the module that processes the alignment instruction, then a corresponding address space needs to be pre-allocated for the module that processes the alignment instruction when designing the chip address mapping scheme. The module that processes the alignment instruction must be able to process instructions falling within its internal address space.

[0021] This invention addresses the problems of high latency and low performance in existing instruction order preservation methods by configuring a communication device within the processor. This device receives the current instruction and determines its type. If the instruction type is determined to be an unaligned instruction, it sends the instruction to a lower-level module for subsequent instruction processing. If the instruction type is determined to be an aligned instruction, it obtains the execution results of the preceding target related instructions. If the execution results of all preceding target related instructions are confirmed to be complete, it executes the aligned instruction processing flow. This solves the problems of high latency and low performance in existing instruction order preservation methods, efficiently ensuring that instructions are completed in order, reducing the latency of instruction order preservation processing, and thus improving overall communication performance.

[0022] Example 2 Figure 2 This is a schematic diagram of the structure of a communication device provided in Embodiment 2 of the present invention, as shown below. Figure 2 As shown, the communication device 10 includes a first judgment module 110, a second judgment module 120, and an instruction processing module 130, wherein: The first judgment module 110 is communicatively connected to the second judgment module 120. It is used to receive the current instruction, determine the instruction processing mode of the current instruction according to the current instruction processing flag status, and send the current instruction to the second judgment module 120 if the instruction processing mode of the current instruction is determined to be the lower-level transmission processing mode. The second judgment module 120 is communicatively connected to the instruction processing module 130. It is used to determine the instruction type of the current instruction, generate a target instruction identification flag according to the instruction type of the current instruction, and send the current instruction and the target instruction identification flag of the current instruction to the instruction processing module 130. The instruction processing module 130 is used to send the current instruction to the lower-level module for subsequent instruction processing when the instruction type of the current instruction is determined to be an unaligned instruction based on the target instruction identification flag of the current instruction; when the instruction type of the current instruction is determined to be an aligned instruction based on the target instruction identification flag of the current instruction, it obtains the instruction execution results of the preceding target related instructions of the current instruction, and executes the aligned instruction processing flow of the current instruction when it is determined that the instruction execution results of the preceding target related instructions of the current instruction are all completed.

[0023] The current instruction processing flag is used to determine whether processing of the current instruction is permitted. The next-level transmission processing mode can be set to allow continued processing of the current instruction. The target instruction identification flag can be used to identify whether the current instruction is an alignment instruction.

[0024] Specifically, the communication device 10 may include a first judgment module 110, a second judgment module 120, and an instruction processing module 130. The first judgment module 110 internally maintains information about the current instruction processing flag state and determines whether to send the current instruction to the second judgment module 120 based on the current instruction processing flag state. When the first judgment module 110 receives the current instruction, it determines the instruction processing method of the current instruction based on the current instruction processing flag state. Different values ​​of the current instruction processing flag state indicate different instruction processing methods. For example, when the current instruction processing flag state value is 0, it indicates that the instruction processing method of the current instruction is prohibited, and processing of the current instruction is not allowed; when the current instruction processing flag state value is 1, it indicates that the instruction processing method of the current instruction is a lower-level transmission processing method, that is, the current instruction is allowed to be transmitted to a lower-level module for processing. Accordingly, if the first judgment module 110 determines that the instruction processing method of the current instruction is a lower-level transmission processing method, it can send the current instruction to the second judgment module 120. If the first judgment module 110 determines that the instruction processing mode of the current instruction is the prohibited processing mode, it can prevent the current instruction from being sent to the second judgment module 120 until it determines that the instruction processing mode of the current instruction is the lower-level transmission processing mode, at which point the current instruction will be sent to the second judgment module 120.

[0025] After receiving the current instruction sent by the first judgment module 110, the second judgment module 120 determines the type of the current instruction and generates a target instruction identification flag based on the instruction type. Optionally, the value of the target instruction identification flag differs depending on the instruction type of the current instruction. For example, when the current instruction is an alignment instruction, the value of the target instruction identification flag can be 1; when the current instruction is a non-alignment instruction, the value of the target instruction identification flag can be 0. Further, the second judgment module 120 sends the current instruction and the target instruction identification flag of the current instruction to the instruction processing module 130 for further processing. That is, the second judgment module 120 is mainly used to determine whether the current instruction is an alignment instruction.

[0026] The instruction processing module 130 can receive the current instruction and the target instruction identification flag of the current instruction sent by the second judgment module 120. Based on the target instruction identification flag, it analyzes the current instruction to determine its type. If the instruction processing module 130 determines that the current instruction is a non-aligned instruction, it can directly send the preceding instruction to the corresponding lower-level module for subsequent instruction processing. If the instruction processing module 130 determines that the current instruction is an aligned instruction, it can obtain the execution results of the preceding target related instructions. If the instruction processing module 130 determines that the execution results of all preceding target related instructions of the current instruction are complete, it executes the aligned instruction processing flow for the current instruction. If the instruction processing module 130 determines that the execution results of not all preceding target related instructions of the current instruction are complete, it prohibits the execution of the aligned instruction processing flow for the current instruction until it determines that the execution results of all preceding target related instructions of the current instruction are complete.

[0027] This invention provides a communication device constructed using a first judgment module, a second judgment module, and an instruction processing module. The first judgment module receives a current instruction, determines its processing method based on the current instruction processing flag, and sends the instruction to the second judgment module if the processing method is determined to be a lower-level transmission processing method. The second judgment module determines the instruction type of the current instruction and generates a target instruction identification flag based on the instruction type. The current instruction and the target instruction identification flag are then sent to the instruction processing module. The instruction processing module determines the instruction type of the current instruction based on the target instruction identification flag. If the instruction type is determined to be a non-aligned instruction, the current instruction is sent to a lower-level module for subsequent instruction processing. If the instruction type is determined to be an aligned instruction based on the target instruction identification flag, the module obtains the execution results of the preceding target related instructions. If the execution results of all preceding target related instructions are completed, the module executes the aligned instruction processing flow for the current instruction. The aforementioned communication device can solve the problems of large delay and low performance of existing instruction order preservation methods, and can efficiently ensure that instructions are completed in order, reduce the delay of instruction order preservation processing, and thus improve the overall communication performance.

[0028] Example 3 Figure 3 This is a schematic diagram of a communication device provided in Embodiment 3 of the present invention. The embodiments of the present invention are based on the above embodiments and are further specified, such as... Figure 3As shown, the instruction processing module 130 of the communication device 10 includes a request distribution and response module 131, a lower-level transmission module 132, and an alignment instruction processing module 133. The request distribution and response module 131 is communicatively connected to the lower-level transmission module 132 and to the alignment instruction processing module 133, wherein: The request distribution response module 131 is used to determine the instruction type of the current instruction based on the target instruction identification flag of the current instruction. If the instruction type of the current instruction is determined to be the non-aligned instruction, the current instruction is sent to the lower-level transmission module 132; if the instruction type of the current instruction is determined to be the aligned instruction, the current instruction is sent to the alignment instruction processing module 133. The request distribution response module 131 is also used to receive response information from the lower-level transmission module 132 and the alignment instruction processing module 133, and send the response information to the upper-level module. The lower-level transmission module 132 is used to send the unaligned instruction to the target lower-level module for subsequent instruction processing; the lower-level transmission module 132 is also used to send the response information returned by the lower level to the request distribution response module 131; The alignment instruction processing module 133 is used to update the current instruction processing flag status of the instruction flag hardware status register to the alignment status value after receiving the alignment instruction, and process the alignment instruction if it is determined that the instruction execution results of the preceding target associated instructions of the current instruction are all completed; after determining that the alignment instruction processing is completed, update the current instruction processing flag status of the instruction flag hardware status register to the non-alignment status value, and send the alignment instruction processing result response information to the request dispatch response module 131.

[0029] The target lower-level module can be a module capable of processing unaligned instructions. An alignment status value indicates that the current instruction processing flag should be disabled. An unaligned status value indicates that the current instruction processing flag can continue processing.

[0030] Specifically, the request distribution response module 131 determines the instruction type of the current instruction based on the target instruction identification flag. If the instruction type is determined to be a non-aligned instruction, instruction distribution can proceed, sending the current instruction to the lower-level transmission module. If the instruction type is determined to be an aligned instruction, the current instruction is sent to the alignment instruction processing module 133 for processing. Simultaneously, the request distribution response module 131 can also receive response information from the lower-level transmission module 132 and the alignment instruction processing module 133, arbitrate the received response information to obtain a single response, and send it to the upper-level module.

[0031] The lower-level transmission module 132 sends the unaligned instruction to the target lower-level module for subsequent instruction processing. The type of the target lower-level module may differ depending on the content of the unaligned instruction. Simultaneously, the lower-level transmission module 132 can also receive response information returned by the lower-level module and send the response information to the request distribution response module 131.

[0032] The first judgment module 110 is internally configured with an instruction flag hardware status register, which is used to update the status value according to the status update indication information output by the instruction processing module. This status value can determine the current instruction processing flag status of the current instruction. After receiving the alignment instruction, the alignment instruction processing module 133 updates the status value of the instruction flag hardware status register to the alignment status value. For example, the status value of the instruction flag hardware status register can be updated to 0 to prohibit the processing of subsequent instructions. Thus, when a subsequent instruction is issued as the current instruction to the first judgment module 110, since the status value of the instruction flag hardware status register is the alignment status value, the subsequent updated current instruction needs to be prohibited from processing. At the same time, the alignment instruction processing module 133 determines whether the execution results of the preceding target related instructions of the current instruction have all been completed. If it is determined that the preceding target related instructions have all been completed, the alignment instruction can continue to be processed; if it is determined that the preceding target related instructions have not all been completed, the alignment instruction is prohibited from being processed. After processing the alignment instruction, the alignment instruction processing module 133 can update the status value of the instruction flag hardware status register to a non-aligned status value. For example, it can update the status value of the instruction flag hardware status register to 1 to indicate that subsequent instructions can continue to be processed. The alignment instruction processing module 133 can also send response information of the alignment instruction processing result to the request distribution response module 131. It should be noted that the alignment instruction is not transmitted further after it is sent to the alignment instruction processing module 133.

[0033] Optionally, the first judgment module 110 may include a judgment submodule and an instruction flag hardware status register ( Figure 3 (Not shown in the diagram). The judgment submodule and the instruction flag hardware status register are communicatively connected, wherein: the judgment submodule is used to obtain the status value output by the instruction flag hardware status register, determine the current instruction processing flag status of the current instruction based on the status value, and determine the instruction processing mode of the current instruction based on the current instruction processing flag status. If the instruction processing mode of the current instruction is determined to be the lower-level transmission processing mode, the current instruction is sent to the second judgment module; the instruction flag hardware status register is used to update the status value according to the status update indication information output by the instruction processing module.

[0034] The judgment submodule is used to determine the instruction processing method and the timing of instruction dispatch for the current instruction. The status value of the instruction flag hardware status register can be used to determine the status of the current instruction processing flag.

[0035] Specifically, the first judgment module 110 can consist of a judgment submodule and an instruction flag hardware status register. After receiving the current instruction, the judgment submodule queries the status value output by the instruction flag hardware status register and determines the current instruction processing flag status based on the status value. For example, when the status value of the instruction flag hardware status register is 0, the current instruction processing flag status indicates that the instruction processing mode of the current instruction is disabled. When the status value of the instruction flag hardware status register is 1, the current instruction processing flag status indicates that the instruction processing mode of the current instruction is a lower-level transmission processing mode. When the judgment submodule determines that the instruction processing mode of the current instruction is a lower-level transmission processing mode based on the status value of the instruction flag hardware status register, it allows instruction distribution and sends the current instruction to the second judgment module. The instruction flag hardware status register updates its status value according to the status update indication information output by the instruction processing module; for example, it can update its status value based on the status update indication information sent by the instruction processing module 133. For example, when the status update indication information sent by the alignment instruction processing module 133 is an aligned status value, the instruction flag hardware status register updates the status value to 0; when the status update indication information sent by the alignment instruction processing module 133 is an unaligned status value, the instruction flag hardware status register updates the status value to 1. The initial status value of the instruction flag hardware status register can be 1.

[0036] In an optional embodiment of the present invention, the second determination module 120 includes an instruction operation type register, an opcode determination submodule, a destination address determination submodule, a destination address register, and an instruction flag generation submodule; the instruction operation type register and the opcode determination submodule are communicatively connected, the destination address determination submodule and the destination address register are communicatively connected, and the opcode determination submodule and the destination address determination submodule are also communicatively connected to the instruction flag generation submodule, wherein: the instruction operation type register is used to store the operation type of the aligned instruction; the opcode determination submodule is used to compare the operation type of the current instruction with the operation type of the aligned instruction stored in the instruction operation type register to obtain... The current instruction's operation type comparison result is obtained; the destination address register stores the destination address of the alignment instruction; the destination address judgment submodule compares the destination address of the current instruction with the destination address of the alignment instruction stored in the destination address register to obtain the current instruction's destination address comparison result; the instruction flag generation submodule obtains the current instruction's operation type comparison result and destination address comparison result, and generates an alignment instruction's instruction identification flag if both the operation type comparison result and the destination address comparison result are successfully compared; if the operation type comparison result and / or the destination address comparison result fail to compare, it generates a non-aligned instruction's instruction identification flag.

[0037] The instruction identification flag is used to identify the type of instruction. For example, the instruction identification flag for an aligned instruction can be 1, while the instruction identification flag for an unaligned instruction can be 0.

[0038] Figure 4 This is a schematic diagram of the internal structure of a second judgment module provided in Embodiment 3 of the present invention. In a specific example, such as Figure 4As shown, the second judgment module can be composed of an instruction operation type register, an opcode judgment submodule, a destination address judgment submodule, a destination address register, and an instruction flag generation submodule. The instruction operation type register stores the operation type of the aligned instruction, and the destination address register stores the destination address of the aligned instruction. After receiving the current instruction, the second judgment module parses the operation type and destination address of the current instruction. The opcode judgment submodule compares the operation type of the current instruction with the operation type of the aligned instruction stored in the instruction operation type register to obtain the operation type comparison result. The destination address judgment submodule compares the destination address of the current instruction with the destination address of the aligned instruction stored in the destination address register to obtain the destination address comparison result. The instruction flag generation submodule obtains the operation type comparison result and the destination address comparison result of the current instruction. If both the operation type comparison result and the destination address comparison result are successful, such as if the current instruction is a write instruction falling within the preset aligned instruction address space, it indicates that the current instruction is an aligned instruction, and an aligned instruction instruction identification flag can be generated. If any one or more of the operation type comparison result and the destination address comparison result fail, it indicates that the current instruction is an unaligned instruction, and an unaligned instruction instruction identification flag can be generated.

[0039] Optionally, the instruction operation type register and destination address register can be statically configured and remain unchanged during operation.

[0040] In an optional embodiment of the present invention, the lower-level transmission module 132 may further be configured with an instruction response counter; the instruction response counter may be used to: update the instruction count value in real time according to the instruction uplink and downlink transmission streams; the alignment instruction processing module may further be used to: obtain the current instruction count value; if the current instruction count value is determined to be a set value, determine that the instruction execution results of the preceding target associated instructions of the current instruction are all completed, and process the alignment instruction according to the alignment instruction processing rules; if the current instruction count value is determined to be a non-set value, wait for the current instruction count value to be updated to the set value, and then process the alignment instruction according to the alignment instruction processing rules.

[0041] Optionally, an instruction response counter can be configured in the lower-level transmission module. This instruction response counter can update the instruction count value in real time according to the instruction uplink and downlink transmission streams. Figure 5 This is a schematic diagram of the structure of an instruction response counter provided in Embodiment 3 of the present invention. For example, as shown... Figure 5 As shown, when the lower-level transmission module sends out an instruction, the value of the instruction response counter is incremented by 1; when the lower-level transmission module receives a response from the lower level, the value of the instruction response counter is decremented by 1; when both occur simultaneously, the value of the instruction response counter remains unchanged.

[0042] Correspondingly, the alignment instruction processing module in the instruction processing unit can obtain the current instruction count value of the instruction response counter. If the current instruction count value is determined to be a set value, such as 0, it can be determined that the execution results of the preceding target related instructions of the current instruction have all been completed. At this time, the alignment instruction processing module can process the alignment instruction according to the alignment instruction processing rules. If the current instruction count value is determined to be a non-set value, such as a non-zero value, it can be determined that the execution results of the preceding target related instructions of the current instruction have not all been completed. At this time, the alignment instruction processing module performs a waiting operation, and after determining that the current instruction count value has been updated to the set value, it processes the alignment instruction according to the alignment instruction processing rules. Processing the alignment instruction according to the alignment instruction processing rules can, for example, involve performing a read operation or a write operation at the destination address of the instruction.

[0043] Figure 6 This is a schematic diagram of the overall workflow of a communication device provided in Embodiment 3 of the present invention. In a specific example, such as Figure 6 As shown, the overall workflow of the above communication device can be as follows: (1) The upper-level module issues an instruction, and the communication device receives the current instruction through the first judgment module.

[0044] (2) The judgment submodule in the first judgment module obtains the status value output by the instruction flag hardware status register, determines the current instruction processing flag status of the current instruction based on the status value, and determines the instruction processing mode of the current instruction based on the current instruction processing flag status. When it is determined that the instruction processing mode of the current instruction is the lower level transmission processing mode, that is, when it is allowed to process the instruction input from the upper level, the current instruction is sent to the second judgment module.

[0045] (3) After receiving the current instruction, the second judgment module parses the operation type and destination address of the current instruction. The internal opcode judgment submodule compares the operation type of the current instruction with the operation type of the aligned instruction stored in the instruction operation type register to obtain the operation type comparison result. The destination address judgment submodule compares the destination address of the current instruction with the destination address of the aligned instruction stored in the destination address register to obtain the destination address comparison result. The instruction flag generation submodule of the second judgment module obtains the operation type comparison result and the destination address comparison result of the current instruction. If both the operation type comparison result and the destination address comparison result are successful, it indicates that the current instruction is an aligned instruction, and an instruction identification flag for aligned instructions can be generated. If any one or more of the operation type comparison result and the destination address comparison result fail, it indicates that the current instruction is an unaligned instruction, and an instruction identification flag for unaligned instructions can be generated. The second judgment module simultaneously sends the current instruction and the target instruction identification flag of the current instruction to the request-dispatch-response module.

[0046] (4) The request distribution and response module performs instruction distribution and response merging processing based on the target instruction identification flag input by the superior module along with the instruction. If the current instruction is an alignment instruction, it is transmitted to the lower-level alignment instruction processing module for processing; if the current instruction is not an alignment instruction, it is distributed to the lower-level transmission module for processing. For instruction responses in the opposite direction, the request distribution and response module arbitrates the responses from the lower-level transmission module and the alignment instruction processing module to obtain a single response, which is then transmitted to the superior module.

[0047] (5) If the current instruction is an unaligned instruction, the lower-level transmission module will send the received unaligned instruction to the corresponding lower-level module for subsequent instruction processing. The lower-level transmission module can also send the response information returned by the lower level to the request distribution response module. The lower-level transmission module is also configured with an instruction response counter to update the instruction count value in real time according to the instruction uplink and downlink transmission streams. The initial value of the instruction response counter is 0; the value of the instruction response counter is incremented by 1 for each instruction sent down by the lower-level transmission module; the value of the instruction response counter is decremented by 1 for each response returned by the lower level; when both occur simultaneously, the value of the instruction response counter remains unchanged. The value of the instruction response counter is used by the alignment instruction processing module.

[0048] (6) If the current instruction is an alignment instruction, the alignment instruction processing module, upon receiving the alignment instruction, updates the current instruction processing flag status in the instruction flag hardware status register to the alignment status value, such as updating it to 0, and obtains the current instruction count value from the instruction response counter in the lower-level transmission module. If the alignment instruction processing module determines that the current instruction count value is a set value, such as the current instruction count value being 0, it can determine that the instruction execution results of the preceding target associated instructions of the current instruction are all completed, and the alignment instruction can be processed according to the alignment instruction processing rules. If the alignment instruction processing module determines that the current instruction count value is not a set value, it can wait until the current instruction count value is updated to the set value before processing the alignment instruction according to the alignment instruction processing rules. After the alignment instruction processing module completes the processing of the alignment instruction, it updates the current instruction processing flag status in the instruction flag hardware status register back to the non-aligned status value, such as updating it to 1, and sends the response information of the alignment instruction processing result to the request distribution response module.

[0049] The above technical solution constructs a communication device using a first judgment module, a second judgment module, a request dispatch response module, a lower-level transmission module, and an alignment instruction processing module. The first judgment module receives the current instruction and determines its current instruction processing flag status based on the status value output by the instruction flag hardware status register from the judgment submodule. If the current instruction's processing mode is determined to be lower-level transmission processing based on the current instruction processing flag status, the current instruction is sent to the second judgment module. The second judgment module determines the instruction type of the current instruction and generates a target instruction identification flag based on the instruction type. The current instruction and the target instruction identification flag are then sent to the request dispatch response module. The request dispatch response module determines the instruction type of the current instruction based on the target instruction identification flag. If the instruction type is determined to be a non-aligned instruction, the current instruction is sent to the lower-level transmission module; if the instruction type is determined to be an aligned instruction, the current instruction is sent to the alignment instruction processing module. The lower-level transmission module can then send non-aligned instructions to the target lower-level module for subsequent instruction processing. Upon receiving an alignment instruction, the alignment instruction processing module updates the current instruction processing flag status in the instruction flag hardware status register to the alignment status value. It then processes the alignment instruction only if it determines that the execution results of all preceding target related instructions of the current instruction have been completed. After processing the alignment instruction, the alignment instruction processing module updates the current instruction processing flag status in the instruction flag hardware status register to the unaligned status value to continue processing subsequent instructions. This communication device can solve the problems of large latency and low performance in existing instruction order-keeping methods, efficiently ensuring that instructions are completed in order, reducing the latency of instruction order-keeping processing, and thus improving overall communication performance.

[0050] Specific application scenarios In the current GDR (GPU Direct RDMA) or GDA (GPU DirectAsync) process, the processing of RDMA (Remote Direct Memory Access) data often involves frequent instruction execution flows. Figure 7 This is a schematic diagram of the operation flow of the sending end in a typical RDMA data transfer process in existing technology. Figure 8 This is a schematic diagram of the receiving end's operation flow in a typical RDMA data transfer process in existing technology. In a specific example, such as... Figure 7 and Figure 8 As shown, the RDMA data transfer process in the GDR procedure mainly includes the following operations: (1) The kernel of the sending GPU (GPU A) notifies the sending host (Host A): There is data that needs to be sent to the device memory of the receiving GPU (GPU B). The data to be sent can be located in the device memory of GPU A.

[0051] (2) Host A writes the corresponding RDMA WQE (Work Queue Element) into the SQ (Send Queue) of RDMAA. The SQ can be located in Host memory.

[0052] (3) After Host A confirms that WQE is written to SQ, it notifies the driver of the source RDMA network card (RDMA network card A) to perform RDMA operation through the Doorbell mechanism (such as writing to the register).

[0053] (4) RDMA network card A reads WQE from SQ and parses and executes it.

[0054] (5) RDMA network card A reads data Data from the corresponding storage (such as the device memory of GPU A).

[0055] (6) RDMA network card A writes the data it reads to the destination RDMA network card, i.e., RDMA network card B, through the RDMA switch.

[0056] (7) Prior to this, the receiving host (Host B) also writes the corresponding RDMA WQE into the RQ (Received Queue) of RDMA B; then notifies RDMA network card B through the doorbell mechanism; RDMA network card B reads the WQE from the RQ and parses and executes it. For the sake of simplicity, step 7 is not shown in the figure.

[0057] (8) RDMA network card B writes this data into the device memory of GPU B through devices such as PCIe (Peripheral Component Interconnect Express) Switch (PCIe hardware switching chip).

[0058] (9) RDM network card B reads the written data from the device memory of the target GPU (GPU B) to confirm that the data has been written to the device memory of the target GPU.

[0059] (10) The RDMA network card B writes the completion information into the CQ (Completion Queue), indicating that the data has been written to the destination address.

[0060] (11) Host B obtains information in CQ through program polling (reading) and other methods, and parses it to find out that the data has been written to the destination address.

[0061] (12) Host B, through a program and via a PCIe switch, notifies GPU B that the kernel data inside the GPU B has been written to the destination address. Specifically, the information is written to a specific memory address inside GPU B through a write operation.

[0062] (13) The kernel inside GPU B obtains information about the specific storage address inside GPU B through program polling (reading) and other methods, and parses it to know that the data has been written to the destination address.

[0063] (14) The kernel inside GPU B reads and uses the data at the destination address through the program.

[0064] In the above steps, step (9) is crucial. This is because although the write data in step (8) and the write completion information in step (10) both come from the write operation of the RDMA network card, their destinations are different: one is the CPU, and the other is the GPU. The paths through which the data flows in steps (8) and (10) are also different. Although for RDMA network card B, the write in step (8) occurs before the write in step (10), from the perspective of the entire architecture, it cannot be guaranteed that when the content carried by the write operation in step (8) arrives at its destination, the content carried by the write operation in step (10) has already arrived at its destination. Therefore, if the notification information arrives early, the GPU may directly read the address of the storage data, and the data read may still be old. Therefore, the prior art adds step (9), that is, adds an RDMA read operation to confirm that the data in step (8) has been written to the destination storage, and then executes step (10) to ensure that the above-mentioned out-of-order problem does not occur. Therefore, the RDMA read operation in step (9) is to ensure the order of data rather than to move data.

[0065] In practical applications, the application needs to schedule the RDMA network card to perform one or more additional RDMA read operations on the data (Data) written to the target GPU's device memory to ensure that the written data (Data) has been written to the target GPU's device memory. A single RDMA read operation to ensure instruction execution order typically includes the following RDMA serial execution steps: the application creates a corresponding WQE for the RDMA network card and fills it into the SQ; after agreed conditions are met, the application notifies the RDMA network card to retrieve the WQE content from the SQ via doorbell write or other methods; the RDMA network card reads the WQE content from the address stored in the SQ (e.g., in the CPU's host memory); the RDMA network card parses the obtained WQE content and performs the corresponding operations. RDMA read: Read data (Data) from the target GPU's device memory; after the RDMA network card completes the operations in the WQE, it writes the corresponding RDMA CQ to the CPU's host memory or the target GPU's device memory.

[0066] The purpose of the aforementioned RDMA read operation is to ensure that the RDMA write data has been written to the destination GPU's device memory before the network card writes the RDMA CQ to the CPU's host memory or the destination GPU's device memory. Performing a single RDMA read operation involves the CPU (application), the RDMA network card, the GPU, and the PCIe switch between them, resulting in a relatively long time (denoted as T0). Furthermore, current applications commonly have the RDMA network card perform several such RDMA read operations, further increasing the actual latency. This increased latency significantly impacts performance. For example, transferring 1MB of data at 200G line speed takes approximately 42µs; a single RDMA read operation (T0) typically takes 3µs, accounting for about 7% of the data transmission latency; if two RDMA read operations are used, this percentage reaches 14%, significantly reducing cluster performance. Moreover, in scenarios involving smaller data transfer volumes, the increased latency from the above approach is even greater.

[0067] In an optional embodiment of the present invention, the communication device can be applied in the GDR or GDA process to perform order-preserving processing of write data operations and CQ (Completion Queue) operations of the RDMA network card.

[0068] To enable the application of communication devices in GDR or GDA processes, the RDMA network card program block required by the current technology can be removed from the host CPU application (software). This block involves one or more RDMA read operations required for order preservation between the RDMA network card's WQE (Write-Queued Operation) to write data to the destination GPU and the WQE to write status back to the host or destination GPU. This eliminates the need for a complete set of RDMA serial operation steps required to execute this block. The removed RDMA serial operation steps mainly include: the application configuring the WQE to the SQ (Session Queuing) for the RDMA network card; the application scheduling the RDMA network card to execute the WQE within the SQ; the RDMA network card acquiring the WQE from the SQ; the RDMA network card parsing and executing the WQE operation within the SQ; and the RDMA network card performing the write CQ (Confirm Queuing).

[0069] Optionally, at least one new alignment instruction A can be added to the CPU's integrated communication library to cooperate with the hardware module of the newly added communication device within the GPU to complete the order-preserving functions of writing data and writing CQ for the RDMA network card. This new alignment instruction A can be an efficient non-blocking write, which does not require waiting for a response. Alignment instructions can be writes, reads, or atomic operations; they can be a single instruction or a set of instructions. The destination address of the alignment instruction can fall within the communication device or in the address space of a lower-level module of the communication device. If the alignment instruction falls within the communication device, a corresponding address space must be pre-allocated for the communication device during the chip design address mapping scheme, and the corresponding communication device must be able to process instructions falling within its internal address space. The physical component where the final destination address of alignment instruction A is located must be able to ultimately process the instruction and not transmit it to lower-level modules (if any); hardware components located before this physical component, upon receiving the alignment instruction, do not process it but only transmit it to the next level. The destination address of the alignment instruction can fall within the alignment module or in the address space of a lower-level module of the alignment module.

[0070] Optionally, the alignment instruction A can be a specific address allocated in the system that is visible to a certain PCIe interface space of the GPU. The program block for alignment instruction A can be instantiated and called within the host CPU application (software), allowing the alignment instruction to execute between writing data and writing the CQ. Simultaneously, at the RDMA network card, the RDMA read operation following the completion of the RDMA data write, along with the corresponding wait and judgment logic, is synchronously removed. This allows the write operations for data and CQ to proceed non-blockingly; that is, after issuing the SQ write data, the network card can immediately issue the corresponding CQ write command without waiting for the SQ write response. The criteria for determining the alignment instruction can be set via registers. Instructions that meet certain operation types and / or whose destination addresses meet preset address values ​​are considered alignment instructions. Different systems can be designed and configured with different criteria for determining the alignment instructions.

[0071] Optionally, in the GDR or GDA process, the communication device can be configured between the PCIe interface module and the bus. When the PCIe interface module and internal bus are generic IP, the communication device can be developed and integrated separately. In special cases, the functions implemented by the communication device can also be integrated into the PCIe interface module and / or internal bus. The communication device implements the following specific hardware functions in the same way: cooperating with the alignment instructions added by the host CPU application (software) to complete the write data and CQ order preservation functions of the RDMA network card. The order preservation function refers to ensuring that the relative order of data elements (such as messages, packets, events, and query results) remains consistent with the original generation or transmission order when the system processes, transmits, or stores data. The communication device can recognize all instructions passing through the PCIe interface: if it is an alignment instruction, it ensures that all preceding write operations have been written to the destination address before executing the alignment instruction within the communication device. Optionally, the alignment instruction can be executed within the communication device. If the instruction is an unaligned instruction, then all preceding alignment instructions must be completed before these unaligned instructions can be sent to this communication device to reach the GPU for processing.

[0072] In an optional embodiment of the present invention, when the communication device is applied to the GDR process, a portion of the GDR process may include the following operations: the RDMA network card reads the target data through RDMA operation and writes the target data into the GPU's video memory via the PCIe hardware switching module; the RDMA network card writes CQ information into the CPU's main memory through the PCIe hardware switching module; the CPU's host program polls the address where the CQ is located to obtain CQ update information; after obtaining the CQ update information, the CPU's host program calls the program block of the communication device to send it to the GPU; the GPU executes alignment instructions through the communication device; and the CPU's host program notifies the GPU core to use the target data through write operation notification information.

[0073] Optionally, the above GDR process may also include the following operations: the GPU kernel obtains the write operation notification information, parses the write operation notification information to obtain the write address of the target data; the GPU kernel obtains the target data through the write address of the target data and uses it.

[0074] The PCIe hardware switching module is also known as the PCIe switch.

[0075] Figure 9 This is a flowchart of RDMA data processing at the receiving end of an integrated communication device in a GDR process provided by an embodiment of the present invention. Figure 10 This is a flowchart illustrating the interaction between various programs and network cards in the existing GDR process. Figure 11This is a flowchart illustrating the interaction between various programs and network interface cards in a GDR (Global Dedicated Line) configuration with a communication device, provided by an embodiment of the present invention. In a specific example, such as... Figures 8-11 As shown, compared to the typical RDMA data transfer process in the prior art, the RDMA data processing flow of the receiver in the updated GDR process mainly includes the following operations: (1) The RDMA network card reads data through RDMA operation, and then the RDMA network card writes the data to the device memory in the GPU through the PCIe switch.

[0076] (2) The RDMA network card writes CQ information into the host memory of the CPU through the PCIe switch.

[0077] (3) The CPU's Host program obtains that CQ has been updated by polling the address of CQ.

[0078] (4) After the CPU host program obtains that the CQ has been updated, it executes the program block of the newly added alignment instruction. For example, if a write operation is performed on the newly added hardware processing module, the program block of the newly added alignment instruction is called and sent to the GPU; the GPU hardware will execute the alignment instruction.

[0079] (5) The CPU's host program does not need to wait for the response of the newly added alignment instruction A. It can immediately notify the GPU's internal kernel to use the data in the aforementioned device memory through a write operation. This "notification instruction" is also implemented by writing to the GPU's internal memory address, which is a kernel notification instruction.

[0080] (6) The kernel inside the GPU obtains the information of the above "notification instruction" through program polling (reading) and other methods, and parses it to know that the data has been written to the destination address.

[0081] (7) The kernel inside the GPU reads and uses the data from the device memory in the GPU through the program.

[0082] In the above process, the Host program mainly performs the following operations: (1) The host application calls the RDMA verbs API (Application Programming Interface) to create a set of WQEs, including information such as the address and length of the data to be transferred. The WQEs instruct the RDMA network interface card (NIC) to write the data to the GPU's device memory. The verbs API is a set of standardized function interfaces used to directly manipulate RDMA hardware resources.

[0083] (2) The host application removes the program blocks used in the existing technology: It calls the RDMA verbs API to create a set of WQEs, including information such as the address and length of the data to be transferred. The WQEs allow the RDMA NIC to read the data written to the GPU's device memory.

[0084] (3) The host driver writes the above WQE to the SQ cache of the network card NIC.

[0085] (4) The host driver notifies the RDMA network card NIC that the new SQ has been updated through Doorbell write and other methods.

[0086] (5) The host application uses polling to confirm whether the network card has completed the above WQE. If it has not completed, it continues polling until it does.

[0087] (6) After WQE execution is complete, the host application calls the newly added alignment instruction block and sends it to the GPU; the GPU hardware will execute the alignment instructions. The program does not need to wait for the completion of this write instruction to continue running subsequent instructions.

[0088] (7) The host application writes the information that the RDMA network card NIC has completed WQE to the GPU cache space and notifies the GPU Kernel.

[0089] In the above process, the RDMA network card mainly performed the following operations: (1) After receiving a notification from the host driver that the new SQ has been updated via Doorbell write or other means, the network card reads the corresponding address to obtain the new SQ.

[0090] (2) The network card performs the RDMA operation defined by WQE to write data to the GPU's device memory.

[0091] (3) After the network card writes all the data to the GPU, it does not need to perform RDMA read operation to read the Data written to the GPU device memory. After the network card NIC writes all the data to the GPU, it writes the task completion information to the CQ cache located in the CPU.

[0092] In the above process, the GPU's internal kernel program mainly performs the following operations: (1) The GPU kernel program uses polling and other methods to confirm whether the host application has written the WQE information of the RDMA network card to the GPU cache space. If the information is obtained and completed, the polling continues until completion.

[0093] (2) The GPU uses the Data written to the GPU's device memory as described above.

[0094] Figure 12 This is a flowchart illustrating RDMA data processing at the receiving end of an integrated communication device in a GDA process, as provided in an embodiment of the present invention. In a specific example, such as... Figure 12 As shown, in the GDA process, the CQ in the GDR process described above is stored in the GPU's device memory. Therefore, the issuance of the alignment instruction in the GDA process does not need to occur in the host program. Instead, a new program block calling the alignment instruction is added in the RDMA network card application (software). This occurs after the RDMA network card has issued all data write operations, without waiting for the response of the data write operations; after issuing the alignment instruction, the write CQ operation can be issued without waiting for the response of the alignment instruction. Thus, it can be seen that the added communication device can also achieve efficient GDA operation without RDMA read by using the same processing method in the GDR process described above.

[0095] It should be noted that, in order to improve the overall system performance and simplify the description, the above embodiments may optionally implement the alignment instructions as a single write instruction. The number of instructions in the alignment instruction set can be multiple, and the instruction operations can be of various types.

[0096] Example 4 Figure 13This is a flowchart of a communication method provided in Embodiment 4 of the present invention. This embodiment is applicable to situations where a communication device employing order-preserving processing performs order-preserving processing on each instruction. This method can be executed by a communication device, which can be implemented in software and / or hardware, and is generally integrated into the processor of an electronic device. This electronic device can be a terminal device or a server device, as long as it can execute the following communication method. The embodiments of the present invention do not limit the specific type of electronic device. Correspondingly, as... Figure 13 As shown, the method includes the following operations: S110. Receive the current instruction and determine the instruction type of the current instruction.

[0097] S120. If it is determined that the instruction type of the current instruction is an unaligned instruction, the current instruction is sent to the lower-level module for subsequent instruction processing.

[0098] S130. If it is determined that the instruction type of the current instruction is an alignment instruction, obtain the instruction execution result of the preceding target associated instruction of the current instruction, and if it is determined that the instruction execution results of the preceding target associated instructions of the current instruction are all completed, execute the alignment instruction processing flow of the current instruction.

[0099] Optionally, receiving the current instruction and determining the instruction type of the current instruction may include: receiving the current instruction, determining the instruction processing mode of the current instruction based on the current instruction processing flag status; if the instruction processing mode of the current instruction is determined to be a lower-level transmission processing mode, determining the instruction type of the current instruction, and generating a target instruction identification flag based on the instruction type of the current instruction.

[0100] Optionally, before determining the instruction processing mode of the current instruction based on the current instruction processing flag state, the method may further include: obtaining the status value output by the instruction flag hardware status register, and determining the current instruction processing flag state of the current instruction based on the status value; the method may further include: updating the status value based on the status update indication information output by the instruction processing module.

[0101] Optionally, generating a target instruction identification flag based on the instruction type of the current instruction may include: comparing the operation type of the current instruction with the operation type of the alignment instruction to obtain an operation type comparison result; comparing the destination address of the current instruction with the destination address of the alignment instruction to obtain a destination address comparison result; generating an instruction identification flag for the alignment instruction if both the operation type comparison result and the destination address comparison result are successfully compared; and generating an instruction identification flag for the non-aligned instruction if the operation type comparison result and / or the destination address comparison result are unsuccessful.

[0102] Optionally, the step of sending the current instruction to a lower-level module for subsequent instruction processing when the instruction type of the current instruction is determined to be an unaligned instruction may include: determining the instruction type of the current instruction based on the target instruction identification flag of the current instruction; and sending the current instruction to the target lower-level module for subsequent instruction processing when the instruction type of the current instruction is determined to be an unaligned instruction. The method further includes: receiving and feeding back response information returned by the lower-level module. The method further includes: updating the status value of the instruction flag hardware status register to an aligned status value when the instruction type of the current instruction is determined to be an aligned instruction; and updating the status value of the instruction flag hardware status register to an unaligned status value after the aligned instruction processing is completed, and sending response information of the aligned instruction processing result upwards.

[0103] Optionally, determining that the execution results of all preceding target associated instructions of the current instruction are completed can include: updating the instruction count value in real time according to the instruction uplink and downlink transmission streams; when the current instruction count value is determined to be a set value, determining that the execution results of all preceding target associated instructions of the current instruction are completed; the method can also include: when the current instruction count value is determined to be non-set value, waiting for the current instruction count value to be updated to the set value, and then processing the alignment instruction according to the alignment instruction processing rules.

[0104] This invention addresses the problems of high latency and low performance in existing instruction order preservation methods by receiving a current instruction and determining its instruction type. If the instruction type is determined to be a non-aligned instruction, the current instruction is sent to a lower-level module for subsequent instruction processing. If the instruction type is determined to be an aligned instruction, the execution results of the preceding target related instructions are obtained. If the execution results of all preceding target related instructions are determined to be completed, the aligned instruction processing flow for the current instruction is executed. This method efficiently ensures that instructions are completed in sequence, reduces the latency of instruction order preservation processing, and thus improves overall communication performance.

[0105] Since the communication method described above is the method executed by the communication device in the embodiments of the present invention, those skilled in the art can understand the specific implementation and various variations of the communication method in this embodiment based on the communication device described in the embodiments of the present invention. Therefore, the specific implementation of the communication method by the communication device in the embodiments of the present invention will not be described in detail here. As long as those skilled in the art implement the communication method corresponding to the communication device in the embodiments of the present invention, it falls within the scope of protection of this application.

[0106] It should be noted that all information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for display, data used for analysis, etc.) involved in this disclosure are information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data comply with the relevant laws, regulations and standards of the relevant regions.

[0107] It should be noted that any arrangement or combination of the technical features in the above embodiments also falls within the protection scope of this invention.

[0108] Example 5 Figure 14 A schematic diagram of an electronic device 20 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0109] like Figure 14As shown, the electronic device 20 includes at least one processor 11, which may include a communication device (not shown) as described in any embodiment of the present invention, and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from the storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 20. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0110] Multiple components in electronic device 20 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of monitors, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 20 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0111] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as communication methods.

[0112] In some embodiments, the communication method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 20 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the communication method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the communication method by any other suitable means (e.g., by means of firmware).

[0113] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0114] Computer programs used to implement the methods of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs can be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0115] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0116] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0117] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0118] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0119] This invention also discloses a computer program product, which includes a computer program that, when executed by a processor, implements the communication method provided in any embodiment of this invention. This program product shares the same inventive concept as the communication methods disclosed in the embodiments of this invention, and therefore will not be described further here.

[0120] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0121] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A communication device, characterized in that, The communication device is integrated within the processor and is used for: Receive the current instruction and determine the instruction type of the current instruction; If the instruction type of the current instruction is determined to be an unaligned instruction, the current instruction is sent to the next-level module for subsequent instruction processing; wherein, the unaligned instruction is an instruction that does not require alignment processing. If the instruction type of the current instruction is determined to be an alignment instruction, the execution result of the preceding target associated instruction of the current instruction is obtained, and if the execution result of the preceding target associated instruction of the current instruction is determined to be completed, the alignment instruction processing flow of the current instruction is executed; wherein, the alignment instruction is an instruction that needs to be aligned, and the preceding target associated instruction is an instruction issued before the current instruction; The alignment process involves executing the specific instruction operation of the alignment instruction after all the preceding instructions have been completed in sequence.

2. The apparatus according to claim 1, characterized in that, It includes a first judgment module, a second judgment module, and an instruction processing module, wherein: The first judgment module is communicatively connected to the second judgment module, and is used to receive the current instruction, determine the instruction processing mode of the current instruction according to the current instruction processing flag status, and send the current instruction to the second judgment module if the instruction processing mode of the current instruction is determined to be the lower-level transmission processing mode. The second judgment module is communicatively connected to the instruction processing module, and is used to determine the instruction type of the current instruction, generate a target instruction identification flag according to the instruction type of the current instruction, and send the current instruction and the target instruction identification flag of the current instruction to the instruction processing module; The instruction processing module is used to send the current instruction to the next-level module for subsequent instruction processing when the instruction type of the current instruction is determined to be the non-aligned instruction based on the target instruction identification flag of the current instruction; when the instruction type of the current instruction is determined to be the aligned instruction based on the target instruction identification flag of the current instruction, it obtains the instruction execution results of the preceding target associated instructions of the current instruction, and executes the aligned instruction processing flow of the current instruction when it is determined that the instruction execution results of the preceding target associated instructions of the current instruction are all completed.

3. The apparatus according to claim 2, characterized in that, The first judgment module includes a judgment submodule and an instruction flag hardware status register; the judgment submodule and the instruction flag hardware status register are communicatively connected, wherein: The judgment submodule is used to obtain the status value output by the instruction flag hardware status register, determine the current instruction processing flag status of the current instruction based on the status value, and determine the instruction processing mode of the current instruction based on the current instruction processing flag status. If the instruction processing mode of the current instruction is determined to be the lower-level transmission processing mode, the current instruction is sent to the second judgment module. The instruction flag hardware status register is used to update the status value according to the status update indication information output by the instruction processing module.

4. The apparatus according to claim 2, characterized in that, The second determination module includes an instruction operation type register, an opcode determination submodule, a destination address determination submodule, a destination address register, and an instruction flag generation submodule; the instruction operation type register and the opcode determination submodule are communicatively connected, the destination address determination submodule and the destination address register are communicatively connected, and the opcode determination submodule and the destination address determination submodule are also communicatively connected to the instruction flag generation submodule, wherein: The instruction operation type register is used to store the operation type of the alignment instruction; The opcode determination submodule is used to compare the operation type of the current instruction with the operation type of the aligned instruction stored in the instruction operation type register, and obtain the operation type comparison result of the current instruction. The destination address register is used to store the destination address of the alignment instruction; The destination address determination submodule is used to compare the destination address of the current instruction with the destination address of the alignment instruction stored in the destination address register to obtain the destination address comparison result of the current instruction. The instruction flag generation submodule is used to obtain the operation type comparison result and the destination address comparison result of the current instruction, and generate an instruction identification flag for an aligned instruction if it is determined that both the operation type comparison result and the destination address comparison result are successfully compared; and generate an instruction identification flag for an unaligned instruction if it is determined that the operation type comparison result and / or the destination address comparison result are unsuccessful.

5. The apparatus according to claim 3, characterized in that, The instruction processing module includes a request distribution and response module, a lower-level transmission module, and an alignment instruction processing module. The request distribution and response module is communicatively connected to the lower-level transmission module and also communicatively connected to the alignment instruction processing module, wherein: The request distribution response module is used to determine the instruction type of the current instruction based on the target instruction identification flag of the current instruction. If the instruction type of the current instruction is determined to be the non-aligned instruction, the current instruction is sent to the lower-level transmission module; if the instruction type of the current instruction is determined to be the aligned instruction, the current instruction is sent to the aligned instruction processing module. The request distribution response module is also used to receive response information from the lower-level transmission module and the aligned instruction processing module, and send the response information to the upper-level module. The lower-level transmission module is used to send the unaligned instruction to the target lower-level module for subsequent instruction processing; the lower-level transmission module is also used to send the response information returned by the lower level to the request distribution response module; The alignment instruction processing module is configured to, upon receiving the alignment instruction, update the current instruction processing flag status of the instruction flag hardware status register to the alignment status value, and process the alignment instruction if it is determined that the execution results of the preceding target associated instructions of the current instruction are all completed; after determining that the alignment instruction processing is completed, update the current instruction processing flag status of the instruction flag hardware status register to the non-alignment status value, and send the alignment instruction processing result response information to the request dispatch response module.

6. The apparatus according to claim 5, characterized in that, The lower-level transmission module is also equipped with an instruction response counter; The instruction response counter is used to: update the instruction count value in real time according to the instruction uplink and downlink transmission streams; The alignment instruction processing module is further configured to: obtain the current instruction count value; if the current instruction count value is determined to be a set value, determine that the instruction execution results of the preceding target associated instructions of the current instruction are all completed, and process the alignment instruction according to the alignment instruction processing rules; if the current instruction count value is determined to be a non-set value, wait for the current instruction count value to be updated to the set value, and then process the alignment instruction according to the alignment instruction processing rules.

7. The apparatus according to any one of claims 1-6, characterized in that, The communication device is configured between the high-speed peripheral component interconnect standard PCIe interface module and the bus.

8. The apparatus according to claim 7, characterized in that, The communication device is used in the process of GPU Direct Remote Direct Memory Access (GDR) or GPU Direct Asynchronous Communication (GDA) to perform order-preserving processing of write data operations and write completion queue (CQ) operations of the Remote Direct Memory Access (RDMA) network card.

9. The apparatus according to claim 8, characterized in that, When the communication device is applied to the GDR process, a portion of the GDR process includes the following operations: The RDMA network card reads target data through RDMA operation and writes the target data into the GPU's video memory through the PCIe hardware switching module; The RDMA network card writes CQ information into the CPU's main memory through the PCIe hardware switching module. The CPU's host program polls the address of CQ to obtain CQ update information; After receiving the CQ update information, the CPU's host program calls the program block of the communication device to send it to the GPU; The GPU executes alignment instructions via the communication device; The CPU's host program notifies the GPU kernel to use the target data via write operation notification information.

10. A communication method, characterized in that, Applied to the communication device according to any one of claims 1-9, the method comprises: Receive the current instruction and determine the instruction type of the current instruction; If the instruction type of the current instruction is determined to be an unaligned instruction, the current instruction is sent to the next-level module for subsequent instruction processing; wherein, the unaligned instruction is an instruction that does not require alignment processing. If the instruction type of the current instruction is determined to be an alignment instruction, the execution result of the preceding target associated instruction of the current instruction is obtained, and if the execution result of the preceding target associated instruction of the current instruction is determined to be completed, the alignment instruction processing flow of the current instruction is executed; wherein, the alignment instruction is an instruction that needs to be aligned, and the preceding target associated instruction is an instruction issued before the current instruction; The alignment process involves executing the specific instruction operation of the alignment instruction after all the preceding instructions have been completed in sequence.

11. An electronic device, characterized in that, The electronic device includes at least one processor, the processor including the communication device according to any one of claims 1-9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the communication method of claim 10.

13. A computer program product, characterized in that, Includes a computer program / instruction, wherein the computer program / instruction, when executed by a processor, implements the communication method of claim 10.

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