A two-cluster battery inter-voltage and SOC double closed-loop equalization control method and system

Abstract

This invention discloses a dual-closed-loop equalization control method and system for voltage and SOC between two battery clusters. It includes a Battery Management System (BMS), a first battery cluster, a second battery cluster, a sampling module, a control and protection module, and an equalization module containing a DC-DC equalization module and a parallel equalization module. The sampling module collects the voltage of each battery cluster, the electrical parameters of the equalization module, and the equalization current. The BMS acquires the SOC and cell temperature of the two battery clusters and sends them to the control and protection module. The control and protection module executes a first closed-loop control strategy of closed-loop verification and dynamic equalization, generating an equalization start command based on the voltage difference and SOC difference, determining the equalization direction, and deciding whether to initiate DC-DC equalization or parallel equalization. It then executes a second closed-loop control strategy based on feedback from the sampling module. This invention solves the problem of insufficient coordination in single-parameter equalization, eliminates equalization blind spots, and thus improves the energy utilization efficiency of the two battery clusters.

Description

Technical Field

[0001] This invention relates to the field of equalization control technology, specifically to a dual closed-loop equalization control method and system for voltage and SOC between two battery clusters. Background Technology

[0002] In high-voltage energy storage and vehicle battery systems, to meet the system's requirements for energy storage capacity and output power, multiple individual cells are typically connected in series to form a high-voltage battery pack. This high-voltage battery pack is defined as a battery cluster. The energy storage and power supply stability of the entire system are improved by operating multiple battery clusters in parallel. This multi-cluster parallel architecture has become the mainstream configuration in the field of high-voltage energy storage and vehicle systems. Its operational stability directly determines the working efficiency and service life of the entire energy storage system. Different inter-cluster balancing methods can be adopted according to the system's energy storage requirements and operating conditions, such as passive energy consumption balancing, traditional active energy transfer balancing, and system control balancing. Each balancing method corresponds to different working logic and implementation conditions.

[0003] Passive energy equalization involves connecting a resistor in parallel across the battery cluster with the higher voltage. This dissipates the excess energy of the battery cluster as heat generated by the resistor until the voltages of the two battery clusters are nearly identical, thus achieving voltage equalization between the clusters.

[0004] Traditional active energy transfer balancing is the current mainstream active balancing solution. Its core is to realize energy transfer between two battery clusters through a bidirectional DC-DC converter. DC-DC converters mostly adopt an isolated full-bridge topology to transfer the energy of battery clusters with higher voltage or SOC to battery clusters with lower voltage or SOC, thereby achieving inter-cluster balancing.

[0005] The system control balancing mainly involves independently controlling the charging and discharging of the two battery clusters. When the voltage difference between the clusters is large, the charging amount is increased for the battery cluster with lower voltage and decreased for the battery cluster with higher voltage. Once the voltage difference between the two battery clusters is reduced to a preset range, the two battery clusters are then controlled to operate in parallel according to system requirements.

[0006] However, most of the above-mentioned equalization methods only adjust a single parameter such as voltage or SOC, and cannot achieve coordinated equalization control of voltage and SOC. As a result, due to the single equalization logic and insufficient coordination, it is difficult to comprehensively and systematically adapt to the equalization needs of the two battery clusters under different operating conditions. There are equalization blind spots, and problems such as low equalization efficiency and accelerated battery life degradation are likely to occur, thereby reducing the energy utilization efficiency of the two battery clusters. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a dual closed-loop equalization control system for voltage and SOC between two battery clusters, including a battery management system (BMS), a first battery cluster, a second battery cluster, a sampling module, a control and protection module, and an equalization module. The equalization module includes a DC-DC equalization module and a parallel equalization module.

[0008] The battery management system (BMS) is used to obtain the state of charge (SOC1) of the first battery cluster, the state of charge (SOC2) of the second battery cluster, and the highest temperature (Tmax) and lowest temperature (Tmin) of the cells in the two battery clusters, and send them to the control and protection module.

[0009] The first battery cluster and the second battery cluster are each composed of multiple strings of cells connected in series, and each has an equivalent internal resistance;

[0010] The sampling module is electrically connected to the first battery cluster, the second battery cluster, the input side of the equalization module, the output side of the equalization module, and the equalization main circuit of the equalization module, respectively, and is used to collect the inter-electrode voltage V1 of the first battery cluster, the inter-electrode voltage V2 of the second battery cluster, the input side voltage V3 of the equalization module, the output side voltage V4 of the equalization module, and the equalization current I1 flowing through the equalization module.

[0011] The control and protection module includes a shunt trip circuit breaker K1, a fuse F1, and a control unit. The shunt trip circuit breaker K1 is connected between the first battery cluster and the input side of the equalization module. The fuse F1 is connected between the output side of the equalization module and the second battery cluster. The control unit is communicatively connected to the battery management system (BMS), the sampling module, the DC-DC equalization module, and the parallel equalization module.

[0012] The input of the DCDC equalization module is connected to the first battery cluster through the shunt trip circuit breaker K1, and the output is connected to the second battery cluster through the fuse F1. The DCDC equalization module is specifically a bidirectional BUCK circuit architecture, which is used to perform efficient energy balance transfer when the voltage difference or SOC difference between the first battery cluster and the second battery cluster is greater than the corresponding first preset threshold.

[0013] The parallel balancing module consists of a DC contactor KM1 combined with the equivalent internal resistance of two battery clusters. The input terminal of the parallel balancing module is connected to the first battery cluster through one end of the DC contactor KM1, and the output terminal is connected to the second battery cluster through the other end of the DC contactor KM1. It is used to perform low-loss energy balance transfer when the voltage difference or SOC difference between the first battery cluster and the second battery cluster is ≤ the corresponding first preset threshold and ≥ the corresponding second preset threshold.

[0014] The control unit receives all electrical sampling data from the sampling module and battery status data sent by the BMS, and executes the first closed-loop control strategy of verification and dynamic equalization. Based on the comprehensive judgment of voltage difference and SOC difference, it generates an equalization start command and determines the equalization mode selection signal. Based on the equalization mode selection signal, it determines the target equalization module to start. If it is a DC-DC equalization module, it dynamically generates a PWM drive signal to start DC-DC equalization, or if it is a parallel equalization module, it generates a DC contactor KM1 energizing command to start parallel equalization. At the same time, the sampling module diagnoses the main circuit status and feeds it back to the control unit based on voltage V1, V2, V3, V4, equalization current I1 and maximum temperature Tmax, thereby executing the corresponding second closed-loop control strategy.

[0015] Furthermore, the present invention also provides a dual-closed-loop equalization control method for voltage and SOC between two battery clusters. This method is implemented based on the dual-closed-loop equalization control system for voltage and SOC between two battery clusters as described above. The dual-closed-loop equalization control method for voltage and SOC between two battery clusters includes the following steps:

[0016] S01: System power-on initialization, the control unit establishes communication connection with the battery management system BMS, sampling module, DC-DC equalization module and parallel equalization module, obtains the rated parameters of the first battery cluster and the second battery cluster, the preset target equalization current and the preset threshold of each parameter, and generates a basic configuration parameter set;

[0017] S02: Execute the first closed-loop control strategy, cyclically acquire the inter-electrode voltages V1 and V2 between the first and second battery clusters, the real-time state of charge (SOC1 and SOC2), and the highest temperature Tmax and lowest temperature Tmin of the cells within the battery clusters. Calculate the voltage difference ΔV and the SOC difference ΔSOC, generating a real-time state and difference dataset. Based on the real-time state and difference dataset, determine whether the temperature pre-protection condition, the first-level equalization trigger condition, or the second-level equalization trigger condition are met. If so, generate an equalization start command and an energy transfer direction identifier, and determine the equalization direction and the corresponding equalization mode selection signal to start the DC-DC equalization module or the parallel equalization module; otherwise, generate an equalization shutdown command and return to the previous state. The system re-monitors; it determines the corresponding target equalization module based on the equalization mode selection signal, and continuously receives voltages V1, V2, V3, V4 and equalization current I1 uploaded by the sampling module, as well as SOC1 and SOC2 periodically uploaded by the BMS, generating a dynamic equalization real-time feedback dataset; if it is a DC-DC equalization module, it performs dual closed-loop control of voltage and SOC, the outer loop SOC closed loop calculates the voltage reference adjustment amount with the goal of eliminating the SOC difference, and the inner loop voltage closed loop calculates the PWM duty cycle with the goal of eliminating the voltage difference and tracking the outer loop output, dynamically adjusting the PWM drive signal; if it is a parallel equalization module, it maintains the DC contactor KM1 engaged, limits the equalization current I1 through the equivalent internal resistance, and monitors the equalization current I1;

[0018] S03: Obtain the corresponding voltages V1, V2, V3, V4, equalization current I1, and maximum temperature Tmax to diagnose the main circuit status. Based on the main circuit status, if the shunt trip circuit breaker K1 and fuse F1 are confirmed to be normally not disconnected, then check whether Tmax is less than the upper temperature limit T_high and whether the equalization current I1 is less than the equalization current threshold. If so, return to S02 to re-execute the first closed-loop control strategy. If not, disconnect the shunt trip circuit breaker K1 through the control unit. Otherwise, notify the BMS equalization protection to stop, thereby ending the equalization process, and return to S02 to continue monitoring.

[0019] The beneficial effects of this application are as follows:

[0020] Through system power-on initialization, a stable communication connection is established between the control unit and the battery management system (BMS), sampling module, DC-DC equalization module, and parallel equalization module. This solves the problem of insufficient coordination in equalization control caused by the independent operation of each module and poor data communication in traditional equalization schemes. This step comprehensively acquires the rated parameters, preset target equalization current, and preset thresholds for various parameters of the first and second battery clusters, integrating scattered system parameters into a complete set of basic configuration parameters. This eliminates the drawbacks of fragmented parameter configuration and lack of unified standards in traditional equalization methods, clarifying the various benchmarks and safety boundaries of equalization control from the source. The basic configuration parameter set covers all the basic information required for equalization control, providing a unified reference for subsequent state monitoring and condition judgment, and providing a standardized basis for switching and operating different equalization modes, avoiding equalization logic errors caused by missing parameters or chaotic configurations. Secondly, the first closed-loop control strategy is executed. This step cyclically collects the inter-electrode voltage, real-time state of charge (SOC), and the highest and lowest temperatures of the cells within the two battery clusters. It calculates the voltage difference and SOC difference, generating a comprehensive real-time status and difference dataset. This overcomes the limitations of traditional solutions that only monitor a single indicator like voltage or SOC, fully reflecting the battery cluster's charge, voltage, and thermal state. Through multiple condition checks, the temperature pre-protection condition is verified first, followed by differentiation between primary and secondary equalization trigger conditions. This ensures battery thermal safety, preventing damage to cells during equalization at high temperatures, and allows for flexible equalization triggering based on differences in battery cluster status, eliminating ineffective or missed equalization. After generating the equalization start command, the energy transfer direction and equalization mode are defined, and the DC-DC converter or parallel equalization module is activated accordingly. Subsequently, multiple sets of voltage, equalization current, and SOC data are continuously collected to form a dynamic equalization real-time feedback dataset. For the DC-DC balancing module, a bidirectional BUCK circuit is used to implement corresponding voltage and SOC dual closed-loop control. The outer loop eliminates SOC difference, and the inner loop eliminates voltage difference, achieving dual parameter coordinated adjustment. For the parallel balancing module, the DC contactor KM1 is stabilized to maintain its engagement state, current is limited, and balancing current is monitored. This completely changes the problem of insufficient coordination in traditional balancing methods, eliminates balancing blind spots, significantly improves balancing efficiency, and delays battery life degradation. Finally, based on voltage, balancing current, and maximum temperature data, the main circuit operation status is comprehensively diagnosed. The shunt trip circuit breaker K1 and fuse F1 are first confirmed to be intact to eliminate safety hazards caused by hardware failures and ensure that the balancing circuit is in normal working condition. Under the premise that the main circuit is normal, the cell temperature and balancing current are further checked to ensure that they are within the safe range. This double verification ensures that overheating and overcurrent problems will not occur during the balancing process, avoiding accelerated cell life degradation due to abnormal operating conditions. If all indicators meet safety standards, return to the previous step and continue executing the first closed-loop control strategy to maintain the balancing process until the two battery clusters reach equilibrium. If the indicators exceed the standards, immediately disconnect the shunt trip circuit breaker K1 and activate hardware protection. If there is a fault in the main circuit, promptly notify the BMS to stop balancing and terminate the balancing process.The entire mechanism enables real-time monitoring, rapid interruption of abnormalities, and closed-loop process during the balancing process. It ensures that the balancing operation complies with safety regulations and allows the system to return to a stable monitoring state, effectively improving the operational safety of the parallel battery system, reducing energy loss, and further improving the overall energy utilization efficiency of the system. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0022] Figure 1 This is a schematic diagram of the module of the dual closed-loop equalization control system for voltage and SOC between the two battery clusters in this embodiment;

[0023] Figure 2 This is a schematic diagram of the electrical principle of the dual closed-loop equalization control system for voltage and SOC between the two battery clusters in this embodiment;

[0024] Figure 3 This is a schematic diagram of the energy flow direction of the DC-DC equalization module in this embodiment;

[0025] Figure 4 This is a flowchart illustrating the control strategy corresponding to the dual closed-loop equalization control system for voltage and SOC between the two battery clusters in this embodiment.

[0026] Figure 5 This is a schematic diagram of the steps of the dual closed-loop equalization control method for voltage and SOC between two battery clusters in this embodiment. Detailed Implementation

[0027] The following drawings disclose several embodiments of the present invention. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential. Furthermore, for the sake of simplicity, some conventional structures and components will be shown in the drawings in a simple schematic manner.

[0028] To further understand the invention's content, features, and effects, the following embodiments are provided, and detailed descriptions are given below in conjunction with the accompanying drawings:

[0029] Reference Figure 1-2 , Figure 1 This is a schematic diagram of the module of the dual closed-loop equalization control system for voltage and SOC between the two battery clusters in this embodiment; Figure 2This is a schematic diagram of the electrical principle of the dual-closed-loop equalization control system for voltage and SOC between two battery clusters in this embodiment. The dual-closed-loop equalization control system for voltage and SOC between two battery clusters in this embodiment includes a battery management system (BMS), a first battery cluster, a second battery cluster, a sampling module, a control and protection module, and an equalization module. The equalization module includes a DC-DC equalization module and a parallel equalization module.

[0030] The battery management system (BMS) is used to obtain the state of charge (SOC1) of the first battery cluster, the state of charge (SOC2) of the second battery cluster, and the highest temperature (Tmax) and lowest temperature (Tmin) of the cells in the two battery clusters, and send them to the control and protection module.

[0031] The first battery cluster and the second battery cluster are each composed of multiple strings of cells connected in series, and each has an equivalent internal resistance;

[0032] The sampling module is electrically connected to the first battery cluster, the second battery cluster, the input side of the equalization module, the output side of the equalization module, and the equalization main circuit of the equalization module, respectively, and is used to collect the inter-electrode voltage V1 of the first battery cluster, the inter-electrode voltage V2 of the second battery cluster, the input side voltage V3 of the equalization module, the output side voltage V4 of the equalization module, and the equalization current I1 flowing through the equalization module.

[0033] The control and protection module includes a shunt trip circuit breaker K1, a fuse F1, and a control unit. The shunt trip circuit breaker K1 is connected between the first battery cluster and the input side of the equalization module. The fuse F1 is connected between the output side of the equalization module and the second battery cluster. The control unit is communicatively connected to the battery management system (BMS), the sampling module, the DC-DC equalization module, and the parallel equalization module.

[0034] The input of the DCDC equalization module is connected to the first battery cluster through the shunt trip circuit breaker K1, and the output is connected to the second battery cluster through the fuse F1. The DCDC equalization module is specifically a bidirectional BUCK circuit architecture, which is used to perform efficient energy balance transfer when the voltage difference or SOC difference between the first battery cluster and the second battery cluster is greater than the corresponding first preset threshold.

[0035] The parallel balancing module consists of a DC contactor KM1 combined with the equivalent internal resistance of two battery clusters. The input terminal of the parallel balancing module is connected to the first battery cluster through one end of the DC contactor KM1, and the output terminal is connected to the second battery cluster through the other end of the DC contactor KM1. It is used to perform low-loss energy balance transfer when the voltage difference or SOC difference between the first battery cluster and the second battery cluster is ≤ the corresponding first preset threshold and ≥ the corresponding second preset threshold.

[0036] The control unit receives all electrical sampling data from the sampling module and battery status data sent by the BMS, and executes the first closed-loop control strategy of verification and dynamic equalization. Based on the comprehensive judgment of voltage difference and SOC difference, it generates an equalization start command and determines the equalization mode selection signal. Based on the equalization mode selection signal, it determines the target equalization module to start. If it is a DC-DC equalization module, it dynamically generates a PWM drive signal to start DC-DC equalization, or if it is a parallel equalization module, it generates a DC contactor KM1 energizing command to start parallel equalization. At the same time, the sampling module diagnoses the main circuit status and feeds it back to the control unit based on voltage V1, V2, V3, V4, equalization current I1 and maximum temperature Tmax, thereby executing the corresponding second closed-loop control strategy.

[0037] In this embodiment of the invention, the Battery Management System (BMS) collects the real-time voltage of each string of cells through a cell voltage acquisition circuit. It then calculates the State of Charge (SOC1) of the first battery cluster and the State of Charge (SOC2) of the second battery cluster using an ampere-hour integration algorithm. Simultaneously, it collects temperature data of all cells within both battery clusters using a thermistor, filters out the highest temperature value (Tmax) and the lowest temperature value (Tmin), and synchronously sends SOC1, SOC2, Tmax, and Tmin to the control and protection module via a preset communication line. Both the first and second battery clusters consist of 102 strings of lithium iron phosphate cells connected in series. The rated voltage of a single string of cells is 3.2V, the rated voltage of a single cluster is 325.8V, and the rated capacity is 304Ah. The equivalent internal resistance of each cluster is obtained by superimposing the series internal resistance of the cells and by testing under actual operating conditions; the equivalent internal resistance of a single cluster is Rn = 51mΩ. The sampling module establishes electrical connections with the positive and negative terminals of the first and second battery clusters, the input side of the equalization module, and the output side of the equalization module through voltage sensors. It collects the inter-terminal voltages V1 and V2 of the first and second battery clusters, the input voltage V3 of the equalization module, and the output voltage V4 of the equalization module. A Hall current sensor connected in series in the equalization main circuit of the equalization module collects the equalization current I1 flowing through the equalization module. The collected analog signals are converted into synchronous digital sampling data after passive RC low-pass filtering, optocoupler isolation amplification, and operational amplifier level shifting. The control and protection module includes a shunt trip circuit breaker K1, a fuse F1, and a control unit. The shunt trip circuit breaker K1 is connected between the positive terminal of the first battery cluster and the input side of the equalization module, and the fuse F1 is connected between the output side of the equalization module and the positive terminal of the second battery cluster. Both K1 and F1 are selected with a rated parameter of 100A and a rated voltage of 450V. K1 can quickly disconnect the equalization main circuit upon receiving a command from the control unit. F1 serves as redundant protection and automatically blows when the circuit current exceeds the rated parameter. The control unit establishes stable communication connections with the battery management system (BMS), sampling module, DC-DC equalization module, and parallel equalization module via wired communication lines.The input of the DC-DC equalization module is connected to the first battery cluster via a shunt trip circuit breaker K1, and the output is connected to the second battery cluster via a fuse F1. The DC-DC equalization module is a bidirectional BUCK circuit architecture, consisting of a first filter capacitor C1, a second filter capacitor C2, a first power switch Q1, a second power switch Q2, a first freewheeling diode D1, a second freewheeling diode D2, and a power storage inductor L1. C1 and C2 have a withstand voltage of 450V and a capacitance of 470μF, and Q1 and Q2 are N-channel enhancement-mode transistors. The power MOSFET has a withstand voltage of 650V and an on-resistance of 10mΩ. D1 and D2 are fast recovery diodes with a reverse withstand voltage of 650V. L1 has a saturation current of 100A and an inductance of 1mH. The DC-DC equalization module is used to perform efficient energy balance transfer when the voltage difference between the first and second battery clusters is greater than 6V or the SOC difference is greater than 5%. The circuit logic is to achieve efficient energy transfer from the high-voltage side battery cluster to the low-voltage side battery cluster by controlling the turn-on and turn-off timing of the power switch and combining the energy storage and release characteristics of the inductor. The parallel balancing module consists of a DC contactor KM1 combined with the equivalent internal resistance of two battery clusters. KM1 has a rated current of 100A and a coil voltage of 24V. The input terminal of the parallel balancing module is connected to the positive terminal of the first battery cluster through one end of the DC contactor KM1, and the output terminal is connected to the positive terminal of the second battery cluster through the other end of the DC contactor KM1. It is used to perform low-loss energy balance transfer when the voltage difference between the first battery cluster and the second battery cluster is ≤6V and ≥0.3V or the SOC difference is ≤5% and ≥1%. The circuit logic is that after KM1 is energized, the two battery clusters form a parallel circuit, and the balancing current is limited by the equivalent internal resistance to reduce the power device loss. The control unit receives all electrical sampling data from the sampling module and battery status data sent by the BMS through a hardware interface. It executes the first closed-loop control strategy of verification and identification and dynamic equalization. Based on the comprehensive judgment of voltage difference ΔV=|V1-V2| and SOC difference ΔSOC=|SOC1-SOC2|, it generates an equalization start command and determines the equalization mode selection signal. Based on the equalization mode selection signal, it determines the target equalization module to start. If it is a DC-DC equalization module, the control unit dynamically generates a PWM drive signal to start DC-DC equalization. If it is a parallel equalization module, it generates a 24V pull-in command to start parallel equalization. At the same time, the sampling module diagnoses the main circuit status based on voltage V1, V2, V3, V4, equalization current I1 and maximum temperature Tmax through voltage logic relationship and current value, and feeds back the diagnosis results to the control unit, thereby executing the corresponding second closed-loop control strategy to realize safe monitoring and closed-loop adjustment of the equalization process.

[0038] Furthermore, such as Figure 4 As shown, Figure 4This is a flowchart illustrating the control strategy corresponding to the dual closed-loop equalization control system for voltage and SOC between the two battery clusters in this embodiment. The first closed-loop control strategy in the control and protection module, which executes verification and dynamic equalization to initiate DC-DC equalization or parallel equalization, includes:

[0039] After the system is powered on, the control unit establishes a communication connection with the battery management system (BMS), sampling module, DC-DC equalization module and parallel equalization module, receives the equalization function enable command issued by the BMS, and obtains the rated voltage Ve, rated internal resistance Rn, preset target equalization current Ij and preset threshold values ​​of each parameter of the first battery cluster and the second battery cluster, and generates a basic configuration parameter set.

[0040] Based on the basic configuration parameter set, the real-time voltages V1 and V2 uploaded by the sampling module and SOC1, SOC2, Tmax, and Tmin uploaded by the BMS are received in a loop. The absolute value of the voltage difference ΔV = |V1-V2| and the absolute value of the SOC difference ΔSOC = |SOC1-SOC2| are calculated, and the extreme value data of the cell temperature are obtained to generate a real-time status and difference dataset.

[0041] Based on the real-time status and difference dataset, it is determined whether the temperature pre-protection condition is met, specifically the lower temperature limit T_low < Tmin and Tmax < upper temperature limit T_high. Simultaneously, it is determined whether the dual equalization trigger condition is met, specifically the first equalization trigger condition ΔV > first voltage threshold V_th1 or ΔSOC > first SOC threshold SOC_th1, and the second equalization trigger condition ΔV < second voltage threshold V_th2 and ΔSOC < second SOC threshold SOC_th2. The judgment results of the temperature pre-protection condition and the dual equalization trigger condition are logically ANDed to generate the first closed-loop test result.

[0042] If the first closed-loop test result indicates that the temperature protection is not triggered and the single-level equalization trigger condition is met or the double-level equalization trigger condition is not met, an equalization start command and an energy transfer direction identifier are generated. The energy transfer direction identifier is determined by comparing the values ​​of V1 and V2, and SOC1 and SOC2, specifically transferring from the battery cluster with the larger value to the battery cluster with the smaller value. The equalization direction is determined based on the energy transfer direction identifier, and the equalization mode selection signal for the corresponding direction is determined based on the equalization direction, the equalization start command, and the real-time status and difference dataset to start the DC-DC equalization module or the parallel equalization module. If the first closed-loop test result indicates that the temperature protection is triggered, or the single-level equalization trigger condition is not met but the double-level equalization trigger condition is met, an equalization shutdown command is generated and the BMS is notified to stop equalization, and the control unit enters a low-power periodic inspection state.

[0043] After starting the DC-DC balancing module or parallel balancing module, the corresponding dynamic balancing control strategy is executed.

[0044] In this embodiment of the invention, the control and protection module includes a shunt trip circuit breaker K1, a fuse F1, and a control unit. Both the shunt trip circuit breaker K1 and the fuse F1 are rated at 100A. K1 is used to quickly disconnect the equalization module, and F1 serves as redundant protection. After the system is powered on, the control unit establishes a stable communication connection with the battery management system (BMS), the sampling module, the DC-DC equalization module, and the parallel equalization module through a preset communication line. No additional data import is required during communication; the control unit directly receives the equalization function enable command issued by the BMS and simultaneously acquires the rated parameters of the first and second battery clusters. The parameters include a rated voltage Ve of 325.8V, a rated internal resistance Rn of 51mΩ, a preset target equalization current Ij of 60.8A, and preset threshold values ​​for each parameter, including a first voltage threshold V_th1 of 6V, a second voltage threshold V_th2 of 0.3V, a first SOC threshold SOC_th1 of 5%, a second SOC threshold SOC_th2 of 1%, a lower temperature limit T_low of 0℃, an upper temperature limit T_high of 60℃, and an equalization current threshold of 75A. These parameters are integrated to generate a basic configuration parameter set, ensuring that all subsequent operations are based on this parameter set. Based on the basic configuration parameter set, the control unit receives the real-time voltage V1 of the first battery cluster and the real-time voltage V2 of the second battery cluster uploaded by the sampling module through the voltage sampling interface and the current sampling interface. At the same time, it receives the real-time SOC1 of the first battery cluster, the real-time SOC2 of the second battery cluster, the highest cell temperature Tmax, and the lowest cell temperature Tmin uploaded by the BMS through the communication interface. The receiving frequency is kept consistent with the output frequency of the sampling module and the BMS. After receiving, the control unit calculates the absolute value of the voltage difference ΔV=|V1-V2| through the internal calculation unit. For example, when V1 is 332.4V and V2 is 325.8V, ΔV=|332.4-325.8|=6.6V. It also calculates ΔSOC=|SOC1-SOC2|. For example, when SOC1 is 81% and SOC2 is 75%, ΔSOC=|81%-75%|=6.0%. At the same time, it extracts the received Tmax and Tmin as the extreme value data of the cell temperature. These calculation results and extracted data are integrated to generate a real-time status and difference dataset. Based on the real-time status and difference dataset, the logic judgment unit inside the control unit first judges the temperature pre-protection condition, that is, whether Tmin is greater than 0℃ and Tmax is less than 60℃. If Tmin is 5℃ and Tmax is 55℃, the temperature pre-protection condition is met. If Tmin is -2℃ or Tmax is 65℃, the temperature pre-protection condition is not met. Simultaneously, the dual balance trigger condition is judged. The first balance trigger condition is ΔV > 6V or ΔSOC > 5%, and the second balance trigger condition is ΔV < 0.3V and ΔSOC < 1%. The logic judgment unit performs a logical AND operation on the judgment results of the temperature pre-protection condition and the dual balance trigger condition to generate the first closed-loop test result.If the first closed-loop test result is that the temperature protection is not triggered, the first-level equalization trigger condition is met, or the second-level equalization trigger condition is not met, the command generation unit of the control unit generates an equalization start command and an energy transfer direction identifier. The energy transfer direction identifier is determined by comparing the magnitudes of V1 and V2, and SOC1 and SOC2. When V1 > V2 and SOC1 > SOC2, the energy transfer direction identifier indicates that energy is transferred from the first battery cluster to the second battery cluster. When V1 < V2 and SOC1 < SOC2, the energy transfer direction identifier indicates that energy is transferred from the second battery cluster to the first battery cluster. The command generation unit is based on the equalization start command, the energy transfer direction identifier, and the real-time status and difference data. The system collects and determines the equalization mode selection signal, and simultaneously starts the DC-DC equalization module or parallel equalization module through the driver interface. The circuit logic involves the control unit outputting a high-level signal to the corresponding equalization module's driver, putting the equalization module into a standby state. If the first closed-loop test result triggers temperature protection, or if temperature protection is not triggered, the first equalization trigger condition is not met, but the second equalization trigger condition is met, the instruction generation unit generates an equalization shutdown instruction and notifies the BMS to stop equalization via the communication line. Simultaneously, the power management unit inside the control unit switches to low-power mode and enters a periodic inspection state. The inspection cycle is set to once every 5 seconds, and each inspection only collects core parameters to reduce energy consumption. After starting the DC-DC equalization module or parallel equalization module, the control unit immediately switches to the corresponding dynamic equalization control mode and executes the corresponding dynamic equalization control strategy.

[0045] Furthermore, such as Figure 4 As shown, determining the equalization mode selection signal in the corresponding direction to activate the DC-DC equalization module or parallel equalization module includes:

[0046] If temperature protection is not triggered, the absolute value of the current voltage difference ΔV is compared in real time with the first voltage threshold V_th1 and the second voltage threshold V_th2, and the absolute value of the current SOC difference ΔSOC is compared with the first SOC threshold SOC_th1 and the second SOC threshold SOC_th2. If ΔV > V_th1 or ΔSOC > SOC_th1, the DC-DC equalization mode is determined to be applicable, a first equalization mode selection signal is generated, and the corresponding drive interface of the DC-DC equalization module is activated. If ΔV ≤ V_th1 and ΔSOC ≤ SOC_th1, ΔV ≥ V_th2 or ΔSOC ≥ SOC_th2, the parallel equalization mode is determined to be applicable, a second equalization mode selection signal is generated, and the corresponding drive interface of the parallel equalization module is activated.

[0047] Based on the first or second equalization mode selection signal and combined with the energy transfer direction identifier, the control unit calls the module drive interface parameters, initial control parameters, and safety parameters corresponding to the selected equalization mode and equalization direction to generate a target equalization module drive configuration set. The control unit sends a PWM drive signal containing the initial duty cycle to the DC-DC equalization module or sends a pull-in command to the DC contactor KM1 of the parallel equalization module based on the target equalization module drive configuration set, and simultaneously reads the real-time data of the side voltage V3, V4 and equalization current I1 fed back by the sampling module to generate a pre-action state verification dataset.

[0048] Analyze the pre-action state verification dataset to verify whether the input-output voltage relationship of the DC-DC equalization module is consistent with the expected equalization direction, or to verify whether the circuit on / off state of the DC contactor KM1 of the parallel equalization module meets the command requirements. If the verification is successful, an equalization module ready confirmation signal is generated, and the DC contactor KM1 is controlled to perform a closing action to select to start the DC-DC equalization module or the parallel equalization module respectively.

[0049] In this embodiment of the invention, when determining the equalization mode selection signal and starting the DC-DC equalization module or parallel equalization module, it is first confirmed that temperature protection is not triggered, i.e., Tmin is between 0℃ and 60℃ and Tmax is between 0℃ and 60℃. The control unit compares the currently calculated absolute value of the voltage difference ΔV with the first voltage threshold V_th1 and the second voltage threshold V_th2 in real time, and at the same time compares the currently calculated absolute value of the SOC difference ΔSOC with the first SOC threshold SOC_th1 and the second SOC threshold SOC_th2 in real time. If ΔV > 6V or ΔS If OC > 5%, the DC-DC equalization mode is deemed applicable, and a first equalization mode selection signal is generated. This signal activates the corresponding drive interface of the DC-DC equalization module via the drive circuit, putting the bidirectional BUCK circuit of the DC-DC equalization module into a ready-to-drive state. If ΔV ≤ 6V and ΔSOC ≤ 5%, ΔV ≥ 0.3V, or ΔSOC ≥ 1%, the parallel equalization mode is deemed applicable, and a second equalization mode selection signal is generated. This signal is a continuous high-level signal, which activates the corresponding drive interface of the parallel equalization module via the drive circuit, putting the DC contactor KM1 of the parallel equalization module into a ready-to-engage state. Based on the first or second equalization mode selection signal, and combined with the energy transfer direction indicator, the control unit retrieves the module drive interface parameters, initial control parameters, and safety parameters corresponding to the selected equalization mode and equalization direction from the internal storage unit. After integration, a target equalization module drive configuration set is generated. The initial control parameters of the DC-DC equalization module include the initial duty cycle, and the initial control parameters of the parallel equalization module include the contactor engagement voltage. Based on the target equalization module drive configuration set, if it is a DC-DC equalization module, the control unit generates a PWM drive signal containing the initial duty cycle and sends it to the power switch control terminal of the DC-DC equalization module through the drive line. Its circuit logic is that the PWM drive signal controls the conduction and cutoff of power transistors Q1 and Q2 in the bidirectional BUCK circuit. If it is a parallel equalization module, the control unit sends a pull-in command to the DC contactor KM1 of the parallel equalization module. The command is a DC voltage signal that meets the pull-in requirements of KM1. At the same time, the control unit reads the real-time data of the side voltage V3, V4 and equalization current I1 fed back by the sampling module through the V3 and V4 voltage sampling interfaces and the I1 current sampling interface of the sampling module, and integrates these data to generate a pre-action state verification dataset.The control unit analyzes the pre-action state verification dataset. If it is a DC-DC equalization module, it verifies whether the input-output voltage relationship of the bidirectional BUCK circuit is consistent with the expected equalization direction. That is, when energy is transferred from the first battery cluster to the second battery cluster, it verifies that V3 (the voltage on the first side of the DC-DC equalization module) is equal to V1, V4 (the voltage on the second side of the DC-DC equalization module) is equal to V2, and V3 > V4. At the same time, it verifies that the direction of the equalization current I1 is consistent with the energy transfer direction. If it is a parallel equalization module, it verifies whether the circuit on / off state of the DC contactor KM1 meets the command requirements. That is, it judges whether KM1 is engaged by the values ​​of V3 and V4. When V1=V3=V4=V2 and I1≠0, it is determined that KM1 is engaged normally. If the verification passes, the verification unit generates a balancing module readiness confirmation signal, and the control unit outputs a control signal to control the corresponding DC contactor KM1 to perform a closing action. If it is a DC-DC balancing module, the shunt trip circuit breaker K1 is closed, allowing the balancing current to flow into the DC-DC balancing module through K1, thus starting the DC-DC balancing module. If it is a parallel balancing module, the shunt trip circuit breaker K1 is closed, and the control unit controls the DC contactor KM1 to close, forming a parallel circuit between the two battery clusters, thus starting the parallel balancing module and completing the balancing module startup operation. During this process, the control unit can only control the shunt trip circuit breaker K1 to trip under certain subsequent conditions; it cannot electrically close the switch. The shunt trip circuit breaker K1 remains closed without the need for circuit maintenance.

[0050] Furthermore, the execution of the corresponding dynamic balancing control strategy after activating the DC-DC balancing module or parallel balancing module includes:

[0051] Based on the equalization module readiness confirmation signal, the corresponding target equalization module is determined, and real-time data V1, V2, V3, V4, I1 uploaded by the sampling module and SOC1 and SOC2 periodically uploaded by the BMS are continuously received to generate a dynamic equalization real-time feedback dataset.

[0052] When the target equalization module is a DC-DC equalization module, a dual closed-loop control based on a bidirectional BUCK circuit for voltage and SOC is executed: An outer-loop SOC closed-loop controller is established, using the SOC difference ΔSOC between the first and second battery clusters as input, and aiming for the final equality of the SOC values ​​of the two clusters. It performs calculations using a preset proportional-integral control algorithm, outputting a voltage reference adjustment ΔV_ref for the inner-loop voltage closed-loop control; an inner-loop voltage closed-loop controller is established, using the voltage difference ΔV and the voltage reference adjustment ΔV_ref as combined inputs to eliminate… In addition to the voltage difference between the two clusters being the direct control target and being processed, the output is used to adjust the PWM duty cycle correction amount ΔD in the bidirectional BUCK circuit corresponding to the equalization direction, generating an inner loop duty cycle correction instruction; based on the inner loop duty cycle correction instruction, combined with the initial duty cycle centrally stored in the target equalization module driver configuration, the real-time PWM duty cycle D_real is calculated, and according to the equalization direction, a PWM drive signal with dead time is generated and sent to the corresponding power switch control terminal in the DC-DC equalization module to adjust the transmission power and drive it to perform DC-DC equalization;

[0053] When the target equalization module is a parallel equalization module, open-loop control based on equivalent internal resistance current limiting is executed: the DC contactor KM1 is kept in a continuously engaged state. At this time, the magnitude of the equalization current I1 is determined by the voltage difference ΔV between the two battery clusters and the sum of the total internal resistances of the two battery clusters, 2Rn, specifically I1 = ΔV / (2Rn). The equalization current I1 is continuously monitored by the sampling module to drive it to perform parallel equalization and transmit it to the control unit; the latest voltage difference ΔV_new and SOC difference ΔSOC_new are calculated, and it is determined whether the double equalization trigger condition is met. If it is met, an equalization completion command is generated and the BMS is notified to stop equalization.

[0054] In this embodiment of the invention, after receiving the equalization module readiness confirmation signal, the control unit determines the target equalization module as a DC-DC equalization module or a parallel equalization module based on the signal level characteristics. Subsequently, it continuously receives the real-time voltage V1 of the first battery cluster, the real-time voltage V2 of the second battery cluster, the voltage V3 of the DC-DC equalization module, the voltage V4 of the parallel equalization module, and the equalization current I1 through the multi-channel sampling interface of the sampling module. At the same time, it receives the real-time SOC1 of the first battery cluster and the real-time SOC2 of the second battery cluster periodically uploaded by the BMS through the communication interface. The receiving frequency is consistent with the output frequency of the sampling module and the BMS. After integrating all the collected and calculated data, a dynamic equalization real-time feedback dataset is generated to provide data support for subsequent equalization control.When the target equalization module is a DC-DC equalization module, it executes a dual closed-loop control based on voltage and SOC using a bidirectional BUCK circuit. An outer-loop SOC closed-loop controller is built inside the control unit. This controller uses the SOC difference ΔSOC between the first and second battery clusters as its core input, and aims to make the SOC values ​​of the two clusters equal. It calls the preset outer-loop proportional coefficient Kp_soc and outer-loop integral coefficient Ki_soc, and completes the calculation through a proportional-integral control algorithm. The corresponding calculation expression is ΔV_ref(k) = Kp_soc × ΔSOC_ The output is current(k) + Ki_soc × ΣΔSOC_current(j), which is the voltage reference adjustment ΔV_ref used for the inner loop voltage closed-loop control. Simultaneously, an independent inner loop voltage closed-loop controller is built. This controller uses the voltage difference ΔV between the two battery clusters and the voltage reference adjustment ΔV_ref as comprehensive inputs, with the direct control objective being to eliminate the voltage difference between the two clusters. It calls another set of independently set inner loop proportional coefficients Kp_v and inner loop integral coefficients Ki_v, and processes the ΔD = Kp_v × (ΔV + ΔV_ref) using a proportional-integral control algorithm. The function is calculated as V_ref) + Ki_v × ∑(ΔV + ΔV_ref), which outputs the PWM duty cycle correction amount ΔD used to adjust the corresponding energy transfer direction in the bidirectional BUCK circuit, generating an inner loop duty cycle correction command. Based on this inner loop duty cycle correction command and the initial duty cycle centrally stored in the target equalization module driver configuration, the control unit calculates the real-time PWM duty cycle D_real through numerical calculation. The calculation process is D_real = initial duty cycle + ΔD. Subsequently, based on the energy transfer direction identifier, the hardware logic circuit generates a PWM duty cycle with a preset dead time. The PWM drive signal is sent to the control terminals of power transistors Q1 and Q2 in the DC-DC equalization module through the drive line. By controlling the turn-on and turn-off timing of the power switches, the energy transfer power is adjusted, driving the bidirectional BUCK circuit to perform DC-DC equalization. The circuit logic is as follows: when energy is transferred from the first battery cluster to the second battery cluster, the control unit outputs a PWM signal to drive Q2 to be continuously turned on, and the BUCK step-down energy transfer is achieved by adjusting the duty cycle of Q1. When energy is transferred in the reverse direction, Q1 is controlled to be continuously turned on, and the duty cycle of Q2 is adjusted to complete the energy transfer.When the target equalization module is a parallel equalization module, open-loop control based on equivalent internal resistance current limiting is executed. The control unit continuously outputs a pull-in holding signal to maintain the continuous pull-in state of DC contactor KM1. At this time, the two battery clusters form a parallel circuit. The magnitude of the equalization current I1 is determined by the voltage difference ΔV between the two battery clusters and the sum of the total internal resistances of the two battery clusters, 2Rn. The specific calculation formula is I1=ΔV / (2Rn). The control unit continuously monitors the real-time value of the equalization current I1 through the sampling module. Based on this value, it drives the parallel equalization module to perform equalization operation and simultaneously feeds back the value of the equalization current I1 to the sampling module. Based on the dynamic equalization real-time feedback dataset, the control unit calculates the latest voltage difference ΔV_new and SOC difference ΔSOC_new. The calculation result is compared with the preset double equalization trigger condition. The double equalization trigger condition is ΔV_new<0.3V and ΔSOC_new<1%. If the calculation result meets the condition, the control unit generates an equalization completion command and notifies the BMS to stop equalization through the communication line, thus completing the entire equalization control process.

[0055] Furthermore, the output of the voltage reference value adjustment amount ΔV_ref includes:

[0056] The SOC difference ΔSOC_current for each cycle is extracted from the dynamic equilibrium real-time feedback dataset, and the voltage reference value adjustment is calculated by calling the preset outer loop proportional coefficient Kp_soc and outer loop integral coefficient Ki_soc. The calculation expression is ΔV_ref(k)=Kp_soc×ΔSOC_current(k)+Ki_soc×ΣΔSOC_current(j), where k is the current control cycle number and j is the historical cycle number from the start of control to the current cycle, generating the original voltage adjustment amount without amplitude limiting. The original voltage adjustment amount without amplitude limiting is subjected to a combination of amplitude limiting and rate of change limiting. The amplitude limiting range is determined based on the rated voltage Ve of the battery cluster and the maximum adjustable voltage range of the DC-DC equalization module, and the rate of change limiting is determined based on the preset maximum voltage adjustment step size allowed in a single control cycle, generating ΔV_ref_limited after amplitude and rate of change limiting.

[0057] The limited ΔV_ref_limited is combined with the voltage reference adjustment from the previous control cycle and subjected to a first-order hysteresis smoothing filter to suppress high-frequency fluctuations caused by SOC fluctuations or sampling noise, generating the final voltage reference adjustment ΔV_ref for the current cycle. The voltage reference adjustment ΔV_ref is then passed to the inner-loop voltage closed-loop controller as part of its voltage tracking target, and the SOC difference and voltage reference adjustment ΔV_ref for the current control cycle are stored for iterative calculation of integral terms and smoothing filtering in the next control cycle.

[0058] In this embodiment of the invention, when adjusting the output voltage reference value by ΔV_ref, the control unit extracts the SOC difference ΔSOC_current within each control cycle from the dynamic equalization real-time feedback dataset. The extraction process involves sequentially reading the ΔSOC_current values ​​from the dataset according to the control cycle number, and then calling the preset outer loop proportional coefficient Kp_soc and outer loop integral coefficient Ki_soc to calculate the original voltage according to the calculation expression ΔV_ref(k)=Kp_soc×ΔSOC_current(k)+Ki_soc×ΣΔSOC_current(j). The adjustment amount is calculated as follows: k is the current control cycle number, j is the sequence number of all historical cycles from the start of control to the current cycle, and ΣΔSOC_current(j) is the accumulated value of all ΔSOC_current values ​​from the start of control to the current cycle. During calculation, the control unit continuously accumulates the ΔSOC_current values ​​of historical cycles through an internal accumulation register. After each control cycle is completed, the current ΔSOC_current(j) value is accumulated into the register to generate the raw voltage adjustment amount without amplitude limiting. The raw voltage adjustment amount is then subjected to a combination of amplitude limiting and rate of change limiting. The amplitude limit range is determined based on the rated voltage Ve of the battery cluster and the maximum adjustable voltage range of the DC-DC equalization module. In this embodiment, the rated voltage Ve is 325.8V, and the maximum adjustable voltage range of the DC-DC equalization module is ±15V. Therefore, the amplitude limit range is set to -15V to 15V. The rate of change limit is determined based on the maximum allowable voltage adjustment step size within a single control cycle. In this embodiment, the maximum voltage adjustment step size within a single control cycle is set to 0.5V. During processing, the control unit first determines whether the original voltage adjustment exceeds the amplitude limit range through a hardware comparison circuit. If it does, it corrects it to the extreme value within the amplitude limit range. Next, it is determined whether the difference between the corrected value and the voltage adjustment amount of the previous control cycle exceeds the maximum voltage adjustment step size. If it does, the difference is corrected to the maximum voltage adjustment step size, generating ΔV_ref_limited after amplitude and rate of change limiting. The ΔV_ref_limited after amplitude limiting is then compared with the voltage reference value adjustment amount of the previous control cycle using a first-order hysteresis smoothing filter. The filtering formula is ΔV_ref_final=α×ΔV_ref_limited+(1-α)×ΔV_ref_last, where α is a preset filtering coefficient with a value range of 0.6 to 0.8. ΔV_ref_last represents the voltage reference adjustment value from the previous control cycle. The filtering process is completed through the filter register inside the control unit. The ΔV_ref_last value from the previous cycle is stored in the register and weighted with the current ΔV_ref_limited to suppress high-frequency fluctuations caused by SOC fluctuations or sampling noise, generating the final voltage reference adjustment value ΔV_ref for the current cycle. This final voltage reference adjustment value ΔV_ref is then passed to the inner-loop voltage closed-loop controller as part of the inner-loop voltage tracking target. Simultaneously, the control unit stores the SOC difference and the voltage reference adjustment value ΔV_ref for the current control cycle in the data storage unit for the integral term accumulation calculation in the next control cycle. The integral term accumulation calculation involves adding the current cycle's SOC difference to the historical accumulated value, providing data support for the next integral calculation. The iterative calculation of the smoothing filter uses the final voltage reference adjustment value ΔV_ref for the current cycle as the ΔV_ref_last for the next cycle, completing the closed-loop calculation and transmission of the entire output voltage reference adjustment value.

[0059] Furthermore, the sampling module includes a multi-channel voltage sampling unit, an equalization current sampling unit, a synchronous signal conditioning and conversion unit, and an online circuit status diagnosis unit;

[0060] The multi-channel voltage sampling unit is used to collect the inter-electrode voltage V1 of the first battery cluster, the inter-electrode voltage V2 of the second battery cluster, the input voltage V3 of the equalization module, and the output voltage V4 of the equalization module using voltage sensors, and generate four raw voltage analog signals.

[0061] The equalization current sampling unit is used to collect the equalization current corresponding to the equalization main circuit using a Hall current sensor and generate a raw current analog signal.

[0062] The synchronous signal conditioning and conversion unit is used to perform anti-aliasing filtering, isolation amplification, level shifting, and bias calibration on four original voltage analog signals and one original current analog signal to eliminate common-mode interference and high-frequency noise, generating five conditioned analog signals. The synchronous signal conditioning and conversion unit also includes an analog-to-digital converter (ADC) for synchronous sampling and high-resolution analog-to-digital conversion of the five conditioned analog signals, generating a synchronous digital sampling dataset containing V1, V2, V3, V4, and I1.

[0063] The online circuit status diagnostic unit is used to receive synchronous digital sampling datasets and diagnose the operating status of the equalization main circuit in real time based on voltage logic relationships and current information.

[0064] Determine the equality relationship between the values ​​of V1, V3, V4, and V2, and the value of I1. If V1 = V3 = V4 ≠ V2, then the fuse F1 is diagnosed as blown, generating the first fault code. If V1 ≠ V3 = V4 = V2, then the shunt trip circuit breaker K1 is diagnosed as open, generating the second fault code. If V1 = V3 ≠ V4 = V2 and I1 = 0, then the equalization function is diagnosed as not started or the DC-DC equalization module is not working, generating the third status code. If V1 = V3 ≠ V4 = V2 and I1 ≠ 0, then the DC-DC equalization module is diagnosed as running, generating the fourth status code. If V1 = V3 = V4 = V2 and I1 ≠ 0, then the parallel equalization module is diagnosed as running, generating the fifth status code.

[0065] The synchronous digital sampling dataset is combined with the generated status code or fault code and timestamped to form a sampling and status diagnosis dataset, which is then fed back and uploaded to the control unit to execute the corresponding second closed-loop control strategy.

[0066] In this embodiment of the invention, the sampling module consists of a multi-channel voltage sampling unit, a balanced current sampling unit, a synchronous signal conditioning and conversion unit, and an online circuit state diagnostic unit. The multi-channel voltage sampling unit uses voltage sensors to collect the inter-electrode voltage V1 of the first battery cluster, the inter-electrode voltage V2 of the second battery cluster, the input voltage V3 of the balanced module, and the output voltage V4 of the balanced module, respectively. During acquisition, the voltage sensors suppress the potential difference interference between battery clusters through a high common-mode rejection ratio, converting the four voltage signals into raw analog voltage signals that meet the requirements of subsequent processing. The circuit logic is that a differential amplifier circuit receives the voltage difference signal between the positive and negative terminals of the battery clusters and transmits it to the output terminal through an isolation device to avoid the influence of the high voltage of the main circuit on the signal processing circuit. The balanced current sampling unit uses a Hall current sensor connected in series in the balanced main circuit to collect the balanced current. Through the magnetic balance principle, the main circuit current is converted into a raw analog current signal proportional to the current. The sensor output signal has a linear correspondence with the main circuit current, realizing lossless current acquisition. The synchronous signal conditioning and conversion unit receives four raw voltage analog signals and one raw current analog signal, and sequentially performs anti-aliasing filtering, isolation amplification, level shifting, and bias calibration. The anti-aliasing filtering uses a passive RC low-pass filter to filter out high-frequency noise higher than half the ADC sampling frequency. The isolation amplification uses an optocoupler to achieve electrical isolation between the analog signal and the digital circuit, eliminating common-mode interference and generating five conditioned analog signals. The analog-to-digital converter (ADC) performs synchronous sampling and high-resolution analog-to-digital conversion on the five conditioned analog signals. The sampling frequency is set to 10kHz and the resolution is set to 16 bits. Synchronous sampling ensures that the five signals are acquired at the same time. After conversion, a synchronous digital sampling dataset containing V1, V2, V3, V4, and I1 is generated. The online circuit status diagnostic unit receives synchronous digital sampling datasets and diagnoses the operating status of the equalization main circuit and control and protection modules in real time based on voltage logic relationships and current information. The diagnostic logic is as follows: if V1=V3=V4≠V2, it diagnoses that fuse F1 has blown and generates the first fault code; if V1≠V3=V4=V2, it diagnoses that the shunt trip circuit breaker K1 is in the open state and generates the second fault code; if V1=V3≠V4=V2 and I1=0, it diagnoses that the equalization function has not been activated or the DC-DC equalization module has not been activated. The system is in operation, generating a third status code. If V1=V3≠V4=V2 and I1≠0, the diagnostic DC-DC equalization module is running, generating a fourth status code. If V1=V3=V4=V2 and I1≠0, the diagnostic parallel equalization module is running, generating a fifth status code. The synchronous digital sampling dataset is combined with the generated status code or fault code and a timestamp is added to form a sampling and status diagnostic dataset. This dataset is then fed back to the control unit via the communication line, thereby executing the corresponding second closed-loop control strategy.

[0067] Furthermore, the online circuit status diagnostic unit also includes:

[0068] The system acquires V1, V3, V4, V2, and I1 data sequences from multiple consecutive sampling periods in a synchronous digital sampling dataset. A moving average filter is applied to effectively suppress random sampling noise and short-term interference, generating a smoothed multi-period voltage and current dataset. Based on this dataset, the rate of change of the difference between V3 and V4 during adjacent sampling periods, as well as the trend and fluctuation of I1, are calculated. Combining the rate of change of the difference and the trend and fluctuation, the sampling and status diagnosis dataset is dynamically corrected and its status confirmed.

[0069] When the basic logic determines that the DC-DC equalization module is running, if the rate of change of the difference between V3 and V4 is consistently at an extremely low value and the trend of I1 is stable with fluctuations less than a preset threshold, then the DC-DC equalization module is confirmed to be in a steady-state buck energy transfer state, and a steady-state DC-DC operation sub-state code is generated. When the basic logic determines that the DC-DC equalization module is running, if the rate of change of the difference between V3 and V4 has a high-frequency pulsating component corresponding to the PWM switching frequency and the waveform of I1 exhibits corresponding pulsating characteristics, then the power switch in the DC-DC equalization module is confirmed to be in a normal PWM switching state, and a PWM switching operation sub-state code is generated. When the basic logic determines that the parallel equalization module is running, the theoretical calculation value needs to be further calculated. The theoretical calculation value is I1_cal = (V1 - V2) / (2Rn). If the deviation between the measured I1 and I1_cal continuously exceeds a preset proportional threshold, then a parallel loop contact resistance abnormality warning code is generated and appended to the fifth state code.

[0070] When the basic logic cannot explicitly match any preset condition, the historical status code sequence is invoked for working mode tracking and reasoning. If the status code of the previous cycle is the fourth status code and the voltage relationship of the current cycle satisfies V1=V3=V4=V2 and I1≠0, it is determined to be a transient process in which the equalization mode has just switched from DC-DC equalization to parallel equalization, and a mode switching transient identifier code is generated. The final status code, sub-status code, warning code or transient identifier code after correction and confirmation are recombined and associated with the smoothed multi-cycle voltage and current dataset to generate a highly reliable sampling and status diagnosis dataset.

[0071] In this embodiment of the invention, the online circuit state diagnostic unit acquires V1, V3, V4, V2 and I1 data sequences from multiple consecutive sampling periods in the synchronous digital sampling dataset, performs moving average filtering, sets the filtering window length to 5 sampling periods, and calculates the arithmetic mean of the data within the window. For example, if the I1 values ​​for 5 consecutive sampling periods are 60.5A, 60.7A, 60.6A, 60.8A and 60.5A, the smoothed value after moving average is (60.5+60.7+60.6+60.8+60.5) / 5=60.62A, suppressing random sampling noise and short-term interference, and generating a smoothed multi-cycle voltage and current dataset. Based on a multi-cycle voltage and current dataset, the rate of change of the difference between V3 and V4 during adjacent sampling cycles is calculated. The formula for the rate of change is Δ(V3-V4) / Δt, where Δt is the sampling cycle interval. In this embodiment, Δt = 0.1ms. Simultaneously, the trend and fluctuation of I1 are calculated. The trend is determined by the difference in I1 between adjacent cycles, and the fluctuation is determined by the deviation range between the I1 data and the smoothed value, generating an auxiliary dataset for voltage change rate and current trend. Combining the auxiliary dataset for voltage change rate and current trend, the sampling and state diagnosis datasets are dynamically corrected and their states confirmed. When the basic logic determines that the DC-DC equalization module is running, if the rate of change of the difference between V3 and V4 is consistently extremely low and the trend of I1 is stable with fluctuations less than a preset threshold (set to 0.5A), then the DC-DC equalization module is confirmed to be in a steady-state buck energy transfer state, generating a steady-state DC-DC operation sub-state code. If the rate of change of the difference between V3 and V4 has a high-frequency pulsation component corresponding to the PWM switching frequency (set to 20kHz), and the waveform of I1 exhibits corresponding pulsation characteristics, then the DC-DC equalization module is confirmed to be in a steady-state buck energy transfer state. If the power switch in the DC-DC equalization module is in a normal PWM switching state, a PWM switching operation sub-state code is generated. When the basic logic determines that the parallel equalization module is running, the theoretical calculation value needs to be further calculated. The theoretical calculation value is I1_cal=(V1-V2) / (2Rn). In this embodiment, Rn=51mΩ. If V1-V2=0.6V, then I1_cal=0.6V / (2×0.051Ω)=5.88A. If the deviation between the measured I1 and I1_cal continues to exceed the preset ratio threshold, which is set to 10%, a parallel loop contact resistance abnormality warning code is generated and appended to the fifth state code.When the basic logic cannot explicitly match any preset condition, the historical status code sequence is invoked for working mode tracking and reasoning. If the status code of the previous cycle is the fourth status code and the voltage relationship of the current cycle satisfies V1=V3=V4=V2 and I1≠0, it is determined to be a transient process in which the equalization mode has just switched from DC-DC equalization to parallel equalization, and a mode switching transient identifier code is generated. The final status code, sub-status code, warning code or transient identifier code after correction and confirmation are recombined and associated with the smoothed multi-cycle voltage and current dataset to generate a highly reliable sampling and status diagnosis dataset, ensuring the stability and accuracy of the status diagnosis results.

[0072] Furthermore, such as Figure 4 As shown, the feedback uploaded to the control unit to execute the corresponding second closed-loop control strategy includes:

[0073] If the sampling and status diagnosis dataset fed back to the control unit confirms that the shunt trip circuit breaker K1 and fuse F1 are normally not disconnected, then check whether Tmax is less than the upper temperature limit T_high and whether the balancing current I1 is less than the balancing current threshold. If so, return to re-execute the first closed-loop control strategy; otherwise, disconnect the shunt trip circuit breaker K1 through the control unit; otherwise, notify the BMS to stop the balancing protection.

[0074] In this embodiment of the invention, after the sampling module uploads the highly reliable sampling and status diagnosis dataset to the control unit, the control unit first parses the status codes and fault codes in the dataset to confirm the operating status of the shunt trip circuit breaker K1 and the fuse F1. If the status code does not contain the first fault code and the second fault code, it is confirmed that the shunt trip circuit breaker K1 and the fuse F1 are normally not disconnected. Subsequently, the control unit calls the internally stored upper temperature limit T_high and equalization current threshold. In this embodiment, the upper temperature limit T_high is 60℃ and the equalization current threshold is 75A. The highest cell temperature Tmax is compared with T_high, and the equalization current I1 is compared with the equalization current threshold. If Tmax < 60℃ and If I1 < 75A, the control unit returns to re-execute the first closed-loop control strategy, recalculates the current voltage difference ΔV_new and SOC difference ΔSOC_new to determine whether to start the DC-DC equalization module or the parallel equalization module; if Tmax ≥ 60℃ or I1 ≥ 75A, the control unit outputs a shunt trip drive signal to drive the shunt trip circuit breaker K1 to trip, cutting off the equalization main circuit to prevent cell overheating or overcurrent damage; if the status code contains the first fault code or the second fault code, that is, confirming that the shunt trip circuit breaker K1 is open or the fuse F1 is blown, the control unit generates an equalization protection stop command, notifies the BMS through the communication line, and synchronously records the fault code information, realizing the second closed-loop control strategy of the equalization process.

[0075] Furthermore, such as Figure 3As shown, Figure 3 This is a schematic diagram of the energy flow direction of the DC-DC equalization module in this embodiment. The bidirectional BUCK circuit is a non-isolated structure based on a bidirectional BUCK converter, including a first filter capacitor C1, a second filter capacitor C2, a first power switch Q1, a second power switch Q2, a first freewheeling diode D1, a second freewheeling diode D2, and a power storage inductor L1;

[0076] The first filter capacitor C1 is connected in parallel between the positive and negative terminals of the first battery cluster;

[0077] The second filter capacitor C2 is connected in parallel between the positive and negative terminals of the second battery cluster;

[0078] The first power switch Q1, the second power switch Q2, and the power storage inductor L1 are connected in series between the first battery cluster and the second battery cluster. The power storage inductor L1 is connected between the first power switch Q1 and the second power switch Q2. The source of the first power switch Q1 is connected to the positive terminal of the first battery cluster, and the drain of the first power switch Q1 is connected to one end of the power storage inductor L1. The source of the second power switch Q2 is connected to the positive terminal of the second battery cluster, and the drain of the second power switch Q2 is connected to the other end of the power storage inductor L1.

[0079] The first freewheeling diode D1 is connected in parallel between the first filter capacitor C1 and the first power switch Q1. The anode of the first freewheeling diode D1 is connected to the negative terminal of the first battery cluster, and the cathode of the first freewheeling diode D1 is connected between the drain of the first power switch Q1 and the power storage inductor L1.

[0080] The second freewheeling diode D2 is connected in parallel between the second filter capacitor C2 and the second power switch Q2. The anode of the second freewheeling diode D2 is connected to the negative terminal of the second battery cluster, and the cathode of the second freewheeling diode D2 is connected between the drain of the second power switch Q2 and the power storage inductor L1.

[0081] When the balancing direction is from the first battery cluster to the second battery cluster, the control unit controls the second power switch Q2 to remain on and applies an adjusted PWM drive signal to the first power switch Q1. At this time, the first power switch Q1, the first freewheeling diode D1, the power storage inductor L1 and the second power switch Q2 constitute a first buck converter from the first filter capacitor C1 to the second filter capacitor C2, wherein the first freewheeling diode D1 serves as a freewheeling path during the Q1 turn-off period.

[0082] When the balancing direction shifts from the second battery cluster to the first battery cluster, the control unit controls the first power switch Q1 to remain on and applies an adjusted PWM drive signal to the second power switch Q2. At this time, the first power switch Q1, the second freewheeling diode D2, the power storage inductor L1, and the second power switch Q2 constitute a second buck converter from the second filter capacitor C2 to the first filter capacitor C1, wherein the second freewheeling diode D2 serves as a freewheeling path during the Q2 turn-off period.

[0083] In this embodiment of the invention, the bidirectional BUCK circuit adopts a non-isolated structure based on a bidirectional BUCK converter, consisting of a first filter capacitor C1, a second filter capacitor C2, a first power switch Q1, a second power switch Q2, a first freewheeling diode D1, a second freewheeling diode D2, and a power storage inductor L1. The first filter capacitor C1 is connected in parallel between the positive and negative terminals of the first battery cluster, with a capacitance of 470μF and a voltage rating of 450V. It is used for high-frequency filtering and energy buffering of the output voltage of the first battery cluster, absorbing voltage ripple generated during DC-DC equalization, and stabilizing the bus voltage on the first battery cluster side. The circuit logic is that when there are high-frequency fluctuations in the output voltage of the first battery cluster, the first filter capacitor C1 smooths out the fluctuations through charging and discharging, maintaining a stable bus voltage. The second filter capacitor C2 is connected in parallel between the positive and negative terminals of the second battery cluster, with parameters identical to the first filter capacitor C1. It is used for high-frequency filtering and energy buffering of the output voltage of the second battery cluster, stabilizing the bus voltage on the second battery cluster side. A first power switch Q1, a second power switch Q2, and a power storage inductor L1 are connected in series between the first battery cluster and the second battery cluster. Both the first power switch Q1 and the second power switch Q2 are N-channel enhancement-mode power MOSFETs with a withstand voltage of 650V and an on-resistance of 10mΩ. The power storage inductor L1 is 1mH with a saturation current of 100A. The power storage inductor L1 is connected between the first power switch Q1 and the second power switch Q2. The source of the first power switch Q1 is connected to the positive terminal of the first battery cluster, and the drain of the first power switch Q1 is connected to one end of the power storage inductor L1. The source of the second power switch Q2 is connected to the positive terminal of the second battery cluster, and the drain of the second power switch Q2 is connected to the other end of the power storage inductor L1, forming a bidirectional energy transmission main circuit. The first freewheeling diode D1 is connected in parallel between the first filter capacitor C1 and the first power switch Q1. The first freewheeling diode D1 is a fast recovery diode with a reverse withstand voltage of 650V and a forward conduction current of 100A. The anode of the first freewheeling diode D1 is connected to the negative terminal of the first battery cluster, and the cathode of the first freewheeling diode D1 is connected between the drain of the first power switch Q1 and the power storage inductor L1. This provides a freewheeling path for the power storage inductor L1 when the first power switch Q1 is turned off, maintaining continuous inductor current. The second freewheeling diode D2 is connected in parallel between the second filter capacitor C2 and the second power switch Q2, with the same parameters as the first freewheeling diode D1. The anode of the second freewheeling diode D2 is connected to the negative terminal of the second battery cluster, and the cathode of the second freewheeling diode D2 is connected between the drain of the second power switch Q2 and the power storage inductor L1. This provides a freewheeling path for the power storage inductor L1 when the second power switch Q2 is turned off.

[0084] Among them, such as Figure 3As shown by the red dashed line, when the balancing direction is from the first battery cluster to the second battery cluster, the control unit outputs a continuous high-level drive signal to the gate of the second power switch Q2, keeping Q2 fully on. Simultaneously, a PWM drive signal, regulated by a dual closed-loop control of voltage and SOC, is applied to the first power switch Q1. The PWM signal frequency is set to 20kHz, and the duty cycle is calculated from the correction amount ΔD output by the inner-loop voltage closed-loop controller and the initial duty cycle. At this time, the first power switch Q1, the first freewheeling diode D1, the power storage inductor L1, and the second power switch Q2 constitute the first buck converter from the first filter capacitor C1 to the second filter capacitor C2. Specifically, when the balancing direction is V1-V2, the controlled switch is Q1, and the continuously conducting transistor is Q2. The circuit operates in two stages: on and off. On stage (Q1 on): The control unit outputs a high-level PWM signal to drive Q1 to conduct, and simultaneously outputs a continuous high-level signal to keep Q2 on. The current path is: positive terminal of the first battery cluster - source of Q1 - drain of Q1 - left end of power storage inductor L1 - right end of L1 - drain of Q2 - source of Q2 - C2 (energy storage or filtering) and positive terminal of the second battery cluster - negative terminal of the second battery cluster, returning to the negative terminal of the first battery cluster through the internal loop of the second battery cluster. During this stage, voltage V1 is applied across L1, and the current in L1 rises linearly at a rate that satisfies ΔI_L=(V1-V2)×Δt_on / L1. L1 stores magnetic energy. Q2 is turned on in synchronous rectification mode, and the channel provides a low-resistance path. The on-state voltage drop is much lower than that of the diode. D1 is reverse biased and cut off because the anode potential (right end of L1 ≈ V2) is lower than the cathode potential (left end of L1 ≈ V1). D2 is also reverse biased and cut off because the anode potential (right end of L1 ≈ V2) is lower than the cathode potential (left end of L1 ≈ V1). Turn-off stage (Q1 turn-off): The control unit outputs a low-level PWM to drive Q1 to turn off, while Q2 remains on. To maintain continuous current flow, L1 generates an induced electromotive force. The potential at its left end is higher than that at its right end, and the current direction remains unchanged. The freewheeling path is: right end of L1 - drain of Q2 - source of Q2 - positive terminal of C2 and the second battery cluster - negative terminal of the second battery cluster - anode of D1 - cathode of D1 - left end of L1. Simultaneously, the channel of Q2 provides a low-resistance path for the freewheeling current. During this stage, L1 releases magnetic energy, and the current decreases linearly at a rate satisfying ΔI_L=(V2)×Δt_off / L1. D1 is positively biased and conducts because its anode potential (right end of L1 ≈ V2) is higher than its cathode potential (negative terminal of the first battery cluster), providing a freewheeling path for L1. D2 remains cut off because its anode potential is lower than its cathode potential, preventing reverse energy leakage.

[0085] like Figure 3As shown by the blue dashed line, when the balancing direction is from the second battery cluster to the first battery cluster, the control unit outputs a continuous high-level drive signal to the gate of the first power switch Q1, keeping Q1 fully on. Simultaneously, a PWM drive signal, regulated by a dual closed-loop control of voltage and SOC, is applied to the second power switch Q2, with the PWM signal frequency consistent with the previous signal. At this time, the first power switch Q1, the second freewheeling diode D2, the power storage inductor L1, and the second power switch Q2 constitute a second-direction buck converter from the second filter capacitor C2 to the first filter capacitor C1. Specifically, when the balancing direction is V2-V1, the controlled switch is Q2, and the continuously conducting transistor is Q1. The circuit operates in two phases: on and off. On phase (Q2 on): The control unit outputs a high-level PWM signal to drive Q2 to conduct, and simultaneously outputs a continuous high-level signal to keep Q1 on. The current path is: positive terminal of the second battery cluster - source of Q2 - drain of Q2 - right end of L1 - left end of L1 - drain of Q1 - source of Q1 - C1 and positive terminal of the first battery cluster - negative terminal of the first battery cluster, returning to the negative terminal of the second battery cluster through the internal loop of the first battery cluster. During this stage, voltage V2 is applied across L1, and the current in L1 rises linearly at a rate satisfying ΔI_L=(V2-V1)×Δt_on / L1. L1 stores magnetic energy. Q1 is turned on in synchronous rectification mode, and the channel provides a low-resistance path. D2 is reverse-biased and cut off because the anode potential (left end of L1 ≈ V1) is lower than the cathode potential (right end of L1 ≈ V2). D1 is also reverse-biased and cut off because the anode potential (left end of L1 ≈ V1) is lower than the cathode potential (right end of L1 ≈ V2). Turn-off stage (Q2 turn-off): The control unit outputs a low-level PWM to drive Q2 to turn off, while Q1 remains on. L1 generates an induced electromotive force to maintain continuous current, with the right end potential higher than the left end potential, and the current direction remains unchanged. The freewheeling path is: left end of L1 - drain of Q1 - source of Q1 - positive terminal of C1 and first battery cluster - negative terminal of first battery cluster - anode of D2 - cathode of D2 - right end of L1. Simultaneously, the Q1 channel provides a low-resistance path for the freewheeling current. During this stage, L1 releases magnetic energy, and the current decreases linearly at a rate satisfying ΔI_L=(V1)×Δt_off / L1. D2 is positively biased and conducts because its anode potential (left end of L1 ≈ V1) is higher than its cathode potential (negative terminal of the second battery cluster), providing a freewheeling path for L1. D1 remains cut off because its anode potential is lower than its cathode potential, preventing reverse energy leakage.

[0086] Furthermore, such as Figure 5 As shown, the present invention also provides a dual-closed-loop equalization control method for voltage and SOC between two battery clusters. This method is implemented based on the dual-closed-loop equalization control system for voltage and SOC between two battery clusters as described above. The dual-closed-loop equalization control method for voltage and SOC between two battery clusters includes the following steps:

[0087] S01: System power-on initialization, the control unit establishes communication connection with the battery management system BMS, sampling module, DC-DC equalization module and parallel equalization module, obtains the rated parameters of the first battery cluster and the second battery cluster, the preset target equalization current and the preset threshold of each parameter, and generates a basic configuration parameter set;

[0088] S02: Execute the first closed-loop control strategy, cyclically acquire the inter-electrode voltages V1 and V2 between the first and second battery clusters, the real-time state of charge (SOC1 and SOC2), and the highest temperature Tmax and lowest temperature Tmin of the cells within the battery clusters. Calculate the voltage difference ΔV and the SOC difference ΔSOC, generating a real-time state and difference dataset. Based on the real-time state and difference dataset, determine whether the temperature pre-protection condition, the first-level equalization trigger condition, or the second-level equalization trigger condition are met. If so, generate an equalization start command and an energy transfer direction identifier, and determine the equalization direction and the corresponding equalization mode selection signal to start the DC-DC equalization module or the parallel equalization module; otherwise, generate an equalization shutdown command and return to the previous state. The system re-monitors; it determines the corresponding target equalization module based on the equalization mode selection signal, and continuously receives voltages V1, V2, V3, V4 and equalization current I1 uploaded by the sampling module, as well as SOC1 and SOC2 periodically uploaded by the BMS, generating a dynamic equalization real-time feedback dataset; if it is a DC-DC equalization module, it performs dual closed-loop control of voltage and SOC, the outer loop SOC closed loop calculates the voltage reference adjustment amount with the goal of eliminating the SOC difference, and the inner loop voltage closed loop calculates the PWM duty cycle with the goal of eliminating the voltage difference and tracking the outer loop output, dynamically adjusting the PWM drive signal; if it is a parallel equalization module, it maintains the DC contactor KM1 engaged, limits the equalization current I1 through the equivalent internal resistance, and monitors the equalization current I1;

[0089] S03: Obtain the corresponding voltages V1, V2, V3, V4, equalization current I1, and maximum temperature Tmax to diagnose the main circuit status. Based on the main circuit status, if the shunt trip circuit breaker K1 and fuse F1 are confirmed to be normally not disconnected, then check whether Tmax is less than the upper temperature limit T_high and whether the equalization current I1 is less than the equalization current threshold. If so, return to S02 to re-execute the first closed-loop control strategy. If not, disconnect the shunt trip circuit breaker K1 through the control unit. Otherwise, notify the BMS equalization protection to stop, thereby ending the equalization process, and return to S02 to continue monitoring.

[0090] In this embodiment of the invention, upon power-on initialization, the control unit establishes a stable communication connection with the battery management system (BMS), sampling module, DC-DC equalization module, and parallel equalization module through a preset communication protocol. It obtains the rated parameters of the first and second battery clusters through the communication interface, including rated voltage Ve=325.8V, rated internal resistance Rn=51mΩ, rated capacity 304Ah, preset target equalization current Ij=60.8A, and preset thresholds for each parameter, including lower temperature limit T_low=0℃, upper temperature limit T_high=60℃, first voltage threshold V_th1=6V, second voltage threshold V_th2=0.3V, first SOC threshold SOC_th1=5%, second SOC threshold SOC_th2=1%, and equalization current threshold 75A. These parameters are integrated and stored through internal hardware registers to generate a basic configuration parameter set. The first closed-loop control strategy is executed. The control unit acquires the inter-electrode voltage V1 of the first battery cluster and the inter-electrode voltage V2 of the second battery cluster through the acquisition interface of the sampling module with a period of 10ms. It also acquires the real-time state of charge (SOC1, SOC2) and the highest temperature Tmax and lowest temperature Tmin of the cells in the battery cluster through the BMS communication interface. The absolute value of the voltage difference ΔV = |V1-V2| is calculated. For example, when V1 = 332.4V and V2 = 325.8V, ΔV = |332.4-325.8| = 6.6V. The absolute value of the SOC difference ΔSOC = |SOC1-SOC2| is calculated. For example, when SOC1 = 81% and SOC2 = 75%, ΔSOC = |81%-75%| = 6%. All data are integrated to generate a real-time state and difference dataset.Based on the real-time status and difference dataset, the control unit performs a judgment through the hardware logic judgment circuit. First, it judges the temperature pre-protection condition, i.e., T_low < Tmin and Tmax < T_high. Then, it judges whether the first-level equalization trigger condition is met, i.e., ΔV > V_th1 or ΔSOC > SOC_th1. Alternatively, it judges whether the first-level equalization trigger condition and the second-level equalization trigger condition are not met, i.e., ΔV ≤ V_th1 and ΔSOC ≤ SOC_th1, ΔV ≥ V_th2 and ΔSOC ≥ SOC_th2. If so, the command generation circuit generates an equalization start command and an energy transfer direction identifier. The energy transfer direction identifier is based on V1 and V2, SOC... The values ​​of C1 and SOC2 are determined. If V1 > V2 and SOC1 > SOC2, energy is transferred from the first battery cluster to the second battery cluster. If V2 > V1 and SOC2 > SOC1, energy is transferred from the second battery cluster to the first battery cluster. Simultaneously, the balancing direction and the corresponding balancing mode selection signal are determined. A DC-DC balancing mode selection signal is generated when ΔV > 6V or ΔSOC > 5%. A parallel balancing mode selection signal is generated when ΔV ≤ 6V and ΔSOC ≤ 5%, and ΔV ≥ 0.3V or ΔSOC ≥ 1%, to activate the DC-DC balancing module or the parallel balancing module. Otherwise, a balancing shutdown command is generated, returning to the re-monitoring state, and data is continuously collected in a loop. Based on the balancing mode selection signal, the corresponding target balancing module is determined. The control unit continuously receives voltages V1, V2, V3, and V4 and balancing current I1 uploaded by the sampling module, as well as SOC1 and SOC2 periodically uploaded by the BMS, with a 10ms periodicity. The receiving frequency is consistent with the output frequency of the sampling module and the BMS. All data are integrated to generate a dynamic balancing real-time feedback dataset. If it is a DC-DC equalization module, it implements dual closed-loop control of voltage and SOC. The control unit internally builds an outer-loop SOC closed-loop controller, using ΔSOC as input and aiming to equalize the two SOC clusters. It calculates the voltage reference adjustment ΔV_ref using preset proportional and integral coefficients. Then, an inner-loop voltage closed-loop controller is built, using ΔV and ΔV_ref as combined inputs, aiming to eliminate voltage differences. It calculates the PWM duty cycle using another set of independent proportional and integral coefficients, dynamically adjusting the PWM drive signal. The circuit logic is implemented by adjusting the duty cycle of the power switching transistors. The control unit controls the energy transfer power of the bidirectional BUCK circuit to achieve efficient energy balance transfer. If it is a parallel equalization module, the control unit continuously outputs a 24V pull-in command to maintain the continuous pull-in state of the DC contactor KM1. At this time, the two battery clusters form a parallel circuit. The magnitude of the equalization current I1 is determined by the voltage difference ΔV and the total internal resistance 2Rn of the two battery clusters. The specific calculation is I1=ΔV / (2Rn). For example, when ΔV=0.6V, I1=0.6V / 0.102Ω≈5.88A. The control unit continuously monitors the real-time value of the equalization current I1 through the sampling module.The control unit acquires the corresponding voltages V1, V2, V3, V4, balancing current I1, and maximum temperature Tmax. It diagnoses the main circuit status using voltage logic and current values. Based on the main circuit status, if the shunt trip circuit breaker K1 and fuse F1 are confirmed to be functioning normally and not disconnected, the hardware logic circuit reconfirms that Tmax < T_high and I1 < balancing current threshold. If so, it returns to S02 to re-execute the first closed-loop control strategy, continuously monitoring and adjusting. If not, the control unit outputs a disconnect command, controlling the shunt trip circuit breaker K1 to quickly disconnect the balancing main circuit and execute overcurrent or overheat protection. If the main circuit status is abnormal, i.e., K1 disconnects or F1 blows, the control unit notifies the BMS to stop the balancing protection via the communication line, thus ending the balancing process and returning to S02 to continue monitoring, ensuring system safety.

[0091] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A two-cluster battery inter-voltage and SOC double closed-loop equalization control system, characterized in that, It includes a battery management system (BMS), a first battery cluster, a second battery cluster, a sampling module, a control and protection module, and an equalization module, wherein the equalization module includes a DC-DC equalization module and a parallel equalization module; The battery management system (BMS) is used to obtain the state of charge (SOC1) of the first battery cluster, the state of charge (SOC2) of the second battery cluster, and the highest temperature (Tmax) and lowest temperature (Tmin) of the cells in the two battery clusters, and send them to the control and protection module. The first battery cluster and the second battery cluster are each composed of multiple strings of cells connected in series, and each has an equivalent internal resistance; The sampling module is electrically connected to the first battery cluster, the second battery cluster, the input side of the equalization module, the output side of the equalization module, and the equalization main circuit of the equalization module, respectively, and is used to collect the inter-electrode voltage V1 of the first battery cluster, the inter-electrode voltage V2 of the second battery cluster, the input side voltage V3 of the equalization module, the output side voltage V4 of the equalization module, and the equalization current I1 flowing through the equalization module. The control and protection module includes a shunt trip circuit breaker K1, a fuse F1, and a control unit. The shunt trip circuit breaker K1 is connected between the first battery cluster and the input side of the equalization module. The fuse F1 is connected between the output side of the equalization module and the second battery cluster. The control unit is communicatively connected to the battery management system (BMS), the sampling module, the DC-DC equalization module, and the parallel equalization module. The input of the DCDC equalization module is connected to the first battery cluster through the shunt trip circuit breaker K1, and the output is connected to the second battery cluster through the fuse F1. The DCDC equalization module is specifically a bidirectional BUCK circuit architecture, which is used to perform efficient energy balance transfer when the voltage difference or SOC difference between the first battery cluster and the second battery cluster is greater than the corresponding first preset threshold. The parallel balancing module consists of a DC contactor KM1 combined with the equivalent internal resistance of two battery clusters. The input terminal of the parallel balancing module is connected to the first battery cluster through one end of the DC contactor KM1, and the output terminal is connected to the second battery cluster through the other end of the DC contactor KM1. It is used to perform low-loss energy balance transfer when the voltage difference or SOC difference between the first battery cluster and the second battery cluster is ≤ the corresponding first preset threshold and ≥ the corresponding second preset threshold. The control unit receives all electrical sampling data from the sampling module and battery status data sent by the BMS, and executes the first closed-loop control strategy of verification and dynamic equalization. Based on the comprehensive judgment of voltage difference and SOC difference, it generates an equalization start command and determines the equalization mode selection signal. Based on the equalization mode selection signal, it determines the target equalization module to start. If it is a DC-DC equalization module, it dynamically generates a PWM drive signal to start DC-DC equalization, or if it is a parallel equalization module, it generates a DC contactor KM1 energizing command to start parallel equalization. At the same time, the sampling module diagnoses the main circuit status and feeds it back to the control unit based on voltage V1, V2, V3, V4, equalization current I1 and maximum temperature Tmax, thereby executing the corresponding second closed-loop control strategy.

2. The dual-cluster inter-battery voltage and SOC dual closed-loop equalization control system according to claim 1, characterized in that, The control and protection module executes a first closed-loop control strategy of verification and dynamic balancing to initiate DC-DC balancing or parallel balancing, including: After the system is powered on, the control unit establishes a communication connection with the battery management system (BMS), sampling module, DC-DC equalization module and parallel equalization module, receives the equalization function enable command issued by the BMS, and obtains the rated voltage Ve, rated internal resistance Rn, preset target equalization current Ij and preset threshold values ​​of each parameter of the first battery cluster and the second battery cluster, and generates a basic configuration parameter set. Based on the basic configuration parameter set, the real-time voltages V1 and V2 uploaded by the sampling module and SOC1, SOC2, Tmax, and Tmin uploaded by the BMS are received in a loop. The absolute value of the voltage difference ΔV = |V1-V2| and the absolute value of the SOC difference ΔSOC = |SOC1-SOC2| are calculated, and the extreme value data of the cell temperature are obtained to generate a real-time status and difference dataset. Based on the real-time status and difference dataset, it is determined whether the temperature pre-protection condition is met, specifically the lower temperature limit T_low < Tmin and Tmax < upper temperature limit T_high. Simultaneously, it is determined whether the dual equalization trigger condition is met, specifically the first equalization trigger condition ΔV > first voltage threshold V_th1 or ΔSOC > first SOC threshold SOC_th1, and the second equalization trigger condition ΔV < second voltage threshold V_th2 and ΔSOC < second SOC threshold SOC_th2. The judgment results of the temperature pre-protection condition and the dual equalization trigger condition are logically ANDed to generate the first closed-loop test result. If the first closed-loop test result indicates that the temperature protection is not triggered and the single-level equalization trigger condition is met or the double-level equalization trigger condition is not met, an equalization start command and an energy transfer direction identifier are generated. The energy transfer direction identifier is determined by comparing the values ​​of V1 and V2, and SOC1 and SOC2, specifically transferring from the battery cluster with the larger value to the battery cluster with the smaller value. The equalization direction is determined based on the energy transfer direction identifier, and the equalization mode selection signal for the corresponding direction is determined based on the equalization direction, the equalization start command, and the real-time status and difference dataset to start the DC-DC equalization module or the parallel equalization module. If the first closed-loop test result indicates that the temperature protection is triggered, or the single-level equalization trigger condition is not met but the double-level equalization trigger condition is met, an equalization shutdown command is generated and the BMS is notified to stop equalization, and the control unit enters a low-power periodic inspection state. After starting the DC-DC equalization module or parallel equalization module, the corresponding dynamic equalization control strategy is executed.

3. The dual closed-loop equalization control system for voltage and SOC between two battery clusters according to claim 2, characterized in that, The step of determining the equalization mode selection signal in the corresponding direction to activate the DC-DC equalization module or the parallel equalization module includes: If temperature protection is not triggered, the absolute value of the current voltage difference ΔV is compared in real time with the first voltage threshold V_th1 and the second voltage threshold V_th2, and the absolute value of the current SOC difference ΔSOC is compared with the first SOC threshold SOC_th1 and the second SOC threshold SOC_th2. If ΔV > V_th1 or ΔSOC > SOC_th1, the DC-DC equalization mode is determined to be applicable, a first equalization mode selection signal is generated, and the corresponding drive interface of the DC-DC equalization module is activated. If ΔV ≤ V_th1 and ΔSOC ≤ SOC_th1, ΔV ≥ V_th2 or ΔSOC ≥ SOC_th2, the parallel equalization mode is determined to be applicable, a second equalization mode selection signal is generated, and the corresponding drive interface of the parallel equalization module is activated. Based on the first or second equalization mode selection signal and combined with the energy transfer direction identifier, the control unit calls the module drive interface parameters, initial control parameters, and safety parameters corresponding to the selected equalization mode and equalization direction to generate a target equalization module drive configuration set. The control unit sends a PWM drive signal containing the initial duty cycle to the DC-DC equalization module or sends a pull-in command to the DC contactor KM1 of the parallel equalization module based on the target equalization module drive configuration set, and simultaneously reads the real-time data of the side voltage V3, V4 and equalization current I1 fed back by the sampling module to generate a pre-action state verification dataset. Analyze the pre-action state verification dataset to verify whether the input-output voltage relationship of the DC-DC equalization module is consistent with the expected equalization direction, or to verify whether the circuit on / off state of the DC contactor KM1 of the parallel equalization module meets the command requirements. If the verification is successful, an equalization module ready confirmation signal is generated, and the DC contactor KM1 is controlled to perform a closing action to select to start the DC-DC equalization module or the parallel equalization module respectively.

4. The dual closed-loop equalization control system for voltage and SOC between two battery clusters according to claim 3, characterized in that, The dynamic balance control strategy executed after activating the DC-DC equalization module or parallel equalization module includes: Based on the equalization module readiness confirmation signal, the corresponding target equalization module is determined, and real-time data V1, V2, V3, V4, I1 uploaded by the sampling module and SOC1 and SOC2 periodically uploaded by the BMS are continuously received to generate a dynamic equalization real-time feedback dataset. When the target equalization module is a DC-DC equalization module, a dual closed-loop control based on a bidirectional BUCK circuit for voltage and SOC is executed: An outer-loop SOC closed-loop controller is established, using the SOC difference ΔSOC between the first and second battery clusters as input, and aiming for the final equality of the SOC values ​​of the two clusters. It performs calculations using a preset proportional-integral control algorithm, outputting a voltage reference adjustment ΔV_ref for the inner-loop voltage closed-loop control; an inner-loop voltage closed-loop controller is established, using the voltage difference ΔV and the voltage reference adjustment ΔV_ref as combined inputs to eliminate… In addition to the voltage difference between the two clusters being the direct control target and being processed, the output is used to adjust the PWM duty cycle correction amount ΔD in the bidirectional BUCK circuit corresponding to the equalization direction, generating an inner loop duty cycle correction instruction; based on the inner loop duty cycle correction instruction, combined with the initial duty cycle centrally stored in the target equalization module driver configuration, the real-time PWM duty cycle D_real is calculated, and according to the equalization direction, a PWM drive signal with dead time is generated and sent to the corresponding power switch control terminal in the DC-DC equalization module to adjust the transmission power and drive it to perform DC-DC equalization; When the target equalization module is a parallel equalization module, open-loop control based on equivalent internal resistance current limiting is executed: the DC contactor KM1 is kept in a continuously engaged state. At this time, the magnitude of the equalization current I1 is determined by the voltage difference ΔV between the two battery clusters and the sum of the total internal resistances of the two battery clusters, 2Rn, specifically I1 = ΔV / (2Rn). The equalization current I1 is continuously monitored by the sampling module to drive it to perform parallel equalization and transmit it to the control unit; the latest voltage difference ΔV_new and SOC difference ΔSOC_new are calculated, and it is determined whether the double equalization trigger condition is met. If it is met, an equalization completion command is generated and the BMS is notified to stop equalization.

5. The dual closed-loop equalization control system for voltage and SOC between two battery clusters according to claim 4, characterized in that, The voltage reference value adjustment ΔV_ref output includes: The SOC difference ΔSOC_current for each cycle is extracted from the dynamic equilibrium real-time feedback dataset, and the voltage reference value adjustment is calculated by calling the preset outer loop proportional coefficient Kp_soc and outer loop integral coefficient Ki_soc. The calculation expression is ΔV_ref(k)=Kp_soc×ΔSOC_current(k)+Ki_soc×ΣΔSOC_current(j), where k is the current control cycle number and j is the historical cycle number from the start of control to the current cycle, generating the original voltage adjustment amount without amplitude limiting. The original voltage adjustment amount without amplitude limiting is subjected to a combination of amplitude limiting and rate of change limiting. The amplitude limiting range is determined based on the rated voltage Ve of the battery cluster and the maximum adjustable voltage range of the DC-DC equalization module, and the rate of change limiting is determined based on the preset maximum voltage adjustment step size allowed in a single control cycle, generating ΔV_ref_limited after amplitude and rate of change limiting. The limited ΔV_ref_limited is combined with the voltage reference adjustment from the previous control cycle and subjected to a first-order hysteresis smoothing filter to suppress high-frequency fluctuations caused by SOC fluctuations or sampling noise, generating the final voltage reference adjustment ΔV_ref for the current cycle. The voltage reference adjustment ΔV_ref is then passed to the inner-loop voltage closed-loop controller as part of its voltage tracking target, and the SOC difference and voltage reference adjustment ΔV_ref for the current control cycle are stored for iterative calculation of integral terms and smoothing filtering in the next control cycle.

6. The dual closed-loop equalization control system for voltage and SOC between two battery clusters according to claim 2, characterized in that, The sampling module includes a multi-channel voltage sampling unit, a balanced current sampling unit, a synchronous signal conditioning and conversion unit, and an online circuit status diagnosis unit. The multi-channel voltage sampling unit is used to collect the inter-electrode voltage V1 of the first battery cluster, the inter-electrode voltage V2 of the second battery cluster, the input voltage V3 of the equalization module, and the output voltage V4 of the equalization module using voltage sensors, and generate four raw voltage analog signals. The equalization current sampling unit is used to collect the equalization current corresponding to the equalization main circuit using a Hall current sensor and generate a raw current analog signal. The synchronous signal conditioning and conversion unit is used to perform anti-aliasing filtering, isolation amplification, level shifting, and bias calibration on four original voltage analog signals and one original current analog signal to eliminate common-mode interference and high-frequency noise, generating five conditioned analog signals. The synchronous signal conditioning and conversion unit also includes an analog-to-digital converter (ADC) for synchronous sampling and high-resolution analog-to-digital conversion of the five conditioned analog signals, generating a synchronous digital sampling dataset containing V1, V2, V3, V4, and I1. The online circuit status diagnostic unit is used to receive synchronous digital sampling datasets and diagnose the operating status of the equalization main circuit in real time based on voltage logic relationships and current information. Determine the equality relationship between the values ​​of V1, V3, V4, and V2, and the value of I1. If V1 = V3 = V4 ≠ V2, then the fuse F1 is diagnosed as blown, generating the first fault code. If V1 ≠ V3 = V4 = V2, then the shunt trip circuit breaker K1 is diagnosed as open, generating the second fault code. If V1 = V3 ≠ V4 = V2 and I1 = 0, then the equalization function is diagnosed as not started or the DC-DC equalization module is not working, generating the third status code. If V1 = V3 ≠ V4 = V2 and I1 ≠ 0, then the DC-DC equalization module is diagnosed as running, generating the fourth status code. If V1 = V3 = V4 = V2 and I1 ≠ 0, then the parallel equalization module is diagnosed as running, generating the fifth status code. The synchronous digital sampling dataset is combined with the generated status code or fault code and timestamped to form a sampling and status diagnosis dataset, which is then fed back and uploaded to the control unit to execute the corresponding second closed-loop control strategy.

7. The dual closed-loop equalization control system for voltage and SOC between two battery clusters according to claim 6, characterized in that, The online circuit status diagnostic unit further includes: The system acquires V1, V3, V4, V2, and I1 data sequences from multiple consecutive sampling periods in a synchronous digital sampling dataset. A moving average filter is applied to effectively suppress random sampling noise and short-term interference, generating a smoothed multi-period voltage and current dataset. Based on this dataset, the rate of change of the difference between V3 and V4 during adjacent sampling periods, as well as the trend and fluctuation of I1, are calculated. Combining the rate of change of the difference and the trend and fluctuation, the sampling and status diagnosis dataset is dynamically corrected and its status confirmed. When the basic logic determines that the DC-DC equalization module is running, if the rate of change of the difference between V3 and V4 is consistently at an extremely low value and the trend of I1 is stable with fluctuations less than a preset threshold, then the DC-DC equalization module is confirmed to be in a steady-state buck energy transfer state, and a steady-state DC-DC operation sub-state code is generated. When the basic logic determines that the DC-DC equalization module is running, if the rate of change of the difference between V3 and V4 has a high-frequency pulsating component corresponding to the PWM switching frequency and the waveform of I1 exhibits corresponding pulsating characteristics, then the power switch in the DC-DC equalization module is confirmed to be in a normal PWM switching state, and a PWM switching operation sub-state code is generated. When the basic logic determines that the parallel equalization module is running, the theoretical calculation value needs to be further calculated. The theoretical calculation value is I1_cal = (V1 - V2) / (2Rn). If the deviation between the measured I1 and I1_cal continuously exceeds a preset proportional threshold, then a parallel loop contact resistance abnormality warning code is generated and appended to the fifth state code. When the basic logic cannot explicitly match any preset condition, the historical status code sequence is invoked for working mode tracking and reasoning. If the status code of the previous cycle is the fourth status code and the voltage relationship of the current cycle satisfies V1=V3=V4=V2 and I1≠0, it is determined to be a transient process in which the equalization mode has just switched from DC-DC equalization to parallel equalization, and a mode switching transient identifier code is generated. The final status code, sub-status code, warning code or transient identifier code after correction and confirmation are recombined and associated with the smoothed multi-cycle voltage and current dataset to generate a highly reliable sampling and status diagnosis dataset.

8. The dual closed-loop equalization control system for voltage and SOC between two battery clusters according to claim 7, characterized in that, The feedback uploaded to the control unit to execute the corresponding second closed-loop control strategy includes: If the sampling and status diagnosis dataset fed back to the control unit confirms that the shunt trip circuit breaker K1 and fuse F1 are normally not disconnected, then check whether Tmax is less than the upper temperature limit T_high and whether the balancing current I1 is less than the balancing current threshold. If so, return to re-execute the first closed-loop control strategy; otherwise, disconnect the shunt trip circuit breaker K1 through the control unit; otherwise, notify the BMS to stop the balancing protection.

9. The dual closed-loop equalization control system for voltage and SOC between two battery clusters according to claim 1, characterized in that, The bidirectional BUCK circuit is a non-isolated structure based on a bidirectional BUCK converter, including a first filter capacitor C1, a second filter capacitor C2, a first power switch Q1, a second power switch Q2, a first freewheeling diode D1, a second freewheeling diode D2, and a power storage inductor L1. The first filter capacitor C1 is connected in parallel between the positive and negative terminals of the first battery cluster; The second filter capacitor C2 is connected in parallel between the positive and negative terminals of the second battery cluster; The first power switch Q1, the second power switch Q2, and the power storage inductor L1 are connected in series between the first battery cluster and the second battery cluster. The power storage inductor L1 is connected between the first power switch Q1 and the second power switch Q2. The source of the first power switch Q1 is connected to the positive terminal of the first battery cluster, and the drain of the first power switch Q1 is connected to one end of the power storage inductor L1. The source of the second power switch Q2 is connected to the positive terminal of the second battery cluster, and the drain of the second power switch Q2 is connected to the other end of the power storage inductor L1. The first freewheeling diode D1 is connected in parallel between the first filter capacitor C1 and the first power switch Q1. The anode of the first freewheeling diode D1 is connected to the negative terminal of the first battery cluster, and the cathode of the first freewheeling diode D1 is connected between the drain of the first power switch Q1 and the power storage inductor L1. The second freewheeling diode D2 is connected in parallel between the second filter capacitor C2 and the second power switch Q2. The anode of the second freewheeling diode D2 is connected to the negative terminal of the second battery cluster, and the cathode of the second freewheeling diode D2 is connected between the drain of the second power switch Q2 and the power storage inductor L1. When the balancing direction is from the first battery cluster to the second battery cluster, the control unit controls the second power switch Q2 to remain on and applies an adjusted PWM drive signal to the first power switch Q1. At this time, the first power switch Q1, the first freewheeling diode D1, the power storage inductor L1 and the second power switch Q2 constitute a first buck converter from the first filter capacitor C1 to the second filter capacitor C2, wherein the first freewheeling diode D1 serves as a freewheeling path during the Q1 turn-off period. When the balancing direction shifts from the second battery cluster to the first battery cluster, the control unit controls the first power switch Q1 to remain on and applies an adjusted PWM drive signal to the second power switch Q2. At this time, the first power switch Q1, the second freewheeling diode D2, the power storage inductor L1, and the second power switch Q2 constitute a second buck converter from the second filter capacitor C2 to the first filter capacitor C1, wherein the second freewheeling diode D2 serves as a freewheeling path during the Q2 turn-off period.

10. A dual-closed-loop equalization control method for voltage and SOC between two battery clusters, characterized in that, The method is implemented based on the dual-closed-loop equalization control system for voltage and SOC between two battery clusters as described in any one of claims 1-9, and the dual-closed-loop equalization control method for voltage and SOC between two battery clusters includes the following steps: S01: System power-on initialization, the control unit establishes communication connection with the battery management system BMS, sampling module, DC-DC equalization module and parallel equalization module, obtains the rated parameters of the first battery cluster and the second battery cluster, the preset target equalization current and the preset threshold of each parameter, and generates a basic configuration parameter set; S02: Execute the first closed-loop control strategy, cyclically acquire the inter-electrode voltages V1 and V2 between the first and second battery clusters, the real-time state of charge (SOC1 and SOC2), and the highest temperature Tmax and lowest temperature Tmin of the cells within the battery clusters. Calculate the voltage difference ΔV and the SOC difference ΔSOC, generating a real-time state and difference dataset. Based on the real-time state and difference dataset, determine whether the temperature pre-protection condition, the first-level equalization trigger condition, or the second-level equalization trigger condition are met. If so, generate an equalization start command and an energy transfer direction identifier, and determine the equalization direction and the corresponding equalization mode selection signal to start the DC-DC equalization module or the parallel equalization module; otherwise, generate an equalization shutdown command and return to the previous state. The system re-monitors; it determines the corresponding target equalization module based on the equalization mode selection signal, and continuously receives voltages V1, V2, V3, V4 and equalization current I1 uploaded by the sampling module, as well as SOC1 and SOC2 periodically uploaded by the BMS, generating a dynamic equalization real-time feedback dataset; if it is a DC-DC equalization module, it performs dual closed-loop control of voltage and SOC, the outer loop SOC closed loop calculates the voltage reference adjustment amount with the goal of eliminating the SOC difference, and the inner loop voltage closed loop calculates the PWM duty cycle with the goal of eliminating the voltage difference and tracking the outer loop output, dynamically adjusting the PWM drive signal; if it is a parallel equalization module, it maintains the DC contactor KM1 engaged, limits the equalization current I1 through the equivalent internal resistance, and monitors the equalization current I1; S03: Obtain the corresponding voltages V1, V2, V3, V4, equalization current I1, and maximum temperature Tmax to diagnose the main circuit status. Based on the main circuit status, if the shunt trip circuit breaker K1 and fuse F1 are confirmed to be normally not disconnected, then check whether Tmax is less than the upper temperature limit T_high and whether the equalization current I1 is less than the equalization current threshold. If so, return to S02 to re-execute the first closed-loop control strategy. If not, disconnect the shunt trip circuit breaker K1 through the control unit. Otherwise, notify the BMS equalization protection to stop, thereby ending the equalization process, and return to S02 to continue monitoring.

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