Data shunting acquisition and adaptive storage method and system based on heterogeneous SoC

Abstract

The present application relates to the technical field of data processing, and relates to a data shunting collection and adaptive storage method and system based on a heterogeneous SoC, to solve the problems of excessively high CPU load and large storage delay when multiple sensors are accessed. The present application accesses multiple sensors at the PL end of a heterogeneous SoC and caches data, sets a shunting threshold to divide the data stream into a high-speed data stream and a low-speed control stream channel, and uses corresponding interfaces for processing to reduce bus load; a logical ring buffer is constructed in the PS end DDR memory, the number of DMA transmission blocks is adjusted according to the occupancy, and after adaptive storage of data is completed in three modes of low delay, standard batch, and extremely fast continuity, the disk read pointer is updated, the buffer area of completed disk writing is released, and the PL end is provided with a new data cyclic writing function. The present application realizes efficient and low-loss storage of a large data stream of multiple sensors through the synergistic effect of a heterogeneous SoC, improves data collection continuity and storage reliability, and prolongs the service life of the storage device.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and specifically to a method and system for heterogeneous SoC data offloading, acquisition, and adaptive storage. Background Technology

[0002] With the rapid iteration of autonomous driving technology and the intelligent upgrading of complex equipment (such as intelligent unmanned equipment and special inspection equipment), multi-source sensor fusion has become the core support for achieving accurate perception and real-time decision-making in systems. In practical application scenarios, systems typically need to simultaneously access multiple types of sensors, such as LiDAR, binocular cameras, inertial measurement units (IMUs), and Global Navigation Satellite Systems (GNSS). These various sensors work together to provide the system with comprehensive data support for environmental perception, location positioning, and attitude detection. The efficiency of data acquisition, transmission stability, and storage reliability directly determine the overall system performance.

[0003] However, existing multi-source sensor data acquisition and storage technologies still have many unresolved issues, as follows:

[0004] The core parameters of different types of sensors vary significantly, and the data types cover a variety of forms, including continuous video streams (such as binocular cameras) and discrete state values ​​(such as angular velocity and acceleration of IMUs). The communication protocols are diverse, including different standards such as CAN bus, RS485, Ethernet, and LVDS, and the transmission rates and data frame formats of various protocols are incompatible with each other. The sampling frequencies range extremely widely, from 10Hz low-frequency sampling of GNSS to 1kHz high-frequency sampling of IMUs. Traditional data acquisition cards mostly adopt fixed interface designs, lack flexible hardware adaptation capabilities, and make it difficult to achieve unified access and synchronous acquisition of multiple source sensors.

[0005] In traditional data acquisition architectures, all sensor data must be transported, parsed, and forwarded through a central processing unit (CPU), with the CPU undertaking all data processing and transmission tasks. When high-frequency, high-bandwidth sensors such as LiDAR and high-definition binocular cameras are connected, massive amounts of data continuously consume CPU computing power, leading to frequent CPU interrupt requests. This not only increases system response latency but may also cause problems such as untimely data processing and buffer overflows, resulting in data packet loss. This severely affects the system's real-time perception and decision-making capabilities in complex scenarios and may even lead to safety hazards for autonomous vehicles and intelligent equipment.

[0006] For high-frequency, large-data streams, traditional storage methods require multiple layers of operating system caching and copying, protocol parsing, and other steps before the data can be written to hard drives or other storage media. This process introduces significant transmission latency, making it unsuitable for the real-time data storage needs of scenarios such as autonomous driving. Furthermore, the multi-layered copying process consumes additional system memory and CPU resources, reducing storage throughput. This not only affects data storage efficiency but also further exacerbates CPU load, creating a vicious cycle of "acquisition-processing-storage," which is ill-suited to the efficient storage requirements of high-frequency, multi-source sensor data. Summary of the Invention

[0007] This invention provides a method and system for heterogeneous SoC data offloading and adaptive storage to solve the problems of excessive CPU load and large storage latency when multiple sensors are accessed in the prior art.

[0008] The method for heterogeneous SoC data offloading and adaptive storage, wherein the heterogeneous SoC includes a PL terminal and a PS terminal, includes the following steps:

[0009] S1. By connecting various types of sensors to the PL terminal, the data stream generated by the sensors is split into a high-speed data stream channel and a low-speed control stream channel through a hardware-level splitting mechanism;

[0010] S2. Process the raw data from various types of sensors at the PL end, and package the processed raw data into a unified frame format by combining the hardware timestamp;

[0011] S3. Map the high-speed data stream in the high-speed data stream channel directly to the DDR memory on the PS side through the AXI4-Stream interface, and map the low-speed control stream in the low-speed control stream channel to the register through the AXI4-Lite interface.

[0012] S4. Construct a logical circular buffer in the DDR memory on the PS side, and monitor the occupancy of the logical circular buffer in real time. And based on the occupancy of the logical circular buffer Dynamically adjust the number of blocks in a single DMA transfer to NVMe memory It completes adaptive storage of data from various types of sensors. After the data is written to disk, it updates the disk read pointer, releases the buffer that has been written to disk, and allows the PL to write new data in a loop.

[0013] Furthermore, the hardware-level traffic splitting mechanism in S1 uses the effective payload size and transmission bandwidth of data frames as classification criteria, sets a traffic splitting threshold, and assigns data whose effective payload size and transmission bandwidth are greater than or equal to the traffic splitting threshold to the high-speed data flow channel, and assigns data whose effective payload size and transmission bandwidth are less than the traffic splitting threshold to the low-speed control flow channel.

[0014] Furthermore, when the PL terminal processes the raw data from various types of sensors, it configures an independent FIFO memory for each sensor interface to achieve real-time caching of the corresponding sensor data.

[0015] Furthermore, the construction of DDR memory on the PS side by... buffer blocks The logical circular buffer consists of the buffer blocks. The size is aligned with the physical page or erase block size of the NVMe SSD, and the PL end is used to write one buffer block at a time. The PS terminal is then notified via interrupt or register, and subsequently, the PL terminal writes the hardware write pointer to the address. Automatically move to the next buffer block.

[0016] Furthermore, the formula for calculating the occupancy of the logical circular buffer is as follows:

[0017] ;

[0018] In the formula, This represents the number of buffer blocks that have not yet been written to disk. A hardware write pointer is used to write the address to the PL terminal. This is a disk read pointer that points to the address where the disk was written to. This represents the total number of buffer blocks in the circular buffer. For This is the modulo operation.

[0019] Furthermore, the dynamic adjustment of the number of blocks transferred to the NVMe memory in a single DMA operation... The strategies include:

[0020] Set low water level threshold and high water level threshold ;

[0021] when When the timeout condition for forced disk write is met, the system enters a low-latency waiting mode and does not immediately write the disk. ;

[0022] when When entering standard batch write mode, set the preset batch block count. Perform batch disk write;

[0023] when When entering high-speed continuous write mode, set... Sets the maximum value supported by DMA and increases the priority of write threads.

[0024] Furthermore, the data is written to disk by the PS sending a physical address command to the NVMe controller, which then directly reads the DDR data via the PCIe bus and writes it to disk, achieving zero copying throughout the process.

[0025] Furthermore, after the data is written to disk, the system updates the disk read pointer according to the number of blocks transmitted in the batch. Release the buffer that has been written to disk, so that the PL can cyclically write new data.

[0026] The present invention also provides a heterogeneous SoC data offloading acquisition and adaptive storage system, which applies the heterogeneous SoC data offloading acquisition and adaptive storage method described above.

[0027] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0028] This invention uses PL-side hardware to divide data into high-speed data flow channels and low-speed control flow channels, achieving hardware-level isolation and splitting of high and low speed data flows. It is equipped with a buffer module that matches the characteristics of the storage medium and designs an adaptive DMA storage scheduling mechanism based on cache state. It constructs a fully hardware-driven, automated data processing link, which significantly reduces system load and effectively solves problems such as congestion in multi-source data transmission, high CPU usage, data lag and packet loss, and low storage efficiency. It significantly improves the real-time performance, stability, and reliability of multi-source sensor data acquisition and storage. Attached Figure Description

[0029] Figure 1 This is a flowchart of the technology of the present invention;

[0030] Figure 2 This is a schematic diagram of pointer operations in a circular buffer;

[0031] Figure 3 This is the state machine transition diagram for adaptive DMA memory scheduling. Detailed Implementation

[0032] The present invention will be further illustrated below with reference to embodiments. These embodiments are for illustrative purposes only and are not intended to limit the invention in any way. It should be understood that the described embodiments are merely some, not all, of the embodiments described in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0033] like Figure 1 As shown, the heterogeneous SoC data offloading and adaptive storage method includes the following steps:

[0034] This embodiment is based on a heterogeneous SoC and connects to an autonomous driving data acquisition vehicle with LiDAR, binocular camera, high-precision GNSS and IMU sensors through a programmable logic terminal (PL). It utilizes the parallel processing characteristics of FPGA to shield the protocol differences between different sensor interfaces and configures an independent FIFO memory for each sensor interface to realize real-time caching of data from each sensor to cope with the impact of sudden data streams.

[0035] At the PL end, the system sets a splitting threshold based on the payload of a single data frame and the continuous transmission bandwidth, dividing the data stream into a high-speed data stream channel and a low-speed control stream channel. High-frequency, large-volume sensor data with a single data frame payload ≥ 1KB and a continuous transmission bandwidth ≥ 1MB / s is assigned to the high-speed data stream channel. The PL end packages the data from the high-speed data stream channel and maps it directly to DDR memory via the AXI4-Stream interface. In conjunction with the DMA controller, the data is directly transferred to the NVMe SSD, achieving zero-copy transmission throughout. Low-frequency, small-volume device status data or control commands with a single data frame payload < 1KB and a continuous transmission bandwidth < 1MB / s are assigned to the low-speed control stream channel. The PL end maps the data from the low-speed control stream channel to a specific register or BRAM address space via the AXI4-Lite interface, which is then read by the PS end via interrupts or polling, preventing fragmented data from occupying the DMA channel and causing frequent interrupts.

[0036] A logical circular buffer consisting of 64 buffer blocks was constructed in the DDR memory on the PS side. A diagram illustrating the pointer operations of the circular buffer is shown below. Figure 2 As shown, Figure 2 middle The current address pointer for writing data to the PL-side FPGA. This is the current address pointer for DMA reading data from the PS side and writing it to disk. The shaded area represents the amount of data that has been cached but not yet written to disk. (The dashed line in the diagram...) and These represent the low-watermark and high-watermark thresholds that trigger different write strategies, respectively. The size of each buffer block. The buffer block size is strictly aligned with the physical page size or the optimal erase block size of the NVMe SSD. Each 4MB of physical contiguous data is sent, which can maximize the utilization of the multi-channel concurrent write characteristics of the internal flash memory chips of the SSD, avoid write amplification effect, optimize the write efficiency of physical sectors and improve throughput performance. There are a total of 64 buffer blocks, and the total capacity of the circular buffer allocated by the system is 4MB × 64 = 256MB. The peak bandwidth of multi-sensor concurrency is 100MB / s. When the system stutters due to operating system scheduling or sudden NVMe latency, the 256MB buffer depth is sufficient to cache about 2.5s of peak data, thereby avoiding sudden data loss in most operating conditions.

[0037] Each time the PL end is filled The PS terminal is then notified via interrupt or register, and subsequently, the pointer is written in hardware. Automatically move to the next buffer block; the PS-side scheduling thread periodically calculates the current occupancy of the logical circular buffer. :

[0038] ;

[0039] In the formula, This represents the number of buffer blocks that have not yet been written to disk. A hardware write pointer is used to write the address to the PL terminal. This is a disk read pointer that points to the address where the disk was written to. This embodiment represents the total number of buffer blocks in the circular buffer. , For This is the modulo operation.

[0040] according to Depending on the specific requirements, the system dynamically adjusts the number of blocks in a single DMA transfer. In this embodiment, Figure 3 The system demonstrates how it adjusts buffer occupancy. In the adaptive DMA memory scheduling state machine transition diagram under different modes, the system dynamically switches states based on the number of occupied blocks:

[0041] Low-latency waiting mode (idle state)

[0042] Set low water level threshold ,set up ,when At that time, the overall occupancy rate of the corresponding buffer was approximately 10%. (Right now When the input data stream is at a low level, the system enters a low-latency idle mode, starts a counter, and temporarily suspends data write-to-disk operations until the timeout forced write-to-disk condition is met, at which point a single-block write-to-disk operation is triggered. This setting effectively avoids frequent wake-ups of the NVMe controller due to small amounts of data, reduces unnecessary bus interactions and device start-ups and shutdowns, thereby reducing system bus load and overall power consumption, ensuring system stability and energy efficiency, and guaranteeing basic data real-time performance.

[0043] Standard batch write mode (working state)

[0044] Set high water level threshold ,set up ,when At that time, the overall occupancy rate of the corresponding buffer was approximately 70%. (Right now When this happens, the system switches to standard batch write mode, setting the number of blocks to be written to disk in batches to a specified value. (That is, the corresponding data size is 16MB), pending system accumulation. This triggers a DMA batch write to disk. This setting ensures that the NVMe SSD is always in a state of large block sequential writes, balancing throughput and the lifespan of the NVMe SSD.

[0045] High-speed continuous write mode (burst mode)

[0046] when (Right now When the overall buffer occupancy exceeds 70%, it indicates a sudden increase in data flow or abnormal obstruction during disk write, posing a risk of buffer overflow. In this case, the system switches to a burst mode for high-speed continuous writing, setting the batch write block count to [value missing]. (That is, the corresponding data volume is 64MB), and the system scheduling priority of the data writing thread is increased to prioritize the execution of buffer data writing operations, so as to quickly clear the buffer and avoid data loss caused by the new data being overwritten and not written to disk. This process is at the cost of occupying some CPU resources of non-real-time tasks to ensure the reliability of core data acquisition.

[0047] according to Figure 3 It can be seen that when the sensor data volume is low, the system is in a low-latency idle state to reduce power consumption; when the data volume is normal, it enters the standard batch write working state to perform batch writes to optimize the lifespan of the NVMe SSD; when a data burst causes the usage to exceed the high watermark threshold... When the burst mode is activated, it enters a high-speed continuous writing mode to write at full speed to prevent packet loss.

[0048] After determining the number of blocks to be written, the system enters the disk write phase. The PS only sends physical address commands to the NVMe SSD, which then reads data directly from DDR via the PCIe bus. Once the NVMe SSD reports completion of the write operation, the system updates the disk read pointer according to the following formula:

[0049] ;

[0050] Release the buffer that has been written to disk, so that the PL can cyclically write new data.

[0051] This invention dynamically distributes sensor data streams at the PL end according to data volume and bandwidth, processing them using high-speed DMA transfer and register mapping methods respectively. This avoids frequent DMA triggers and interrupts for small data volumes, significantly reducing system bus load and improving stability when multiple sensors are accessed in parallel. Secondly, it employs a ring buffer structure aligned with the NVMe physical block size, combined with a multi-threshold adaptive scheduling strategy. This reduces hard drive startup and shutdown to lower power consumption in low data rate scenarios, enables large-block sequential writing to extend the lifespan of NVMe SSDs under normal operating conditions, and rapidly increases write bandwidth in data burst scenarios, balancing low latency, high throughput, and storage reliability. The overall solution fully leverages the hardware and software synergy advantages of heterogeneous SoCs to achieve efficient, stable, and low-loss storage of large data streams from multiple sensors.

[0052] Of course, the above description is not intended to limit the present invention, and the present invention is not limited to the examples given above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. A method for heterogeneous SoC data offloading and adaptive storage, wherein the heterogeneous SoC includes a PL terminal and a PS terminal, characterized in that, Includes the following steps: S1. By using the PL terminal to connect to various types of sensors, the data stream generated by the sensors is split into a high-speed data stream channel and a low-speed control stream channel through a hardware-level splitting mechanism. The hardware-level splitting mechanism uses the effective payload size and transmission bandwidth of the data frame as the classification basis, sets a splitting threshold, and assigns data whose effective payload size and transmission bandwidth are greater than or equal to the splitting threshold to the high-speed data stream channel, and assigns data whose effective payload size and transmission bandwidth are less than the splitting threshold to the low-speed control stream channel. S2. Process the raw data from various types of sensors at the PL end, and package the processed raw data into a unified frame format by combining the hardware timestamp; S3. Map the high-speed data stream in the high-speed data stream channel directly to the DDR memory on the PS side through the AXI4-Stream interface, and map the low-speed control stream in the low-speed control stream channel to the register through the AXI4-Lite interface. S4. Construct a system in the DDR memory on the PS side using... buffer blocks The logical circular buffer is formed. The total number of buffer blocks in the circular buffer is used to monitor the occupancy of the logical circular buffer in real time. And based on the occupancy of the logical circular buffer. Dynamically adjust the number of blocks in a single DMA transfer to NVMe memory The system adaptively stores data from various types of sensors. After the data is written to disk, the disk read pointer is updated, and the buffer that has been written to disk is released, allowing the PL terminal to cyclically write new data. Its size is aligned with the physical page or erase block size of the NVMe SSD.

2. The method for heterogeneous SoC-based data offloading and adaptive storage according to claim 1, characterized in that, When the PL terminal processes raw data from various types of sensors, it configures an independent FIFO memory for each sensor interface to achieve real-time caching of the corresponding sensor data.

3. The method for heterogeneous SoC-based data offloading and adaptive storage according to claim 1, characterized in that, Each time a buffer block is filled at the PL terminal The PS terminal is then notified via interrupt or register, and subsequently, the PL terminal writes the hardware write pointer to the address. Automatically move to the next buffer block.

4. The method for heterogeneous SoC-based data offloading and adaptive storage according to claim 3, characterized in that, The formula for calculating the occupancy of the logical ring buffer is: ； In the formula, This represents the number of buffer blocks that have not yet been written to disk. A hardware write pointer is used to write the address to the PL terminal. This is a disk read pointer that points to the address where the disk was written to. This represents the total number of buffer blocks in the circular buffer. For This is the modulo operation.

5. The method for heterogeneous SoC-based data offloading and adaptive storage according to claim 1, characterized in that, The dynamic adjustment of the number of blocks in a single DMA transfer to NVMe memory The strategies include: Set low water level threshold and high water level threshold ; when When the timeout condition for forced disk write is met, the system enters a low-latency waiting mode and does not immediately write the disk. ; when When entering standard batch write mode, set the preset batch block count. Perform batch disk write; when When entering high-speed continuous write mode, set... Sets the maximum value supported by DMA and increases the priority of write threads.

6. The method for heterogeneous SoC-based data offloading and adaptive storage according to claim 1, characterized in that, The data is written to disk by the PS sending a physical address command to the NVMe controller, which then reads the DDR data directly through the PCIe bus and writes it to disk, achieving zero copying throughout the process.

7. The method for heterogeneous SoC-based data offloading and adaptive storage according to claim 1, characterized in that, After the data is written to disk, the system updates the disk read pointer according to the number of blocks transferred in the batch. Release the buffer that has been written to disk, so that the PL can cyclically write new data.

8. A heterogeneous SoC-based data offloading and adaptive storage system, characterized in that, The method for heterogeneous SoC data offloading and adaptive storage as described in any one of claims 1 to 7 is applied.

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