Accelerated QLC write digital stream management device and storage controller chip
By accelerating the QLC write digital stream management device and optimizing the write process of QLC storage particles, the problem of time extension caused by the need for two writes of QLC storage particles is solved, thereby improving data write efficiency and host processing bandwidth.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HEFEI DATANG STORAGE TECH CO LTD
- Filing Date
- 2026-01-28
- Publication Date
- 2026-05-12
AI Technical Summary
Existing storage controller chips require two write operations on QLC storage chips, which prolongs data write time and reduces host processing bandwidth.
An accelerated QLC write digital stream management device is adopted, including a data DMA, a write command parsing and distribution module, and a buffer release management module. Through data copying and status control, the write data stream management is optimized, firmware processing overhead is reduced, and write command execution efficiency is improved.
It reduces the complexity of QLC NAND flash write commands, improves the execution efficiency of write commands, reduces CPU usage, and enhances data transfer efficiency.
Smart Images
Figure CN122019427A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of storage controller technology, and more specifically to an accelerated QLC write digital stream management device and storage controller chip. Background Technology
[0002] For QLC storage particles, due to the requirements of their usage, for the same batch of data to be written to the QLC storage particles, two write operations need to be performed on the QLC storage particles.
[0003] When using QLC storage chips, data sent from the host needs to be written twice before it can be stored in the chip. Existing storage controller chips are not well-designed to support the two-write function, resulting in longer data writing times and affecting the data throughput of the storage controller chip.
[0004] If we wait for both write operations to complete, the time it takes for the storage controller chip to process each write operation will be greatly extended, which will reduce the host's processing bandwidth. Summary of the Invention
[0005] To address the shortcomings of existing technologies, this invention provides an accelerated QLC write digital stream management device and storage controller chip, thereby solving the problem of time delay caused by waiting for two write operations to complete when writing data to QLC storage chips.
[0006] In a first aspect, the present invention provides an accelerated QLC write digital stream management device, comprising a data DMA, a write command parsing and distribution module, and a buffer release management module. Data DMA is used to copy the data to be written to the destination buffer and, after the copying is complete, feeds back to the write command parsing and distribution module to update the data buffer status table; the data in the destination buffer is used for reading during secondary writing. The write command parsing and distribution module is used to retrieve control words from the control word queue, retrieve the corresponding write command from the write command queue based on the control word, configure data DMA based on the control word, and add a release command to the release command queue after it is known that the copy is complete. The cache release management module retrieves the cache command from the data cache status table and releases the corresponding cache.
[0007] As can be seen from the above technical solution, the present invention provides an accelerated QLC write digital stream management device that ensures that the storage particle controller can obtain valid write data during two writes through data replication and status control; it reduces the complexity of QLC particle write command processing and improves the execution efficiency of write commands; at the same time, using the write data stream management device can reduce the loss of firmware processing multiple writes and reduce the CPU usage.
[0008] Optionally, the write command parsing and distribution module determines whether to retrieve the corresponding write command from the write command queue based on the write pattern field in the control word. The write command parsing and distribution module configures the timing for the data DMA to copy the data to be written to the destination buffer based on the write mode field in the control word. The write mode field includes: execute immediately, start on the first write, and start after the first write.
[0009] Optionally, the data to be written is copied from the source buffer to the destination buffer, and the data in the source buffer is used for reading during the first write.
[0010] Optionally, the data cache status table includes fields such as a replication completion flag and a cache address; the replication completion flag indicates whether data replication is complete and is updated by the write command parsing and distribution module; the cache address indicates the storage address of the data to be written.
[0011] Optionally, the source cache and the destination cache are pre-defined regions in RAM, and the write direction field in the control word includes: SRAM to DRAM, SRAM to SRAM, DRAM to SRAM, and DRAM to DRAM.
[0012] Optionally, the fields in the release command include: release command number, release address, and release length.
[0013] In a second aspect, the present invention provides a memory controller chip, including an accelerated QLC write digital stream management device in any possible implementation of the first aspect.
[0014] By adopting the above technical solution, this application has the following beneficial effects: This invention ensures that the memory chip controller can retrieve valid write data during both write operations through data replication and status control, reducing the complexity of QLC chip write command processing and improving the execution efficiency of write commands; at the same time, the use of a write data stream management device can reduce the loss of firmware processing multiple writes and reduce CPU usage. When performing data replication, multiple write modes and write directions are provided, which can work together to effectively utilize the internal bus bandwidth of the storage chip and improve data transmission efficiency. Attached Figure Description
[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.
[0016] Figure 1This diagram illustrates a structural block diagram of an accelerated QLC write digital stream management device provided by an embodiment of the present invention; Figure 2 A flowchart illustrating the operation of the accelerated QLC write digital stream management device provided in an embodiment of the present invention is shown. Figure 3 A structural block diagram of a memory controller chip provided in an embodiment of the present invention is shown. Detailed Implementation
[0017] The embodiments of the technical solution of the present invention will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of the present invention and are therefore merely examples, and should not be construed as limiting the scope of protection of the present invention. It should be noted that, unless otherwise stated, the technical or scientific terms used in this application should have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.
[0018] When using QLC storage chips, data from the host needs to be written twice before it can be stored in the chip. If we wait for both writes to complete directly, the time it takes for the storage controller chip to process each write will be greatly increased, which will reduce the host's processing bandwidth.
[0019] Based on this, such as Figure 1 As shown, this embodiment provides an accelerated QLC write digital stream management device, including a data DMA, a write command parsing and distribution module, and a cache release management module. The data DMA is used to copy the data to be written to the destination cache area and, after the copy is completed, feeds back to the write command parsing and distribution module to update the data cache status table. The data in the destination cache area is used for reading during secondary writing. The write command parsing and distribution module is used to retrieve a control word from the control word queue, retrieve the corresponding write command from the write command queue according to the control word, and configure the data DMA according to the control word. After knowing that the copy is completed, it adds a release command to the release command queue. The cache release management module retrieves the cache command according to the data cache status table and releases the corresponding cache.
[0020] Based on the accelerated QLC write digital stream management device provided in this embodiment, the received write data is stored in different areas, and different modules alternately complete the data writing work. After the first write is completed, the relevant cache is released; at the same time, the data for the second write has been copied to the destination cache area. During the second write, the write data is read from the destination cache area and the write operation is performed.
[0021] Both the firmware and the memory chip controller can add write commands and control words to the write data stream management device, storing the write command queue and control word queue respectively. The write command structure is shown in Table 1, and includes a write command number, the source address of the write data, the destination address of the write data, and the data length. The source and destination addresses can be any address within the address range of SRAM or DRAM.
[0022] Table 1
[0023] The control word structure is shown in Table 2. It includes a write command number, with each control word corresponding to a single write command; a write mode, allowing for data copying options (immediate execution, starting on the first write, or starting after the first write); and a write direction, supporting four directions: SRAM to DRAM, SRAM to SRAM, DRAM to SRAM, and DRAM to DRAM. Data copying can occur in these four directions.
[0024] Table 2
[0025] Optionally, the write command parsing and distribution module determines whether to retrieve the corresponding write command from the write command queue based on the write mode field in the control word. The write command parsing and distribution module configures the timing for the data DMA to copy the data to be written to the destination buffer based on the write mode field in the control word. The write mode field includes: execute immediately, start on the first write, and start after the first write.
[0026] Data DMA is used to independently complete data copying, reducing the workload of other modules. Data DMA parses the source address, destination address, data transfer length, and write direction parameters sent by the write command distribution module, and then copies the data to be written to the destination storage area. Typically, a dedicated secondary write data storage area is reserved in SRAM and DRAM for easy functional debugging.
[0027] Different write modes allow the data DMA to select appropriate times to transfer data, avoiding bus congestion. For example, in immediate execution mode, the data DMA immediately copies data upon receiving a write command, while the memory chip controller is performing pre-write register configuration and has not yet accessed the data to be written; the data DMA can exclusively occupy the data read bandwidth and quickly complete the copy. After the first write, data copying can be hidden between different write command processing, achieving a better pipelined processing mechanism. Synchronous start of the first write ensures that for data requiring synchronous processing, data writing and data copying are completed simultaneously. While there may be bandwidth conflicts, simultaneous completion is guaranteed.
[0028] If the write mode is executed immediately, the data is retrieved upon receiving the command; if the write mode begins on the first write operation, copying starts simultaneously with the write operation; if the write mode begins after the first write operation, copying occurs after the first write operation is completed. These three modes are provided to allow users to adjust the copying timing based on bandwidth availability.
[0029] Immediate execution is suitable when data bandwidth is limited. Choosing immediate write allows the copying process to be completed in advance, avoiding contention between copy and write operations for access to the same data area. In this case, bandwidth is not consumed during the first write. However, if the data is updated between its arrival and the first write, it needs to be copied to the target buffer again, which can sometimes prolong data processing time.
[0030] Copying at the start of the first write operation ensures that data is accurately delivered to the corresponding sender simultaneously with the write operation. This consumes more bandwidth, but the logic is relatively simple. Copying and writing operations compete for access to the same data area, and conflicts can reduce data read efficiency. If the received data has been updated before the first write, the last updated data is copied to the buffer during the second write operation.
[0031] Copying occurs after the first write operation, eliminating data update issues. However, this data copying will impact the bandwidth for subsequent writes. Additionally, the initial write operation takes a relatively long time.
[0032] Continuous writing is suitable for the immediate execution write mode; small batch writing is suitable for the copy-at-the-beginning write mode; and single-entry writing is suitable for the copy-at-the-beginning write mode. Users can specify the appropriate mode based on bandwidth requirements to improve data transfer efficiency.
[0033] In one embodiment, the data to be written is copied from the source buffer to the destination buffer, and the data in the source buffer is used for reading during the first write operation. The source buffer and the destination buffer are pre-defined areas in RAM, and the write direction field in the control word includes: SRAM to DRAM, SRAM to SRAM, DRAM to SRAM, and DRAM to DRAM.
[0034] After data DMA replication is complete, it notifies the write command parsing and distribution module to update the data cache status table. As shown in Table 3, the data cache status table includes fields such as write stage flag, replication completion flag, and cache address. The write stage flag indicates the current state of the data to be written: pending write, writing, replicating, or both writing and replicating are complete. The replication completion flag indicates whether data replication is complete and is updated by the write command parsing and distribution module. The cache address indicates the storage location of the data to be written.
[0035] Table 3
[0036] After the write command parsing and distribution module receives the copy, it adds a release command to the release command queue, as shown in Table 4. The fields in the release command include: release command number, release address (the starting address of the memory to be released), and release length. The release management module retrieves the release command from the data cache status table, invalidates the corresponding entry, and releases the cache; after release, the cache can be reassigned to receive other data.
[0037] Table 4
[0038] The main working process of accelerating the QLC write data stream management device is as follows: Figure 2 As shown.
[0039] The host can send write data commands to the write data stream management device through the interface to complete the write data replication of QLC. When the storage particle controller writes data to the storage particle for the first time, it uses the data to be written in the cache. The cache is released after the first write is completed.
[0040] Furthermore, the firmware can directly write data to the storage chips by operating the storage chip controller via an interface. In this case, the storage chip controller needs to send the write command to the write data stream management device. The write data stream management device retrieves the write command based on the control word, completes the data copying, and releases the buffer after the storage chip controller completes the first write. Simultaneously, the data to be written is copied to the secondary write storage area. The released buffer can then be used for other data writing on the host.
[0041] In one embodiment, such as Figure 3 As shown, a storage controller chip is also provided, including the accelerated QLC write digital stream management device provided in the above embodiments, and further including a PCIe interface, an NVMe protocol processing module, a cache control module, a storage access module, a storage particle controller, and a DRAM access control module. The storage controller chip receives commands from the host to access the storage particle via the PCIe interface, which are then processed by the CPU and converted into operation signals for the storage particle controller. The cache control module stores the data to be read / written in on-chip SRAM or off-chip DRAM; for QLC storage particles, the accelerated QLC write digital stream management device is specifically responsible for managing the data written to the QLC storage particle, improving data access efficiency, and cooperating with the storage particle controller to complete two write operations on the QLC storage particle.
[0042] The above embodiments are only used to provide a detailed description of the technical solutions of this application. However, the descriptions of the above embodiments are only for the purpose of helping to understand the methods of the embodiments of the present invention and should not be construed as limiting the embodiments of the present invention. Any variations or substitutions that can be easily conceived by those skilled in the art should be covered within the protection scope of the embodiments of the present invention.
Claims
1. A device for accelerating QLC write digital stream management, characterized in that, This includes a data DMA module, a write command parsing and distribution module, and a cache release management module. Data DMA is used to copy the data to be written to the destination buffer and, after the copying is complete, feeds back to the write command parsing and distribution module to update the data buffer status table; the data in the destination buffer is used for reading during secondary writing. The write command parsing and distribution module is used to retrieve control words from the control word queue, retrieve the corresponding write command from the write command queue based on the control word, configure data DMA based on the control word, and add a release command to the release command queue after it is known that the copy is complete. The cache release management module retrieves the release command from the data cache status table and releases the corresponding cache.
2. The apparatus according to claim 1, characterized in that, The write command parsing and distribution module determines whether to retrieve the corresponding write command from the write command queue based on the write pattern field in the control word. The write command parsing and distribution module configures the timing for the data DMA to copy the data to be written to the destination buffer based on the write mode field in the control word. The write mode field includes: execute immediately, start on the first write, and start after the first write.
3. The apparatus according to claim 2, characterized in that, The data to be written is copied from the source buffer to the destination buffer, and the data in the source buffer is used for reading during the first write.
4. The apparatus according to claim 3, characterized in that, The data cache status table includes fields for a replication completion flag and a cache address. The replication completion flag indicates whether data replication is complete and is updated by the write command parsing and distribution module. The cache address indicates the storage location of the data to be written.
5. The apparatus according to claim 4, characterized in that, The source cache and the destination cache are pre-defined regions in RAM, and the write direction field in the control word includes: SRAM to DRAM, SRAM to SRAM, DRAM to SRAM, and DRAM to DRAM.
6. The apparatus according to claim 1, characterized in that, The fields in the release command include: release command number, release address, and release length.
7. A memory controller chip, characterized in that, Includes the accelerated QLC write digital stream management device as described in any one of claims 1 to 6.