Inter-core communication method, device, system and equipment and computer readable storage medium

Abstract

The invention discloses an inter-core communication method, device, system and equipment and a computer readable storage medium, aims to realize stable and efficient inter-core communication, and is applied to an inter-core communication component comprising a plurality of first data channel groups, and each first data channel group comprises a first data sending channel and a first data receiving channel which correspond to each other; comprising the following steps: receiving first communication data sent by a first kernel, selecting a first target data channel group, and storing the first communication data to a first target storage position corresponding to a first target data sending channel in the first target data channel group; sending an interruption notice to the second kernel to enable the second kernel to obtain the first communication data at the first target storage position; receiving first response data sent by the second kernel, and storing the first response data to a second target storage position corresponding to a first target data receiving channel in the first target data channel group; and sending an interruption notification to the first kernel to enable the first kernel to obtain the first response data at the second target storage position.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to an inter-core communication method, as well as an inter-core communication device, system, electronic device, and computer-readable storage medium. Background Technology

[0002] With the development of technologies such as artificial intelligence, cloud computing, big data, and 5G communication, servers have ushered in new development opportunities. Modern processor chips are becoming increasingly complex and powerful, and they are gradually evolving from single-core to multi-core processors. These cores may run different operating systems to implement different functions. For multi-core, multi-operating system tasks that often require collaborative processing, inter-core communication between multiple cores is essential to achieve this collaborative function, and the inter-core communication mechanism also affects the overall system performance.

[0003] Currently, inter-core communication can be achieved based on "soft interrupts + shared memory." When the sending CPU core needs to send data, it places the data in shared memory and then triggers a soft interrupt to notify the receiving CPU core, which then traverses the shared memory to receive the data. However, multiple cores may simultaneously operate on shared memory. If multiple cores simultaneously write data to the same location in shared memory, a conflict will occur, causing communication failure. Furthermore, when the receiving CPU core receives a soft interrupt, it needs to traverse the shared memory to find the location of the target data before it can read the data. It cannot immediately find the location of the target data through the soft interrupt, resulting in low efficiency. Therefore, traditional inter-core communication methods suffer from low communication efficiency and instability.

[0004] Therefore, how to achieve more stable and efficient inter-core communication is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide an inter-core communication method that can achieve more stable and efficient inter-core communication; another purpose of this application is to provide an inter-core communication device, system, electronic device, computer-readable storage medium, and computer program product, all of which have the above-mentioned beneficial effects.

[0006] In a first aspect, this application provides an inter-core communication method applied to an inter-core communication component, the inter-core communication component including a plurality of first data channel groups, each of the first data channel groups including a first data transmission channel and a first data reception channel corresponding to each other; the method includes:

[0007] Receive first communication data sent by the first kernel, select a first target data channel group from multiple first data channel groups, and save the first communication data to the first target storage location bound to the first target data sending channel in the first target data channel group;

[0008] Send a first interrupt notification to the second kernel, so that the second kernel can obtain the first communication data from the first target storage location according to the first interrupt notification;

[0009] Receive the first response data sent by the second kernel, and save the first response data to the second target storage location bound to the first target data receiving channel in the first target data channel group; the first response data corresponds to the first communication data.

[0010] A second interrupt notification is sent to the first kernel, so that the first kernel can obtain the first response data from the second target storage location according to the second interrupt notification.

[0011] Optionally, selecting a first target data channel group from among multiple first data channel groups and saving the first communication data to a first target storage location bound to the first target data transmission channel in the first target data channel group includes:

[0012] Among the multiple first data channel groups, the first data channel group in which neither the status register of the first data transmission channel nor the first data reception channel has a data flag bit is selected as the first target data channel group;

[0013] The first communication data is saved to the first target storage location bound to the first target data transmission channel in the first target data channel group.

[0014] Optionally, sending a first interrupt notification to the second kernel, so that the second kernel obtains the first communication data from the first target storage location according to the first interrupt notification, includes:

[0015] Send the channel message of the first target data transmission channel to the first kernel, so that the first kernel writes the interrupt flag bit into the control register corresponding to the first target data transmission channel to generate the first interrupt notification;

[0016] The first interrupt notification is sent to the second kernel, so that the second kernel can obtain the first communication data from the first target storage location according to the first interrupt notification.

[0017] Optionally, sending a second interrupt notification to the first kernel, so that the first kernel retrieves the first response data from the second target storage location according to the second interrupt notification, includes:

[0018] Send the second interrupt notification to the first kernel to cause the first kernel to switch from a sleep state to a wake-up state, and in the wake-up state, retrieve the first response data from the second target storage location according to the second interrupt notification;

[0019] The first kernel transitions from the wake-up state to the sleep state after writing the interrupt flag into the control register corresponding to the first target data transmission channel.

[0020] Optionally, after sending a second interrupt notification to the first kernel, so that the first kernel obtains the first response data from the second target storage location according to the second interrupt notification, the method further includes:

[0021] The first clear notification is received through the status clear register corresponding to the first target data transmission channel; the first clear notification is generated by the second kernel writing a clear flag bit into the status clear register corresponding to the first target data transmission channel after sending the first response data.

[0022] Release the first target data transmission channel according to the first zeroing notification;

[0023] The second clearing notification is received through the status clearing register corresponding to the first target data receiving channel; the second clearing notification is generated by the first kernel writing a clearing flag bit into the status clearing register corresponding to the first target data receiving channel after receiving the first response data.

[0024] Release the second target data receiving channel according to the second zeroing notification.

[0025] Optionally, the inter-core communication component further includes multiple first event channel groups, each first event channel group including a corresponding first event sending channel and a first event receiving channel; the method further includes:

[0026] Receive the first event notification sent by the first kernel, and select the first target event channel group from multiple first event channel groups;

[0027] A third interrupt notification is sent to the second kernel, so that the second kernel obtains the first event notification through the first target event sending channel in the first target event channel group according to the third interrupt notification;

[0028] Receive a first response event sent by the second kernel; the first response event corresponds to the first event notification;

[0029] A fourth interrupt notification is sent to the first kernel, so that the first kernel can obtain the first response event through the first target event receiving channel in the first target event channel group according to the fourth interrupt notification.

[0030] Secondly, this application also discloses an inter-core communication device applied to an inter-core communication component, the inter-core communication component including a plurality of first data channel groups, each of the first data channel groups including a first data transmission channel and a first data reception channel corresponding to each other; the device includes:

[0031] The first receiving module is used to receive the first communication data sent by the first kernel, select a first target data channel group from a plurality of first data channel groups, and save the first communication data to the first target storage location bound to the first target data sending channel in the first target data channel group.

[0032] A first sending module is configured to send a first interrupt notification to a second kernel, so that the second kernel can obtain the first communication data from the first target storage location according to the first interrupt notification.

[0033] The second receiving module is used to receive the first response data sent by the second kernel and save the first response data to the second target storage location bound to the first target data receiving channel in the first target data channel group; the first response data corresponds to the first communication data.

[0034] The second sending module is used to send a second interrupt notification to the first kernel, so that the first kernel can obtain the first response data from the second target storage location according to the second interrupt notification.

[0035] Thirdly, this application also discloses an inter-core communication system, including an inter-core communication component, a first kernel, and a second kernel; the inter-core communication component is communicatively connected to the first kernel and the second kernel respectively; the inter-core communication component includes a plurality of first data channel groups, each of the first data channel groups including a first data transmission channel and a first data reception channel corresponding to each other; the inter-core communication component is used to implement the steps of any of the inter-core communication methods described above.

[0036] Fourthly, this application also discloses an electronic device, comprising:

[0037] Memory, used to store computer programs;

[0038] A processor, used to implement any of the inter-core communication methods described above when executing the computer program.

[0039] Fifthly, this application also discloses a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the inter-core communication methods described above.

[0040] In a sixth aspect, the present invention also discloses a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of any of the inter-core communication methods described above.

[0041] This application provides an inter-core communication method applied to an inter-core communication component. The inter-core communication component includes multiple first data channel groups, each of which includes a first data transmission channel and a first data reception channel corresponding to each other. The method includes: receiving first communication data sent by a first kernel; selecting a first target data channel group from the multiple first data channel groups; saving the first communication data to a first target storage location bound to a first target data transmission channel in the first target data channel group; sending a first interrupt notification to a second kernel, so that the second kernel can retrieve the first communication data from the first target storage location according to the first interrupt notification; receiving first response data sent by the second kernel; saving the first response data to a second target storage location bound to a first target data reception channel in the first target data channel group; the first response data corresponds to the first communication data; and sending a second interrupt notification to the first kernel, so that the first kernel can retrieve the first response data from the second target storage location according to the second interrupt notification.

[0042] By applying the technical solution provided in this application, an inter-core communication component is added between the first kernel and the second kernel. This inter-core communication component includes multiple first data channel groups, each of which includes a corresponding first data transmission channel and a first data reception channel. Each first data transmission channel and each first data reception channel are pre-bound to their respective corresponding storage locations for storing inter-core communication data. Based on this, during inter-core communication, when the first kernel sends first communication data to the second kernel, the inter-core communication component can select a first target data channel group and temporarily store the first communication data in the first target storage location bound to the first target data transmission channel. It then notifies the second kernel to retrieve the first communication data from the first target storage location by triggering an interrupt. When the second kernel sends first response data back to the first kernel, the inter-core communication component can temporarily store the first response data in the second target storage location bound to the first target data reception channel corresponding to the first target data transmission channel. It then notifies the first kernel to retrieve the first response data from the second target storage location by triggering an interrupt, thereby realizing data communication between the first kernel and the second kernel. As can be seen, this technical solution sets up multiple data transmission channels in the inter-core communication component, and pre-binds each data transmission channel to its corresponding storage location for storing the communication data transmitted by the corresponding data transmission channel. This can effectively avoid the problem of communication failure caused by multiple cores writing communication data to the same storage location at the same time, and also eliminates the need for the data acquisition kernel to traverse the entire storage location to find the target communication data, thereby achieving stable and efficient inter-core communication.

[0043] In one embodiment of this application, the inter-core communication component may further include multiple first event channel groups, and each first event channel group includes a corresponding first event sending channel and a first event receiving channel. Each first event sending channel and each first event receiving channel does not need to be bound to a storage location and is only used to implement inter-core event notification. Therefore, this technical solution, based on the data channels in the inter-core communication component to achieve inter-core data communication, can also implement inter-core event notification based on the event channels in the inter-core communication component, thus possessing higher practicality.

[0044] The inter-nuclear communication device, system, electronic device, computer-readable storage medium, and computer program product provided in this application also have the above-mentioned technical effects, and will not be described in detail here. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the prior art and the embodiments of this application, the accompanying drawings used in the description of the prior art and the embodiments of this application will be briefly introduced below. Of course, the accompanying drawings described below with respect to the embodiments of this application are only a part of the embodiments in this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort, and such other drawings also fall within the protection scope of this application.

[0046] Figure 1 A flowchart illustrating an inter-core communication method provided in this application;

[0047] Figure 2 A schematic diagram of the data channel structure in an inter-core communication component provided in this application;

[0048] Figure 3 A schematic diagram of the structure of an event channel in an inter-core communication component provided in this application;

[0049] Figure 4 A schematic diagram of the hardware and software architecture of an inter-core communication component provided in this application;

[0050] Figure 5 A flowchart illustrating an inter-core data communication method provided in this application;

[0051] Figure 6 A flowchart illustrating an inter-core event communication method provided in this application;

[0052] Figure 7 A schematic diagram of an inter-nuclear communication device provided in this application;

[0053] Figure 8 This application provides a schematic diagram of the structure of an inter-nuclear communication system.

[0054] Figure 9 This is a schematic diagram of the structure of an electronic device provided in this application. Detailed Implementation

[0055] The core of this application is to provide an inter-core communication method that can achieve more stable and efficient inter-core communication; another core aspect of this application is to provide an inter-core communication device, system, electronic device, computer-readable storage medium, and computer program product, all of which have the aforementioned beneficial effects.

[0056] To provide a clearer and more complete description of the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0057] This application provides an inter-core communication method.

[0058] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating an inter-core communication method provided in this application. The inter-core communication method is applied to an inter-core communication component, which may include multiple first data channel groups (i.e., the data channel group corresponding to the first kernel in the following text). Each first data channel group includes a first data transmission channel (for the first kernel to send communication data) and a first data reception channel (for the first kernel to receive communication data) that correspond to each other. The inter-core communication method may include the following steps S101 to S104.

[0059] S101: Receive the first communication data sent by the first kernel, select the first target data channel group from multiple first data channel groups, and save the first communication data to the first target storage location bound to the first target data sending channel in the first target data channel group.

[0060] This step aims to receive and save the first communication data, which is the communication data sent from the first kernel to the second kernel. Specifically, the inter-core communication component, acting as a data communication tool between the first and second kernels, can acquire the first communication data sent from the first kernel to the second kernel. Then, it selects a first target data channel group from multiple first data channel groups. Specifically, it can select a first data channel group that is in an idle state (both the corresponding first data sending channel and the first data receiving channel are in an idle state) as the first target data channel group for transmitting the first communication data. At this time, the inter-core communication component can first save the first communication data to the first target storage location bound to the first target data sending channel in the first target data channel group for the second kernel to read.

[0061] In one embodiment of this application, selecting a first target data channel group from multiple first data channel groups and saving the first communication data to the first target storage location bound to the first target data transmission channel in the first target data channel group may include: selecting a first data channel group from multiple first data channel groups where neither the status register of the first data transmission channel nor the first data reception channel has a data flag bit set as the first target data channel group; and saving the first communication data to the first target storage location bound to the first target data transmission channel in the first target data channel group.

[0062] As described above, when selecting the first target data channel group, a first data channel group that is in an idle state can be selected as the first target data channel group for transmitting the first communication data. Based on this, the working state of the first data channel group can be determined through a status register. Specifically, a corresponding status register can be pre-configured for each first data transmission channel and each first data reception channel to record the working state of the corresponding data channel. When a data flag is written to the register, it indicates that the corresponding data channel is being used to transmit communication data and is not in an idle state; when no data flag is written to the register, it indicates that the corresponding data channel is not being used to transmit communication data and is in an idle state. Therefore, among all the first data channel groups, the first data channel group whose status registers for both the first data transmission channel and the first data reception channel do not have data flags can be selected as the first target data channel group.

[0063] S102: Send a first interrupt notification to the second kernel so that the second kernel can obtain the first communication data at the first target storage location according to the first interrupt notification.

[0064] This step aims to enable the inter-core communication component to notify the second kernel of an interrupt, so that the second kernel can read and obtain the first communication data from the first target storage location. Specifically, the first interrupt notification is sent by the inter-core communication component to the second kernel after saving the first communication data to the first target storage location.

[0065] In one embodiment of this application, sending a first interrupt notification to a second kernel so that the second kernel can obtain first communication data at a first target storage location according to the first interrupt notification may include: sending a channel message of a first target data transmission channel to the first kernel so that the first kernel writes an interrupt flag bit into the control register corresponding to the first target data transmission channel to generate a first interrupt notification; and sending the first interrupt notification to the second kernel so that the second kernel can obtain first communication data at a first target storage location according to the first interrupt notification.

[0066] This application provides a method for generating a first interrupt notification. Specifically, a corresponding control register can be pre-configured for each first data transmission channel. When an interrupt flag is written into the register, a first interrupt notification can be automatically generated. In implementation, after the inter-core communication component selects and determines the first target data channel group, it can send the channel information (such as the channel identifier) ​​of the first target data transmission channel to the first kernel. The first kernel can then actively write the interrupt flag into the control register corresponding to the first target data transmission channel to generate the first interrupt notification.

[0067] S103: Receive the first response data sent by the second kernel, and save the first response data to the second target storage location bound to the first target data receiving channel in the first target data channel group; the first response data corresponds to the first communication data.

[0068] This step aims to receive and save the first response data, which is communication data fed back from the second kernel to the first kernel. The second kernel obtains this data after acquiring and processing it. Specifically, the inter-core communication component, acting as a data communication tool between the first and second kernels, can acquire the first response data fed back from the second kernel to the first kernel and then directly save it to the second target storage location bound to the first target data receiving channel in the first target data channel group, for the first kernel to read.

[0069] S104: Send a second interrupt notification to the first kernel so that the first kernel can obtain the first response data at the second target storage location according to the second interrupt notification.

[0070] This step aims to enable the inter-core communication component to notify the first kernel of an interrupt, so that the first kernel can read and obtain the first response data from the second target memory location. Specifically, the second interrupt notification is sent by the inter-core communication component to the first kernel after saving the first response data to the second target memory location.

[0071] It is understandable that since the second kernel reads the first communication data sent by the first kernel from the first target storage location bound to the first target data transmission channel in the first target data channel group, it can directly know that the first response data it is about to feed back to the first kernel will be sent to the first kernel through the first target data reception channel in the first target data channel group (because the first target data reception channel corresponds to the first target data transmission channel). Therefore, after the second kernel sends the first response data to the inter-core communication component, it can directly write the interrupt flag bit into the control register corresponding to the first target data reception channel to generate a second interrupt notification, and send it to the first kernel through the inter-core communication component. Thus, the first kernel can read the first response data from the second target storage location according to the second interrupt notification.

[0072] In one embodiment of this application, sending a second interrupt notification to the first kernel so that the first kernel can obtain first response data at the second target storage location according to the second interrupt notification may include: sending a second interrupt notification to the first kernel so that the first kernel changes from a sleep state to a wake-up state, and obtains first response data at the second target storage location according to the second interrupt notification in the wake-up state; wherein, the first kernel changes from a wake-up state to a sleep state after writing the interrupt flag bit into the control register corresponding to the first target data transmission channel.

[0073] Specifically, to effectively avoid wasting kernel resources, the first kernel, after sending the first communication data and writing the interrupt flag into the control register corresponding to the first target data transmission channel, can directly enter a sleep state to wait for wake-up. When the first kernel receives the second interrupt notification, it can enter a wake-up state to obtain the first acknowledgment data corresponding to the first communication data. It is understandable that after the first kernel sends the first communication data, it needs to wait for the second kernel to complete data reception, data processing, and return an acknowledgment. This process involves a certain "waiting delay." If the first kernel remains awake, it will continuously occupy kernel computing resources, resulting in resource waste. However, if the first kernel enters a sleep state at this time, its kernel resources can be scheduled to other tasks, effectively improving kernel resource utilization.

[0074] Furthermore, after sending the second interrupt notification to the first kernel so that the first kernel can obtain the first response data at the second target storage location according to the second interrupt notification, the process may further include: receiving the first clear notification through the status clear register corresponding to the first target data transmission channel; the first clear notification is generated by the second kernel writing a clear flag bit into the status clear register corresponding to the first target data transmission channel after sending the first response data; releasing the first target data transmission channel according to the first clear notification; receiving the second clear notification through the status clear register corresponding to the first target data reception channel; the second clear notification is generated by the first kernel writing a clear flag bit into the status clear register corresponding to the first target data reception channel after receiving the first response data; releasing the second target data reception channel according to the second clear notification.

[0075] Specifically, to effectively avoid wasting data channel resources, after completing data communication between the first and second cores, the first target data transmission channel and the second target data reception channel can be released to provide an idle first data channel group for new data communication. In implementation, a corresponding status clearing register can be pre-configured for each first data transmission channel and each first data reception channel. When a clearing flag is written to it, a clearing notification is automatically generated to allow the inter-core communication component to release the corresponding data channel. Specifically, the clearing flag corresponding to the first clearing notification is written by the second core to the status clearing register corresponding to the first target data transmission channel after sending the first acknowledgment data, to release the first target data transmission channel; the clearing flag corresponding to the second clearing notification is written by the first core to the status clearing register corresponding to the first target data reception channel after receiving the first acknowledgment data, to release the first target data reception channel.

[0076] As can be seen, the inter-core communication method provided in this application adds an inter-core communication component between the first core and the second core. This component includes multiple first data channel groups, each of which includes a corresponding first data transmission channel and a first data reception channel. Each first data transmission channel and each first data reception channel are pre-bound to their respective corresponding storage locations for storing inter-core communication data. Based on this, during inter-core communication, when the first core sends first communication data to the second core, the inter-core communication component can select a first target data channel group and temporarily store the first communication data in the first target storage location bound to the first target data transmission channel. It then notifies the second core to retrieve the first communication data from the first target storage location by triggering an interrupt. When the second core sends first response data back to the first core, the inter-core communication component can temporarily store the first response data in the second target storage location bound to the first target data reception channel corresponding to the first target data transmission channel. It then notifies the first core to retrieve the first response data from the second target storage location by triggering an interrupt, thereby achieving data communication between the first core and the second core. As can be seen, this technical solution sets up multiple data transmission channels in the inter-core communication component, and pre-binds each data transmission channel to its corresponding storage location for storing the communication data transmitted by the corresponding data transmission channel. This can effectively avoid the problem of communication failure caused by multiple cores writing communication data to the same storage location at the same time, and also eliminates the need for the data acquisition kernel to traverse the entire storage location to find the target communication data, thereby achieving stable and efficient inter-core communication.

[0077] In one embodiment of this application, the inter-core communication component further includes a plurality of first event channel groups, each first event channel group including a first event sending channel and a first event receiving channel corresponding to each other; the method further includes: receiving a first event notification sent by a first kernel; selecting a first target event channel group from the plurality of first event channel groups; sending a third interrupt notification to a second kernel, so that the second kernel obtains the first event notification through the first target event sending channel in the first target event channel group according to the third interrupt notification; receiving a first response event sent by the second kernel; the first response event corresponds to the first event notification; sending a fourth interrupt notification to the first kernel, so that the first kernel obtains the first response event through the first target event receiving channel in the first target event channel group according to the fourth interrupt notification.

[0078] Specifically, the inter-core communication component may also include multiple first event channel groups (event channel groups corresponding to the first kernel), and each first event channel group includes a first event sending channel (for the first kernel to send event notifications) and a first event receiving channel (for the first kernel to receive event notifications). Unlike the first data channel group mentioned above, each first event sending channel and each first event receiving channel does not need to be bound to a storage location, because the event notification does not need to transmit data, and is only used to implement the event notification from the first kernel to the second kernel.

[0079] Therefore, this technical solution, based on the data channel in the inter-core communication component to realize inter-core data communication, can also realize inter-core event notification based on the event channel in the inter-core communication component, thus having higher practicality.

[0080] In one embodiment of this application, the inter-core communication component further includes multiple second data channel groups (data channel groups corresponding to the second kernel), each second data channel group including a corresponding second data transmission channel (for the second kernel to send communication data) and a second data reception channel (for the second kernel to receive communication data); the inter-core communication method may further include: receiving second communication data sent by the second kernel; selecting a second target data channel group from the multiple second data channel groups; saving the second communication data to a third target storage location bound to the second target data transmission channel in the second target data channel group; sending a fifth interrupt notification to the first kernel, so that the first kernel can obtain the second communication data from the third target storage location according to the fifth interrupt notification; receiving second response data sent by the first kernel; saving the second response data to a fourth target storage location bound to the second target data reception channel in the second target data channel group; the second response data corresponds to the second communication data; and sending a sixth interrupt notification to the second kernel, so that the second kernel can obtain the second response data from the fourth target storage location according to the sixth interrupt notification.

[0081] Furthermore, the inter-core communication component also includes multiple second event channel groups (event channel groups corresponding to the second kernel), each second event channel group including a corresponding second event sending channel (for the second kernel to send event notifications) and a second event receiving channel (for the second kernel to receive event notifications); the inter-core communication method may also include: receiving a second event notification sent by the second kernel; selecting a second target event channel group from the multiple second event channel groups; sending a seventh interrupt notification to the first kernel, so that the first kernel can obtain the second event notification through the second target event sending channel in the second target event channel group according to the seventh interrupt notification; receiving a second response event sent by the first kernel; the second response event corresponds to the second event notification; sending an eighth interrupt notification to the second kernel, so that the second kernel can obtain the second response event through the second target event receiving channel in the second target event channel group according to the eighth interrupt notification.

[0082] It should be noted that in the inter-core communication scenario where the first kernel sends communication data and event notifications to the second kernel as described above, the above embodiments correspond to the inter-core communication scenario where the second kernel sends communication data and event notifications to the first kernel. The specific implementation method can be referred to the embodiments described above, and will not be repeated here.

[0083] This application provides another method for inter-core communication.

[0084] This application uses a dual-core CPU as an example to describe the inter-core communication method, namely CPU1 and CPU2, with Linux and RTOS operating systems respectively. Specifically, CPU1 runs Linux, and CPU2 runs RTOS. A hardware module (essentially an inter-core communication component) exists between the two cores for inter-core communication, and both CPU cores can access this hardware module.

[0085] Please refer to Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the data channel structure in an inter-core communication component provided in this application. Figure 3 This is a schematic diagram of the structure of an event channel in an inter-core communication component provided in this application. Figure 2As shown, the data channel includes data sending channels and data receiving channels. Taking four groups of data channels as an example, namely data channel group 0, group 1, group 2, and group 3, each group includes four data channels. For example, data channel group 0 includes CPU1 sending data channel 0, CPU1 receiving data channel 0, CPU2 sending data channel 0, and CPU2 receiving data channel 0. The data channels are directional. For example, CPU1 sending data channel is for CPU1 writing and CPU2 reading; CPU1 receiving data channel is for CPU2 writing and CPU1 reading; CPU2 sending data channel is for CPU2 writing and CPU1 reading; and CPU2 receiving data channel is for CPU1 writing and CPU2 reading. Each data channel is bound to a segment of address space on DDR / SRAM for storing inter-core communication data. For example, the address space mapped to each data channel can be 1KB in size. Figure 3 As shown, the event channel and data channel are basically the same. The difference is that the event channel is not bound to a segment of address space on DDR / SRAM. The event channel is mainly used for event notification and cannot be used to transmit specific data.

[0086] Furthermore, each data channel and each event channel is configured with three corresponding registers for communication control: a channel control register, a channel status register, and a channel status clearing register. The following description uses the data transmission and reception channels of CPU1 as an example. The registers of the data transmission and reception channels and event channels of CPU2 are similar to those of the data transmission and reception channels of CPU1, except that the data transmission direction differs; therefore, they will not be described separately in this embodiment.

[0087] 1. CPU1 Data Transmission Channel Control Register: Only CPU1 can perform write operations. Writing 1 to the corresponding bit will generate a corresponding interrupt from CPU2. WO indicates write-only. As shown in Table 1, Table 1 is a description table of the data transmission channel control register:

[0088] Table 1. Description of Data Transmission Channel Control Registers

[0089]

[0090] 2. CPU1 Data Transmission Channel Status Register: 0 indicates the channel is empty, and CPU1 can use the corresponding data channel to send data; 1 indicates the channel has data, and CPU2 can receive data from the corresponding data channel; RO indicates read-only. See Table 2 for an explanation of the data transmission channel status register.

[0091] Table 2. Description of Data Transmission Channel Status Register

[0092]

[0093] 3. CPU1 Data Transmission Channel Status Clear Register: Only CPU2 processor can perform write operations on this register. Writing 1 will clear the corresponding bit in the status register. WO indicates write-only. As shown in Table 3, Table 3 is a description of the data transmission channel status clear register.

[0094] Table 3. Explanation of Data Transmission Channel Status Clear Register

[0095]

[0096] 4. CPU1 Data Receive Channel Control Register: Only CPU2 processor can perform write operations. Writing 1 to the corresponding bit will generate a corresponding interrupt on CPU1. WO indicates write-only. As shown in Table 4, Table 4 is a description table of the data receive channel control register:

[0097] Table 4. Description of Data Receive Channel Control Registers

[0098]

[0099] 5. CPU1 Data Receive Channel Status Register: 0 indicates the channel is empty, and CPU2 can use the corresponding data channel to send response data to CPU1; 1 indicates there is data in the channel, and CPU1 can receive data from the corresponding data channel; RO indicates read-only. See Table 5 for an explanation of the data receive channel status register.

[0100] Table 5. Description of Data Receive Channel Status Register

[0101]

[0102] 6. CPU1 Data Receive Channel Status Clear Register: Only CPU1 processor can perform write operations. Writing 1 will clear the corresponding bit in the status register. WO indicates write-only. As shown in Table 6, Table 6 is a description of the data receive channel status clear register:

[0103] Table 6. Explanation of Data Receive Channel Status Clear Register

[0104]

[0105] For further information, please refer to [link / reference]. Figure 4 , Figure 4 This is a schematic diagram of the hardware and software architecture of an inter-core communication component provided in this application. CPU1 and CPU2 communicate with each other through an inter-core communication hardware module. The software requires an inter-core communication hardware module driver. On the driver, there is an inter-core communication monitoring module responsible for communicating with the inter-core communication hardware module driver. At the same time, the inter-core communication monitoring module is also responsible for communicating with specific intra-core processes.

[0106] Finally, please refer to Figure 5 , Figure 5 This is a flowchart illustrating an inter-core data communication method provided in this application. Taking the process of a Linux system sending communication data to an RTOS system as an example: First, a process in the Linux system sends communication data to the inter-core communication monitoring module. The inter-core communication monitoring module is responsible for communicating with the inter-core communication hardware module driver, opening the device file, and using the Linux system's general interface ioctl to send communication data to the inter-core communication hardware module driver. After receiving the communication data, the inter-core communication hardware module driver searches for an idle transmission channel (the corresponding bit in the status register of the transmission and reception channels is 0, indicating that the corresponding channel is empty). If no idle transmission channel is found, the data transmission fails. If an idle transmission channel is found, the communication data is copied to the storage space corresponding to the idle channel. Then, the control register corresponding to the transmission channel triggers an interrupt to notify the RTOS system, and the Linux system will sleep, waiting for the RTOS system to return acknowledgment data to wake it up. After receiving an interrupt notification for inter-core communication, the RTOS system copies the communication data from the corresponding channel to a queue and wakes up the corresponding data processing task to process the communication data in the queue. Then, it copies the acknowledgment data to the corresponding receive channel of CPU1 (e.g., if CPU1 transmit channel 0 is used for sending data, then CPU1 receive channel 0 is used here). It sets the control register of the CPU1 receive channel, triggers an interrupt, and notifies the Linux system to receive the acknowledgment data. Finally, the RTOS system clears the corresponding status bit in the status clear register of the CPU1 transmit channel and releases that transmit channel. The Linux system, awakened by the inter-core communication interrupt, receives the acknowledgment data from the corresponding receive channel, then sets the receive channel status clear register to release the receive channel. Afterward, the inter-core communication hardware module driver in the Linux system returns the received acknowledgment data to the process in the Linux system. Of course, the process of the RTOS system sending data to the Linux system and the process of the Linux system sending data to the RTOS system are basically the same, and will not be repeated here.

[0107] Please refer to Figure 6 , Figure 6This is a flowchart illustrating an inter-core event communication method provided in this application. Taking the process of a Linux system sending an event notification to an RTOS system as an example: First, process 1 in the Linux system needs to send an event notification to the RTOS system. It sends a command to the inter-core communication monitoring module. The inter-core communication module sends the event notification to the inter-core communication hardware module driver. The inter-core communication hardware module driver searches for an idle event sending channel (the corresponding bits in the send and receive channel status registers are both 0, indicating that the corresponding channel is empty). If no idle event channel is found, the sending fails. If an idle event channel is found, the CPU1 event channel register is set to trigger an interrupt notification to the RTOS system. Then, the Linux system sleeps, waiting for the interrupt notification from the corresponding event receiving channel. When the RTOS system receives the inter-core communication interrupt, it calls the corresponding callback function to handle the event notification, sets the CPU1 event receiving channel register, triggers an interrupt notification to the Linux system, and finally sets the CPU1 event sending channel status clear register. After receiving the corresponding event receiving channel interrupt, the Linux system sets the CPU1 event receiving channel status clear register, releases the channel, and finally returns the event result to process 1. Of course, the process of an RTOS system sending events to a Linux system is basically the same as the process of a Linux system sending events to an RTOS system, so it will not be repeated here.

[0108] Therefore, the inter-core communication method provided in this application adds an inter-core communication component between the first core and the second core. This component includes multiple data channel groups, each containing corresponding data sending and receiving channels for transmitting inter-core communication data. Each data sending and receiving channel is pre-bound to its corresponding storage location for temporary storage of the inter-core communication data. Thus, this technical solution effectively avoids communication failures caused by multiple cores simultaneously writing communication data to the same storage location, and eliminates the need for the data acquisition kernel to traverse the entire storage location to find the target communication data, thereby achieving stable and efficient inter-core communication. Furthermore, the inter-core communication component can also include multiple event channel groups, each containing corresponding event sending and receiving channels for inter-core event notification. Therefore, this technical solution, in addition to implementing inter-core data communication based on the data channels in the inter-core communication component, can also implement inter-core event notification based on the event channels, making it more practical.

[0109] This application provides an inter-core communication device.

[0110] Please refer to Figure 7 , Figure 7This application provides a schematic diagram of an inter-core communication device. The device is applied to an inter-core communication component, which may include multiple first data channel groups. Each first data channel group includes a corresponding first data transmission channel and a first data reception channel. The inter-core communication method apparatus may include:

[0111] The first receiving module 1 is used to receive the first communication data sent by the first kernel, select the first target data channel group from multiple first data channel groups, and save the first communication data to the first target storage location bound to the first target data sending channel in the first target data channel group.

[0112] The first sending module 2 is used to send a first interrupt notification to the second kernel, so that the second kernel can obtain the first communication data at the first target storage location according to the first interrupt notification;

[0113] The second receiving module 3 is used to receive the first response data sent by the second kernel and save the first response data to the second target storage location bound to the first target data receiving channel in the first target data channel group; the first response data corresponds to the first communication data.

[0114] The second sending module 4 is used to send a second interrupt notification to the first kernel, so that the first kernel can obtain the first response data at the second target storage location according to the second interrupt notification.

[0115] As can be seen, the inter-core communication device provided in this application embodiment adds an inter-core communication component between the first core and the second core. This inter-core communication component includes multiple first data channel groups, and each first data channel group includes a corresponding first data transmission channel and a first data reception channel. Each first data transmission channel and each first data reception channel are pre-bound to their respective corresponding storage locations for storing inter-core communication data. Based on this, during inter-core communication, when the first core sends first communication data to the second core, the inter-core communication component can select a first target data channel group and temporarily store the first communication data in the first target storage location bound to the first target data transmission channel. It then notifies the second core to retrieve the first communication data from the first target storage location by triggering an interrupt. When the second core sends first response data back to the first core, the inter-core communication component can temporarily store the first response data in the second target storage location bound to the first target data reception channel corresponding to the first target data transmission channel. It then notifies the first core to retrieve the first response data from the second target storage location by triggering an interrupt, thereby realizing data communication between the first core and the second core. As can be seen, this technical solution sets up multiple data transmission channels in the inter-core communication component, and pre-binds each data transmission channel to its corresponding storage location for storing the communication data transmitted by the corresponding data transmission channel. This can effectively avoid the problem of communication failure caused by multiple cores writing communication data to the same storage location at the same time, and also eliminates the need for the data acquisition kernel to traverse the entire storage location to find the target communication data, thereby achieving stable and efficient inter-core communication.

[0116] In one embodiment of this application, the first receiving module 1 can be specifically used to select, among multiple first data channel groups, a first data channel group in which neither the status register of the first data sending channel nor the first data receiving channel has a data flag bit set as the first target data channel group; and to save the first communication data to the first target storage location bound to the first target data sending channel in the first target data channel group.

[0117] In one embodiment of this application, the first sending module 2 can be specifically used to send a channel message of the first target data sending channel to the first kernel, so that the first kernel writes an interrupt flag bit into the control register corresponding to the first target data sending channel to generate a first interrupt notification; and send the first interrupt notification to the second kernel, so that the second kernel obtains the first communication data at the first target storage location according to the first interrupt notification.

[0118] In one embodiment of this application, the second sending module 4 can be specifically used to send a second interrupt notification to the first kernel, so that the first kernel changes from a sleep state to a wake-up state, and obtains the first response data in the second target storage location according to the second interrupt notification in the wake-up state; wherein, the first kernel changes from a wake-up state to a sleep state after writing the interrupt flag bit into the control register corresponding to the first target data sending channel.

[0119] In one embodiment of this application, the inter-core communication method apparatus may further include a release module, configured to receive a first clearing notification through a status clearing register corresponding to the first target data transmission channel after sending a second interrupt notification to the first kernel, so that the first kernel obtains the first response data at the second target storage location according to the second interrupt notification; the first clearing notification is generated by the second kernel writing a clearing flag bit into the status clearing register corresponding to the first target data transmission channel after sending the first response data; the first target data transmission channel is released according to the first clearing notification; a second clearing notification is received through a status clearing register corresponding to the first target data reception channel; the second clearing notification is generated by the first kernel writing a clearing flag bit into the status clearing register corresponding to the first target data reception channel after receiving the first response data; the second target data reception channel is released according to the second clearing notification.

[0120] In one embodiment of this application, the inter-core communication component may further include multiple first event channel groups, each first event channel group may include a first event sending channel and a first event receiving channel corresponding to each other; the inter-core communication method apparatus may further include an event communication module, used to receive a first event notification sent by a first kernel, select a first target event channel group from the multiple first event channel groups; send a third interrupt notification to a second kernel, so that the second kernel obtains the first event notification through the first target event sending channel in the first target event channel group according to the third interrupt notification; receive a first response event sent by the second kernel; the first response event corresponds to the first event notification; send a fourth interrupt notification to the first kernel, so that the first kernel obtains the first response event through the first target event receiving channel in the first target event channel group according to the fourth interrupt notification.

[0121] For a description of the apparatus provided in the embodiments of this application, please refer to the above method embodiments; further details will not be repeated here.

[0122] This application provides an inter-core communication system.

[0123] Please refer to Figure 8 , Figure 8This application provides a schematic diagram of an inter-core communication system, which may include: an inter-core communication component 100, a first core 200, and a second core 300; the inter-core communication component 100 is communicatively connected to the first core 200 and the second core 300; the inter-core communication component 100 includes multiple first data channel groups, each first data channel group including a first data transmission channel and a first data reception channel corresponding to each other; the inter-core communication component 100 is used to implement the steps of any of the above-described inter-core communication methods.

[0124] For a description of the system provided in the embodiments of this application, please refer to the above method embodiments; further details will not be repeated here.

[0125] This application provides an electronic device.

[0126] Please refer to Figure 9 , Figure 9 This application provides a schematic diagram of the structure of an electronic device, which may include:

[0127] Memory 11 is used to store computer programs;

[0128] The processor 10 is configured to execute computer programs and implement steps of any of the inter-core communication methods described above.

[0129] like Figure 9 The diagram shows the structural composition of an electronic device, which may include a processor 10, a memory 11, a communication interface 12, and a communication bus 13. The processor 10, memory 11, and communication interface 12 all communicate with each other through the communication bus 13.

[0130] In this embodiment, the processor 10 may be a central processing unit (CPU), an application-specific integrated circuit, a digital signal processor, a field-programmable gate array, or other programmable logic devices. The processor 10 may call programs stored in the memory 11; specifically, the processor 10 may execute the operations described in the embodiment of the inter-core communication method.

[0131] The memory 11 is used to store one or more programs. The programs may include program code, which includes computer operation instructions. In this embodiment, the memory 11 stores at least a program for implementing the following functions:

[0132] The system receives first communication data sent by a first kernel, selects a first target data channel group from multiple first data channel groups, and saves the first communication data to a first target storage location bound to the first target data sending channel in the first target data channel group; sends a first interrupt notification to a second kernel, so that the second kernel can retrieve the first communication data from the first target storage location according to the first interrupt notification; receives first response data sent by the second kernel, and saves the first response data to a second target storage location bound to the first target data receiving channel in the first target data channel group; the first response data corresponds to the first communication data; and sends a second interrupt notification to the first kernel, so that the first kernel can retrieve the first response data from the second target storage location according to the second interrupt notification.

[0133] In one possible implementation, memory 11 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; and the data storage area may store data created during use. Furthermore, memory 11 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device or other volatile solid-state storage device.

[0134] Communication interface 12 can be an interface for the communication module, used to connect with other devices or systems.

[0135] Of course, it should be noted that, Figure 9 The structure shown does not constitute a limitation on the electronic device in the embodiments of this application. In practical applications, the electronic device may include more than Figure 9 More or fewer components as shown, or combinations of certain components.

[0136] This application provides a computer-readable storage medium.

[0137] The computer-readable storage medium provided in this application embodiment stores a computer program, which, when executed by a processor, can implement the steps of any of the inter-core communication methods described above.

[0138] The computer-readable storage medium can be any available medium that a computer can store, or an inter-core communication device such as a server or data center that integrates one or more available media. For example, it can be any medium that can store computer program code, such as magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives).

[0139] For a description of the computer-readable storage medium provided in the embodiments of this application, please refer to the above method embodiments; further details will not be repeated here.

[0140] This application provides a computer program product.

[0141] The computer program product provided in this application includes a computer program / instruction, which, when executed by a processor, can implement the steps of any of the inter-core communication methods described above.

[0142] Specifically, in the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, in the form of a computer program product.

[0143] The computer program product may include one or more computer programs / instructions, which, when loaded and executed on a computer, can generate all or part of the processes or functions described in the embodiments of this application. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line, etc.) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0144] For a description of the computer program products provided in the embodiments of this application, please refer to the above method embodiments; further details will not be repeated here.

[0145] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0146] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0147] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0148] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A method for inter-core communication, characterized in that, The method is applied to an inter-core communication component, the inter-core communication component comprising a plurality of first data channel groups, each first data channel group comprising a corresponding first data transmission channel and a first data reception channel; the method includes: Receive the first communication data sent by the first kernel, select the first target data channel group from multiple first data channel groups, and save the first communication data to the first target storage location bound to the first target data sending channel in the first target data channel group; Send a first interrupt notification to the second kernel, so that the second kernel can obtain the first communication data from the first target storage location according to the first interrupt notification; Receive the first response data sent by the second kernel, and save the first response data to the second target storage location bound to the first target data receiving channel in the first target data channel group; the first response data corresponds to the first communication data. A second interrupt notification is sent to the first kernel, so that the first kernel can obtain the first response data from the second target storage location according to the second interrupt notification.

2. The inter-nuclear communication method according to claim 1, characterized in that, Selecting a first target data channel group from multiple first data channel groups, and saving the first communication data to the first target storage location bound to the first target data transmission channel in the first target data channel group, including: Among the multiple first data channel groups, the first data channel group in which neither the status register of the first data transmission channel nor the first data reception channel has a data flag bit is selected as the first target data channel group; The first communication data is saved to the first target storage location bound to the first target data transmission channel in the first target data channel group.

3. The inter-nuclear communication method according to claim 1, characterized in that, Sending a first interrupt notification to the second kernel, so that the second kernel can retrieve the first communication data from the first target storage location according to the first interrupt notification, includes: Send the channel message of the first target data transmission channel to the first kernel, so that the first kernel writes the interrupt flag bit into the control register corresponding to the first target data transmission channel to generate the first interrupt notification; The first interrupt notification is sent to the second kernel, so that the second kernel can obtain the first communication data from the first target storage location according to the first interrupt notification.

4. The inter-nuclear communication method according to claim 3, characterized in that, Sending a second interrupt notification to the first kernel, so that the first kernel can retrieve the first response data from the second target storage location according to the second interrupt notification, including: Send the second interrupt notification to the first kernel to cause the first kernel to switch from a sleep state to a wake-up state, and in the wake-up state, retrieve the first response data from the second target storage location according to the second interrupt notification; The first kernel transitions from the wake-up state to the sleep state after writing the interrupt flag into the control register corresponding to the first target data transmission channel.

5. The inter-core communication method according to claim 1, characterized in that, After sending a second interrupt notification to the first kernel, so that the first kernel retrieves the first response data from the second target storage location based on the second interrupt notification, the method further includes: The first clear notification is received through the status clear register corresponding to the first target data transmission channel; the first clear notification is generated by the second kernel writing a clear flag bit into the status clear register corresponding to the first target data transmission channel after sending the first response data. Release the first target data transmission channel according to the first zeroing notification; The second clearing notification is received through the status clearing register corresponding to the first target data receiving channel; the second clearing notification is generated by the first kernel writing a clearing flag bit into the status clearing register corresponding to the first target data receiving channel after receiving the first response data. Release the second target data receiving channel according to the second zeroing notification.

6. The inter-core communication method according to any one of claims 1 to 5, characterized in that, The inter-core communication component further includes multiple first event channel groups, each of which includes a corresponding first event sending channel and a first event receiving channel. The method further includes: Receive the first event notification sent by the first kernel, and select the first target event channel group from multiple first event channel groups; Send a third interrupt notification to the second kernel, so that the second kernel can obtain the first event notification through the first target event sending channel in the first target event channel group according to the third interrupt notification; Receive a first response event sent by the second kernel; the first response event corresponds to the first event notification; A fourth interrupt notification is sent to the first kernel, so that the first kernel can obtain the first response event through the first target event receiving channel in the first target event channel group according to the fourth interrupt notification.

7. An inter-nuclear communication device, characterized in that, An apparatus is applied to an inter-core communication component, the inter-core communication component comprising a plurality of first data channel groups, each first data channel group comprising a corresponding first data transmission channel and a first data reception channel; the apparatus includes: The first receiving module is used to receive the first communication data sent by the first kernel, select a first target data channel group from a plurality of first data channel groups, and save the first communication data to the first target storage location bound to the first target data sending channel in the first target data channel group. A first sending module is configured to send a first interrupt notification to a second kernel, so that the second kernel can obtain the first communication data from the first target storage location according to the first interrupt notification. The second receiving module is used to receive the first response data sent by the second kernel and save the first response data to the second target storage location bound to the first target data receiving channel in the first target data channel group; the first response data corresponds to the first communication data. The second sending module is used to send a second interrupt notification to the first kernel, so that the first kernel can obtain the first response data from the second target storage location according to the second interrupt notification.

8. An inter-nuclear communication system, characterized in that, The system includes an inter-core communication component, a first kernel, and a second kernel; the inter-core communication component is communicatively connected to the first kernel and the second kernel respectively; the inter-core communication component includes a plurality of first data channel groups, each of the first data channel groups including a first data transmission channel and a first data reception channel corresponding to each other; the inter-core communication component is used to implement the steps of the inter-core communication method as described in any one of claims 1 to 6.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the inter-core communication method as described in any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the inter-core communication method as described in any one of claims 1 to 6.

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