A general shuttle scheduling method and system

Abstract

The application relates to the technical field of quantum computing, and discloses a general shuttle scheduling method and system. The method comprises the following steps: formalizing modeling of architecture constraints of quantum computing hardware, converting hardware physical limitations into a set of Boolean satisfiability constraints through a Boolean satisfiability expression; extracting features of an input quantum circuit, constructing a directed acyclic graph model, extracting a dependency relationship between operations, and forming logical constraints; generating a shuttle scheduling scheme based on the set of Boolean satisfiability constraints and the logical constraints; the shuttle scheduling scheme comprises an accurate optimal scheduling mode and an efficient approximate scheduling mode; the application establishes a standardized shuttle scheduling process, which can quickly adapt to various quantum computing hardware architectures; through dichotomy search optimization and divide-and-conquer approximation strategies, the efficient processing of large-scale quantum circuits is realized while the optimality of small-scale quantum circuits is ensured.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, specifically to a general shuttle scheduling method and system. Background Technology

[0002] Quantum computing holds promise for surpassing classical computing in solving specific problems, with physical platforms such as ion traps and neutral atoms attracting significant attention due to their advantages, including high-fidelity gate operations and long coherence times. In these scalable architectures based on qubit shuttles (such as quantum charge-coupled devices, QCCDs), qubits need to move between different physical regions to interact, and the efficiency of the shuttle scheduling scheme directly determines the execution time and fidelity of the quantum circuit.

[0003] Existing shuttle scheduling techniques mainly fall into two categories. The first is based on exact solutions, using Boolean satisfiability (SAT) solvers or integer programming to search for the globally optimal scheduling sequence, guaranteeing the finding of the theoretically minimum number of time steps under given constraints. However, such methods face severe scalability issues as the number of qubits and line depth increases, with solution time growing exponentially, making them prone to timeouts in practical applications. The second is based on heuristic search or rule-based methods, using greedy strategies or phased planning to quickly generate feasible scheduling schemes, capable of handling large-scale lines. However, due to the lack of global optimality guarantees, these methods often generate a large number of redundant movement operations, leading to decreased scheduling efficiency and prolonged execution time.

[0004] More importantly, most existing technologies are custom-designed for specific hardware architectures (such as one-dimensional linear ion traps or specific topologies), lacking cross-platform versatility. When hardware layout or physical constraints change, scheduling algorithms need to be redesigned or significantly adjusted, making it difficult to adapt to the diverse development needs of quantum computing chips.

[0005] To address the aforementioned issues, there is an urgent need for a shuttle scheduling framework that can balance versatility, optimality, and scalability to support efficient scheduling across different quantum computing hardware platforms. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a general shuttle scheduling method and system. This invention decouples the algorithm and architecture through Boolean satisfiability (SAT) modeling, establishing a standardized shuttle scheduling process that can quickly adapt to various quantum computing hardware architectures. Through binary search optimization and divide-and-conquer approximation strategies, it achieves efficient processing of large-scale quantum circuits while ensuring optimality for small-scale quantum circuits. To address the problem of ineffective moves easily generated by approximation schemes, a dynamic programming algorithm eliminates redundant scheduling segments in linear time, effectively reducing the risk of decoherence of qubits.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a general shuttle scheduling method, comprising:

[0009] Formal modeling of the architectural constraints of quantum computing hardware is performed, and the physical constraints of the hardware are transformed into a set of Boolean satisfiability constraints through Boolean satisfiability expressions;

[0010] Feature extraction is performed on the input quantum circuit to construct a directed acyclic graph model, and the dependencies between operations are extracted to form logical constraints;

[0011] Based on the Boolean satisfiability constraint set and logical constraints, a shuttle scheduling scheme is generated. The shuttle scheduling scheme includes an exact optimal scheduling mode and an efficient approximate scheduling mode. The exact optimal scheduling mode uses a binary search strategy to iteratively solve for the minimum time step until a satisfiable solution is obtained. The efficient approximate scheduling mode uses a divide-and-conquer strategy to divide the quantum circuit into sub-units, solves each sub-unit separately, and then dynamically splices them into a global scheduling sequence. The spliced ​​global scheduling sequence is then optimized by eliminating redundant segments.

[0012] In one embodiment, the step of transforming hardware physical constraints into a set of Boolean satisfyability constraints using a Boolean satisfyability expression specifically includes:

[0013] Position Existence and Uniqueness Constraints: Each Quantum Bit in a Quantum Circuit at any time step They must all occupy exactly one physical location;

[0014] Location capacity mutual exclusion constraint: for each physical location At most one qubit can be accommodated at any given time step, meaning that for any two different qubits... and It is not allowed to occupy the same physical location at the same time;

[0015] The closest traveler constraint: if the quantum bit At time step Located in physical location Then the quantum bit At time step The physical location can only be a set of physical locations. One of the options is to remain stationary or move to an adjacent physical location; for boundary physical locations, options outside the range will be omitted.

[0016] Uncrossable constraint: Quantum bit and They cannot skip each other.

[0017] In one embodiment, the step of extracting features from the input quantum circuit, constructing a directed acyclic graph model, and extracting dependencies between operations to form logical constraints specifically includes:

[0018] In a directed acyclic graph (DAG) model, each node uniquely corresponds to a quantum operation in a quantum circuit. A Boolean variable is defined for each node to represent the completion state of the corresponding quantum operation. Each edge in the DAG model reflects the qubit dependency and control dependency between quantum operations. The DAG model needs to satisfy the topological order binding constraint: if a quantum operation is marked as completed, all its preceding quantum operations must be in a completed state.

[0019] In one embodiment, the quantum operations include single-qubit gate operations, two-qubit gate operations, and measurement operations;

[0020] The qubit dependency is as follows: when two gate operations share at least one qubit, a predecessor-successor relationship must be established based on the timing of the two gate operations in the quantum circuit.

[0021] Control dependency: For controlled quantum gate operations, operations on the control bits must take precedence over operations on the target bits and are connected by directed edges.

[0022] In one embodiment, the binary search strategy adopted by the precise optimal scheduling mode specifically includes: setting upper and lower bounds for the time step, taking the middle value to perform Boolean satisfiability calculation, updating the upper bound if it is satisfiable, updating the lower bound otherwise, iterating until the upper and lower bounds converge to obtain the minimum time step.

[0023] In one embodiment, the preset time step upper and lower bounds are used to perform Boolean satisfiability calculations by taking the median value. If satisfiability is achieved, the upper bound is updated; otherwise, the lower bound is updated. This process is iterated until the upper and lower bounds converge to obtain the minimum time step. Specifically, this includes:

[0024] The binary search strategy is based on the monotonicity of the scheduling solution space: for steps smaller than the minimum time step... The estimated value is unsatisfiable according to Boolean satisfiability; for the estimated value greater than or equal to the minimum time step, the result is satisfiable; by maintaining the left and right boundaries of the search interval, the intermediate value is calculated in each iteration for solution. If the result is satisfiable, the upper bound is updated and the current solution is recorded. If the result is unsatisfiable, the lower bound is updated; and auxiliary boundary variables are introduced for pruning optimization. The search is terminated when adjacent search intervals are detected.

[0025] In one embodiment, the efficient approximate scheduling mode employs a divide-and-conquer strategy to divide the quantum circuit into sub-units, solves each sub-unit separately, and then dynamically concatenates them into a global scheduling sequence, specifically including:

[0026] Based on the topological structure of the directed acyclic graph, the quantum circuit is divided into several sub-units, maintaining the original topological order between sub-units and preserving the dependencies between quantum operations within the sub-units. When solving each sub-unit independently, an adaptive time window mechanism is adopted to estimate the preset initial time constraints based on hardware characteristics. If there is no solution under the current constraints, the time window is dynamically expanded using elastic coefficients and the solution is re-solved. Finally, the local scheduling sequences of each sub-unit are concatenated into a global scheduling sequence.

[0027] In one embodiment, the optimization of eliminating redundant fragments in the spliced ​​global scheduling sequence specifically includes:

[0028] The global scheduling sequence is divided into no-operation intervals based on the execution time of quantum gate operations; the layout of qubits in each no-operation interval is mapped to an integer layout code to obtain an integer sequence; redundant subsequences in the integer sequence are eliminated by a dynamic programming algorithm, wherein the redundant subsequence is defined as a continuous time step with the same layout code at the beginning and end and no quantum gate operations in the middle.

[0029] In one embodiment, the elimination of redundant subsequences in an integer sequence using a dynamic programming algorithm specifically includes:

[0030] Construct a state array result, where the i-th element of result is... This represents the shortest length of the subsequence formed by the layout encoding of the first i time steps of the integer sequence after eliminating all redundancy;

[0031] Iterate through each layout code in the integer sequence in order. For the (i+1)th layout code... :

[0032] like If it has not appeared before, then ;

[0033] like If it has appeared before, then for all satisfying... and At position k, calculate the candidate value result[k], and take the minimum value among all candidate values. Set as The smaller of the minimum values;

[0034] At the same time, an auxiliary record table is maintained to store the minimum result[k] corresponding to each layout code in real time.

[0035] In a second aspect, the present invention provides a computer system including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method of any embodiment of the first aspect.

[0036] Compared with the prior art, the beneficial technical effects of the present invention are:

[0037] This invention formally models diverse hardware constraints using Boolean satisfiability expressions, decoupling the scheduling algorithm from the underlying physical architecture. By integrating a precise optimization algorithm based on binary search and an efficient approximation algorithm based on divide-and-conquer strategy, it flexibly provides optimal or highly scalable shuttle scheduling schemes for quantum circuits of different sizes. Attached Figure Description

[0038] Figure 1 This is a flowchart of the method of the present invention;

[0039] Figure 2 This is an overall framework diagram of the present invention;

[0040] Figure 3 This is an example diagram of an ion trap architecture for a one-dimensional quantum charge-coupled device (QCCD). Detailed Implementation

[0041] A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

[0042] like Figure 1 As shown, a general shuttle scheduling method of the present invention includes the following steps:

[0043] S1 formally models the architectural constraints of quantum computing hardware, transforming the physical constraints of the hardware into a set of Boolean satisfiability constraints through Boolean satisfiability expressions;

[0044] S2 extracts features from the input quantum circuit, constructs a directed acyclic graph model, and extracts the dependencies between operations to form logical constraints;

[0045] S3. Based on the Boolean satisfiability constraint set and logical constraints, a shuttle scheduling scheme is generated. The shuttle scheduling scheme includes an exact optimal scheduling mode and an efficient approximate scheduling mode. The exact optimal scheduling mode uses a binary search strategy to iteratively solve for the minimum time step until a satisfiable solution is obtained. The efficient approximate scheduling mode uses a divide-and-conquer strategy to divide the quantum circuit into sub-units, solves each sub-unit separately, and then dynamically splices them into a global scheduling sequence. The spliced ​​global scheduling sequence is then optimized by eliminating redundant segments.

[0046] The following is a detailed explanation in several parts.

[0047] 1. Hardware architecture constraint modeling.

[0048] This invention does not target a single chip layout, but rather abstracts hardware constraints into a set of configurable Boolean satisfiability (SAT) constraints. For any given scheduling-based quantum computing chip (such as ion trap quantum computing, neutral atom quantum computing, etc.), it is only necessary to express the physical constraints of the hardware (such as chip structure topology diagram, qubit operation constraints) using Boolean satisfiability (SAT) expressions to incorporate them into the framework of this invention.

[0049] (1) Hardware architecture example:

[0050] The following is an example of adaptation based on the one-dimensional quantum charge-coupled device (QCCD) architecture in ion trap quantum computing. Figure 3 For a minimized one-dimensional linear quantum charge-coupled device (QCCD) architecture, the following physical model assumptions are adopted:

[0051] Topology: There are L discrete qubit regions arranged in a one-dimensional linear link.

[0052] Capacity constraint: Each physical location can hold at most one qubit.

[0053] Local connectivity: Within each time step, a qubit can remain in its original position or move to an adjacent physical location.

[0054] Order preservation: During the shuttle movement, the relative order of all qubits in the one-dimensional structure cannot be changed.

[0055] This invention adopts a time-step-based shuttle paradigm, where the time step is the basic unit for coordinating parallel movement with other underlying operations.

[0056] (2) Hardware architecture constraint modeling example: For the above hardware architecture, use Representing a quantum bit ; Represents the total number of time steps; uses a Boolean variable. At time step Time qubit Does it exist in physical location? In the middle, it can be transformed into the following Boolean satisfiability (SAT) model:

[0057] Existence and uniqueness of position: for each qubit at any time step Each qubit must occupy exactly one physical location. This prevents qubits from disappearing or appearing in multiple physical locations simultaneously.

[0058] ;

[0059] The above formula uses symbols related to discrete mathematical propositional logic, where: This indicates a large disjunction, i.e., a large disjunction on the index. from arrive The proposition is ORed to ensure that in the set... At least one position in the variable satisfies the propositional variable. ; Indicates the upper bound of the index or the size of the set; The AND operator represents conjunction, or logical AND, used to connect two subforms that must both be true. This represents the grand conjunction, which means that all conditions are met. Perform a continuous AND operation on all terms; It indicates negation, i.e., logical NOT, and when combined with the following conjunction, it is used to prevent any two different positions from simultaneously satisfying the propositional variable.

[0060] Location capacity mutual exclusion: each physical location At most one qubit can be accommodated at any given time step. That is, for any two different qubits... and They are not allowed to occupy the same physical location at the same time:

[0061] .

[0062] Recent shuttle: A time step is the smallest unit of time in a model to perform an operation. If a quantum bit... At time step Located in physical location Then it is at time step The physical location can only be a set. One of them (i.e., stay stationary or move to an adjacent physical location). For boundary physical locations, items outside the range (such as...) or () will be omitted:

[0063] ;

[0064] This indicates a logical OR.

[0065] Uncrossable constraint: Quantum bit and They cannot skip over each other. A collision occurs when two qubits are in adjacent physical locations and attempt to swap their physical locations within a time step. Therefore, prohibiting such swaps ensures that the relative order of the qubits remains unchanged.

[0066] .

[0067] 2. Quantum circuit feature extraction.

[0068] The goal of this section is to map the input quantum circuit C into a feature graph model based on a directed acyclic graph (DAG) to abstract quantum gate operations and their topological constraints.

[0069] (1) Node definition and attribute extraction:

[0070] For an input quantum circuit, its corresponding directed acyclic graph (DAG) mainly contains the following properties:

[0071] Node set Each node One operation that uniquely corresponds to a quantum circuit (Including single-bit gates, double-bit gates, measurement operations, etc.);

[0072] Node state variables: Define boolean variables for each node. , used to indicate the operation The completion status, This indicates that the operation is complete. This indicates that the operation was not completed;

[0073] Operation mapping: Suppose that the quantum circuit contains a set of operations. Then each operation This corresponds to a node in a directed acyclic graph (DAG).

[0074] (2) Edge definition and dependency modeling:

[0075] Directed edges of nodes in a directed acyclic graph (DAG) This reflects two core dependencies between quantum operations, ensuring the correctness of the logical execution order:

[0076] Quantum bit dependence: when two gates operate and When sharing at least one common qubit, a predecessor-successor relationship must be established based on their temporal sequence in the quantum circuit. That is, the subsequent operation can only begin after the operation at the predecessor position has been completed, thus maintaining the causal order of logical execution. This relationship ensures the sequential order of operations.

[0077] Control dependency: For controlled quantum gates (such as CNOT and Tofoli gates), operations on the control bits must take precedence over operations on the target bits and are connected by directed edges.

[0078] (3) Formulation of logical constraints:

[0079] To ensure that the generated shuttle schedule is logically valid, it must satisfy the topological order binding constraint. Let... For operation The set of all direct predecessor nodes must satisfy the following necessary and sufficient condition: .

[0080] This formula indicates that if the operation... If it is marked as completed, then all its preceding operations... All elements must be in a completed state. This ensures that the shuttle scheduling strictly follows the inherent logic of the quantum algorithm.

[0081] 3. Generation of shuttle scheduling scheme.

[0082] Step 3 includes the following modes:

[0083] Mode A, Precise Optimal Scheduling (OptSchedule):

[0084] The core advantage of using Boolean Satisfiability (SAT) solvers for shuttle scheduling planning lies in their mathematical completeness, which guarantees finding the theoretically global optimal solution, i.e., the minimum number of time steps required to complete the target quantum circuit. This invention designs and implements an enhanced optimal time-step approximation algorithm, utilizing a binary search strategy to replace the inefficient linear search. The implementation of this strategy is based on the monotonicity of the qubit scheduling solution space: that is, for all qubits with a time step less than the optimal time step... The estimated value will necessarily be unsatisfiable according to the Boolean satisfiability (SAT) solution; however, for all values ​​greater than or equal to... The estimated value is guaranteed to be satisfiable. Based on this mathematical logic, the algorithm quickly narrows the solution range by maintaining the left and right boundaries of the search interval. In each iteration, the intermediate value is calculated and Boolean satisfiability (SAT) is performed: if the result is satisfiable, the current solution is recorded and the upper bound is narrowed to explore a shorter time step; if it is unsatisfiable, the lower bound is raised. In addition, the algorithm introduces auxiliary boundary variables for pruning optimization, and the search is terminated immediately when adjacent search intervals are detected, thereby eliminating redundant solution operations. The corresponding pseudocode of the algorithm is shown in Table 1.

[0085] Table 1. Optimal time steps algorithm based on binary search

[0086]

[0087] In Table 1, the first and second lines of code represent the initialization of the search interval for the algorithm, setting the left boundary of the search, `left`, to the minimum value. The right boundary (right) is set to the maximum value. Lines 3 and 4 define the safety boundaries, ensuring robustness of boundary checks by extending the initial range by 2 units on each side. Line 5 enables the loop condition, continuing binary probing as long as the left boundary is not greater than the right boundary. Line 6 calculates the median, taking the midpoint `mid` of the current search range and rounding it down. Line 7 executes the core solver function, calling `SolveSAT(mid)` to verify if the problem is solvable at the current step. Line 8 enters the solvable case branch; if `result = ...`... SAT executes the logic in lines 9 to 13; lines 9 to 11 check the optimality termination condition, and if the previous step of mid has reached the lower bound, mid is returned directly as the optimal solution; lines 12 and 13 update the right half boundary, record that mid is the new upper bound, and compress the search range to the left to find a smaller feasible solution; lines 14 to 20 handle the unsolvable case, and if the current mid is UNSAT (unsatisfiable), this branch is entered; lines 15 to 17 check the boundary overflow condition, and if the next step of mid has reached the upper bound, mid+1 is returned; lines 18 and 19 update the left half boundary, record that mid is the new lower bound, and the search range is moved to the right; line 21 ends the loop; line 22 returns the result of no solution found if no internal return is triggered in the entire search interval.

[0088] Mode B, FastSchedule (Efficient Approximate Scheduling):

[0089] To address the computational bottleneck of large-scale circuits, this invention designs an approximate solution algorithm based on the divide-and-conquer approach. First, a circuit partitioning algorithm strictly adheres to dependencies, dividing the massive original circuit into several manageable sub-units based on the topological structure of a directed acyclic graph (DAG). This process strictly follows two core principles: maintaining the original topological order between sub-units and preserving the operational dependencies within each sub-unit, thereby reducing a difficult problem to a series of independent and easily manageable micro-sub-problems. When solving sub-units independently, an adaptive time window mechanism is used to avoid the high overhead of repeated trials near the lower bound of the optimal solution: an initial time constraint is preset using an estimation function based on hardware characteristics; if no solution is found under the current constraint, the time window is dynamically expanded using an elastic coefficient, and the solution is recalculated, thus quickly identifying a feasible solution. Finally, a dynamic splicing algorithm integrates the local scheduling sequences of each sub-unit into a global scheduling sequence.

[0090] The scheduling sequence generated by the efficient approximate scheduling module employs a locally independent solution and splicing strategy, and the generated sequence still has room for optimization globally. This invention considers the following optimization points: Non-optimal global scheduling sequences may contain redundant segments, where the qubits undergo a series of moves, and the physical layout reverts to the state at the beginning of the segment, without any effective quantum gate operations being performed in between. Formally, this can be defined as: if there are time steps in the scheduling sequence... and ( They have the exact same physical layout of qubits and are within the same time interval. If no valid quantum gate operation is performed within that time step interval, then... These constitute redundant segments. Since these segments contain consecutive invalid time steps, directly deleting them can significantly shorten the total scheduling time without affecting the scheduling result. Based on the above definition, the physical-level motion optimization problem can be abstracted into a mathematical sequence reduction problem, enabling redundant segments to be efficiently identified in large-scale scheduling sequences. The specific problem transformation includes the following two key steps:

[0091] Effective interval partitioning: To prevent accidentally deleting time steps containing necessary quantum operations during optimization, it is first necessary to partition the interval based on the execution time of the operations. The complete scheduling sequence is decomposed into several consecutive time intervals. ,in Indicates the first Each quantum gate corresponds to a specific time point during execution. This division ensures that redundant segments can only exist within a single no-operation interval, thus decomposing the global optimization problem into a local optimization problem within that interval.

[0092] State encoding mapping: To facilitate algorithm processing, a mapping from the complex physical layout of qubits to simple integers needs to be established within each time interval. Define injective functions. ,in This represents the set of all possible physical layouts of qubits. For any time step... Its corresponding layout code value is This mapping satisfies the necessary and sufficient condition. That is, the same physical layout is equivalent to the same encoded integer. This represents the state code of a qubit at a given time step.

[0093] Through the above transformation, the originally complex physical scheduling optimization problem is abstracted into a purely mathematical problem, which is called the redundancy segment problem: given an integer sequence If it exists and Then you can delete the subsequence. The goal of optimization is to improve the final sequence by performing such deletion operations. Minimize the length.

[0094] To address the problem of redundant segments after transformation, this invention proposes an efficient solution algorithm based on dynamic programming. This algorithm utilizes the optimal substructure property in a multi-stage decision-making process to decompose the solution of the shortest length of the global scheduling sequence into interrelated subproblems. Specifically, a state array is constructed. ,in Defined as the first integer sequence of the input A subsequence consisting of elements The shortest length after eliminating all redundancy. The algorithm constructs the globally optimal solution step by step through a linear traversal using a memoization mechanism. In computation... At that time, the algorithm is based on the current element To determine the optimal transfer path, evaluate the following three decision scenarios, considering whether they have occurred before:

[0095] No preceding match: if If an element has not appeared before, it cannot form a closed-loop redundancy; therefore, it must be retained, and its length is incremented. .

[0096] Eliminate redundancy: If With a previous element ( If they are the same, then there exists an elimination interval. The possibility of this. At this point, if the elimination interval is chosen, the target sequence length becomes... (Reverting the current state to) (State at any given time). The algorithm will work on all conditions that are met. Select to The smallest one.

[0097] Preservation is better: even if a match exists. The cost of directly retaining the current element Still less than the cost after any jump elimination If so, then choose not to eliminate.

[0098] Based on the above logic, the state transition equation of this algorithm can be formally described as follows:

[0099] ;

[0100] The pseudocode corresponding to the above algorithm is shown in Table 2.

[0101] Table 2, Redundancy Segment Elimination Algorithm

[0102]

[0103] In Table 2, lines 1 to 2 represent the basic parameters of the initialization sequence, which are prepared for subsequent memory allocation by obtaining the length n of the input sequence nums and its maximum value maximum; lines 3 to 7 represent the establishment of auxiliary data structures, including a list record for recording numerical states, a list position for storing position information, a result array for recording dynamic programming results, and a two-dimensional tuple list delSeg for storing redundant segment information, and the initial state result[0] is set to 0; line 8 represents the start of the traversal loop, which processes each element in the sequence in turn; lines 9 to 13 represent the current element When nums[i] appears for the first time, update its corresponding result cost, record its state and current position in the record, and inherit the deletion record from the previous stage; lines 14 to 27 indicate that duplicate elements in existing records are processed, and the path is optimized by branching judgment; lines 15 to 22 indicate that if the cost of the current path is lower, update result[i] and try to correct the globally optimal record of the value in the record and position; lines 23 to 26 indicate that if the cost of the historical record is better, the current segment is determined to be redundant, and the current segment (pos, i) is merged into the delSeg record by finding the position pos where the value last appeared; lines 29 to 31 indicate that after the traversal is completed, the actual deletion operation is performed on the original sequence according to the final generated delSeg[n] record, and the optimized optimal sequence is returned.

[0104] To ensure the algorithm can handle large-scale data, an auxiliary record table is maintained in the implementation to store the minimum value corresponding to each layout code in real time. This makes the state transition equation... Query operations can be performed The algorithm completes within a short timeframe without requiring backtracking. Therefore, the overall time complexity is strictly controlled within a given timeframe. (in (where is the sequence length), and the space complexity is O(n). (Used to store the state array).

[0105] The overall architecture of this invention is as follows Figure 2 As shown, Figure 2 In the original line This represents four qubits. H stands for Hadamard gate, and RX, RY, and RZ represent single-qubit quantum gates rotating around the X, Y, and Z axes, respectively. The CNOT symbol (a structure connecting a dot and a plus sign) represents a controlled NOT gate, and the instrument symbol on the right side of the quantum circuit represents a measurement operation. The middle section represents a directed acyclic graph, where circles represent nodes and arrowed lines represent edges.

[0106] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0107] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple steps or stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention, and no reference numerals in the claims should be construed as limiting the scope of the claims.

[0110] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A general shuttle scheduling method, characterized in that, include: Formal modeling of the architectural constraints of quantum computing hardware is performed, and the physical constraints of the hardware are transformed into a set of Boolean satisfiability constraints through Boolean satisfiability expressions; Feature extraction is performed on the input quantum circuit to construct a directed acyclic graph model, and the dependencies between operations are extracted to form logical constraints; Based on the Boolean satisfiability constraint set and logical constraints, a shuttle scheduling scheme is generated. The shuttle scheduling scheme includes an exact optimal scheduling mode and an efficient approximate scheduling mode. The exact optimal scheduling mode uses a binary search strategy to iteratively solve for the minimum time step until a satisfiable solution is obtained. The efficient approximate scheduling mode uses a divide-and-conquer strategy to divide the quantum circuit into sub-units, solves each sub-unit separately, and then dynamically splices them into a global scheduling sequence. The spliced ​​global scheduling sequence is then optimized by eliminating redundant segments.

2. The general shuttle scheduling method according to claim 1, characterized in that, The process of transforming hardware physical constraints into a set of Boolean satisfyability constraints using Boolean satisfiability expressions specifically includes: Position Existence and Uniqueness Constraints: Each Quantum Bit in a Quantum Circuit at any time step They must all occupy exactly one physical location; Location capacity mutual exclusion constraint: for each physical location At most one qubit can be accommodated at any given time step, meaning that for any two different qubits... and It is not allowed to occupy the same physical location at the same time; The closest traveler constraint: if the quantum bit At time step Located in physical location Then the quantum bit At time step The physical location can only be a set of physical locations. One of the options is to remain stationary or move to an adjacent physical location; for boundary physical locations, options outside the range will be omitted. Uncrossable constraint: Quantum bit and They cannot skip each other.

3. The general shuttle scheduling method according to claim 1, characterized in that, The process of extracting features from the input quantum circuit, constructing a directed acyclic graph model, and extracting dependencies between operations to form logical constraints specifically includes: In a directed acyclic graph (DAG) model, each node uniquely corresponds to a quantum operation in a quantum circuit. A Boolean variable is defined for each node to represent the completion state of the corresponding quantum operation. Each edge in the DAG model reflects the qubit dependency and control dependency between quantum operations. The DAG model needs to satisfy the topological order binding constraint: if a quantum operation is marked as completed, all its preceding quantum operations must be in a completed state.

4. The general shuttle scheduling method according to claim 3, characterized in that, The quantum operations include single-qubit gate operations, two-qubit gate operations, and measurement operations; The qubit dependency is as follows: when two gate operations share at least one qubit, a predecessor-successor relationship must be established based on the timing of the two gate operations in the quantum circuit. Control dependency: For controlled quantum gate operations, operations on the control bits must take precedence over operations on the target bits and are connected by directed edges.

5. The general shuttle scheduling method according to claim 1, characterized in that, The precise optimal scheduling mode employs a binary search strategy, which specifically includes: setting upper and lower bounds for the time step, taking the middle value for Boolean satisfiability calculation, updating the upper bound if it is satisfiable, updating the lower bound otherwise, and iterating until the upper and lower bounds converge to obtain the minimum time step.

6. A general shuttle scheduling method according to claim 5, characterized in that, The preset time step upper and lower bounds are used to perform Boolean satisfiability calculations by taking the median value. If the time step is satisfiable, the upper bound is updated; otherwise, the lower bound is updated. This process is iterated until the upper and lower bounds converge to obtain the minimum time step. Specifically, this includes: The binary search strategy is based on the monotonicity of the scheduling solution space: for steps smaller than the minimum time step... The estimated value is unsatisfiable according to Boolean satisfiability; for the estimated value greater than or equal to the minimum time step, the result is satisfiable; by maintaining the left and right boundaries of the search interval, the intermediate value is calculated in each iteration for solution. If the result is satisfiable, the upper bound is updated and the current solution is recorded. If the result is unsatisfiable, the lower bound is updated; and auxiliary boundary variables are introduced for pruning optimization. The search is terminated when adjacent search intervals are detected.

7. The general shuttle scheduling method according to claim 1, characterized in that, The efficient approximate scheduling mode employs a divide-and-conquer strategy to divide the quantum circuit into sub-units, solves each sub-unit separately, and then dynamically concatenates them into a global scheduling sequence. Specifically, it includes: Based on the topological structure of the directed acyclic graph, the quantum circuit is divided into several sub-units, maintaining the original topological order between sub-units and preserving the dependencies between quantum operations within the sub-units. When solving each sub-unit independently, an adaptive time window mechanism is adopted to estimate the preset initial time constraints based on hardware characteristics. If there is no solution under the current constraints, the time window is dynamically expanded using elastic coefficients and the solution is re-solved. Finally, the local scheduling sequences of each sub-unit are concatenated into a global scheduling sequence.

8. The general shuttle scheduling method according to claim 1, characterized in that, The optimization of eliminating redundant fragments in the spliced ​​global scheduling sequence specifically includes: The global scheduling sequence is divided into no-operation intervals based on the execution time of quantum gate operations; the layout of qubits in each no-operation interval is mapped to an integer layout code to obtain an integer sequence; redundant subsequences in the integer sequence are eliminated by a dynamic programming algorithm, wherein the redundant subsequence is defined as a continuous time step with the same layout code at the beginning and end and no quantum gate operations in the middle.

9. A general shuttle scheduling method according to claim 8, characterized in that, The elimination of redundant subsequences in an integer sequence using a dynamic programming algorithm specifically includes: Construct a state array result, where the i-th element of result is... This represents the shortest length of the subsequence formed by the layout encoding of the first i time steps of the integer sequence after eliminating all redundancy; Iterate through each layout code in the integer sequence in order. For the (i+1)th layout code... : like If it has not appeared before, then ; like If it has appeared before, then for all satisfying... and At position k, calculate the candidate value result[k], and take the minimum value among all candidate values. Set as The smaller of the minimum values; At the same time, an auxiliary record table is maintained to store the minimum result[k] corresponding to each layout code in real time.

10. A computer system comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 9.

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