Nested quantum error-correcting codes for fault-tolerant quantum computation

Abstract

A method for operating a quantum computer with a set of qubits is disclosed. The quantum algorithm redundantly encodes quantum information in each physical qubit. Each physical qubit redundantly encodes quantum information. A set of physical qubits is used to form a set of logical qubits. Each logical qubit is formed from a separate subset of the physical qubits. Each logical qubit redundantly encodes quantum information. Each separate subset of physical qubits is disjoint from every other separate subset of physical qubits. A first quantum error correction (QEC) code is performed on each logical qubit. The first QEC code detects a first set of parity conditions across the separate subset of physical qubits forming the logical qubits. A second QEC code can be performed on the set of logical qubits. The second QEC code detects a second set of parity conditions across the set of logical qubits.

Description

[0001] Priority Statement

[0002] This application claims priority to U.S. Provisional Application No. 63 / 594,865, filed October 31, 2023, entitled “NESTED QUANTUM ERROR CORRECTIONCODES FOR FAULT-TOLERANT QUANTUM COMPUTATION”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to quantum computing systems, and more specifically to nested quantum error correction (QEC) codes for fault-tolerant quantum computing. Background Technology

[0004] Quantum computing is a computational method that utilizes quantum effects, such as superposition and entanglement, to perform specific calculations more efficiently than classical digital computers. Unlike digital computers that store and manipulate information in the form of bits (e.g., "1" or "0"), quantum computing systems can manipulate information using qubits. A qubit can refer to a quantum device capable of superimposing multiple states, such as data in "0" and "1" states, and / or to the superposition of data itself in multiple states. In conventional terminology, the superposition of "0" and "1" states in a quantum system can be represented, for example, as a + b The "0" and "1" states of a digital computer are similar to those of a quantum bit. and Ground state. Summary of the Invention

[0005] Various aspects and advantages of embodiments of this disclosure will be set forth in part in the description which follows, or may be learned from the description or by practice of the embodiments.

[0006] One example aspect of this disclosure relates to a method for operating a fault-tolerant quantum computing system. The method includes operating a quantum algorithm on the quantum computing system. The quantum algorithm redundantly encodes quantum information in each physical qubit of a set of qubits, such that each physical qubit in the set of qubits redundantly encodes quantum information. When executing the quantum algorithm, the set of physical qubits is used to form a set of logical qubits. Each logical qubit in the set of logical qubits is formed via a separate subset of the set of physical qubits, such that each logical qubit in the set of logical qubits redundantly encodes quantum information. Each separate subset of physical qubits is disjoint from every other separate subset of physical qubits. When executing the quantum algorithm, a first quantum error correction (QEC) code is executed on each logical qubit in the set of logical qubits. The first QEC code detects a first set of parity conditions across the separate subsets of physical qubits forming the logical qubits. When executing the quantum algorithm, a second QEC code may be executed on the set of logical qubits. The second QEC code detects a second set of parity conditions across the set of logical qubits.

[0007] Other aspects of this disclosure relate to various systems, methods, apparatuses, non-transitory computer-readable media, computer-readable instructions, and computing devices.

[0008] These and other features, aspects, and advantages of the various embodiments of this disclosure will be better understood with reference to the following description and the appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and, together with the description, explain the relevant principles. Attached Figure Description

[0009] Referring to the accompanying drawings, a detailed discussion of embodiments is set forth in this specification for those skilled in the art, in which:

[0010] Figure 1 An example quantum computing system according to an exemplary embodiment of the present disclosure is depicted.

[0011] Figure 2 A conceptual visualization of nested quantum error-correcting codes according to various embodiments is depicted.

[0012] Figure 3A 1D nested quantum error-correcting codes according to various embodiments are described.

[0013] Figure 3B 2D nested quantum error-correcting codes according to various embodiments are described.

[0014] Figure 3C Tables showing instructions for stabilizers and logic generators for 2D yoke surface codes according to various embodiments are illustrated.

[0015] Figure 4A A pipeline diagram for measuring multibody stabilizers is shown according to various embodiments.

[0016] Figure 4B A piping diagram illustrating the operation of adding protection against hook errors according to various embodiments is shown.

[0017] Figure 5A The use of lattice manipulation to examine the X-type and Z-type stabilizers of iceberg codes according to various embodiments is demonstrated.

[0018] Figure 5B A pipeline diagram of the complete syndrome cycle according to various embodiments of nested QEC codes is shown.

[0019] Figure 6 Decoding of the outer code abstracted from the complementary gap is demonstrated according to various embodiments.

[0020] Figure 7 The layouts of both cold storage architectures and hot storage architectures for lattice surgery according to various embodiments are shown.

[0021] Figure 8 A flowchart depicts an example method for operating a fault-tolerant quantum computing system according to an example embodiment of the present disclosure. Detailed Implementation

[0022] An exemplary aspect of this disclosure relates to nested quantum error-correcting (QEC) codes for fault-tolerant quantum computing. Nested surface codes (e.g., yoke surface codes) are discussed throughout. However, embodiments are not limited to surface codes and can be generalized to nested versions of other QEC codes (e.g., toroidal codes other than surface codes). The discussion throughout focuses on two-layer nested QEC codes with an inner QEC code (e.g., a surface code) and an outer QEC code (e.g., a 1D or 2D parity-check code). However, embodiments are not limited to two-layer nested codes. Similar to programming loop structures, any number of nested layers can be employed in embodiments. For example, an intermediate QEC code can be sandwiched between the inner and outer codes to form a three-layer nested QEC code. The number of layers can depend on the error rate of the underlying physical qubits, the error rate of the target logical qubits, the total number of available physical qubits, the ability to scale the layers, and / or the complexity of the underlying quantum algorithm deployed on the hardware.

[0023] An inner surface code can operate on each logical qubit in a set of logical qubits. Each logical qubit in the set of logical qubits is implemented by a set of physical qubits. Each logical qubit in the set of qubits (including stabilizers for detecting and correcting errors) can be referred to as a separate surface code in the surface code set. These stabilizers can be referred to as inner stabilizers. An inner code can consist of a set of surface codes (or, alternatively, a set of logical qubits and a subset of inner stables). The inner code detects and corrects at least a subset of errors that occur in the physical qubits that form the logical qubits. Surface codes in the surface code set can be coupled (e.g., yoke stable subsets) via one or more outer stabilizers (e.g., yoke stable subsets). An outer code can consist of a set of logical qubits and a subset of yoke stables (e.g., outer stable subsets) coupled (or yoke stable subsets) of logical qubits. The outer code detects and corrects at least a subset of errors that cannot be detected by the inner code (e.g., multiple errors exceeding the detection threshold of the inner code). Therefore, because the outer code can detect errors with higher multiplicity, the inner code can achieve the same (or lower) overall error rate using surface codes with smaller distances.

[0024] In other words, the inner surface code suppresses noise to a level where the superior parameters of the outer code become more important than the high fault tolerance of the surface code. The inner surface code also provides a lattice-operation-like mechanism to perform operations between distant qubits. The outer code then suppresses the remaining noise to the level required by the algorithm, with the final footprint being smaller than if only the surface code were used alone.

[0025] Traditional surface codes can tolerate noise (e.g., qubit errors), but also come with significant qubit overhead. As mentioned above, some embodiments of this paper employ surface codes as inner codes linked to high-speed outer codes (e.g., 1D or 2D parity-check codes). This two-layer nesting approach is referred to throughout as yoke-type surface codes. However, also as mentioned above, other embodiments may employ additional layers and / or other QEC codes. These outer parity-check codes prioritize code processing rate over low-weighted check operators and distances. A 1D parity-check code can be a [[n, n-2, 2]] code, where n-2 is the number of logical qubits implemented by the inner code. By nesting error codes, the embodiments provide a reduction in qubit overhead. That is, because the outer code detects and corrects errors on the logical qubits within the inner code, each (inner code) logical qubit can be formed by a reduced number of physical qubits compared to traditional surface codes. The overall error rate of nested codes is less than or equal to the overall error rate of traditional surface codes; however, the qubit overhead in nested codes is significantly reduced compared to traditional codes. For example, as shown below, compared to traditional surface codes, the 1D yoke surface code of this embodiment uses half the number of qubits to achieve < 10 -9The target logic error rate. The 2D yoke surface code of the embodiment uses one-third of the number of qubits to achieve < 10. -15 The target logical error rate. Therefore, the embodiment provides a noteworthy improvement in terms of the expected cost of building a large-scale fault-tolerant quantum computer.

[0026] Surface codes are leading contenders for error-correcting codes in the architecture of large-scale fault-tolerant quantum computers due to their forgiving quality and connectivity requirements. The main drawback of surface codes is their extremely stringent number requirement. Given the underlying error rate of current qubit implementations, for surface codes, each logical qubit may require 1000 to 2000 physical qubits to achieve a sufficiently low error rate, allowing algorithms that are difficult to handle classically, such as Shor's algorithm, to run at a reasonable physical error rate.

[0027] The embodiments described in this paper reduce this overhead by implementing nested QEC codes (e.g., inner and outer codes). The inner surface code suppresses noise to a level where the superior parameters of the outer code become more important than the high fault tolerance of the surface code. The inner surface code also provides a lattice-operation-like mechanism to perform operations between distant qubits. The outer code then suppresses the remaining noise to the level required by the algorithm, with the final footprint being smaller than if only the surface code were used alone.

[0028] Some QEC codes envision overlay codes as having high distance, high speed, and low-density parity. Small parity provides two important advantages. First, their syndrome extraction circuitry is small, and therefore the entropy injected into the system when measuring the stabilizer is low. Second, their locality limits, and sometimes eliminates, damage caused by correlation errors. However, simultaneously requiring these properties often necessitates complexity and larger block sizes to see the improvement overhead, as inner-surface codes provide expensive inner qubits.

[0029] Some embodiments employ parity-check codes as outer codes, thereby focusing on achieving high code processing rates. In some embodiments, 1D parity-check outer codes are employed, such as [[n, n-2, 2]] codes. By utilizing the “soft” information provided by the surface codes, the need for higher distance constructions can be avoided in the form of complementary gaps with minimum weight perfect matching. This significantly enhances the performance of the outer codes, where these gaps determine the edge weights of the outer error graph that can be decoded using standard matching techniques. In the 1D case, it elevates the original error detection code to behave like an error correction code. By using surface codes to suppress errors in each individual operation, it can be ensured that the noise injected when measuring many logical qubits is not too large. Furthermore, during lattice operations, these high-weighted hook errors can be avoided by adding protection against corrupted high-weighted hook errors. Specifically, these corrupted errors can be oriented in the time-like direction, and parity is “slowed down” to implement the added protection against these corrupted errors.

[0030] This disclosure provides numerous technical effects and benefits. For example, embodiments employ nested QEC codes (e.g., yoke surface codes). Various embodiments of yoke surface codes are 2 / 3 the size of normal surface codes with a reasonable target logic error rate. Reducing the number of qubits required for surface codes is highly useful, as the required number of physical qubits limits the applicability of standard surface codes. Embodiments envision both Yberg codes and iceberg codes as yoke surface codes.

[0031] Exemplary embodiments of this disclosure will now be discussed in more detail with reference to the accompanying drawings.

[0032] Figure 1 An example quantum computing system 100 is depicted. System 100 is an example of a system of one or more classical computers and / or quantum computing devices located at one or more locations, in which the systems, components and techniques described below may be implemented. Those skilled in the art will understand, using the disclosure provided herein, that other quantum computing devices or systems may be used without departing from the scope of this disclosure.

[0033] System 100 includes quantum hardware 102 that communicates data with one or more classical processors 104. The classical processor 104 can be configured to execute computer-readable instructions stored in one or more memory devices to perform operations, such as any of the operations described herein. Quantum hardware 102 includes components for performing quantum computing. For example, quantum hardware 102 includes a quantum system 110, a control device 112, and a readout device 114 (e.g., a readout resonator). Quantum system 110 may include registers of one or more multilevel quantum subsystems, such as qubits (e.g., qubit 120). In some implementations, the multilevel quantum subsystem may include superconducting qubits, such as magnetic flux qubits, charge qubits, transmon qubits, gmon qubits, spin-based qubits, etc.

[0034] The type of multilevel quantum system utilized by system 100 can vary. For example, in some cases, it may be convenient to include one or more readout devices 114 attached to one or more superconducting qubits (e.g., transmon qubits, flux qubits, gmon qubits, xmon qubits, or other qubits). In other cases, ion traps, photonic devices, or superconducting cavities can be used (e.g., which allow for the preparation of states without the need for qubits). Further examples of implementations of multilevel quantum systems include fluxmon qubits, silicon quantum dots, or phosphorus-impurity qubits.

[0035] Quantum circuits can be constructed and applied to registers of qubits included in quantum system 110 via multiple control lines coupled to one or more control devices 112. Example control devices 112 operating on qubit registers can be used to implement quantum gates or quantum circuits with multiple quantum gates, such as Pauli gates, Hadamard gates, controlled-NOT (CNOT) gates, controlled-phase gates, T-gates, multi-qubit quantum gates, coupler quantum gates, etc. One or more control devices 112 can be configured to operate quantum system 110 via one or more corresponding control parameters (e.g., one or more physical control parameters). For example, in some implementations, the multi-level quantum subsystem can be superconducting qubits, and control devices 112 can be configured to provide control pulses to the control lines to generate magnetic fields to adjust the frequency of the qubits.

[0036] The quantum hardware 102 may also include a readout device 114 (e.g., a readout resonator). Measurement results 108 obtained via the measurement device can be provided to the classical processor 104 for processing and analysis. In some implementations, the quantum hardware 102 may include quantum circuits, and the control device 112 and the readout device 114 may implement one or more quantum logic gates that operate the quantum system 102 via physical control parameters (e.g., microwave pulses) transmitted through wires included in the quantum hardware 102. Further examples of the control device include an arbitrary waveform generator, where a DAC (digital-to-analog converter) creates the signal.

[0037] The readout device 114 can be configured to perform a quantum measurement on the quantum system 110 and send the measurement result 108 to the classical processor 104. Additionally, the quantum hardware 102 can be configured to receive data from the classical processor 104 specifying physical control qubit parameter values ​​106. The quantum hardware 102 can use the received physical control qubit parameter values ​​106 to update the actions of the control device 112 and the readout device 114 on the quantum system 110. For example, the quantum hardware 102 can receive data specifying a new value representing the voltage intensity of one or more DACs included in the control device 112, and the quantum hardware can update the actions of the DACs on the quantum system 110 accordingly. The classical processor 104 can be configured, for example, to initialize the quantum system 110 in an initial quantum state by sending data specifying an initial parameter set 106 to the quantum hardware 102.

[0038] In some implementations, the readout device 114 may utilize the elements of a quantum system (such as qubits). and The impedance difference of a state is used to measure the state of an element (e.g., a qubit). For example, due to the nonlinearity of a qubit, when a qubit is in a state... or state The resonant frequency of the readout resonator can be different. Therefore, the microwave pulse reflected from the readout device 114 carries an amplitude and phase shift that depends on the qubit state. In some implementations, a Purcell filter can be used in conjunction with the readout device 114 to block microwave propagation at the qubit frequency.

[0039] In some embodiments, the quantum system 110 may include, for example, a plurality of qubits 120 arranged in a two-dimensional grid 122. For clarity, Figure 1The two-dimensional grid 122 depicted includes 4x4 qubits; however, in some implementations, system 110 may include fewer or more qubits. In some embodiments, multiple qubits 120 may interact with each other via multiple qubit couplers (e.g., qubit coupler 124). A qubit coupler can define the nearest neighbor interaction between the multiple qubits 120. In some implementations, the strength of the multiple qubit couplers is an adjustable parameter. In some cases, the multiple qubit couplers included in the quantum computing system 100 may be couplers with a fixed coupling strength.

[0040] In some implementations, the plurality of qubits 120 may include data qubits (such as qubit 126) and measurement qubits (such as qubit 128). Data qubits are qubits that participate in computations performed by system 100. Measurement qubits are qubits that can be used to determine the result of a computation performed by the data qubits. That is, during computation, the unknown state of the data qubits is transferred to the measurement qubits using appropriate physical operations and measured via appropriate measurement operations performed on the measurement qubits.

[0041] In some implementations, each of the multiple qubits 120 can be operated using appropriate operating frequencies (such as idle frequency and / or interaction frequency and / or readout frequency and / or reset frequency). The operating frequencies can vary from qubit to qubit. For example, each qubit can be idle at different operating frequencies. The operating frequencies of the qubits 120 can be selected before computation is performed.

[0042] Figure 1 An example quantum computing system is described that can be used to implement the methods and operations according to the example aspects of this disclosure. Other quantum computing systems may be used without departing from the scope of this disclosure.

[0043] Figure 2 A conceptual visualization of a nested quantum error-correcting (QEC) code 200 according to various embodiments is depicted. It should be noted that... Figure 2The nested QEC code 200 provides visualizations of various embodiments. The visualizations illustrate various concepts of non-limiting embodiments. The nested QEC code 200 includes inner codes and outer codes. More specifically, the inner codes are surface codes operating on eight logical qubits. One of the eight logical qubits is designated as logical qubit 202. The inner codes are surface region codes operating on each of the eight logical qubits (including logical qubit 202). Thus, the inner codes can implement eight separate surface codes, one surface code for each of the eight logical qubits. The inner surface codes include XXXX and ZZZZ stabletons for non-boundary checking. Boundary checking includes XX and ZZ stabletons.

[0044] The outer code of the nested QEC code 200 includes a yoke stabilizer 204 coupled (or yoke-connected) with eight logical qubits. Figure 2 In a non-limiting embodiment, the yoke stabilizer is The stabilizer, where the L subscript indicates that the yoke stabilizer 204 is stabilizing a logical qubit (not an individual physical qubit), and the tensor product superscript indicates that it has eight Y checks, one Y check for each of the eight logical qubits.

[0045] Quantum parity check code

[0046] This section describes 1D and 2D (quantum) parity-check codes forming outer codes in various embodiments. Quantum parity-check Calderbank, Shorm, Steane (CSS) codes are generalizations of classical parity-check codes. Qubits are arranged in a 1D or 2D array, and the parity of each row or each row and column is checked. The following discussion focuses on these codes because their parity checks are geometrically simple, and their rates rapidly approach 1 as their capacity increases. However, the embodiments are not limited to 1D or 2D CSS codes.

[0047] Unlike classical parity-check codes, certain parity requirements can be implemented to ensure stable subcommutation of these codes. In 1D embodiments, the code length can be required to be divisible by two. In 2D embodiments, the code side length can be required to be divisible by four. More generally, rD parity-check codes can have each side length divisible by 2r. The reason is that the row and column operators of the opposite Pauli type are anticommutative because they intersect at a single position. Utilizing these restricted side length parity requirements, this can be solved by changing the order of the qubits in the rows and columns of different Pauli types. Specifically, for row vectors... and Support for Z-shaped row and column parity checks can be modified to...

[0048] as well as

[0049] ,

[0050] To ensure they are always compatible with row and column X-type checks.

[0051] The r-dimensional parity check code has a distance of 2r, where the minimum weighted logical operators form the vertices of an r-dimensional cube. It has parameters [[] by counting the number of independent checks. , , ]], where n i This is the side length of the r-dimensional array. Specifically, for 1D and 2D codes, the code families [[n, n-2, 2]] and [[n]] can be obtained respectively. 2 , n 2 -4n + 2,4]).

[0052] Figure 3A A 1D nested quantum error-correcting (QEC) code 300 is depicted according to various embodiments. That is, the outer code of the QEC code 300 includes 1D X and Z parity checks. The outer code overlays the inner code, which includes surface codes on each “piece” of physical qubits. Each surface code of the inner code protects its logical qubits to a distance of 6. The combination of the outer and inner codes protects the logical qubits to a distance of 12. Each logical qubit is indicated by a square outline surrounding (represented by dots) the set of physical qubits. Thus, a 2D array of logical qubits is shown in Figure 3. There are six rows and eight columns of logical qubits in the 2D array of logical qubits. Each row of logical qubits (e.g., surface code pieces) includes six logical qubits (e.g., the leftmost six logical qubits in the row) “yoke” (or coupled) via 1D (X and Z) parity checks. The two rightmost logical qubits in a row are represented as fixed to measure the degree of freedom of each parity check.

[0053] In each row, the eight-body X-stabilizer and Z-stabilizer are measured. The X-stabilizer measurements are labeled as operators in the top row. The line is shaded to indicate that... The operator is providing the juxtaposition. The Z-stabilizer is marked as the operator in the fourth line. The line is shaded to indicate that... The operators are providing the yoke. These 1D parity-check stabilizers are formed from the logic operators of the underlying 6-distance surface code. Therefore, the 1D QEC code 300 can protect 36 logic qubits up to a distance of 12. In some embodiments, and in ideal scenarios, the 1D QEC code 300 can increase the code processing rate of the surface code by four times.

[0054] Figure 3BA 2D nested quantum error-correcting (QEC) code 320 according to various embodiments is depicted. That is, the outer code of the QEC code 320 includes 2D X and Z parity checks. Figure 3B As shown, X and Z parity checks are performed across rows and columns. That is, in each row and each column, both the X and Z stabilizers are measured. The Z-type stabilizer is applied to the code permutation (as indicated by the arrow) to commutate with the X-type stabilizer. In total, the 2D QEC code 320 holds 34 logical qubits at a distance of 12. In some embodiments, the 2D QEC code 320 can increase the code processing rate of the surface code by a factor of sixteen.

[0055] Figure 3C Table 340 illustrates indicators for stabilizers and logic generators for 2D yoke surface codes according to various embodiments. More specifically, Table 340 describes 2D [[16, 2, 4]] yoke surface codes. Each cell of Table 340 shows the entry for the stabilizer as... Pauli term lattice; one term for each of the 16 physical qubits. Note that two of the listed checks are redundant. For example, the product of all X-column checks equals the product of all X-row checks, and the product of all Z-double-column checks equals the product of all Z-double-row checks.

[0056] Lattice surgical construction

[0057] This section discusses the details of the lattice-operated construction used to measure the stabilizer and analyze its overhead and fault-tolerant properties. The stabilizer of the overlaid code can be measured when codes are linked on the surface code. The workspace required for periodically measuring the stabilizer of the overlaid code may be larger than that required to store only qubits. Furthermore, the effects of errors occurring during lattice operations need to be considered in order to understand the behavior of the overlaid code.

[0058] From one perspective, lattice operations can be considered as constructs built from parity measurements. However, a more useful perspective is to view lattice operations as instantiations of ZX calculus. In this latter perspective, the building blocks of lattice operations are not operations on qubits, but rather the connections between nodes. A well-constructed lattice operation then becomes an exercise (within the ZX calculus pipeline diagram) in arranging, routing, and rotating pipelines so that they are linked together in the desired manner.

[0059] Figure 4A Pipeline diagrams for measuring multibody stabilizers according to various embodiments are shown. Figure 4AIn the diagram, lighter shades correspond to X-shaped boundaries, and darker shades correspond to Z-shaped boundaries. The first pipeline diagram 400 (on the left) illustrates an 8-body Z-shaped row check, where the measured observables extending parallel to the X-shaped boundaries are highlighted with shaded lines. The second pipeline diagram 410 (on the right) illustrates an 8-body Z-shaped double-row check. Inside, the shaded-line correlated surfaces correlate the Z-shaped error strings within the central bar with the four Z-shaped error strings on the outer corridor. This is analogous to the Z-shaped hook errors propagating from the measurement qubits to the four data qubits of the outer code. Some of these correlated errors may not be preventable by the outer code.

[0060] When executing fault-tolerant circuits according to these pipeline diagrams, it may be almost unimportant to concern oneself with which observables are corrupted during circuit execution. It can be assumed that any corrupted observable can destroy the circuit. However, when chaining surface codes into outer codes, it may be important to concern oneself with error propagation in roughly the same way as when extracting fault-tolerant syndromes at the base code level. One drawback of using high-density parity-check (HDPC) codes is that the presence of these high-weighted stabilizers can simultaneously cause correlated faults in multiple observables, which may not be correctable by the outer code. These can be analogous to hook errors propagating from measurement qubits to many data qubits.

[0061] However, unlike physical qubits, surface code qubits possess the property of adjusting the distance between boundaries to bias against different error mechanisms. For example, the protection against correlated errors can be extended to suppress its probability below that of the chained code. This can be achieved by increasing the space occupied by the chained code by extending the size of the base code. However, a second property of surface codes is that their circuitry may be independent of their spatial and temporal orientation. Therefore, this extended protection can be oriented in the temporal direction, thus keeping the space occupied by the yoke surface code fixed. Cost may increase the length of the syndrome period of the outer code, which in turn may increase the distance required for the inner code. However, the error rate scales polynomially with the length of the syndrome period and inversely exponentially with the distance of the inner code.

[0062] Figure 4B Piping diagram 420 illustrates the operation of adding protection against hook errors according to various embodiments. Figure 4A In this circuit, protection against hook errors (i.e., the boundaries in the shared pipe on the shaded-line-related surface) is achieved by extending the distance between the boundaries where the hook error is condensed. This increases the overall qubit occupancy of the circuit. However, this can be oriented towards temporal extension, thus trading a smaller qubit occupancy for a longer syndrome extraction period.

[0063] Because they each have a distance of 2 (for example, see...) Figure 4BFor 1D and 2D yoke surface codes of 4 and 5, the stabilizer check can be extended by two and four times, respectively. This may be overly conservative for four reasons. First, the 'narrow' surface code should have increased error suppression relative to its square counterpart. Second, the effective error suppression factor of the 1D (2D) yoke surface code is subquadrant (subquadrant) in terms of the error suppression factor of the underlying surface code. Third, the cumulative probability of this error mechanism scales linearly with the number of fragments and rounds. It can be shown that the cumulative error probability of the error mechanism protected by the yoke surface code scales superlinearly. These three observations indicate that the error per fragment-round caused by one of these hook errors should be much lower than the error per fragment-round caused by other protected errors. Fourth, the total number of fragment-rounds exposed to the hook error is a small fraction of the total number of fragment-rounds in the entire memory. However, in our estimates, the estimates may be flawed in terms of care, and some embodiments may use overly slow syndrome measurements.

[0064] Figure 5A The use of lattice manipulation to examine X-type and Z-type stabilizers of iceberg codes according to various embodiments is demonstrated. More specifically, in Figure 5A In this process, the stable subcurrents of the ZX calculus can be evaluated to confirm that X is being measured. n and Z n The stabilizer is propagating encoded logical qubits. The defect diagram is not scaled; the connections between the slices are stretched to show the topology. For 4d rounds, the process occupies 2 × n logical qubit slices. Slice rotations alternate between left and right rotations to satisfy boundary tightness constraints. The defect diagram with highlighted observables shows how the yoke stabilizer is measured and prepared.

[0065] Figure 5B Pipeline diagrams of the complete syndrome cycle of nested QEC codes according to various embodiments are shown. Pipeline diagram 570 (e.g., top diagram) shows the complete syndrome cycle of a 1D yoke surface code. Pipeline diagram 580 (e.g., bottom diagram) shows the complete syndrome cycle of a 2D yoke surface code.

[0066] To construct a complete syndrome extraction circuit, the circuit can be built piecemeal. Figure 5A In this study, X-type and Z-type row stabilizers are measured by combining parity measurements with patch rotation and the corresponding ZX diagrams. For example... Figure 5BAs shown, these puzzle pieces can be assembled to form a complete syndrome-based cyclic circuit. Note that additional workspace may be required to perform these measurements. For example, for 1D yoke surface codes, a single workspace row can be used to sequentially measure each 1D yoke surface code block, similar to the measurement qubits that migrate across code blocks to extract stabilizer measurements. Making each block a single additional row reduces the overall footprint, but again lengthens the syndrome extraction cycle of the outer code. Finding a balance between these effects is important because we must include the overhead of this workspace in the overall footprint of the yoke surface code.

[0067] complementary gap distribution

[0068] This section discusses the distribution of complementary gaps in surface codes and how such distributions and coarsening of lattice operations can be used to estimate the performance of yoke surface codes. From the perspective of the outer code, the syndrome of the inner code provides valuable information about the probability of errors at specific locations. Minimum-weighted perfect matching can be used to evaluate the confidence of the decoder's decision and pass this information to the outer code to identify possible culprit errors. Operationally, given a block of surface code memory with boundaries, detectors for all boundary edges connected to one edge of the error graph can be formed. This enhancement maintains the graph structure, and turning the boundary detector on / off forces the decoder to match / not match the corresponding boundary. The resulting two matches are the decoder's best hypothesis for the error set, thus explaining the two topologically distinct error classes. The log-likelihood ratio of these two hypotheses can be called the complementary gap—the log ratio of the probabilities of minimum-weighted matching and complementary matching. A complementary gap close to 0 indicates that the decoder is not confident in its decision, while a high complementary gap indicates that the decoder is highly confident. Figure 6 As shown, this information may be crucial for the external code and can be used to decode it.

[0069] Figure 6 Decoding of the outer code abstracted from complementary gaps is demonstrated according to various embodiments. More specifically, Figure 6 Error diagram 600 is shown. Error diagram 600 is... × X-shaped error map of 2D yoke surface codes in a phenomenological error model on an array. Error map 600 is a fully bipartite map extended to time. The two edges of the bipartite graph correspond to row and column detectors. Individual edges and their endpoint detectors are highlighted with dashed lines (e.g., hash lines); other time-series edges have been removed for clarity. In the middle of error graph 600 is a slice of the underlying surface code error graph, where two yoke detectors are highlighted at the boundaries with hash patterns. Dark-shaded (e.g., filled) nodes are detectors, and light-shaded (e.g., unfilled) nodes are detected events. Dark edges correspond to minimum-weighted matches, other edges correspond to complementary matches, and light-shaded edges are common to both. Assuming all edges have equal probability p, the log-likelihood ratio of two matches is... Then, the external error map is formed by XORing the juxtapositions triggered by the minimum weight misconfiguration. Assuming all edges have equal probability p, the log-likelihood ratio of two matches is... Then, an external error map is formed by XORing the yokes triggered by the minimum-weight misconfiguration. Assuming all edges have equal probability p, the cost of flipping these yokes is given by the log-likelihood ratio of the two matched edges, which in this case is... It is assigned as the weight of the outer edge.

[0070] These distributions of complementary gaps in the surface code may be important for the outer code and can be used for decoding the outer code. To decode the outer code, a minimum weighted perfect match can be used. These complementary gaps can be passed to assign instance-specific edge weights to the outer error graph, such as... Figure 6 As shown.

[0071] Several methods exist to extend this process to a correlated matching decoder. In this work, a two-channel correlated matching decoder can be employed. To calculate the complementary gap in the Z-based memory experiment, the Z-type error map can be reweighted using an X-type error map 600, and then the complementary gap of the reweighted Z-type error map can be calculated.

[0072] These gap distributions may take a smooth, simple form after the initial noise begins at low distances due to finite size effects. After modifying the gaps by 0.9x, it can be observed that the gaps are well calibrated—the probability of success predicted by the gaps approaches the true empirical probability of success. That is, the decoder's confidence can be rescaled to account for slight overconfidence in its high-confidence predictions. Furthermore, the output of this calibration may slowly degrade as the number of rounds is scaled up to higher rounds. The complementary gap distribution over mn rounds can be well approximated by the minimum of m samples from the gap distribution over n rounds. Taken together, these approximations allow the ability to extrapolate the probability of a particular gap and the resulting probability of failure from the gap distribution over a relatively small number (e.g., 10d rounds).

[0073] Hot storage architecture and cold storage architecture

[0074] Above the abstract level of lattice manipulation lies the concept of storage architecture. Examples envision two types of storage architectures: "cold storage" and "hot storage." Some embodiments employ cold storage, others hot storage, and still others a combination of both.

[0075] Figure 7 The layouts of both cold and hot storage architectures for lattice manipulation, according to various embodiments, are shown. More specifically, Figure 7 The layouts for hot and cold storage are shown, assuming the yoke is checked every 1000 rounds. The top two 2D "occupancy maps" for cold and hot storage illustrate how space is allocated for the two different storage architectures. The bottom two 3D "defect maps" for cold and hot storage show the operation of the two different storage architectures over time. In the 2D occupancy maps, each row is a separate set of yoke-type qubits. White-filled squares correspond to available storage, while other squares correspond to various overheads. In cold storage, a row of workspace is shared among the rows of storage to measure the yoke. In hot storage, the access channels that were originally present are used to measure the yoke.

[0076] In "cold storage," qubits are stored in a form that is as dense as possible but cannot be operated on immediately. Operating on a qubit in cold storage requires first removing it from storage. Specifically, this means that not all qubits have access channels close to them. Some workspace may still be needed because the yoke needs to be checked periodically, but this workspace can be shared among many qubit groups. As mentioned above, Figure 7 The spatial and spatiotemporal layouts that can be used to estimate the size of a cold storage architecture are shown.

[0077] By exposing two boundaries to each surface chip block, storage can be "even hotter" than considered in this paper. Note that when lattice operations require access to unexposed boundaries, it can be assumed that qubits in hot storage are rotated as needed. The necessity of performing these rotations is a key consideration when using placement algorithms.

[0078] In hot storage, juxtaposed qubits can be manipulated via lattice operations while they are encoded. The observables of each encoded qubit are scattered across two surface code pieces, but lattice operations can stitch the two pieces together as easily as stitching a single piece together. In this context, the cost is practically the same, since access to the aisle is occupied regardless of how many pieces are touched. There are two main caveats regarding the ability to perform lattice operations on juxtaposed qubits. First, lattice operations may not always satisfy the boundary closeness constraint. Second, because the juxtaposition is only checked periodically, it is not known whether the lattice operation has been affected by corrections until the next juxtaposition check is completed. If the lattice operation is part of executing a non-Clifford gate, the non-Clifford gate will be prevented from completing until the juxtaposition is checked again.

[0079] Example Method

[0080] Figure 8 A flowchart depicts an example method 800 for operating a fault-tolerant quantum computing system according to an example embodiment of the present disclosure. The quantum computing system includes a set of physical qubits. At block 802, the quantum computing system can execute a quantum algorithm. The quantum algorithm can redundantly encode quantum information in each physical qubit of the qubit set, such that each physical qubit in the physical qubit set redundantly encodes quantum information. When executing the quantum algorithm, the set of physical qubits can be used to form a set of logical qubits. Each logical qubit in the set of logical qubits can be formed via a separate subset of the set of physical qubits, such that each logical qubit in the set of logical qubits redundantly encodes quantum information. Each separate subset of physical qubits can be disjoint from every other separate subset of physical qubits. Although Figure 8 The steps performed in a particular order are depicted for illustrative and discussion purposes, but the method of this disclosure is not limited to the particular illustrated order or arrangement. The steps of method 800 may be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of this disclosure.

[0081] At box 804, and while executing the quantum algorithm, the quantum computing system can perform a first quantum error correction (QEC) code on each logical qubit in the set of logical qubits. The first QEC code can detect a first set of parity conditions across the individual physical qubit subsets that form the logical qubits.

[0082] At box 806, and while executing the quantum algorithm, the quantum computing system can perform a second QEC code on the set of logical qubits. The second QEC code detects a second parity condition set across the set of logical qubits.

[0083] At box 808, and while executing the quantum algorithm, the quantum computing system can perform lattice operations on at least a portion of the qubit set based on at least one of a first parity condition set across a single physical qubit subset or a second parity condition set across a logical qubit set. As long as the quantum algorithm is being executed, method 800 can return from box 808 to box 804.

[0084] In some embodiments, the first QEC code is a surface code. The second QEC code may be a 1D parity check code. In other embodiments, the second QEC code may be a 2D parity check code.

[0085] A set of physical qubits can be arranged in a first two-dimensional (2D) grid of physical qubits. Each individual subset of physical qubits forming a logical qubit set can be a contiguous 2D physical qubit patch in the first 2D grid. The logical qubit set can be arranged in a second 2D grid of logical qubits. The second 2D grid of logical qubits can be superimposed on the first 2D grid of physical qubits. The second 2D grid of logical qubits can be coarser than the first 2D grid of physical qubits.

[0086] In some embodiments, the second parity condition set of the second QEC code includes one or more parity checks for each row of a second 2D grid for logical qubits. In such embodiments, the one or more parity checks for each row of the second 2D grid for logical qubits may include one or more Z-based parity checks. The second QEC code may include one or more Z-type stabilizers that measure one or more Z-based parity checks for each row of the second 2D grid for logical qubits. The one or more Z-type stabilizers may be juxtaposed with logical qubits included in rows of the 2D grid of logical qubits. The one or more parity checks for each row of the second 2D grid for logical qubits may include one or more X-based parity checks. The second QEC code may include one or more X-type stabilizers that measure one or more X-based parity checks for each row of the second 2D grid for logical qubits. In such embodiments, the one or more X-type stabilizers are juxtaposed with logical qubits included in rows of the 2D grid of logical qubits.

[0087] In various embodiments, the second parity condition set of the second QEC code includes one or more parity checks for each column of a second 2D grid for logical qubits. In such embodiments, the one or more parity checks for each column of the second 2D grid for logical qubits may include one or more Z-based parity checks. The second QEC code may include one or more Z-type stabilizers that measure one or more Z-based parity checks for each column of the second 2D grid for logical qubits. The one or more Z-type stabilizers may be juxtaposed with logical qubits included in columns of the 2D grid of logical qubits. The one or more parity checks for each column of the second 2D grid for logical qubits may include one or more X-based parity checks. The second QEC code may include one or more X-type stabilizers that measure one or more X-based parity checks for each column of the second 2D grid for logical qubits. In such embodiments, the one or more X-type stabilizers are juxtaposed with logical qubits included in columns of the 2D grid of logical qubits.

[0088] In some embodiments, performing a lattice operation may include employing a hot storage architecture that operates on a portion of the qubit set. In other embodiments, performing a lattice operation may include employing a hot storage architecture that operates on a portion of the qubit set.

[0089] The implementations of digital, classical, and / or quantum topics, as well as digital function operations and quantum operations, described in this specification can be implemented in digital electronic circuit systems, suitable quantum circuit systems, or more generally, quantum computing systems, in tangibly implemented digital and / or quantum computer software or firmware, in digital and / or quantum computer hardware (including the structures disclosed in this specification and their structural equivalents), or in combinations of one or more of them. The term "quantum computing system" may include, but is not limited to, quantum computers / computing systems, quantum information processing systems, quantum cryptography systems, or quantum simulators.

[0090] The implementation of the digital and / or quantum themes described in this specification can be implemented as one or more digital and / or quantum computer programs, i.e., one or more modules of digital and / or quantum computer program instructions encoded on a tangible, non-transitory storage medium for execution by a data processing device or for controlling the operation of a data processing device. The digital and / or quantum computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubit / qubit structures, or a combination thereof. Alternatively or additionally, the program instructions can be encoded on an artificially generated propagation signal (e.g., a machine-generated electrical, optical, or electromagnetic signal) capable of encoding digital and / or quantum information, which is generated to encode the digital and / or quantum information for transmission to a suitable receiver device for execution by the data processing device.

[0091] The terms quantum information and quantum data refer to information or data carried, stored, or preserved by quantum systems, where the smallest nontrivial system is a qubit, i.e., a system that defines a unit of quantum information. It should be understood that the term "qubit" encompasses all quantum systems that can be appropriately approximated as a two-level system in the corresponding context. Such quantum systems can include multi-level systems, for example, systems with two or more levels. For instance, such systems can include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational ground state is considered as both the ground state and the first excited state; however, it should be understood that other settings where the computational state is considered as a higher-level excited state (e.g., a qubit) are also possible.

[0092] The term "data processing device" refers to digital and / or quantum data processing hardware and encompasses all kinds of devices, apparatuses, and machines for processing digital and / or quantum data, including, for example, programmable digital processors, programmable quantum processors, digital computers, quantum computers, or multiple digital and quantum processors or computers, and combinations thereof. The device may also be or include dedicated logic circuit systems, such as FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits), or quantum simulators, i.e., quantum data processing devices designed to simulate or generate information about a particular quantum system. Specifically, a quantum simulator is a dedicated quantum computer without the ability to perform general-purpose quantum computing. In addition to hardware, the device may optionally include code that creates an execution environment for digital and / or quantum computer programs, such as code constituting processor firmware, protocol stacks, database management systems, operating systems, or combinations thereof.

[0093] Digital or classical computer programs, which can also be referred to or described as programs, software, software applications, modules, software modules, scripts, or code, can be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and can be deployed in any form, including as standalone programs or as modules, components, subroutines, or other units suitable for use in a digital computing environment. Quantum computer programs, which can also be referred to or described as programs, software, software applications, modules, software modules, scripts, or code, can be written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages) and translated into a suitable quantum programming language, or can be written in quantum programming languages ​​such as QCL, Quipper, Cirq, etc.

[0094] Digital and / or quantum computer programs may, but do not necessarily, correspond to files in a file system. Programs may be stored as a portion of a file containing other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinating files (e.g., files storing one or more modules, subroutines, or code sections). Digital and / or quantum computer programs may be deployed to execute on a single digital or quantum computer, or on multiple digital and / or quantum computers located at one site or distributed across multiple sites and interconnected via digital and / or quantum data communication networks. A quantum data communication network is understood to be a network that can transmit quantum data using quantum systems (e.g., qubits). Generally, digital data communication networks cannot transmit quantum data; however, quantum data communication networks can transmit both quantum data and digital data.

[0095] The processes and logic flows described in this specification can be executed by one or more programmable digital and / or quantum computers (which, where appropriate, operate using one or more digital and / or quantum processors) executing one or more digital and / or quantum computer programs to perform functions by manipulating input digital and quantum data and generating outputs. The processes and logic flows can also be executed by a dedicated logic circuit system (e.g., an FPGA or ASIC or a quantum simulator) or by a combination of a dedicated logic circuit system or quantum simulator and one or more programmable digital and / or quantum computers, and the device can also be implemented as such a dedicated logic circuit system or such combination.

[0096] For a system "configured" or "operable to" perform a specific operation or action, this means that the system has software, firmware, hardware, or a combination thereof installed thereon that causes the system to perform the operation or action in operation. For one or more digital and / or quantum computer programs to be configured to perform a specific operation or action, this means that the one or more programs include instructions that cause the digital and / or quantum data processing device to perform the operation or action when executed by the device. A quantum computer can receive instructions from a digital computer that cause the quantum computing device to perform the operation or action when executed by the quantum computing device.

[0097] Digital and / or quantum computers suitable for executing digital and / or quantum computer programs may be based on general-purpose or special-purpose digital and / or quantum microprocessors or both, or any other kind of central digital and / or quantum processing unit. Generally, the central digital and / or quantum processing unit receives instructions and digital and / or quantum data from read-only memory, or random access memory, or a quantum system suitable for transmitting quantum data (e.g., photons), or a combination thereof.

[0098] Some example elements of a digital and / or quantum computer are a central processing unit (CPU) that makes or executes instructions and one or more memory devices for storing instructions and digital and / or quantum data. The CPU and memory may be supplemented by or incorporated into a dedicated logic circuit system or quantum simulator. Generally, a digital and / or quantum computer will also include one or more mass storage devices for storing digital and / or quantum data, such as magnetic disks, magneto-optical disks, or optical disks, or quantum systems suitable for storing quantum information, or operatively coupled to receive digital and / or quantum data from or to such mass storage devices, or both. However, a digital and / or quantum computer need not have such devices.

[0099] Digital and / or quantum computer-readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memories, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks; and quantum systems, such as trapped atoms or electrons. It should be understood that quantum memory is a device capable of storing quantum data for a long period with high fidelity and high efficiency, for example, using light for transmission and using matter for storage and preservation of quantum characteristics (such as superposition or quantum coherence) of the quantum data at an optical-material interface.

[0100] Control of the various systems or portions thereof described in this specification may be implemented using digital and / or quantum computer program products, which include instructions stored on one or more tangible, non-transitory, machine-readable storage media and executable on one or more digital and / or quantum processing devices. The systems or portions thereof described in this specification may each be implemented as an apparatus, method, or electronic system, which may include one or more digital and / or quantum processing devices and memory for storing executable instructions to perform the operations described in this specification.

[0101] While this specification contains numerous details of specific implementations, these details should not be construed as limiting the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations. Certain features described in this specification within the context of individual implementations may also be implemented in combination within a single implementation. Conversely, individual features described within the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features are described above as functioning in certain combinations, and even initially claimed to be so, one or more features from a claimed combination may, in some cases, be removed from said combination, and the claimed combination may be for a sub-combination or a variation thereof.

[0102] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring such operations to be performed in the specific order shown or in sequential order, or requiring all shown operations to achieve the desired result. In some cases, multitasking and parallel processing can be advantageous. Furthermore, the separation of the various system modules and components in the implementation described above should not be construed as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or encapsulated in multiple software products.

[0103] Specific implementations of this subject matter have been described. Other implementations are within the scope of the appended claims. For example, the actions described in the claims can be performed in a different order and still achieve the desired result. As an example, the processes depicted in the figures do not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing can be advantageous.

Claims

1. A method for operating a quantum computing system comprising a set of physical qubits, the method comprising: A quantum algorithm is executed, which redundantly encodes quantum information in each physical qubit of the set of qubits, such that each physical qubit in the set of qubits redundantly encodes the quantum information. When the quantum algorithm is executed, the set of qubits is used to form a set of logical qubits, each logical qubit in the set of logical qubits being formed via a separate subset of the set of qubits, such that each logical qubit in the set of logical qubits redundantly encodes the quantum information, and each separate subset of physical qubits is disjoint from every other separate subset of physical qubits. When executing the quantum algorithm, a first quantum error correction (QEC) code is executed for each logical qubit in the set of logical qubits, wherein the first QEC code detects a first set of parity conditions across the individual physical qubit subsets that form the logical qubits; as well as When executing the quantum algorithm, a second QEC code is executed on the set of logical qubits, wherein the second QEC code detects a second parity condition set across the set of logical qubits.

2. The method of claim 1, wherein the first QEC code is a surface code.

3. The method of claim 2, wherein the second QEC code is a 1D parity check code.

4. The method of claim 2, wherein the second QEC code is a 2D parity check code.

5. The method of claim 1, wherein the set of physical qubits is arranged in a first two-dimensional 2D grid of physical qubits, each individual subset of physical qubits forming the logical qubits in the set of logical qubits is a continuous 2D physical qubit patch in the first 2D grid, and the set of logical qubits is arranged in a second 2D grid of logical qubits superimposed on the first 2D grid of physical qubits, and wherein the second 2D grid of logical qubits is coarser than the first 2D grid of physical qubits.

6. The method of claim 5, wherein the second parity condition set of the second QEC code comprises one or more parity checks for each row of the second 2D grid of logical qubits.

7. The method of claim 6, wherein the one or more parity checks for each row of the second 2D grid for the logical qubits include one or more Z-based parity checks, and the second QEC code includes one or more Z-type stabilizers that measure the one or more Z-based parity checks for each row of the second 2D grid for the logical qubits.

8. The method of claim 7, wherein the one or more Z-type stable sub-yokes are included in the logical qubits in rows of the 2D grid of logical qubits.

9. The method of claim 6, wherein the one or more parity checks for each row of the second 2D grid for the logical qubits include one or more X-based parity checks, and the second QEC code includes one or more X-type stabilizers that measure the one or more X-based parity checks for each row of the second 2D grid for the logical qubits.

10. The method of claim 9, wherein the one or more X-type stable sub-yokes are included in the logical qubits in rows of the 2D grid of logical qubits.

11. The method of claim 5, wherein the second parity condition set of the second QEC code comprises one or more parity checks for each column of the second 2D grid of logical qubits.

12. The method of claim 11, wherein the one or more parity checks for each column of the second 2D grid for the logical qubit include one or more Z-based parity checks, and the second QEC code includes one or more Z-type stabilizers that measure the one or more Z-based parity checks for each column of the second 2D grid for the logical qubit.

13. The method of claim 12, wherein the one or more Z-type stable sub-yokes are included in the logical qubits in columns of the 2D grid of logical qubits.

14. The method of claim 11, wherein the one or more parity checks for each column of the second 2D grid for the logical qubits include one or more X-based parity checks, and the second QEC code includes one or more X-type stabilizers that measure the one or more X-based parity checks for each column of the second 2D grid for the logical qubits.

15. The method of claim 14, wherein the one or more X-type stable sub-yokes are included in the logical qubits in columns of the 2D grid of logical qubits.

16. The method of claim 1, further comprising: When executing the quantum algorithm, lattice operations are performed on at least a portion of the set of qubits based on at least one of the first parity condition set across the individual physical qubit subset or the second parity condition set across the logical qubit set.

17. The method of claim 16, wherein performing the lattice operation comprises employing a hot storage architecture operating on said portion of the set of qubits.

18. The method of claim 16, wherein performing the lattice operation comprises employing a cold storage architecture operating on said portion of the set of qubits.

19. A quantum computing system, comprising: A quantum processor, comprising a set of qubits; One or more memory devices storing computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform operations characterizing the QLC, the operations including: A quantum algorithm is executed, which redundantly encodes quantum information in each physical qubit of the set of qubits, such that each physical qubit in the set of qubits redundantly encodes the quantum information. When the quantum algorithm is executed, the set of qubits is used to form a set of logical qubits, each logical qubit in the set of logical qubits being formed via a separate subset of the set of qubits, such that each logical qubit in the set of logical qubits redundantly encodes the quantum information, and each separate subset of physical qubits is disjoint from every other separate subset of physical qubits. When executing the quantum algorithm, a first quantum error correction (QEC) code is executed for each logical qubit in the set of logical qubits, wherein the first QEC code detects a first set of parity conditions across the individual physical qubit subsets that form the logical qubits; as well as When executing the quantum algorithm, a second QEC code is executed on the set of logical qubits, wherein the second QEC code detects a second parity condition set across the set of logical qubits.

20. The quantum computing system of claim 19, wherein the first QEC code is a surface code, and the second QEC code is a 1D or 2D parity check code.

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