PCIe XDMA-based broadband satellite terminal data transmission method

Abstract

The invention belongs to the technical field of broadband satellite terminal data transmission processing, and particularly relates to a broadband satellite terminal data transmission method based on PCIe XDMA, which can realize high-speed and low-speed data exchange through a PCIe interface and an AXI bus. The invention relates to a data exchange method between a satellite signal processing unit and an information processing unit in a broadband satellite terminal, which specifically realizes high-speed and low-speed data exchange through a PCIe interface and an AXI bus, adopts a DMA Bridge to convert the PCIe bus into the AXI bus, realizes bridge connection of the signal processing unit and the information processing unit, simultaneously mounts high-speed and low-speed equipment on the bus, and realizes data exchange between the signal processing unit and the information processing unit. The method has the capability of accessing high-speed equipment through DMA and accessing low-speed equipment through a Lite bus, and the flexible expansion capability is realized by distinguishing a plurality of different equipment through an AXI bus address.

Description

Technical Field

[0001] This invention belongs to the field of broadband satellite terminal data transmission and processing technology, specifically relating to a broadband satellite terminal data transmission method based on PCIe XDMA. Background Technology

[0002] The satellite communication terminal is a key component of satellite communication equipment, with its core function being data exchange between the ground and the satellite. For the satellite downlink, the satellite terminal receives the frequency-converted signal processed by the antenna feeder unit, and recovers the original information after orthogonal frequency conversion, baseband signal demodulation / decoding, and network protocol conversion. For the satellite uplink, the satellite terminal receives network data, encapsulates the data according to the satellite air interface standard, performs baseband encoding and modulation, and orthogonal frequency conversion before sending it to the antenna feeder unit for transmission to the satellite. The signal processing unit primarily handles baseband signal and orthogonal frequency conversion processing, typically implemented within an FPGA; the information processing unit primarily handles protocol conversion, typically implemented in an embedded CPU. Data exchange between the signal processing unit and the information processing unit is achieved through data transmission. Data exchange processing is a crucial part of the satellite terminal, and its performance determines the overall processing capability of the satellite terminal. The embedded CPU uses various buses and interfaces to interact with the FPGA. Some low-speed buses, such as I2C, SPI, and UART, can only handle low-speed data exchange, while higher-speed data exchange requires higher-speed interfaces, such as the CPU's expansion bus, Ethernet interface, and PCI / PCIe. Among them, the extended bus protocol is relatively simple, and its switching rate depends on the extended bus clock frequency. However, due to its use of parallel data transmission, it is difficult to achieve data transmission speeds of hundreds of Mbps. Moreover, the extended bus is often related to the CPU architecture and needs to be adjusted synchronously during product upgrades and iterations. The Ethernet interface has a data transmission capability of Gbps and the interface is relatively simple, but it needs to handle the relatively complex Ethernet transmission protocol inside the FPGA. PCIe uses serial transmission, has a simple interface, and high data throughput. In the PCIe 6.0 standard, the x1 interface can achieve a data transmission speed of up to 7.563 GB / s. High-performance FPGAs and embedded CPUs all support the PCIe interface, and PCIe has replaced PCI as the mainstream bus in high-speed applications.

[0003] With the deployment and application of multi-beam, high-capacity satellites, higher demands are placed on the signal processing and protocol conversion capabilities of satellite terminals. Transmission bandwidth has increased to tens to hundreds of MHz, further requiring higher data exchange and processing capabilities. Furthermore, as a critical component of satellite terminals, maintaining the stability of interfaces and processing methods is particularly important during product iteration and upgrades. Simultaneously, data exchange and processing should also possess a certain degree of scalability.

[0004] As can be seen, satellite terminals typically consist of a satellite signal processing unit and an information processing unit. The satellite signal processing unit mainly performs intermediate frequency and baseband signal processing, usually implemented using a high-capacity FPGA; the information processing unit mainly performs protocol processing, usually implemented using an embedded CPU. Data transmission processing, as the bridge between the satellite signal processing unit and the information processing unit, is the core part of satellite terminal processing. Due to the characteristics of satellite link transmission, uplink and downlink data exchange exhibit typical asymmetric characteristics, with the downlink transmission bandwidth usually being higher than the uplink bandwidth. With the deployment and application of multi-beam, high-capacity satellites, satellite communication is developing towards higher frequency bands and higher bandwidths. This places higher demands on the processing power, scalability, and product iteration and upgrade capabilities of satellite terminals. The communication bandwidth supported by satellite terminals has developed from tens of MHz to hundreds of MHz, requiring satellite terminals to have higher-speed data exchange capabilities. In addition to completing high-speed data exchange, it should also have low-speed data exchange capabilities such as equipment status monitoring and parameter configuration. More importantly, it is also necessary to consider the compatibility and scalability of subsequent products, and to have good portability during product iteration. Summary of the Invention

[0005] In view of this, the present invention provides a broadband satellite terminal data transmission method based on PCIe XDMA, which can realize high-speed and low-speed data exchange through PCIe interface and AXI bus.

[0006] To achieve the objectives of this invention, the following technical solutions are provided.

[0007] A broadband satellite terminal data transmission method based on PCIe XDMA, wherein the signal processing unit of the satellite terminal is implemented using an FPGA, and the information processing unit is implemented using an embedded CPU. The FPGA and the embedded CPU are connected via a PCIe interface. The method includes: An XDMA core is generated in the FPGA to convert the PCIe interface protocol into the AXI bus protocol. The XDMA core provides both the standard AXI bus and the AXI Lite bus. The high-speed data transmission device is mounted on the standard AXI bus. The high-speed data transmission device is a storage unit built on asynchronous dual-port RAM, which is used to process the uplink data and downlink data of the satellite terminal respectively. The AXI Lite bus is used to connect low-speed data transmission devices for configuring working parameters and acquiring operating status. During data exchange, a PCIe interrupt is triggered to notify the embedded CPU to initiate a DMA read / write operation. When the interrupt triggering condition is met, the FPGA sends an interrupt request to the embedded CPU.

[0008] The specific method of constructing the storage unit based on asynchronous dual-port RAM is as follows: independent asynchronous dual-port RAMs are allocated for the uplink and downlink respectively. The write end of the uplink RAM and the read end of the downlink RAM are connected to the embedded CPU, and the read end of the uplink RAM and the write end of the downlink RAM are connected to the FPGA. When the data packet is stored in the dual-port RAM, the storage boundary is a power of 2 close to its maximum packet length, and a specific byte is used at the beginning position of the data packet to identify the actual length of the data packet.

[0009] The interrupt triggering conditions include the amount of cached data exceeding a preset threshold or the data write timer timing out.

[0010] When allocating cache capacity for the dual-port RAM of the uplink and downlink respectively, the calculation and allocation are based on the interrupt response time of the embedded CPU, the data transmission rate of the corresponding link, and the reserved cache redundancy space.

[0011] The operating status obtained through the AXI Lite bus includes the data storage depth of the dual-port RAM, read / write pointers, and interrupt status vector.

[0012] Beneficial effects 1. This invention relates to a data exchange method between a satellite signal processing unit and an information processing unit in a broadband satellite terminal. Specifically, it achieves high-speed and low-speed data exchange through a PCIe interface and an AXI bus. A DMA Bridge is used to convert the PCIe bus into an AXI bus, thereby bridging the signal processing unit and the information processing unit. The bus can simultaneously connect to both high-speed and low-speed devices, enabling access to high-speed devices via DMA and low-speed devices via the Lite bus. Furthermore, the AXI bus address distinguishes multiple different devices, enabling flexible expansion capabilities.

[0013] 2. In this invention, a high-speed PCIe bus is used as the data exchange and processing bus for the satellite terminal, providing ample transmission bandwidth while ensuring stability during product iteration and upgrades. An XDMA Bridge is introduced to achieve protocol conversion between the PCIe bus and AXI / AXI-lite buses. A bidirectional asymmetric data storage and interaction scheme is designed, enabling high-speed data exchange between multiple clock domains. The AXI-lite bus is used to connect low-speed devices, enabling access to parameter configuration and internal operating status, and providing a certain degree of scalability.

[0014] 3. The low-speed and high-speed data interaction of this invention meets the high-speed data transmission requirements of broadband satellite terminals. The advantages of this invention lie in using a single bus to achieve high-speed and low-speed data exchange, utilizing dual-port RAM to solve the problem of cross-clock high-speed data transmission in bidirectional asymmetric applications in satellite terminals, designing a threshold-based interrupt mechanism combined with a timer to achieve data exchange, effectively improving data exchange efficiency, employing AXI-lite to support low-speed data interaction requirements and possessing certain scalability capabilities, and utilizing the mainstream PCIe transmission interface to ensure product stability during iterative upgrades. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the satellite terminal structure involved in the method of the present invention.

[0016] Figure 2 This is a schematic diagram illustrating the data interaction principle based on PCIe XDMA in this invention.

[0017] Figure 3 This is a schematic diagram of the data interaction processing flow based on PCIe soft interrupts in this invention. Detailed Implementation

[0018] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0019] This invention provides a broadband satellite terminal data transmission method based on PCIe XDMA, specifically for satellite terminals employing high-capacity FPGAs and high-performance embedded CPUs, with the FPGA and CPU connected via a PCIe interface. The FPGA internally supports XDMA and AXI buses. The method includes the following steps: Step 1: The signal processing unit in the satellite terminal adopts a high-capacity FPGA, and the information processing unit adopts an embedded CPU. The FPGA and the embedded CPU are connected through a PCIe interface. Specifically, the satellite terminal employs a high-capacity FPGA and an embedded CPU. The FPGA performs signal processing, while the embedded CPU handles information processing. Data exchange between the FPGA and the embedded CPU is achieved via a PCIe interface. Figure 1 As shown.

[0020] Step 2: Generate an XDMA core in the FPGA to bridge the PCIe and AXI bus. The AXI bus includes the standard AXI bus and the AXI lite bus, both of which are the AXI bus masters used to connect AXIslave devices inside the FPGA.

[0021] Specifically, an XDMA core is generated within the FPGA, supporting the standard AXI bus and AXI lite bus. Acting as the AXI Master, it connects to the Slave devices within the FPGA. The XDMA core provides a PCIe interrupt interface, supporting the initiation of PCIe interrupt requests to the CPU, such as... Figure 2 As shown.

[0022] Step 3: The standard AXI bus is used to complete high-speed DMA data transfer. To address the multi-clock domain data transfer in the asymmetric uplink and downlink links of satellite transmission, two independent asynchronous dual-port RAMs are used to process uplink and downlink data respectively, connected to the AXI bus via an AXI Block Memory Controller. In the uplink and downlink dual-port RAMs, the storage boundary for data packets is defined as a power of 2 or greater than the maximum packet length. The first two bytes of the data packet identify its actual length. Each DMA data packet read / write operation is performed in multiples of the maximum packet length, and then the actual data packet is extracted based on the byte length.

[0023] Specifically, an AXI Block Memory Controller is generated in the FPGA and attached to the AXI standard bus of the XDMA core. The AXI Block Memory Controller transforms the AXI bus read / write operation into simple BRAM read / write access. Dual-port RAMs are generated for both uplink and downlink. The downlink RAM is written to by the FPGA and read out by the CPU; the uplink RAM is written to by the CPU and read out by the FPGA. The uplink and downlink write clocks are consistent with the FPGA operating frequencies for both links.

[0024] Based on the CPU's interrupt response capability and the uplink / downlink data rates, allocate cache capacity for the uplink and downlink respectively. For example, if the CPU interrupt response capability is 5ms, and the uplink / downlink data rates are 1Mbps / 100Mbps respectively, considering a 5x cache redundancy, the allocated uplink and downlink cache capacities are 25kb and 2.5Mb respectively.

[0025] When writing to dual-port RAM, the maximum packet length is a power of 2 as the data packet storage boundary. For example, if the maximum length of the following packet data is 16,000 bits, the actual storage depth is 16,384 bits. The first two bytes are used as the actual length of the packet data and are written last after the packet data is received. The unit is bytes.

[0026] Step 4: The AXI lite bus is used to complete low-speed data processing, enabling the configuration of working parameters and the acquisition of operating status, including the data storage depth, read / write pointers, and interrupt status vectors of the dual-port RAM; the read / write status of the RAM is notified to the embedded CPU through the AXI-lite bus.

[0027] Step 5: During data exchange, the embedded CPU is notified to initiate DMA read / write operations via PCIe interrupts. An interrupt is triggered when the cache space exceeds a threshold or a timer expires. For downlink data, the FPGA maintains a write pointer in the RAM, and the CPU maintains a read pointer. The FPGA calculates the number of data packets written to the RAM based on the read and write pointers. When the number of written packets exceeds a threshold or the write data packet timer expires, an interrupt is sent to the CPU to notify it to retrieve the data. For uplink data, the CPU maintains a write pointer, and the FPGA maintains a read pointer. The FPGA calculates the number of data packets in the RAM, and notifies the CPU to write data when the remaining space exceeds a threshold.

[0028] In addition, for the downlink, to prevent a small amount of data from remaining in the cache for a long time because it does not reach the cache threshold, a timer is set when writing data. The timer duration is 1ms. When the timer expires, an interrupt is triggered, and the CPU reads the cached data. Figure 3 This is a schematic diagram of the data interaction processing flow based on PCIe soft interrupts in this invention.

[0029] The broadband satellite terminal data transmission method based on PCIe XDMA provided by this invention achieves efficient and reliable data exchange between the signal processing unit and the information processing unit inside the satellite terminal through an overall process. First, a high-speed PCIe bus is used as the interconnection foundation, providing ample transmission capacity to support the ever-increasing bandwidth of satellite communication. Simultaneously, this interface is a standard and universal interface, ensuring compatibility and stability during product upgrades. Second, by integrating an XDMA core within the FPGA, a clever bridge between the PCIe protocol and the AXI bus protocol is achieved, enabling a single bus system to simultaneously serve high-speed DMA data transmission and low-speed control status access, simplifying system design.

[0030] Specifically, independent asynchronous dual-port RAMs are used to process uplink and downlink asymmetric data streams separately, effectively solving the problem of high-speed data transmission across multiple clock domains between the FPGA and CPU. By setting data packet storage boundaries and length markers, regularized storage and efficient retrieval of data packets are achieved. The defined thresholds, combined with the timer interrupt triggering mechanism, ensure efficient batch transmission when the data volume is large, while preventing small amounts of data from being stuck for a long time due to not reaching the threshold, significantly improving the real-time performance and overall efficiency of data exchange.

[0031] Furthermore, the cache capacity is scientifically allocated based on CPU processing power and link speed, ensuring stable system operation under various loads. The AXI Lite bus allows flexible access to various status and configuration parameters, which not only meets the basic needs of device monitoring and debugging but also facilitates system function expansion, giving this method good adaptability and scalability. In summary, this method combines the advantages of high-speed transmission, stability and reliability, high efficiency and flexibility, making it particularly suitable for the data processing needs of next-generation broadband satellite terminals.

[0032] This invention includes, but is not limited to, the above embodiments. Any equivalent substitutions or partial improvements made under the spirit and principles of this invention shall be considered within the scope of protection of this invention.

Claims

1. A broadband satellite terminal data transmission method based on PCIe XDMA, characterized in that, The satellite terminal's signal processing unit is implemented using an FPGA, and its information processing unit is implemented using an embedded CPU. The FPGA and the embedded CPU are connected via a PCIe interface. The method includes: An XDMA core is generated in the FPGA to convert the PCIe interface protocol into the AXI bus protocol. The XDMA core provides both the standard AXI bus and the AXI Lite bus. The high-speed data transmission device is mounted on the standard AXI bus. The high-speed data transmission device is a storage unit built on asynchronous dual-port RAM, which is used to process the uplink data and downlink data of the satellite terminal respectively. The AXI Lite bus is used to connect low-speed data transmission devices for configuring working parameters and acquiring operating status. During data exchange, a PCIe interrupt is triggered to notify the embedded CPU to initiate a DMA read / write operation. When the interrupt triggering condition is met, the FPGA sends an interrupt request to the embedded CPU.

2. The method according to claim 1, characterized in that, The specific method of constructing the storage unit based on asynchronous dual-port RAM is as follows: independent asynchronous dual-port RAMs are allocated for the uplink and downlink respectively, the write end of the uplink RAM and the read end of the downlink RAM are connected to the embedded CPU, and the read end of the uplink RAM and the write end of the downlink RAM are connected to the FPGA. When data packets are stored in dual-port RAM, the storage boundary is a power of 2 that is close to the maximum packet length, and a specific byte is used at the beginning of the data packet to identify the actual length of the data packet.

3. The method according to claim 1 or 2, characterized in that, The interrupt triggering conditions include the amount of cached data exceeding a preset threshold or the data write timer timing out.

4. The method according to claim 1 or 2, characterized in that, When allocating cache capacity for the dual-port RAM of the uplink and downlink respectively, the calculation and allocation are based on the interrupt response time of the embedded CPU, the data transmission rate of the corresponding link, and the reserved cache redundancy space.

5. The method according to claim 1, characterized in that, The operating status obtained through the AXI Lite bus includes the data storage depth of the dual-port RAM, read / write pointers, and interrupt status vector.

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