Methods and structures employing metal oxides for direct metal bonding

Abstract

A semiconductor element is provided over the conductive feature at the hybrid bonding surface, with a microstructure metal oxide layer. The microstructure metal oxide layer includes fine metal oxide particles, such as nanoparticles. The particles may be formed over the conductive feature by oxidizing a metal included in the conductive feature, or by providing a metal oxide over the conductive feature. When directly bonded to another element, the microstructure metal oxide layer can form a strong bond at the bonding interface at a significantly reduced annealing temperature.

Description

Technical Field

[0001] This disclosure relates to direct bonding of microelectronic devices, and more specifically to direct metal bonding, such as hybrid bonding. Background Technology

[0002] The microelectronics industry has experienced tremendous growth over the past few decades. However, the market's demand for higher input / output (I / O) density and faster interconnects between chips is relentless. This demand has driven integrated circuit (IC) system design into a three-dimensional architecture. Solder bumps and microbumps provide vertical interconnects between chips as a form of wafer-level packaging by using small metal bumps on the die. Hybrid bonding can provide solutions for ultra-high density interconnect features.

[0003] Hybrid bonding, such as DBI, which is commercially available from Adeia of San Jose, CA ® This technology avoids the use of metal bumps and instead uses direct metal-to-metal (e.g., copper-to-copper) conductive feature connections to connect the dies within the package. In the bonding layer of each bonded element, conductive features (such as metal contact pads) are embedded in the dielectric material. The hybrid bonding surfaces can be planarized and cleaned by chemical mechanical polishing (CMP) to remove particles and contaminants. Plasma activation can generate active sites on the dielectric material of the hybrid bonding surface of at least one of the two elements to be bonded. The two bonded elements are precisely aligned and bonded together in a bonding apparatus, with the active sites on the bonding surfaces bonded to each other. Dielectric bonding can be performed at room temperature. Annealing processes can help bond aligned conductive features and also strengthen the bonding between the dielectric materials.

[0004] Although hybrid bonding has greatly improved the ability to form high-density and reliable connections between microelectronics, there is still a need to improve yield, reduce costs, and / or reduce thermal budget consumption. Attached Figure Description

[0005] Specific embodiments will be described with reference to the following figures, which are provided by way of example only and not as limitations.

[0006] Figures 1 to 4 This is a schematic cross-sectional view illustrating an example process for manufacturing a semiconductor device with conductive features on a metal oxide substrate for hybrid bonding.

[0007] Figures 5 to 7B This is a schematic cross-sectional view illustrating an example process for co-bonding an element with a conductive metal oxide to another element.

[0008] Figure 8A This is an atomic force microscope (AFM) image, showing the results based on... Figures 1 to 4 The morphology of the upper surface of the experimental die produced by the process.

[0009] Figure 8B These are transmission electron microscope (TEM) images, showing the results according to... Figures 1 to 7B The cross-section of the experimental bonded structure produced by the process.

[0010] Figure 8C It is an energy-dispersive spectroscopy (EDS) line scan, spanning the generation Figure 8B Bonding interfaces of experimental bonding structures in images.

[0011] Figures 9 to 14 This is a schematic cross-sectional view illustrating another example process for manufacturing a semiconductor device with conductive features on a metal oxide substrate for hybrid bonding.

[0012] Figures 15A to 16 It includes Figure 14 A schematic cross-sectional view of the bonding structure of a semiconductor device.

[0013] Figures 17 to 18 This is a schematic cross-sectional view illustrating another example process for manufacturing a semiconductor device with conductive features on a metal oxide substrate for hybrid bonding.

[0014] Figures 19 to 21 This is a schematic cross-sectional view illustrating an example process of co-bonding a wafer with a conductive metal oxide layer to another wafer.

[0015] Figures 22 to 26 This is a schematic cross-sectional view illustrating an example process for co-bonding a wafer with a conductive metal oxide to multiple chips.

[0016] Figures 27 to 28 This is a schematic cross-sectional view illustrating an example hybrid bonding structure with conductive features of different widths.

[0017] Figure 29 It is a schematic cross-sectional view of two microelectronic components configured to be hybrid-bonded together.

[0018] Figure 30 It includes Figure 29 A schematic cross-sectional view of the bonding structure of two microelectronic components. Detailed Implementation

[0019] The annealing temperature and duration used to form direct conductor-to-conductor (e.g., metal-to-metal) bonds are critical in the fabrication of directly bonded components. Lower annealing temperatures and / or shorter annealing durations are desirable, for example, to reduce heat budget consumption and stress due to coefficient of thermal expansion (CTE) mismatch. Various bonding layer structures and methods for producing such bonded semiconductor elements can be implemented to achieve lower annealing temperatures, thereby fully fusing the contact pads or other conductive features of the bonded semiconductor element together. One way to reduce the annealing temperature involves providing a metal oxide on the conductive features, which can enable bonding at lower annealing temperatures and may still be beneficial, although it introduces oxygen into the bonded metal contacts.

[0020] Figures 1 to 4 The illustration shows an example embodiment of a manufacturing process for forming metal oxides on conductive features for direct bonding, such as contact pads, lines, or vias. Figure 1 A schematic cross-sectional view of at least a portion of element 100 (such as a microelectronic structure, semiconductor substrate, semiconductor element, or microelectronic component) is shown. Element 100 may include a substrate 102, such as a bulk semiconductor material (e.g., silicon), an interposer substrate, a semiconductor package substrate, a planar substrate, a dielectric substrate, a passive device substrate, or a microelectromechanical system (MEMS) substrate. The substrate 102 may include active circuitry, including transistors and / or other electronic devices, which are at least partially formed therein. A substrate non-conductive or dielectric material layer 104 may be provided on the substrate 102, having conductive features 110 embedded therein. A first non-conductive or dielectric layer 106 may be provided on the dielectric material layer 104. An intermediate via 112 may be embedded in the first dielectric layer 106. An upper or second non-conductive or dielectric layer 108 may be provided on the first dielectric layer 106, and a patterned conductive material 114 may be at least partially embedded therein to provide conductive features. In some embodiments, the conductive features may be provided by deposition and etching. In the illustrated embodiment, stages of the damascus process are shown. Trenches or cavities are formed in the second dielectric layer 108 and then filled with a conductive material 114. The conductive material 114 may overfill the cavities, including a capping layer over the field region of the second dielectric layer 108. A barrier layer 116 may be provided between the second dielectric layer 108 and the conductive material 114 to restrict the diffusion of the conductive material 114 into the second dielectric layer 108. Additional dielectric layers, such as dielectric barrier materials, may also be provided as part of or between the illustrated dielectric layers 104, 106, 108.

[0021] In some embodiments, a seed layer may be disposed on the barrier layer 116, such as by copper sputtering. In some embodiments, the conductive material 114 and the intermediate via 112 are formed together, for example by a double damask process, in which case the barrier layer 116 between the conductive material 114 and the intermediate via 112 may be omitted. Other methods known in the art are used to omit the barrier material between conductive features.

[0022] exist Figure 1 In this bonding layer, each of the first dielectric layer 106 and the second dielectric layer 108 may include an inorganic dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc. In some embodiments, one or both of the first dielectric layer 106 and the second dielectric layer 108 may be a low-k dielectric material (e.g., porous silicon oxide, organosilicon glass (SiCOH), or amorphous carbon). Each of the conductive features, including the intermediate via 112, the conductive material 114, and the underlying conductive feature 110, may include a metal, such as copper, nickel, chromium, gold, indium, ruthenium, tin, platinum, silver, molybdenum, palladium, metal silicides, cobalt, zinc, tungsten, tantalum, titanium, aluminum, and alloys thereof, or a non-metallic conductive material (e.g., doped silicon). In some embodiments, the conductive material 114 in the bonding layer primarily includes copper.

[0023] Reference Figure 2 If necessary, component 100 may undergo an annealing process to optimize the grain structure of the conductive features. Subsequently or prior, excess conductive material 114 and barrier layer 116 disposed on the top surface of the second dielectric layer 108 may be removed, and possibly the top portion of the dielectric layer 108 may be removed to leave a planarized upper surface 118, such as by CMP. After planarization, the remaining conductive material portion 114 is confined within its isolated cavity and thus becomes conductive feature 114a, as shown. Figure 2 As shown. Conductive feature 114a may be a conductive contact pad or other conductive functional or non-functional feature, such as a dummy pad, lateral trace, or the upper end of a via (such as a through-substrate via TSV). The upper surface 118 of component 100 includes the upper surface of the second dielectric layer 108 and the upper surface of conductive feature 114a. For embodiments where both the dielectric and conductive feature will be directly bonded, and planarization is applicable to direct dielectric bonding, the top layer of component 100, including the second dielectric layer 108 and conductive feature 114a in the illustrated embodiment, may be referred to as a hybrid bonding layer, and the upper surface 118 may be considered as a bonding surface. Those skilled in the art will understand that, in other embodiments, the processes described herein can be applied to more... Figure 2The diagram illustrates more complex or simpler structures, such as more or fewer metallization levels between the device level and the bonding layer. Those skilled in the art will also understand that the processes and structures described herein are also applicable to non-IC microelectronic components, such as, but not limited to, passive devices, MEMS, interposers, and other package substrates.

[0024] like Figure 3 As shown, the top portion of conductive feature 114a is selectively removed (e.g., by etching) to form recess 122. The depth of recess 122 can be between approximately 5 nm and 30 nm, for example, between approximately 10 nm and 20 nm, or between approximately 20 nm and 30 nm. In some embodiments, deeper recesses can be formed (e.g., between approximately 10 nm and 50 nm or even deeper), depending in part on the structure of contact feature 114a and the expansion volume of the underlying metal during hybrid bonding. Those skilled in the art will understand that... Figure 3 The recess 122 can be formed by a separate recess operation after planarization and annealing, as described above, or it can be formed as described above regarding... Figure 2 The described CMP process results in the recess of conductive feature 114a by appropriately selecting physical components (e.g., pad hardness, speed) and chemical components (e.g., paste selectivity), as... Figure 3 As shown schematically in the diagram.

[0025] exist Figure 4 In this example, element 100 has been exposed to an oxidizing environment that oxidizes the upper portion of conductive feature 114a, which may include a metal. The oxidation process can be plasma oxidation (e.g., by exposure to oxygen-containing plasma), thermal oxidation, ozone exposure, or wet oxidation (e.g., by exposure to inorganic or organic oxidants, such as peroxides). Figure 3 The element 100 can undergo an ashing process, in which the products of oxygen-containing plasma are provided to the element. This process is called "ashing" because it is traditionally used to burn off organic photoresist. In some embodiments, oxidation can be performed simultaneously with the removal of photoresist, other organic protective layers, and / or residues of such organic materials.

[0026] like Figure 4As shown, during the oxidation process, oxygen can react with a metal that is exposed on the upper surface of the conductive feature 114a. Therefore, a metal oxide layer 124 is selectively formed on each of the conductive features 114a. Because this oxidation process relies on diffusion, the metal oxide in the metal oxide layer 124 and the metal in the underlying conductive feature 114a may be interwoven. The average thickness of the metal oxide layer 124 can be at least 2 nm, and in some embodiments can be up to 30 nm, for example, between about 5 nm and 30 nm, or between about 10 nm and 25 nm. The metal oxide layer 124 tends to have a particulate microstructure, such as nanoparticles, with a surface roughness of at least about 1 nm root mean square (RMS), or at least about 2 nm RMS, for example, between about 2 nm and 5 nm RMS, or between about 1.5 nm and 4 nm RMS. For example, the metal oxide may comprise particles having an average size (e.g., the average of the largest particle sizes) in the range of approximately 2 nm to 100 nm (e.g., an average size in the range of approximately 3 nm to 80 nm, or in the range of approximately 5 nm to 50 nm). The tendency of the oxide to grow and form microstructures (e.g., nanoparticles or micropores) may cause volume expansion of the ultimately formed metal oxide layer 124. Depending on the depth of the pre-oxidation recess 122, the expansion may leave a shallower recess 126 as shown, or it may cause the metal oxide to protrude above the upper dielectric surface of the hybrid bonding layer. If a protruding recess is desired, selective metal oxide etching may be applied to recess the metal oxide layer 124 into the cavity within the second dielectric layer 108, thereby forming the shallow recess 126 illustrated above the metal oxide layer 124. Figure 4 The upper surface 118 includes both a dielectric surface (which can be prepared for direct bonding) and the surface of the metal oxide layer 124.

[0027] exist Figure 4 During the oxidation process, the conductive feature 114a may decouple or detach from the surrounding second dielectric layer 108 due to some oxidation occurring along the sidewalls of the conductive feature 114a and / or the surrounding barrier layer 116. This decoupling can facilitate the free expansion of the conductive feature 114a and the metal oxide layer 124 above it relative to the surrounding material during the subsequent bonding annealing process, thus enhancing the bonding process.

[0028] refer to Figure 5 , Figure 4Element 100 (the first element) and second element 200 are prepared to be bonded. One or both of elements 100 and 200 can be prepared for direct bonding as described herein, including planarization suitable for direct bonding and activation and / or termination to increase dielectric-dielectric bond strength. While the first element 100 includes a metal oxide layer 124, which may have the microstructure described above at the upper surface 118 of each of the conductive features 114a, the second element 200 does not have such a metal oxide layer on the conductive feature 214. In other embodiments, the conductive feature 214 of the second element 200 may include a metal oxide layer like the first element 100. Figure 5 As shown, the conductive feature 214 of the second element 200 is aligned with the corresponding conductive feature 114a of the first element 100. After the alignment of the conductive features 114a and 214, the second element 200 is moved along direction 220 (e.g., operated by a bonding device) to be directly bonded to the first element 100.

[0029] exist Figure 6 In this process, the second element 200 is directly bonded to the first element 100 without intermediate adhesive to form the bonding structure 1. As previously described, the bonding surfaces (upper surface 118) of the first element 100 and / or the bonding surface 218 of the second element 200 can be activated and / or terminated prior to the hybrid bonding process. For example, the upper surface 118 of the first element 100, including the metal oxide layer 124, can be exposed to nitrogen-containing plasma, which may result in an increase in nitrogen content near the bonding interface between the insulating and conductive materials. Therefore, the dielectric layer 208 of the second element 200 can be directly bonded to the second dielectric layer 108 of the first element 100. The initial direct bonding of the dielectric surfaces can be performed at room temperature. At this stage, the conductive feature 214 of the second element 200 is not (fully) bonded to the conductive feature 114a of the element 100. In some embodiments, the conductive features 114a, 214 of the two elements 100, 200 are recessed relative to the dielectric layers 108, 208 surrounding them, such that... Figure 6 At the stage, there is a gap (not shown) between the corresponding conductive features 114a and 214.

[0030] Move to Figure 7AThe bonding structure 1 undergoes an annealing process to heat the bonded elements 100 and 200 to a high temperature and hold it for a sufficient duration to complete the bonding of conductive feature 114a to conductive feature 214. The bonding between dielectric layers 108 and 208 can also be strengthened during the annealing process. During the annealing process, conductive feature 114a of the first element 100 may expand due to a mismatch in the coefficient of thermal expansion (CTE) between the metallic material of conductive feature 114a (and any underlying metallic structure) and the surrounding second dielectric material 108. Those skilled in the art will understand that the CTE is typically smaller for dielectric materials (e.g., silicon oxide) than for conductive materials (e.g., copper). Similarly, conductive feature 214 of the second element 200 may also tend to expand, similar to conductive feature 114a, due to the CTE mismatch. The expansion of conductive features 114a and 214 causes the metal oxide layer 124 above each of conductive features 114a to press against the corresponding conductive feature 214. The free movement of conductive feature 114a (including the metal oxide layer 124 disposed thereon) enhances the pressure generated between conductive features 114a and 214 due to the aforementioned sidewall decoupling. Under the influence of the increased annealing temperature and expansion force, conductive features 114a and 214 may directly bond to each other.

[0031] During the annealing process, the increased annealing temperature and prolonged annealing duration may cause changes in the metal oxide layer 124. First, oxygen in the metal oxide layer 124 may be released. Some of this oxygen may diffuse into the bonded conductive features 114a, 214. Second, some residual metal oxides in the metal oxide layer 124 may migrate from the initial interface into the bonded conductive features 114a, 214. Therefore, after annealing, the conductive features 114a, 214 may have a relatively high oxygen content, in the form of residual metal oxides, free oxygen, and / or dissolved oxygen. This oxygen content may exceed the oxygen concentration typically below 20 ppm in electroplated copper. For example, within approximately 100 nm of the bonding interface, the oxygen content of the merged conductive features 114a, 214 may be greater than 50 ppm, such as between 100 ppm and 10,000 ppm, or between 60 ppm and 5,000 ppm. In some embodiments, the oxygen content in approximately 100 nm of the bonding interface may exceed the oxygen saturation levels of the materials of the conductive features(s) 114a and / or 214, such as greater than the 120 ppm oxygen saturation level in copper. In comparison, the copper structure 114a beneath the bonding layer (e.g., a redistribution layer or BEOL beneath the contact pads) may have an oxygen content of less than 20 ppm. When the metal oxide layer 124 is exposed to nitrogen (e.g., nitrogen-containing plasma products) for activation and / or termination of the insulating layer, the nitrogen content incorporated into the bonding metal features may also increase relative to a process without adding metal oxide to the conductive features, and has been found to be in the range of approximately 5% to 200% for the nominal pads 114a without the metal oxide layer 124.

[0032] Following annealing, conductive feature 114a of element 100 may be fused and bonded to the corresponding conductive feature 214 of element 200 via metal oxide layer 124. Electrical connections can be formed between the corresponding conductive features 114a and 214, exhibiting surprisingly low resistance despite the initial presence of metal oxide at the interface. Furthermore, physical diffusion may cause changes in the microstructure of the conductive material. At the end of the annealing process, metal particles from conductive features 114a and 214 may have grown to extend across the hybrid bonding interface.

[0033] refer to Figure 7BDue to the CTE mismatch between the conductive feature and the surrounding dielectric material, conductive feature 114a and the corresponding conductive feature 214 press against each other. The metal oxide layer 124 on top of conductive feature 114a before annealing, as shown in the figure, may fuse with the opposing conductive feature 214. In some embodiments, the force generated by the CTE mismatch and the fusion at elevated annealing temperatures may cause the conductive features 114a, 214 in the bonding region 230 at the mixed bonding interface to expand outwards, forming a sidewall structure with laterally protruding features, such as... Figure 7B The diagram is schematic. In some embodiments, there may be no raised sidewalls at the bonding interface. The contour and microstructure of the bonding region 230 depend not only on the microstructure between the conductive features at bonding time, but also on the annealing temperature and duration. Similarly, whether any residual microstructural features (e.g., nanoparticle structures) from the metal oxide layer 124 remain in the bonding structure 1 to distinguish the particle structure at the interface from the particle structure further away from the conductive features 114a, 214 may also depend on the annealing temperature and duration.

[0034] Compared to direct bonding of two semiconductor elements without the metal oxide layer 124, the metal oxide layer 124 facilitates high-quality direct bonding of conductive features at lower annealing temperatures (equivalent or better bonded conductor conductivity and yield). The microstructure provided by the metal oxide layer 124 can reduce the bonding temperature and enhance metal diffusion. Furthermore, any oxidation of the sidewalls of the conductive feature can decouple the conductive feature from the surrounding dielectric, facilitating the expansion of the conductive feature and thus reducing the annealing temperature for a given amount of expansion. The physical stress generated by the significant mutual expansion of the conductive features also facilitates metal grain growth across the bonding interface at lower temperatures. Both of these aspects facilitate the use of reduced or no recesses in the conductive feature relative to the surrounding dielectric, which can improve uniformity across the substrate and reduce the annealing temperature for a given metal bond conductivity, reliability, and yield. Further benefits can be achieved when both the first element 100 and the second element 200 have metal oxide layers on their conductive features 114a and 214. However, when one of the first element 100 and the second element 200 includes a metal oxide layer on its conductive feature 114a or 214, the annealing temperature can be significantly reduced compared to the annealing temperature required for equivalent metal bonding reliability when there is no intermediate metal oxide layer. For example, if both conductive feature 114a of the first element 100 and conductive feature 214 of the second element 200 are made of copper and there is no metal oxide layer between them, the annealing temperature may be 250°C or higher to achieve low resistance and high process yield. When one of the first element 100 and the second element 200 has a metal oxide layer 124 on its conductive feature 114a or 214, the annealing temperature may be lower than 250°C, lower than 200°C, or lower than 180°C to achieve equivalent resistance and process yield results. For example, the annealing temperature for directly bonding conductive feature 114a to conductive feature 214 can be reduced to the range of 150°C to 250°C, 100°C to 200°C, or 80°C to 180°C. For equivalent annealing effects, the range of temperature reduction may also be affected by the microstructure of the metal oxide layer 124. For example, the annealing temperature for an average metal oxide particle size of approximately 10 nanometers may be significantly lower than the annealing temperature for an average metal oxide particle size of approximately 50 nanometers for equivalent bonding effects.

[0035] In some embodiments, the conductive feature 114a of the first element 100 primarily (>50 atom %) comprises copper, and the conductive feature 214 of the second element 200 may comprise common metallic materials such as copper, silver, nickel, gold, indium, zirconium, molybdenum, zinc, tungsten, tantalum, or titanium, aluminum, or alloys thereof. In some embodiments, the metallic materials forming conductive features 114a and 214 may each comprise two different metals. For example, the metallic material of conductive feature 114a of element 100 primarily comprises copper, and the metallic material of conductive feature 214 of element 200 comprises nickel, thus being a copper-to-nickel (Cu / Ni) combination. Other combinations of metallic materials for conductive features 114a and 214 may include a copper-to-manganese (Cu / Mn) combination and a copper-to-silver (Cu / Ag) combination.

[0036] Conduct experiments, following the guidelines Figures 1 to 4 The process described above fabricates a first element (e.g., a die) 100 to form a copper oxide layer over copper contact pads embedded in a silicon oxide dielectric material. The copper contact pads and the surrounding silicon oxide together form a bonding layer. The first element 100 is then directly bonded to a second element 200 having corresponding copper contact pads, following the process described above. Figure 5 The process described up to 8 involves direct bonding. Specifically, the first element 100 undergoes an ashing process by exposure to an oxygen-containing plasma for a period between 60 seconds and 31 minutes. After a metal oxide layer 124 is formed on the conductive layer 114a of the first element 100, the bonding surface is activated. In some embodiments, both the first element 100 and the second element 200 may be activated. The prepared bonding surface is cleaned or rinsed with DI water and dried. After bonding, the bonding structure 1 is oven annealed at 200°C for 2 hours to bond the contact pads of 114a and 214. At room temperature, the chain resistance of the bonding structure (through the electrical path of the multiple bonded contact pads) for testing purposes is measured on the first element 100. After the electrical measurements, additional heat treatment may be performed, for example, by thermal annealing at 225°C for 1 hour and then annealing again at 250°C for 1 hour. Intermediate electrical tests may be performed between the last two annealing processes.

[0037] Figure 8A This is an atomic force microscopy (AFM) image showing the morphology of the upper surface 118b of the first die after an ashing process that forms a copper oxide layer on top of the copper contact pad 114b. It can be seen that the copper contact pad 114b with copper oxide is recessed by approximately 10 nm. Furthermore, the sidewalls of the copper contact pad 114b show indications of decoupling 117a and 117b. The indication of decoupling 117a extends downwards from the upper surface of the copper contact pad 114b by more than 20 nm. Figure 8AThe decoupling 117a shown is analogous to the physical gap at the sidewall of the copper contact pad 114b. As described above and will be further explained, this decoupling allows the copper contact pad 114b to expand freely relative to the surrounding material during subsequent bonding and annealing processes, thus enhancing bonding quality.

[0038] The experimental results also show that the upper surface of the copper contact pad 114b of the first die is roughened after ashing. For example, after 21 minutes of ashing, the surface roughness of the copper contact pad 114b increases to approximately 2.56 nm RMS. After 31 minutes of ashing, the surface roughness of the copper contact pad 114b increases to approximately 2.89 nm RMS. These results are compared with control samples that did not undergo the ashing process. The surface roughness of the copper contact pad 114b for the control samples is approximately 1.24 nm RMS. The increase in the surface roughness of the copper contact pad 114b implies that the formed copper oxide may have an ultrafine or nanoparticle microstructure.

[0039] Figure 8B The image shows a transmission electron microscope (TEM) image of a partial cross-section of the bonded structure 1a produced in the experiment described above. As shown, the contact pads 114b of the first die and 214b of the second die are tightly bonded, with no gap between them at interface 232. (See also: Regarding...) Figure 7A and 7B As described above, no obvious granular metal layer is present on the top portion of the copper contact pad 114b. Experimental results show that this process has high yield, high bond strength, and low resistance.

[0040] Figure 8C This is a line scan of the energy dispersive spectroscopy (EDS) spectrum across the 1a interface of the bonded structure at 230°. Figure 8C In the diagram, interface 232 is located at the middle 60 nm position. The copper contact pad 114b of the first die is on the upper right side of the 60 nm position, as shown below. Figure 8C As shown. Figure 8C The graphs include oxygen content curve 242 and nitrogen content curve 244. It can be seen that oxygen content curve 242 is in the range of approximately 1.5 atom % to close to 3 atom %. This oxygen content level is higher than that of the control sample. The higher oxygen content may originate from copper oxide formed during the ashing process. The higher nitrogen content (in the range of approximately 3.8 atom % to approximately 6 atom %) may originate from the separate activation / termination of the first and second dies, for example, through exposure to nitrogen-containing plasma.

[0041] exist Figures 1 to 4 In the embodiment shown, the metal oxide layer 124 is formed by oxidizing the upper surface of the conductive feature 114a. Figures 1 to 4 One advantage of the oxidation process is that the metal oxide layer 124 can be selectively and directly formed on the conductive feature 114a. However, metal oxide particles can be formed on the upper surface of the conductive feature 114a in other ways.

[0042] Figures 9 to 18 The illustration shows example embodiments of providing a metal oxide layer on conductive feature 114a using different techniques.

[0043] This process is from Figure 1 The illustrated structure begins with element 100 being formed having a patterned conductive material 114, which is at least partially embedded in a second dielectric layer 108. The conductive material 114 can be connected to underlying conductive features or circuitry within the embedded layer 104 via an intermediate via 112. At the illustrated stage of the process, the conductive material 114 still comprises a capping layer over the field region of the second dielectric layer 108. A barrier layer 116 may be provided between the second dielectric layer 108 and the conductive material 114, including a horizontal separation between the second dielectric layer 108 and the conductive material 114, to restrict the diffusion of the conductive material 114 into the second dielectric layer 108.

[0044] and Figure 2 The process is similar; if desired, component 100 can undergo an annealing process to optimize the grain structure of the conductive features. Subsequently, excess conductive material 114 disposed on barrier layer 116 can be removed to leave a planarized upper surface 118a, such as by CMP. After planarization, the remaining conductive material portion 114 is confined within its isolated cavity and thus becomes conductive feature 114a, as shown. Figure 9 As shown. With Figure 2 Unlike other components, the upper surface 118a of component 100 includes the surface of the barrier layer 116 and the upper surface of the conductive feature 114a to facilitate subsequent polishing processes. The conductive feature 114a can be a conductive contact pad or other conductive functional or non-functional structure, such as a dummy pad, a lateral trace, or the upper end of a via, for example, a through-substrate via (TSV). In embodiments employing hybrid bonding, the top layer of component 100, including the second dielectric layer 108 and the conductive feature 114a in the illustrated embodiment, can be referred to as a hybrid bonding layer, although... Figure 9 In this example, the upper surface 118a may not yet be prepared for hybrid bonding. Those skilled in the art will understand that in other embodiments, the process described herein can be applied to... Figure 9The diagram illustrates more complex or simpler structures, such as those with more or fewer metallization levels between the device level and the bonding layer. Those skilled in the art will also understand that the processes and structures described herein are also applicable to non-IC microelectronic components, such as, but not limited to, passive devices, MEMS, interposers, and other packaging substrates.

[0045] Such as about Figure 3 The top portion of the conductive feature 114a can be selectively removed (e.g., by etching) to form the recess 128, as described above. Figure 10 As shown. The recess can be formed during the polishing process of the capping layer from the conductive feature 114a, or in a subsequent wet or dry etch-back process. Depending on the structure of the contact feature 114a and the specific thin-film process involved, the depth of the recess 128 can be between approximately 0.1 μm and 0.5 μm (100 nm to 500 nm), for example, between approximately 100 nm and 300 nm, or between approximately 200 nm and 400 nm. In some embodiments, shallower or deeper recesses can be formed, for example, between approximately 50 nm and 100 nm, or between 400 nm and 800 nm.

[0046] refer to Figure 11 Component 100 can be cleaned (e.g., by sputtering). Subsequently, a metal layer 130 is coated over the upper surfaces of the recess 128 and the barrier layer 116. Both the metal layer 130 and the conductive feature 114a may comprise, for example, primarily copper. In some embodiments, the metal layer 130 may comprise copper, and the conductive feature 114a may comprise various materials such as nickel, chromium, gold, indium, ruthenium, tin, platinum, silver, molybdenum, palladium, metal silicides, cobalt, zinc, tungsten, tantalum, titanium, aluminum, and alloys thereof or alloys with copper, or non-metallic conductive materials (e.g., doped silicon). The metal layer 130 may be coated by physical vapor deposition (PVD) at temperatures below 100°C (e.g., below 50°C). In some embodiments, the metal layer 130 may be formed on the upper surface of component 100 by a liquid deposition solution (electroplating) or a suspension (spin-coating). The metal layer may have the microstructure it has at the time of its formation. For example, the metal grains in the metal layer 130 may have an average size in the range of about 2 nm to 100 nm (e.g., the average of the maximum grain size) (e.g., the average size in the range of about 8 nm to 80 nm, or in the range of about 5 nm to 50 nm).

[0047] exist Figure 12In this process, excess metal material of the metal layer 130 above the barrier layer 116, a portion of the barrier layer 116 disposed on top of the second dielectric layer 108, and possibly the top portion of the dielectric layer 108 can be removed to leave a planarized upper surface 118, for example by chemical mechanical polishing (CMP). This planarization process makes the upper surface 118 suitable for direct bonding in hybrid bonding embodiments. After the planarization process, the remaining metal layer 130 is constrained on top of the corresponding conductive features 114a, which are separated from the second dielectric layer 108. The metal layer 130 above the conductive features 114a may be recessed during or after the polishing process to leave recesses 132, such as... Figure 12 As shown. The depth of the recess 132 can be in the range of 5 nm to 100 nm (e.g., 10 nm to 80 nm, 20 nm to 60 nm).

[0048] Move to Figure 13 The element 100 is exposed to an oxidizing environment that oxidizes the metal layer 130 above the conductive feature 114a, transforming at least the upper portion of the metal layer 130 into a metal oxide layer 134. Therefore, each of the metal oxide layers 134 can be connected to the corresponding conductive feature 114a, with the metal layer 130 sandwiched between them. Because this oxidation process relies on diffusion, there may not be a clear boundary between the metal oxide layer 134 and any remaining metal layer 130. In some embodiments, the oxidation process may consume all of the metal layers 130. In this case, there is no metal layer 130 between the metal oxide layer 134 and the conductive feature 114a. The oxidation process can be plasma oxidation (e.g., by exposure to oxygen-containing plasma), thermal oxidation, ozone exposure, or wet oxidation (e.g., by exposure to inorganic or organic peroxides). In the example, Figure 13 The element 100 can undergo an ashing process in which the product of an oxygen-containing plasma is provided to the element. Since the metal oxide layer 134 is transformed by oxidation of the metal layer 130 having an ultrafine-grained microstructure, the metal oxide layer 134 may inherit an ultrafine-grained microstructure, such as nanoparticles. Alternatively, an oxidation process may impart a microstructure. For example, the metal oxide layer 134 may comprise particles having an average size (e.g., the average of the largest particle sizes) in the range of about 2 nm to 100 nm (e.g., an average size in the range of about 8 nm to 80 nm, or in the range of about 5 nm to 50 nm). Both the oxidation process and the final metal oxide layer 134 can be as described regarding... Figure 4 As stated above.

[0049] Similarly, regarding Figure 4The oxidation process may cause the final metal oxide layer 134 to expand in volume and protrude above the upper dielectric surface 118 of the hybrid bonding layer, such as... Figure 13 As shown. Therefore, in Figure 14 In this process, a process (e.g., planarization or wet or dry selective etching) can be applied to recess the metal oxide layer 134 into the cavity of the second dielectric layer 108, from which the metal oxide layer 124 protrudes. After a planarization process (e.g., CMP), the metal oxide layer 134 may be slightly recessed. In other embodiments, the metal oxide layer 134 may remain protruding. The upper surface 118 may undergo activation and / or termination processes, such as nitrogen treatment, to facilitate direct dielectric bonding, as described above.

[0050] refer to Figure 15A Component 100 (first component) via about Figure 5 The bonding method shown in Figure 8 is used to directly bond the first element 100 to the second element 200, forming a bonding structure 1, without intermediate adhesive. The second dielectric layer 108 of the first element 100 can be directly bonded to the dielectric layer 208 of the second element 200 at room temperature.

[0051] refer to Figure 15B Subsequently, the bonding structure 1 can undergo an annealing process at the annealing temperature for a sufficient duration to complete the bonding between conductive feature 114a and conductive feature 214. The bonding between dielectric layers 108 and 208 can also be strengthened during the annealing process. The increased temperature and extended duration of the annealing process may cause the metal material in conductive features 114a and 214 (including the metal in the conductive features below) to expand more than the surrounding dielectric materials 108 and 208, due to the above... Figure 7A The CTE mismatch is being discussed. This expansion may cause the metal oxide layer 134 to be pressed against the conductive layer 214.

[0052] In addition, such as regarding Figure 7A Oxygen in the metal oxide layer 134 can be released and may diffuse into conductive features 114a and 214. Residual metal oxide may also diffuse into conductive features 114a and 214. Depending on the annealing temperature and duration, at the end of the annealing process, each of the conductive features 114a (including metal layer 130 and metal oxide layer 134) may merge to appear as a single identifiable feature, such as... Figure 15B As shown. As mentioned above, the region near the bonding interface may have a higher oxygen content and a higher residual metal oxide content. In some embodiments, if the deposited metal layer 130 and the conductive feature 114a do not contain the same metal, the residual portion of the metal layer 130 after annealing may be identifiable. For example, in relation to Figure 11In the described process, a copper metal layer 130 may be deposited on a conductive feature 114a with different materials.

[0053] Such as about Figure 7A The ultrafine (e.g., nanoparticle) microstructure of the metal oxide layer 134 discussed herein facilitates high-quality hybrid bonding of conductive features at lower annealing temperatures, compared to bonding of two semiconductor elements without such a microstructured metal oxide layer 134.

[0054] refer to Figure 16 In another embodiment, Figure 13 The first element 100 (including a metal oxide layer 134 protruding from its cavity) can be used for hybrid bonding without recessing the metal oxide layer 134. To accommodate the protruding metal oxide layer 134 of the first element 100, the second element 200 may have a recess selectively formed at the conductive feature 214. Therefore, in Figure 16 In the bonding structure 1, the bonding interface between conductive features 114a and 214 is located in the cavity accommodating conductive feature 214 on the side of the second element 200, such as... Figure 16 As shown. Subsequent annealing to complete the bonding of conductive features 114a and 214 may leave residues as described above. Figure 15B The hybrid bonding structure differs in that the bonding interface between conductive features 114a and 214, and the resulting region of higher oxygen concentration, may be shifted to the side of element 200.

[0055] Another example embodiment of the process for forming a metal oxide layer on top of a conductive feature in a microelectronic structure is as follows: Figure 17-18 As shown. The process begins in the state of component 100, including as follows: Figure 10 The recessed conductive feature 114a is shown. For example... Figure 17 As shown, element 100 can be cleaned (e.g., by sputtering), and metal oxide layer 142 can be coated directly onto element 100, including filling recess 128 and coating over barrier layer 116. Metal oxide material 142 can include, for example, copper oxide deposited by high-pressure reactive sputtering. This reactive sputtering process can be performed in an argon (Ar) environment at a pressure of 0.05 Torr to 0.4 Torr to promote collisions between sputtered copper atoms and oxygen, thereby forming a copper oxide layer that may include ultrafine particles (e.g., nanoparticles). Therefore, metal oxide material 142 may include an ultrafine microstructure. The average size of the metal oxide particles (e.g., the average of the maximum particle size) may be in the range of about 2 nm to 100 nm (e.g., an average size in the range of about 8 nm to 80 nm, or in the range of about 5 nm to 50 nm).

[0056] exist Figure 18 In this process, excess metal oxide material layer 142 above barrier layer 116, barrier layer 116 disposed above the upper surface of second dielectric layer 108, and possibly the top portion of dielectric layer 108 can be removed to leave a planarized upper surface 118, for example, by CMP. Upper surface 118 can be sufficiently planarized for direct bonding. After the planarization process, the remaining metal oxide material 142 is metal oxide layer 142a, which is confined within cavities above corresponding conductive features 114a separated by the second dielectric layer 108. After the planarization process, metal oxide layer 142a may be slightly recessed, or subsequent recessing operations may be performed. As described above, the presence of metal oxide layer 142a in the element 100 to be bonded allows for smaller recesses, which in turn promotes uniformity across the substrate and more reliable metal bonding.

[0057] The metal oxide material 142 can be deposited directly onto the conductive feature by other means. For example, the metal oxide material 142 can be formed by spin-coating metal oxide particles onto the upper surface of the conductive feature 114a. As another example, the metal oxide material layer 142 can be formed by electrolytic deposition or chemical vapor deposition (CVD). Figure 18 The element 100 having the metal oxide layer 142a can be activated and / or terminated, and can be directly bonded, particularly by hybrid bonding, to another element, the process following the... Figure 5 As described in -8.

[0058] Each of the above methods may produce different metal oxide grain microstructures in metal oxide layers 124, 134, and 142a. For example, Figure 4 The oxidation process shown results in the growth of metal oxides from the existing upper surface of conductive feature 114a. Therefore, the microstructure of the metal oxide particles in metal oxide layer 124 may possess unique characteristics of the particle formation process. Furthermore, different oxidants, such as in-situ or remote oxygen plasma, thermal oxidation, ozone exposure, wet chemical oxidation, or electrolytic oxidation products, can lead to different and unique properties. If the metal oxide particles are transformed by a coated metal layer 130 including the microstructure, as discussed above... Figure 13 The microstructure of the metal oxide layer 134 may possess unique characteristics of metal deposition and in-situ oxidation processes. If the metal oxide layer is directly deposited (whether by sputtering, spin coating, or other methods) onto the conductive feature 114a to form the metal oxide layer 142a, as... Figure 17-18As shown, the microstructure of the metal oxide layer may exhibit unique characteristics of a specific direct deposition process. Other processes, such as electrolysis or CVD, may also have unique characteristics in the microstructure of the resulting oxide layer. Furthermore, the post-annealing microstructure near the metal-metal interface in bonding structure 1 may carry characteristics indicative of the oxidation process used to form metal oxide layers 124, 134, and 142a.

[0059] Another potential benefit of embodiments of this disclosure may be the decoupling of the sidewalls between the conductive feature 114a and the surrounding second dielectric layer 108. Both the oxidation embodiment and the metal oxide deposition embodiment may expose the sidewalls of the conductive feature 114a and / or the adjacent barrier material 116 to oxygen to varying degrees. (As stated above regarding...) Figure 4 Even slight oxidation of these sidewalls of conductive feature 114a can advantageously decouple or detach conductive feature 114a from the surrounding insulating material. This decoupling facilitates the free expansion of conductive feature 114a relative to the surrounding material during the bonding annealing process, thereby allowing for greater internal pressure for a given recess size, or for a smaller recess size for a given internal pressure. The sidewall decoupling characteristic may also benefit the production of microelectronic devices with conductive features of varying widths in the bonded structure by reducing variations in thermal expansion during the annealing process for conductive features of different sizes, which will be discussed later.

[0060] Furthermore, in each of the methods described above, the microstructure (e.g., grain size) of the metal oxide layer can be controlled by process control parameters. For example, the size or diameter of the metal oxide grains can be fine-tuned by routine experiments with oxidation or deposition conditions.

[0061] Regarding components 100 and 200, both of which are individual device chips, Figure 5 -Figures 8 and 15- Figure 16 The hybrid bonding process shown can represent die-to-die (D2D) hybrid bonding involving metal oxide layers at the bonding interface. Metal oxide layers can also be applied to wafer-to-wafer (W2W) hybrid bonding and die-to-wafer (D2W) hybrid bonding to reduce annealing temperatures.

[0062] Figures 19-21 The diagram illustrates a hybrid bonding process that bonds two wafer elements 300 and 400 together to form a W2W bond structure 2. Figure 19In this design, element 300 is a wafer comprising a plurality of die modules 301, which may be identical to each other. These die modules 301 may also differ from each other, but may be arranged within the first wafer element 300 for subsequent dicing. Each die module 301 includes one or more contact pads 314 (or other conductive features configured to contact other conductive features) embedded in a dielectric layer 308. A metal oxide layer 324 is disposed on each contact pad 314 at a bonding surface of the first wafer element 300. As described above, the metal oxide layer 324 may comprise ultrafine metal oxide particles, such as nanoparticles. Figure 19 A second wafer element 400 is also shown, comprising a plurality of die modules 401, each die module 401 aligned with a corresponding die module 301 of the first wafer element 300. Each of the die modules 401 includes one or more contact pads 414 embedded in a dielectric layer 408. Both of the wafer elements 300 and 400 are sufficiently planarized for direct bonding. One or both of the wafer elements 300 and 400 may be activated and / or terminated for direct bonding, after which the wafer elements 300 and 400 are co-bonded together. In the illustrated embodiment, only the first wafer element 300 has a metal oxide layer 324 provided on its contact pads 314; in other embodiments, such a metal oxide layer may be provided on the contact pads of both wafers.

[0063] refer to Figure 20 The bonding structure 2 of wafer elements 300 and 400 may undergo an annealing process at elevated temperatures for a predetermined time. (See also: Regarding...) Figure 7A During the annealing process, each contact pad 314, 414 may expand due to the CTE mismatch between the metal material of the contact pads 314, 414 and the surrounding dielectric materials 308, 408. Therefore, the contact pads 314, 414 fuse with the metal oxide layer 324 sandwiched therebetween. The microstructure of the metal oxide layer 324, including ultrafine particles, can significantly reduce the annealing temperature and facilitate interdiffusion and necking between the contact pads 314, 414, as described above. The fusion between the metal oxide layer 324 on the contact pad 314 and the contact pad 414 may create a continuous bonding region 230, such as... Figure 7BAs shown. During the annealing process, metal oxides or free oxygen from the metal oxide layer 324 can diffuse through the surrounding material, allowing the final bonded contact pads 314, 414 to have a relatively high oxygen content as described above. Compared to the absence of the metal oxide layer 324, the metal oxide layer 324 facilitates lower annealing temperatures and more free thermal expansion. Therefore, good bonding quality and electrical connection between the contact pads 314 of the first wafer element 300 and the contact pads 414 of the second wafer element 400 can be established at low bonding temperatures. Depending on the annealing conditions and the method of forming the metal oxide layer 324, the residual microstructure characteristics of the metal oxide layer 324 may or may not be retained in the bonding structure 2 after annealing.

[0064] like Figure 21 As shown, the top surface of the W2W bond structure 2 can be coated with a protective layer 440. Subsequently, the bond structure 2 can be cut (e.g., by laser, saw blade, or plasma cutting) to separate multiple bond modules 3. The sidewalls of the individual modules 301, 401 within each bond module 3 can be flush with each other because they are formed through a common cutting process. Figure 21 During the cutting process, the bonding structure 2 may be supported by the dicing membrane 350.

[0065] Figures 22-26 The diagram illustrates a hybrid bonding process for D2W bonding, where the die is bonded to the wafer. (Reference) Figure 22 The wafer element 500 includes multiple die modules, which may be identical or different from each other, but can be arranged for subsequent dicing of bonding structure layers. Each die module may include one or more contact pads 514 (or other conductive features) embedded in the dielectric layer 508 and may be recessed relative to the dielectric layer 508 as disclosed herein. Figure 22 As shown, the wafer element 500 is supported by a dicing film 550 and coated with a protective layer 540. Subsequently, the wafer element 500 is diced (e.g., by mechanical dicing, laser dicing, or plasma dicing) to separate the die modules and form a plurality of dies 501. At this time, the dies 501 are supported by the dicing film 550, maintaining their original lateral positions relative to each other. In some embodiments, the upper surface 518 of the wafer element 500 may be activated before coating the protective layer 540. In some embodiments, the upper surface 518 of the wafer element 500 may not be activated before the coating process.

[0066] exist Figure 23In the process, the protective layer 540 is peeled off, exposing the upper bonding surface 518 of each separated die 501. The dies 501 set on the dicing film 550 can be cleaned in preparation for subsequent processes. Note that individual die modules may have been tested using the probe pads of the wafer element 500 before dicing, or may have been tested after dicing and removal of the protective layer 540, and only known qualified dies (KGD) are used in subsequent bonding.

[0067] exist Figure 24 In this process, multiple dies 501 mounted on a dicing membrane 550 may undergo an activation process to activate the upper surface 518 of each die 501 (if the upper surface has not been activated before). The activation process may include exposing the multiple dies 501 to the products of a plasma 562 (e.g., remote or in-situ oxygen- and / or nitrogen-containing plasma) for a period of time in a processing chamber 560. Subsequently, the dies 501 may be rinsed and dried.

[0068] exist Figure 25 In this configuration, multiple dies 501 can be individually picked up and placed onto corresponding die modules 601 of wafer element 600 to form a bonded, D2W bonded structure 4. Alternatively, dies 501 can be mounted to a carrier and placed on wafer element 600 in a “group” manner, wherein each die 501 is aligned with each die module 601. In this case, the dielectric layer 508 of each die 501 is bonded to the dielectric layer 608 of the corresponding die module 601 in wafer element 600, which dielectric layer 608 can be prepared for bonding, such as by sufficiently planarizing as described herein. In some embodiments, the bonding surface of the dielectric layer 508 is activated; in other embodiments, both the die 501 and the die module 601 are activated. Each die module 601 of element 600 includes one or more contact pads 614 embedded in the dielectric layer 608. Figure 19 As described in the first wafer element 300, a microstructured metal oxide layer 624 is disposed on each contact pad 614 at the bonding surface of the die module 601 (e.g., formed selectively by oxidation for hybrid bonding). The metal oxide layer 624 may include ultrafine metal oxide particles (e.g., nanoparticles). Initial bonding of the die 501 to the wafer element 600 can be performed at room temperature, and the aligned contact pads 514, 614 and the intermediate metal oxide layer 624 disposed therebetween may have gaps between them at this stage. If gaps exist, they may be relatively small, given that the metal oxide layer 624 facilitates uniform and reliable metal bonding across the wafer 600 at relatively low temperatures (compared to processes without the metal oxide layer 624).

[0069] refer to Figure 26The D2W bonding structure 4, including die 501 and wafer element 600, undergoes high-temperature annealing. (See also: Regarding...) Figure 7A Figure 15 and Figure 20 During the annealing process, each contact pad 514, 614 can expand due to the mismatch in the coefficients of thermal expansion between the metal material of the contact pads 514, 614 (and the conductive features) and the surrounding dielectric materials 508, 608. Therefore, contact pad 614 is pressed against and fused with the corresponding contact pad 514, with a metal oxide layer 624 sandwiched between them. As described above, this metal oxide layer 624 can have an ultrafine-grained (e.g., nanoparticle) microstructure, which can significantly reduce the annealing temperature for metal-to-metal bonding and promote interdiffusion across the interface and eventual necking, as described above. The fusion between the metal oxide layer 624 on the contact pad 614 and the contact pad 514 can create a continuous bonding region, as described above. Figure 7B As discussed above, a good bond and electrical connection can be established between the contact pads 614 of wafer element 600 and the contact pads 514 of die 501. As described above, when at least one of wafer element 600 and wafer element 500 (e.g., die module 501) includes a metal oxide layer in each corresponding contact pad 514 or 614, the annealing temperature can be significantly reduced. During the annealing process, metal oxide or free oxygen from the metal oxide layer 624 can diffuse through the surrounding material, allowing the finally bonded contact pads 514, 614 to have a relatively high oxygen content (e.g., oxygen saturation or supersaturation), as described above. Compared to the absence of the metal oxide layer 624, the metal oxide layer 624 facilitates a lower annealing temperature and allows for freer thermal expansion. Depending on the annealing conditions and the method of forming the metal oxide layer 624, the residual microstructure features of the metal oxide layer 624 may or may not be retained in the bonding structure 4 after annealing.

[0070] Subsequently, the bonding structure 4 can be cut, for example by mechanical cutting, laser cutting, or plasma cutting, to separate it into multiple bonding modules. Each module includes a die 501 and a die from the separated die module 601, which are then bonded together by a hybrid bonding process. Each cut bonding module can be equivalent to... Figure 7A The D2D bonding structure 1 shown may vary, especially if the gaps between the dies 501 are filled before cutting.

[0071] Although examples of semiconductor dies and wafers are shown and discussed, those skilled in the art will understand that metal oxides can be provided in hybrid bonding layers for contact pads of other types of microelectronic components. Such microelectronic components may include, for example, interposers, semiconductor packages, flat panels, dielectric substrates, surface mount devices, passive devices, MEMS devices, etc.

[0072] The decoupling sidewall (e.g., gap formation) characteristics between conductive features and surrounding insulating material may facilitate the formation of conductive features of varying widths across the bonding interface in bonded structures without sacrificing the uniformity of the metal bonding across the substrate. Figure 27 In the bonding structure 5, two elements 700 are included, each comprising two columns of conductive features A and B. For example... Figure 27 As shown, on the upper right side, the width D of the first conductive feature 714A is... A Width D greater than the second conductive feature 714B B And similar to the corresponding conductive features of the upper element 700. At least one of the elements 700 includes a metal oxide layer (not shown) above the conductive features 714A, 714B prior to hybrid bonding. Due to the microstructure disclosed herein in the metal oxide layer above the conductive features 714A, 714B, and the resulting decoupling of the conductive feature sidewalls from the surrounding insulating material 708, the width D of the conductive feature is... A and D B They can be significantly different from each other without sacrificing the uniformity of the metal bonding across the substrate. For example... Figure 27 As shown, D A >D B .

[0073] refer to Figure 28 The bonding structure 6 includes structures with significantly different widths D. C D D and D E The conductive features C, D, and E. When each of the conductive features 764C, 764D, and 764E includes a metal oxide layer (not shown) at the hybrid bonding interface, the width D C D D and D E They can be significantly different from each other without sacrificing the uniformity of the metal bonding across the substrate. For example... Figure 28 As shown, D C >D D >D E .

[0074] The various embodiments disclosed herein relate to direct-bonding structures in which two or more elements can be directly bonded together without an intermediate adhesive. This process and structure are referred to herein as a “direct-bonding” process or a “directly bonded” structure. Direct bonding can involve bonding one material on one element to another material on another element (also referred to herein as “uniform” direct bonding), where the materials on the different elements need not be the same, and conventional adhesives are not used. Direct bonding can also involve bonding multiple materials on one element to multiple materials on another element (e.g., hybrid bonding).

[0075] In some implementations (not shown), each bonding layer has one material. In these uniform direct bonding processes, only one material is directly bonded to each component. Examples of uniform direct bonding processes include ZIBOND, commercially available from Adeia of San Jose, CA. ® The materials of the opposing bonding layers on different components can be the same or different, and can include elemental or compound materials. For example, in some embodiments, non-conductive bonding layers can be deposited over an entire portion of a substrate without patterning with conductive features (e.g., pads). In other embodiments, bonding layers can be patterned on one or two components and can be the same or different from each other, but a material from each component is directly bonded across the surface of the component without adhesive (or, if the component sizes are different, the bonding spans the surface of the smaller component). In another embodiment of uniform direct bonding, one or two non-conductive bonding layers may include one or more conductive features, but these conductive features are not involved in the bonding. For example, in some embodiments, opposing non-conductive bonding layers can be uniformly and directly bonded to each other, and a substrate can be formed through one component after bonding via substrate vias to provide electrical communication with another component.

[0076] In various embodiments, bonding layers 808a and / or 808b may comprise non-conductive materials, such as dielectric materials or undoped semiconductor materials, such as undoped silicon, which may comprise native oxides. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectric materials, such as silicon oxide, silicon nitride, or silicon oxynitride, or may comprise carbon, such as silicon carbide, silicon oxycarbonitride, low-k dielectric materials, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon, or materials comprising diamond surfaces. Such carbon-containing ceramic materials, although comprising carbon, may be considered inorganic materials. In some embodiments, the dielectric material at the bonding surface does not comprise polymeric materials, such as epoxy resins (e.g., epoxy adhesives, cured epoxy resins, or epoxy composites, such as FR-4 materials), resins, or molding materials.

[0077] In other embodiments, the bonding layer may include a conductive material, such as a deposited conductive oxide material, for example, indium tin oxide, as disclosed in U.S. Provisional Patent Application No. 63 / 524,564 (filed June 30, 2023), the entire contents of which are incorporated herein by reference to provide examples of conductive bonding layers that do not have interface short-circuit contacts.

[0078] In direct bonding, the first and second elements can be directly bonded to each other without adhesive, unlike deposition processes, and produce interfaces that are structurally different from those produced by deposition. In one application, the width of the first element in the bonded structure is similar to the width of the second element. In other embodiments, the width of the first element in the bonded structure differs from the width of the second element. The width or area of ​​the larger element in the bonded structure can be at least 10% larger than the width or area of ​​the smaller element. Furthermore, the interface between direct-bonded structures, unlike the interface beneath the deposited layer, can include defect regions containing nanoscale voids (nanopores). These nanopores may be formed due to the activation of one or both bonding surfaces (e.g., exposure to plasma, as described below).

[0079] The bonding interface between non-conductive bonded surfaces may include a higher concentration of material from activation and / or final chemical processing compared to the bulk material of the bonded layer. For example, in embodiments using nitrogen plasma for activation, a nitrogen concentration peak may be formed at the bonding interface. In some embodiments, this nitrogen concentration peak may be detected using secondary ion mass spectrometry. In various embodiments, for example, nitrogen termination treatment (e.g., exposing the bonded surfaces to nitrogen-containing plasma) may replace the OH groups of the hydrolyzed (OH-terminated) surface with NH2 molecules to create a nitrogen-terminated surface. In embodiments using oxygen plasma for activation, an oxygen concentration peak may be formed at the bonding interface between non-conductive bonded surfaces. In some embodiments, the bonding interface may include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. Direct bonding may include covalent bonds with a strength higher than van der Waals bonds. The bonded layer may also include surfaces polished to a high smoothness.

[0080] In direct bonding processes, such as homogeneous direct bonding and hybrid bonding, two components are bonded together without an intermediate binder. In indirect bonding processes that utilize binders, an intermediate material is typically applied to one or both components to facilitate a physical bond between them. For example, in some binder-based processes, a flowable binder (e.g., organic binders, such as epoxy resins, which may include conductive filler materials) can be applied to one or both components and cured to form a physical (rather than chemical or covalent) bond between the components. Typical organic binders lack strong chemical or covalent bonds with either component. In such processes, the bond between components is weak and / or easily reversed, such as by reheating or removing the flux.

[0081] In contrast, direct bonding processes join two elements by forming strong chemical bonds (e.g., covalent bonds) between opposing nonconductive materials. For example, in a direct bonding process between nonconductive materials, one or both nonconductive surfaces of the two elements are planarized and chemically prepared (e.g., activated and / or terminated) such that strong chemical bonds (e.g., covalent bonds) are formed when the elements come into contact, with a strength higher than van der Waals or hydrogen bonds. In some embodiments (e.g., between opposing dielectric surfaces, such as opposing silicon oxide surfaces), the chemical bonds can occur spontaneously upon contact at room temperature. In some embodiments, the chemical bonds between opposing nonconductive materials can be strengthened after annealing the elements.

[0082] As previously mentioned, hybrid bonding is a type of direct bonding in which non-conductive features are directly bonded to each other, and conductive features are directly bonded to conductive features of the components to be bonded. The non-conductive bonding materials and interfaces can be as described above, while the conductive bond can be formed, for example, as a direct metal-to-metal connection. In conventional metal bonding processes, a fusible metal alloy (e.g., solder) can be provided between the conductors of two components, heated to melt the alloy, and then cooled to form a connection between the two components. The resulting bond typically exposes a clear interface with the conductors from both components and can be reversed by reheating. In contrast, the direct metal bonding employed in hybrid bonding does not require melting or an intermediate fusible metal alloy and can result in strong mechanical and electrical connections, typically exhibiting interdiffusion of the conductive features of the bond and grain growth across the bonding interface between components, even without the much higher temperatures and pressures of thermocompression bonding.

[0083] Figure 29 and Figure 30 The diagram schematically illustrates cross-sectional side views of the first element 802 and the second element 804, respectively, before and after the process for forming a direct-bonded structure (and more specifically, a hybrid-bonded structure), according to some embodiments. Figure 30In the hybrid bonding structure 800, a first element 802 and a second element 804 are directly bonded to each other at a bonding interface 818 without intermediate adhesive. A conductive feature 806a of the first element 802 can be electrically connected to a corresponding conductive feature 806b of the second element 804. In the hybrid bonding structure 800 shown, conductive features 806a are directly bonded to corresponding conductive features 806b without intermediate solder or conductive adhesive.

[0084] In the illustrated embodiment, conductive features 806a and 806b are respectively embedded as part of the first bonding layer 808a of the first element 802 and the second bonding layer 808b of the second element 804, and can be considered as part of the first bonding layer 808a of the first element 802 and the second bonding layer 808b of the second element 804. The field regions of the bonding layers 808a and 808b extend between and partially or completely surround the conductive features 806a and 806b. The bonding layers 808a and 808b may include non-conductive material layers suitable for direct bonding, as described above, and the field regions are directly bonded to each other without adhesive. The non-conductive bonding layers 808a and 808b may be disposed on the respective front sides 814a and 814b of the substrate portions 810a and 810b.

[0085] First element 802 and second element 804 may include microelectronic components, such as semiconductor elements, including, for example, integrated device dies, wafers, passive devices, discrete active devices (such as power switches), MEMS, etc. In some embodiments, the substrate portion may include device portions, such as bulk semiconductor (e.g., silicon) portions of elements 802, 804, and back-end process (BEOL) interconnect layers above such semiconductor portions. Bonding layers 808a, 808b may be provided during device manufacturing as part of such BEOL layers, as part of redistribution layers (RDLs), or as specific bonding layers added to existing devices, wherein bonding pads extend from underlying contacts. Active devices and / or circuitry may be patterned and / or otherwise disposed in or on substrate portions 810a, 810b, and may be in electrical communication with at least some of conductive features 806a, 806b. Active devices and / or circuitry may be disposed at or near substrate portions 810a, 814b, and / or at or near the opposite back sides 816a, 816b of substrate portions 810a, 810b. In other embodiments, substrate portions 810a, 810b may not include active circuitry, but may include dummy substrates, passive intermediaries, passive optical elements (e.g., glass substrates, gratings, lenses), etc. Bonding layers 808a, 808b are shown as being provided on the front side of the element, but similar bonding layers may be additionally or alternatively provided on the back side of the element.

[0086] In some embodiments, substrate portions 810a and 810b may have significantly different coefficients of thermal expansion (CTE), and bonding elements including such different substrate portions can form heterogeneous bonding structures. The CTE difference between substrate portions 810a and 810b, particularly between the bulk semiconductor (typically single-crystal) portions of substrate portions 810a and 810b, can be greater than 5 ppm / ℃ or greater than 10 ppm / ℃. For example, the CTE difference between substrate portions 810a and 810b can be in the range of 5 ppm / ℃ to 100 ppm / ℃, 5 ppm / ℃ to 40 ppm / ℃, 10 ppm / ℃ to 100 ppm / ℃, or 10 ppm / ℃ to 40 ppm / ℃.

[0087] In some embodiments, one of the substrate portions 810a and 810b may include a photoelectric single-crystal material for optical piezoelectric or pyroelectric applications, including perovskite materials, and the other of the substrate portions 810a and 810b may include a more conventional substrate material. For example, one of the substrate portions 810a and 810b may include lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and the other of the substrate portions 810a and 810b may include silicon (Si), quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the substrate portions 810a and 810b may include a group III-V single semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other of the substrate portions 810a and 810b may include a non-group III-V semiconductor material, such as silicon (Si), or may include other materials with similar CTE, such as quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the substrate portions 810a and 810b includes a semiconductor material, while the other of the substrate portions 810a and 810b includes an encapsulation material, such as a glass, organic, or ceramic substrate.

[0088] In some arrangements, the first element 802 may include a monolithic element, such as a monolithic integrated device die. In other arrangements, the first element 802 may include a carrier or substrate (e.g., a semiconductor wafer) comprising multiple (e.g., tens, hundreds, or more) device regions that, when diced, form multiple integrated device dies, although in other embodiments, such a carrier may be a package substrate or a passive or active intermediary. Similarly, the second element 804 may include a monolithic element, such as a monolithic integrated device die. In other arrangements, the second element 804 may include a carrier or substrate (e.g., a semiconductor wafer). Therefore, the embodiments disclosed herein are applicable to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a W2W process, two or more wafers may be directly bonded to each other (e.g., direct hybrid bonding) and diced using a suitable dicing process. After cutting, the side edges of the cut structure (e.g., the side edges of two bonding elements) may be substantially flush (xy dimensions substantially aligned) and / or the bonding interface edges of the bonding and cut elements may be co-extended and may include markings indicating the common cutting process used for the bonding structure (e.g., sawing markings if a sawing process is used).

[0089] Although only two elements 802 and 804 are shown, any suitable number of elements can be stacked in the bonding structure 800. For example, a third element (not shown) can be stacked on the second element 804, a fourth element (not shown) can be stacked on the third element, and so on. In this embodiment, substrate vias (TSVs) can be formed to provide vertical electrical communication between and / or among the vertically stacked elements. Additionally or alternatively, one or more additional elements (not shown) can be stacked adjacent to each other laterally along the first element 802. In some embodiments, the laterally stacked additional elements may be smaller than the second element. In some embodiments, the bonding structure can be encapsulated with an insulating material, such as an inorganic dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). One or more insulating layers can be provided on the bonding structure. For example, in some embodiments, a first insulating layer can be conformally deposited on the bonding structure, and a second insulating layer (which may include the same material as the first insulating layer or a different material) can be provided on the first insulating layer.

[0090] To facilitate direct bonding between bonding layers 808a and 808b, the bonding layers 808a and 808b can be prepared for direct bonding. Non-conductive bonding surfaces 812a and 812b on the upper or outer surfaces of the bonding layers 808a and 808b can be prepared for direct bonding by polishing (e.g., by chemical mechanical polishing (CMP)). The roughness of the polished bonding surfaces 812a and 812b can be less than 30 Å rms. For example, the roughness of the bonding surfaces 812a and 812b can be in the range of approximately 0.1 Å rms to 15 Å rms, 0.5 Å rms to 10 Å rms, or 1 Å rms to 5 Å rms. Polishing can also be tuned to cause the conductive features 806a and 806b to be recessed relative to the field regions of the bonding layers 808a and 808b.

[0091] Preparation for direct bonding may further include cleaning one or both of the bonding surfaces 812a, 812b and exposing them to plasma and / or an etchant to activate at least one of the surfaces 812a, 812b. In some embodiments, one or both of the surfaces 812a, 812b may be terminated with a substance after activation or during activation (e.g., during plasma and / or etching processes). Without being limited to theory, in some embodiments, the activation process may be performed to break the chemical bonds at the bonding surfaces(s) 812a, 812b, and the termination process may provide additional chemicals at the bonding surfaces(s) 812a, 812b that alter the chemical bonds and / or improve the bonding energy during direct bonding. In some embodiments, activation and termination are provided in the same step, for example, using plasma to activate and terminate the surfaces(s) 812a, 812b. In other embodiments, one or both of the bonding surfaces 812a, 812b may be terminated in a separate treatment to provide additional substances for direct bonding. In various embodiments, the terminating substance may include nitrogen. For example, in some embodiments, the bonding surfaces (multiple) 812a, 812b may be exposed to nitrogen-containing plasma. Depending on the material of the bonding surfaces 812a, 812b, other terminating substances may be suitable for improving the bonding energy. Furthermore, in some embodiments, the bonding surfaces (multiple) 812a, 812b may be exposed to fluorine. For example, one or more fluorine concentration peaks may be present at or near the bonding interface 818 between the first element 802 and the second element 804. Typically, fluorine concentration peaks appear at the interfaces between material layers. Additional examples of activation and / or termination treatments can be found in U.S. Patent No. 9,391,143, column 5, lines 55 through 7, line 3; column 8, lines 52 through 9, lines 45; column 10, lines 24-36; column 11, lines 24-32, 42-47, 52-55, and 60-64; column 12, lines 3-14, 31-33, and 55-67; ​​column 14, lines 38-40 and 44-50; and U.S. Patent No. 10,434,749, column 4, lines 41-50; column 5, lines 7-22, 39, and 55-61; column 8, lines 25-31, 35-40, and 49-56; and column 12, lines 46-61, the teachings of which are incorporated herein by reference.

[0092] Therefore, in the direct-bonded structure 800, the bonding interface 818 between the two non-conductive materials (e.g., bonding layers 808a, 808b) may include a very smooth interface with a high nitrogen (or other terminating substance) content and / or a fluorine concentration peak at the bonding interface 818. In some embodiments, the nitrogen and / or fluorine concentration peaks can be detected using various types of detection techniques, such as SIMS techniques. The polished bonding surfaces 812a and 812b may be slightly rougher after the activation process (e.g., approximately 1 Å rms to 30 Å rms, 3 Å rms to 20 Å rms, or possibly rougher). In some embodiments, activation and / or termination may result in a slightly smoother surface prior to bonding, such as in cases where plasma treatment preferably erodes high points on the bonding surface.

[0093] Non-conductive bonding layers 808a and 808b can be directly bonded to each other without the use of adhesives. In some embodiments, elements 802 and 804 are bonded together at room temperature without the application of voltage or external pressure or force other than that used to initiate contact between the two elements 802 and 804. Contact alone can result in direct bonding (e.g., covalent dielectric bonding) between the non-conductive surfaces of bonding layers 808a and 808b. Subsequent annealing of the bonding structure 800 can result in direct bonding of conductive features 806a and 806b.

[0094] In some embodiments, prior to direct bonding, conductive features 806a and 806b are recessed relative to the surrounding field region, such that after dielectric bonding and before annealing, the total gap between opposing contacts is less than 15 nm or less than 10 nm. Because the recess depth for conductive features 806a and 806b may vary on each element due to process variations, the gap may represent the maximum or average gap between corresponding conductive features 806a and 806b of the two bonded elements (before annealing). After annealing, conductive features 806a and 806b may expand and contact each other to form a metal-to-metal direct bond.

[0095] During annealing, the conductive features 806a, 806b (e.g., metallic materials) can expand, while the direct bonding between the surrounding non-conductive materials of the bonding layers 808a, 808b resists element separation, causing thermal expansion to increase the internal contact pressure between the opposing conductive features. Annealing may also cause metal grains to grow at the bonding interface, allowing grains from one element to migrate across the bonding interface at least partially into the other element, and vice versa. Therefore, in some hybrid bonding embodiments, the opposing conductive materials are joined at a temperature not exceeding the melting temperature of the conductive materials, allowing the bonding to be formed at a lower annealing temperature compared to welding or hot-press bonding.

[0096] In various embodiments, conductive features 806a, 806b may include discrete pads, contacts, electrodes, or traces, which are at least partially embedded in non-conductive field regions of bonding layers 808a, 808b. In some embodiments, conductive features 806a, 806b may include exposed contact surfaces of TSVs (e.g., via silicon vias).

[0097] As described above, in some embodiments, in Figure 29 In elements 802 and 804, prior to direct bonding, portions of the corresponding conductive features 806a and 806b can be recessed below the non-conductive bonding surfaces 812a and 812b. For example, the recesses may be less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, e.g., in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. Due to process variations, both the dielectric thickness and the conductor recess depth may vary on the element. Therefore, the aforementioned recess depth range can be applied to individual conductive features 806a and 806b, or to the average recess depth relative to a local non-conductive field region. Even for individual conductive features 806a and 806b, the vertical recess may vary on the feature, and therefore can be measured at or near the lateral midpoint or center of the cavity forming a given conductive feature 806a or 806b, or at the side of the cavity.

[0098] Advantageously, hybrid bonding techniques (such as direct bonding interconnects, or DBI) can be used. ® This technology, commercially available from Adeia of San Jose, CA, enables high-density connections (e.g., for small or fine pitches in regular arrays) between conductive features 806a and 806b across a direct bonding interface 818.

[0099] In some embodiments, the pitch p of conductive features 806a, 806b (such as conductive traces embedded in the bonding surface of one of the bonding elements) may be less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm, less than 2 μm, or even less than 1 μm. For some applications, the ratio of the pitch of conductive features 806a and 806b to one of the lateral dimensions (e.g., diameter) of the bonding pad is less than 20, or less than 10, or less than 5, or less than 3, and sometimes less than 2 is desirable. In various embodiments, conductive features 806a and 806b and / or traces may comprise copper or copper alloys, although other metals may be suitable, such as nickel, aluminum, or alloys thereof. The conductive features disclosed herein, such as conductive features 806a and 806b, may comprise fine-grained metals (e.g., fine-grained copper). In addition, the main lateral dimensions (such as pad diameter) can also be small, for example, in the range of approximately 0.25 μm to 30 μm, in the range of approximately 0.25 μm to 5 μm, or in the range of approximately 0.5 μm to 5 μm. For the hybrid bonded elements 802 and 804 shown in the figure, the orientations of one or more of the conductive features 806a and 806b from the opposing elements may be opposite to each other. As is known in the art, conductive features can typically be formed with nearly vertical sidewalls, particularly when the conductor sidewalls are defined by directional reactive ion etching (RIE) by directly etching the conductive material or indirectly etching the surrounding insulator using an damascene process. However, some slight taper may be present in the conductor sidewalls, where the conductor becomes narrower away from the surface initially exposed to the etch. The taper may be more pronounced when the conductive sidewalls are defined directly or indirectly by isotropic wet etching or by dry etching. In the illustrated embodiment, at least one conductive feature 806b (and / or at least one internal conductive feature, such as a BEOL feature) in the bonding layer 808b of the upper element 804 may taper or narrow upwards (away from the bonding surface 812b). In contrast, at least one conductive feature 806a (and / or at least one internal conductive feature, such as a BEOL feature) in the bonding layer 808a of the lower element 802 may taper or narrow downwards (away from the bonding surface 812a). Similarly, any bonding layers (not shown) on the back sides 816a, 816b of elements 802, 804 may taper or narrow away from the back side, having a relative taper orientation relative to the front conductive features 806a, 806b of the same element.

[0100] As described above, during the annealing stage of the mixed bonding, conductive features 806a and 806b can expand and contact each other to form a direct metal-to-metal bond. In some embodiments, the materials of conductive features 806a and 806b of opposite elements 802 and 804 can diffuse into each other during the annealing process. In some embodiments, metal grains grow across the bonding interface 818. In some embodiments, the metal is copper or includes copper, and its grains can be oriented along the 111 crystal plane to improve copper diffusion at the bonding interface 818. In some embodiments, conductive features 806a and 806b can include a nanotwinned copper grain structure, which facilitates the merging of conductive features during annealing. At or near the bonded conductive features 806a and 806b, there is substantially no gap between the non-conductive bonding layers 808a and 808b. In some embodiments, a barrier layer can be provided below and / or laterally surround the conductive features 806a and 806b (e.g., possibly including copper). However, in other embodiments, there may be no barrier layer beneath conductive features 806a and 806b.

[0101] In one aspect of this disclosure, a hybrid bonding process includes providing a first element and a second element, and bonding the first element to the second element. The first element includes a first dielectric material having a first bonding surface, a first conductive feature at least partially embedded in the first dielectric material, and a metal oxide layer formed on the first conductive feature and exposed at the first bonding surface. The second element includes a second dielectric material having a second bonding surface, and a second conductive feature at least partially embedded in the second dielectric material. The process of bonding the first element to the second element includes directly bonding the first dielectric material to the second dielectric material, provided that a metal oxide layer exists between the first and second conductive features.

[0102] In some embodiments, the first dielectric material is directly bonded to the second dielectric material at room temperature.

[0103] In some embodiments, the process for hybrid bonding further includes annealing the first element and the second element at an annealing temperature to directly bond the first conductive feature to the second conductive feature. In some embodiments, the metal oxide is copper, and the annealing temperature is below approximately 250°C. In some embodiments, the first conductive feature includes one or more of copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, and titanium, and the second conductive feature includes one or more of copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, and titanium.

[0104] In another aspect of this disclosure, the microelectronic structure for low-temperature hybrid bonding includes a first bonding layer having a first upper surface prepared for hybrid bonding. The first bonding layer includes a first conductive feature having a metal oxide layer disposed thereon, and the metal oxide layer being exposed at the first upper surface. A first dielectric material surrounds the first conductive feature, wherein the first dielectric material is exposed at the first upper surface.

[0105] In some embodiments, the first conductive feature includes one or more of copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, and titanium.

[0106] In some embodiments, the first conductive feature is at least partially separated from the surrounding dielectric material, wherein the separation is at least partially achieved by the provided metal oxide.

[0107] In some embodiments, the metal oxide layer comprises copper oxide. The metal oxide layer has a thickness of at least about 20 nm. Furthermore, the first upper surface formed by the metal oxide layer has a surface roughness of at least 2 nm RMS.

[0108] In some embodiments, the oxide layer comprises nanoparticles. The nanoparticles have an average maximum size in the range of approximately 2 nm to 100 nm.

[0109] In some embodiments, the metal oxide layer is formed by oxidizing the metal of the first conductive characteristic. This oxidation is plasma oxidation, thermal oxidation, ozone exposure, or wet oxidation using inorganic or organic peroxides.

[0110] In another aspect of this disclosure, the bonding structure includes a first element and a second element, wherein the first element is directly bonded to the second element. The first element includes a first bonding layer. The first bonding layer includes a first dielectric material having a first upper surface, and a first conductive feature at least partially embedded in the first dielectric material at the upper surface. The second element includes a second bonding layer. The second bonding layer includes a second dielectric material having a second upper surface, and a second conductive feature at least partially embedded in the second dielectric material at the second upper surface. The direct bonding of the first and second elements includes directly bonding the first upper surface to the second upper surface at a bonding interface, wherein the first conductive feature is directly bonded to the second conductive feature to form a bonding contact, and the bonding contact has an oxygen content greater than 100 ppm in the metal (e.g., copper) within approximately 100 nm of the bonding interface.

[0111] In some embodiments, the second conductive feature includes one or more of copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, and titanium.

[0112] In some embodiments, within a 100 nm range at the bonding interface, the oxygen content is greater than the oxygen saturation level in the first conductive feature and / or the second conductive feature. In some embodiments, the oxygen content in the bonding contact includes oxygen from the metal oxide formed from the metal of the first conductive feature.

[0113] In another aspect of this disclosure, a process for fabricating a first element for direct hybrid bonding to a second element includes providing a metal oxide layer forming an upper portion of a first conductive feature of the first element, and fabricating and preparing a first bonding surface of the first bonding layer for direct hybrid bonding. The first conductive feature is embedded in a first dielectric material, wherein the first conductive feature and the first dielectric material form the first bonding layer of the first element, and the metal oxide layer of the first conductive feature is exposed at the first bonding surface.

[0114] In some embodiments, the metal oxide layer comprises an oxide of the metal of the first conductive feature. In some embodiments, the first conductive feature comprises a metal. Furthermore, the metal of the first conductive feature and the metal in the metal oxide layer may be copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, or titanium.

[0115] In some embodiments, the metal oxide layer comprises nanoparticles. The nanoparticles have an average maximum size in the range of approximately 2 nm to 100 nm.

[0116] In some embodiments, the process for fabricating the first element for direct hybrid bonding to the second element further includes forming a recess in the first conductive feature relative to the upper surface of the first bonding layer before providing a metal oxide layer over the first conductive feature. The recess is in the range of approximately 10 nm to 50 nm relative to the upper surface.

[0117] In some embodiments, providing a metal oxide layer over a first conductive feature includes depositing a conductive material layer over the first conductive feature and oxidizing the conductive material layer. In some embodiments, providing a metal oxide layer includes oxidizing the material of the first conductive feature. In some embodiments, oxidizing the material of the first conductive feature includes the product of exposing the first element to oxygen plasma. In some embodiments, oxidizing the material of the first conductive feature includes thermal oxidation. In some embodiments, oxidizing the material of the first conductive feature includes wet oxidation. In some embodiments, providing a metal oxide layer includes sputtering a metal oxide layer onto the first conductive feature and a first dielectric material.

[0118] In some embodiments, preparing the first bonding surface includes planarizing the first bonding surface. Preparing the first bonding surface also includes activating the surface of the first dielectric material.

[0119] In another aspect of this disclosure, a microelectronic device includes a substrate, a first hybrid bonding layer disposed on the substrate, wherein the first hybrid bonding layer has a bonding surface, a dielectric material forming a portion of the first hybrid bonding layer, and at least one first conductive feature embedded in the dielectric material. The at least one first conductive feature is exposed at the bonding surface, and the at least one first conductive feature has an oxide portion at the bonding surface.

[0120] In some embodiments, the oxide portion comprises nanoparticles.

[0121] In some embodiments, the substrate includes silicon, an intermediary, a semiconductor package, a flat panel, or a dielectric substrate.

[0122] Unless the context explicitly requires otherwise, throughout the description and claims, the terms “comprise,” “comprising,” “include,” and “including” should be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense; that is, meaning “including but not limited to.” The term “coupled” as commonly used herein refers to two or more elements that can be directly connected or connected through one or more intermediate elements. Similarly, the term “connected” as commonly used herein refers to two or more elements that can be directly connected or connected through one or more intermediate elements. Furthermore, the terms “this document,” “above,” “below,” and similar terms used herein refer to the entire application, not a specific part thereof. Additionally, as used herein, when describing a first element “on” or “above” a second element, the first element may be directly on or above the second element such that the first and second elements are in direct contact, or the first element may be indirectly on or above the second element such that one or more elements are located between the first and second elements. Where the context allows, words used in the above detailed description in singular or plural form may also include plural or singular forms respectively. Regarding the word "or" in a list of two or more items, it encompasses all of the following interpretations: any item in the list, all items in the list, and any combination of items in the list.

[0123] Furthermore, the conditional language used herein, such as “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as,” etc., unless expressly stated otherwise or understood otherwise in the context used, is generally intended to convey that certain embodiments include certain features, elements, and / or states that are not included in other embodiments. Therefore, such conditional language is not generally intended to imply that features, elements, and / or states are required in any way for one or more embodiments.

[0124] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel apparatuses, methods, and systems described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the methods and systems described herein without departing from the spirit of this disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks can be implemented in a variety of different ways. Any suitable combination of elements and actions of the various embodiments described above can be combined to provide further embodiments. The appended claims and their equivalents are intended to cover such forms or modifications falling within the scope and spirit of this disclosure.

Claims

1. A method for hybrid bonding, comprising: A first element is provided, the first element comprising a first dielectric material having a first bonding surface, a first conductive feature at least partially embedded in the first dielectric material, and a metal oxide layer formed on the first conductive feature and exposed at the first bonding surface; A second element is provided, the second element comprising a second dielectric material having a second bonding surface and a second conductive feature at least partially embedded in the second dielectric material; as well as Directly bonding the first element to the second element includes, in the case where the metal oxide layer is present between the first conductive feature and the second conductive feature, directly bonding the first dielectric material to the second dielectric material.

2. The method according to claim 1, wherein the first dielectric material is directly bonded to the second dielectric material at room temperature.

3. The method of claim 1 further includes annealing the first element and the second element at an annealing temperature to directly bond the first conductive feature to the second conductive feature.

4. The method of claim 3, wherein the metal of the metal oxide is copper, and the annealing temperature is below about 250°C.

5. The method of claim 4, wherein the annealing temperature is below about 200°C.

6. The method of claim 4, wherein the annealing temperature is below about 180°C.

7. The method of claim 4, wherein the first conductive feature comprises one or more of copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, and titanium.

8. The method of claim 4, wherein the second conductive feature comprises one or more of copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, and titanium.

9. A microelectronic structure for low-temperature hybrid bonding, comprising: A first bonding layer having a first upper surface prepared for hybrid bonding, the first bonding layer comprising: A first conductive feature, the first conductive feature having a metal oxide layer disposed thereon, the metal oxide layer being exposed at the first upper surface, and A first dielectric material surrounds the first conductive feature, and the first dielectric material is exposed at the first upper surface.

10. The microelectronic structure according to claim 9, wherein the first conductive feature comprises one or more of copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, and titanium.

11. The microelectronic structure of claim 10, wherein the first conductive feature is at least partially separated from the surrounding dielectric material, wherein the separation is at least partially achieved by the disposed metal oxide.

12. The microelectronic structure according to claim 9, wherein the metal oxide layer comprises copper oxide.

13. The microelectronic structure of claim 12, wherein the metal oxide layer has a thickness of at least about 20 nm.

14. The microelectronic structure of claim 9, wherein the first upper surface formed by the metal oxide layer has a surface roughness of at least 2 nm RMS.

15. The microelectronic structure according to claim 9, wherein the oxide layer comprises nanoparticles.

16. The microelectronic structure of claim 15, wherein the nanoparticles have an average maximum size in the range of about 2 nm to 100 nm.

17. The microelectronic structure of claim 9, wherein the metal oxide layer is formed by oxidizing the metal of the first conductive feature.

18. The microelectronic structure of claim 17, wherein the oxidation is plasma oxidation, thermal oxidation, ozone exposure, or wet oxidation with inorganic or organic peroxides.

19. A bonding structure, comprising: A first element, the first element comprising a first bonding layer, the first bonding layer comprising: A first dielectric material having a first upper surface, and A first conductive feature is at least partially embedded in the first dielectric material at the upper surface; The second element includes a second bonding layer, the second bonding layer comprising: A second dielectric material having a second upper surface, and A second conductive feature at least partially embedded in the second dielectric material at the second upper surface; and The first upper surface is directly bonded to the second upper surface at the bonding interface, and the first conductive feature is directly bonded to the second conductive feature to form a bonding contact portion, wherein the bonding contact portion has an oxygen content of greater than 100 ppm in the metal within approximately 100 nm of the bonding interface.

20. The bonding structure of claim 19, wherein the second conductive feature comprises one or more of copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, and titanium.

21. The bonding structure according to claim 19, wherein within 100 nm of the bonding interface, the oxygen content is greater than the oxygen saturation level of the first conductive feature and / or the second conductive feature.

22. The bonding structure according to claim 19, wherein the oxygen content in the bonding contact portion comprises oxygen in a metal oxide formed from the metal of the first conductive structure.

23. A method for preparing a first element for direct mixing and bonding to a second element, comprising: A metal oxide layer is provided to form an upper portion of a first conductive feature, wherein the first conductive feature is embedded in a first dielectric material, and the first conductive feature and the first dielectric material form a first bonding layer of the first element; as well as A first bonding surface is prepared for direct hybrid bonding of the first bonding layer, wherein the metal oxide layer of the first conductive feature is exposed at the first bonding surface.

24. The method of claim 23, wherein the metal oxide layer comprises an oxide of the metal of the first conductive feature.

25. The method of claim 23, wherein the first conductive feature comprises a metal.

26. The method of claim 25, wherein the metal of the first conductive feature and the metal in the metal oxide layer are copper, nickel, gold, indium, molybdenum, zinc, tungsten, tantalum, or titanium.

27. The method of claim 23, wherein the metal oxide layer comprises nanoparticles.

28. The method of claim 27, wherein the nanoparticles have an average maximum size in the range of about 2 nm to 100 nm.

29. The method of claim 23, further comprising: Before providing the metal oxide layer over the first conductive feature, a recess is formed in the first conductive feature relative to the upper surface of the first bonding layer.

30. The method of claim 29, wherein the depth of the recess is in the range of about 10 nm to 80 nm relative to the upper surface.

31. The method of claim 23, wherein providing the metal oxide layer over the first conductive feature comprises depositing a conductive material layer over the first conductive feature and oxidizing the first conductive material layer.

32. The method of claim 23, wherein providing the metal oxide layer comprises oxidizing a material of the first conductive feature.

33. The method of claim 31 or 32, wherein oxidation comprises the product of exposing the first element to an oxygen plasma.

34. The method of claim 31 or 32, wherein the oxidation comprises thermal oxidation.

35. The method according to claim 31 or 32, wherein the oxidation comprises wet oxidation.

36. The method of claim 23, wherein providing the metal oxide layer comprises sputtering the metal oxide layer onto the first conductive feature and the first dielectric material.

37. The method according to any one of claims 23 to 36, wherein preparing the first bonding surface includes planarizing the first bonding surface.

38. The method of claim 37, wherein preparing the first bonding surface further includes activating the surface of the first dielectric material.

39. A microelectronic device, comprising: Substrate; A first hybrid bonding layer is disposed on the substrate, and the first hybrid bonding layer has a bonding surface; Dielectric material, forming a portion of the first hybrid bonding layer; as well as At least one first conductive feature is embedded in a dielectric material, the at least one first conductive feature is exposed at the bonding surface, and the at least one first conductive feature has an oxide portion at the bonding surface.

40. The device of claim 39, wherein the oxide portion comprises nanoparticles.

41. The device of claim 39, wherein the substrate comprises silicon, an intermediary, a semiconductor package, a flat panel, or a dielectric substrate.

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