Wafer-level sr am in-memory computing array activation control system and method

Abstract

The application discloses a wafer-level SRAM in-memory computing array activation control system and method, wherein the activation control system comprises an activation controller and an SRAM in-memory computing array; the SRAM in-memory computing array comprises a plurality of sub-arrays; the activation controller is used for acquiring a control field of a data packet header, generating an activation token valid signal if an activation token field in the control field is equal to a preset encoding value; based on the activation token valid signal, a target processing unit is determined according to the control field; based on a sub-array activation mask field in the control field, a sub-array sleep control signal of a target sub-array corresponding to the target processing unit is generated; and the target sub-array is powered on or powered off according to the sub-array sleep control signal; the application can realize on-demand dynamic power-on and timely sleep control at the sub-array level in a data stream driven computing scenario, thereby reducing the static power consumption of a large-scale array and improving the responsiveness and energy efficiency of a computing pipeline.

Description

Technical Field

[0001] This invention relates to the field of large-scale integrated circuit design technology, and in particular to a wafer-level SRAM in-memory computing array activation control system and method. Background Technology

[0002] Wafer-scale compute-in-memory (CIM) chips perform data operations directly within the memory array, reducing the overhead of data movement between processing and storage units. This has led to their widespread application in high-performance computing and artificial intelligence acceleration. However, in applications integrating a large number of CIM units at the wafer-level, effectively suppressing the static power consumption of the memory array while ensuring the continuity of the data flow computation pipeline and the stability of execution timing remains a critical technical challenge.

[0003] Existing wafer-level in-memory computing chips typically consist of multiple processing elements (PEs), each integrating a large-capacity SRAM in-memory computing array, and organizing parallel computing tasks in a data-stream manner. In existing solutions, power management and activation control of the in-memory computing array usually rely on global configuration streams or software scheduling mechanisms, i.e., controlling the overall power-on or power-off of the in-memory computing array within the processing unit during computing task execution. Furthermore, to ensure the timing consistency and stability of the array operation, the relevant activation and reconfiguration processes typically require configuration update and synchronization control flows, inevitably introducing microsecond-level control latency.

[0004] However, the aforementioned existing technical solutions still have certain limitations in wafer-level large-scale integration applications. On the one hand, when the in-memory computing array remains powered on during non-working periods or under partial load conditions, it generates significant static leakage power consumption, especially when only some subarrays participate in computation, with the non-participating subarrays still receiving power, leading to unnecessary energy consumption. On the other hand, array activation methods triggered by software or global configuration mechanisms have long response delays in the control path, making it difficult to precisely match the real-time execution rhythm of the data flow computing pipeline, easily introducing additional waiting cycles, thus adversely affecting the overall system energy efficiency and execution efficiency.

[0005] This section is intended to provide background or context for the embodiments of the invention set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0006] This invention provides a wafer-level SRAM in-memory computing array activation control system to achieve on-demand dynamic power-on and timely sleep control at the subarray level in data flow-driven computing scenarios, thereby reducing the static power consumption of large-scale arrays and improving the responsiveness and energy efficiency of computing pipelines.

[0007] The wafer-level SRAM in-memory computing array activation control system includes: an activation controller and an SRAM in-memory computing array; The SRAM in-memory computing array includes multiple sub-arrays; The activation controller is used to obtain the control field of the data packet header. If the activation token field in the control field is equal to a preset encoding value, an activation token valid signal is generated. Based on the activation token valid signal, the target processing unit is determined according to the control field. Based on the subarray activation mask field in the control field, a subarray sleep control signal for the target subarray corresponding to the target processing unit is generated. The target subarray is powered on or off according to the subarray sleep control signal.

[0008] In some embodiments, the activation controller includes: a token parser, configured to receive data packets, read the control field from the header of the data packets, determine whether the activation token field is equal to a preset encoded value; if so, generate an activation token valid signal.

[0009] In some embodiments, the control field further includes a cyclic redundancy check field; the activation controller further includes a verifier, configured to perform verification processing on the control field after receiving the activation token valid signal to obtain a verification value; match the cyclic redundancy check field with the verification value; and generate a verification pass signal if the cyclic redundancy check field and the verification value are successfully matched.

[0010] In some embodiments, the control field further includes: a target processing unit horizontal coordinate field and a target processing unit vertical coordinate field; the activation controller includes: a power gating driver, used to determine the target processing unit according to the target processing unit horizontal coordinate field and the target processing unit vertical coordinate field after receiving the verification pass signal; input each bit of the subarray activation mask field to the corresponding inverter for inversion processing to obtain each subarray sleep control signal; and control the corresponding target subarray to power on or power off according to the subarray sleep control signal.

[0011] In some embodiments, the power gate driver is specifically used to control the gate of the corresponding transistor to turn on when the subarray sleep control signal is low, so as to power on the corresponding target subarray; and to control the gate of the corresponding transistor to turn off when the subarray sleep control signal is high, so as to power off the corresponding target subarray.

[0012] In some embodiments, the activation controller further includes: a sleep trigger, configured to monitor whether the target subarray has generated a computation result data packet; if the computation result data packet has been generated and the on-chip network's transmit valid signal is a rising edge, generate a power-off request signal and set the subarray sleep control signal of the target subarray to a high level, so that the target subarray enters a sleep state.

[0013] In some embodiments, the system further includes a data stream interface for transmitting the computation result data packet to the on-chip network.

[0014] This invention also provides a wafer-level SRAM in-memory computing array activation control method to achieve on-demand dynamic power-on and timely sleep control at the subarray level in data flow-driven computing scenarios, thereby reducing the static power consumption of large-scale arrays and improving the responsiveness and energy efficiency of computing pipelines.

[0015] The wafer-level SRAM in-memory computing array activation control method includes: SRAM in-memory computing arrays consist of multiple subarrays; The activation controller acquires the control field of the data packet header. If the activation token field in the control field is equal to a preset encoding value, an activation token valid signal is generated. Based on the activation token valid signal, the target processing unit is determined according to the control field. Based on the subarray activation mask field in the control field, a subarray sleep control signal for the target subarray corresponding to the target processing unit is generated. The target subarray is powered on or off according to the subarray sleep control signal.

[0016] This invention also provides a chip, including the above-described wafer-level SRAM in-memory computing array activation control system.

[0017] Specifically, this invention is applicable to wafer-level chips, wherein the wafer-level chip can be configured with multiple computing cores, some or all of which include the matrix multiplication and addition operation unit of this invention; the chip can be used in scenarios such as AI large model training and high-performance scientific computing, and by integrating a high-density MAC array at the wafer-level scale, the advantages of this invention, such as multi-data type fusion, low power consumption, and high parallelism, are realized.

[0018] This invention also provides a board card including the above-mentioned chip.

[0019] This invention also provides an electronic device including the aforementioned circuit board.

[0020] The wafer-level SRAM in-memory computing array activation control system and method provided in this invention sets an activation token field and a subarray activation mask field in the packet header of the data packet, and the activation controller parses and determines the control fields at the hardware level. This enables the in-memory computing array to perform precise power-on or power-off control on the target processing unit and its internal subarrays as needed when data arrives, thereby avoiding the ineffective energy consumption caused by the traditional power supply method with the entire processing unit as the granularity, and significantly reducing the static leakage power consumption of large-scale SRAM arrays. Based on the activation token valid signal directly triggering power gating control, the dependence on software scheduling or global configuration process is reduced, which effectively compresses the activation response latency and helps maintain the continuity of data flow computing pipeline execution. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the structure of the wafer-level SRAM in-memory computing array activation control system in an embodiment of the present invention; Figure 2 This is a timing diagram of the wafer-level SRAM in-memory computing array activation control method in an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with relevant laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been authorized and agreed upon by the customer.

[0023] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.

[0024] To address the issues of coarse power supply granularity and high static power consumption in existing wafer-scale SRAM compute-in-memory (CIM) arrays, as well as the large response latency caused by the activation process relying on software or global configuration, which makes it difficult to match the data flow computing pipeline cycle time, this application provides a wafer-scale SRAM compute-in-memory array activation control system.

[0025] This activation control system sets an activation token field and a subarray activation mask field in the packet header. The activation controller parses and verifies the control fields in the packet header and directly drives the power gating controller based on the subarray activation mask field, achieving on-demand power-on or power-off control of the subarrays. After the computation result packet is sent, the corresponding subarray is further triggered to enter a sleep state. This achieves power supply only to the subarrays involved in the computation and power-off processing for the subarrays not involved in the computation without increasing software scheduling overhead, effectively suppressing static leakage power consumption. By triggering hardware activation in real time when the data stream arrives, activation response latency is reduced and pipeline execution continuity is ensured. Independent verification of the control fields in the packet header avoids the risk of false activation.

[0026] like Figure 1 As shown, the present invention provides a wafer-level SRAM in-memory computing array activation control system, including: an activation controller and an SRAM in-memory computing array.

[0027] SRAM in-memory computing arrays consist of multiple subarrays.

[0028] The activation controller is used to obtain the control field of the data packet header. If the activation token field in the control field equals a preset encoded value, an activation token validity signal is generated. Based on the activation token validity signal, the target processing unit is determined according to the control field. Based on the subarray activation mask field in the control field, a subarray sleep control signal is generated for the target subarray corresponding to the target processing unit. The target subarray is powered on or off according to the subarray sleep control signal.

[0029] According to the above embodiments, by setting an activation token field and a subarray activation mask field in the packet header, and having the activation controller parse and determine the control fields at the hardware level, the in-memory computing array can perform precise power-on or power-off control on the target processing unit and its internal subarrays as needed when data arrives. This avoids the ineffective energy consumption caused by the traditional power supply method that uses the entire processing unit as the granularity, and significantly reduces the static leakage power consumption of large-scale SRAM arrays. Based on the activation token's valid signal directly triggering power gating control, the dependence on software scheduling or global configuration processes is reduced, effectively compressing the activation response latency and helping to maintain the continuity of the data flow computing pipeline execution.

[0030] In this embodiment of the invention, a wafer includes multiple processing elements (PEs), each processing element integrating an SRAM in-memory computing array. The SRAM in-memory computing array is further divided into multiple sub-arrays. For example, as... Figure 1 As shown, an SRAM in-memory computing array includes subarrays 0 to 7.

[0031] In some embodiments, such as Figure 1 As shown, the activation controller includes: a token parser, used to receive data packets, read the control field from the packet header, and determine whether the activation token field is equal to a preset encoded value. If so, it generates an activation token valid signal.

[0032] In this embodiment of the invention, the structure of the packet header control field is shown in Table 1.

[0033] Table 1

[0034] The token resolver receives data packets via a Network-on-Chip (NoC) interface and reads the 32-bit control field from the packet header in parallel. Determine the activation token field Is it the preset encoding value 10b? When At that time, the token resolver generates an activation token valid signal. It then sends an activation token validity signal to the verifier. This token parser is a 32-bit parallel comparator.

[0035] When the activation token field When the value is 10b, it indicates that the currently received data packet is a data packet used to trigger the activation of the SRAM in-memory computing array. When the activation token field... When the value is 00b, it indicates that the currently received data packet is a normal data packet. When the activation token field... When the value is 01b, it indicates that the currently received data packet is a control data packet. For ordinary data packets and control data packets, the corresponding processing can be completed without triggering the activation operation of the SRAM in-memory computing array.

[0036] For example, the combined logic delay of the above token parser in parsing and judging data packets is less than 0.8ns.

[0037] According to the above embodiments, the token parser in the activation controller performs hardware-level parallel parsing of the packet headers arriving through the on-chip network, and generates an activation token valid signal immediately when the activation token field is detected to be equal to a preset encoded value. This triggers subsequent power gating and array activation operations without requiring software scheduling or global configuration processes, tightly coupling the activation process with the data stream transmission process and establishing a hardware autonomous control mechanism that triggers activation upon packet arrival. Since the parsing and determination process is implemented using combinational logic, and the corresponding control path is relatively short, the activation trigger latency is mainly limited by a small amount of logic propagation delay, which can be controlled within the nanosecond range. For example, the overall activation latency does not exceed 200ns, effectively reducing the waiting overhead introduced by traditional control methods and ensuring the continuity and real-time performance of the data stream computation pipeline.

[0038] In some embodiments, the activation controller further includes: a verifier, configured to perform verification processing on the control field after receiving a valid activation token signal to obtain a verification value. The cyclic redundancy check (CRUD) field is matched with the verification value. If the CRUD field and the verification value match successfully, a verification pass signal is generated.

[0039] In this embodiment of the invention, the control field further includes a Cyclic Redundancy Check (CRC) field. This CRC field is set after the subarray activation mask field.

[0040] The sending end sends the 32-bit control field to be verified. Bitwise or bytewise inputs are sequentially entered into the Linear Feedback Shift Register (LFSR) circuit. For each bit of data input, the LFSR circuit performs shift and XOR operations on the register contents according to a preset CRC8 generator polynomial. This process is repeated for all 32-bit control fields. After the input is completed, the remaining 8 bits of the register value in the linear feedback shift register circuit are the CRC8 check value. The sending end writes the CRC8 check value as the CRC field into the packet header control field of the data packet.

[0041] At the receiving end, after receiving the activation token valid signal output by the token parser, the verifier uses the same CRC8 generator polynomial and the same linear feedback shift register circuit as the sending end to process the control field. The CRC8 checksum is recalculated and compared with the CRC field carried in the packet header. If the CRC field matches the CRC8 checksum, a checksum pass signal is generated. The system then sends a pass signal to the power gating driver. If the CRC field does not match the CRC8 checksum, the currently received data packet is discarded, and the error flag inside the controller is set to valid. This prevents subsequent power gating drivers from performing corresponding control actions.

[0042] According to the above embodiment, after receiving a valid activation token signal, the activation controller performs independent CRC8 check processing on the control field in the packet header and matches the calculated check value with the cyclic redundancy check field carried in the packet header. Only when the two match is a check pass signal generated, allowing the subsequent power gating driver to take effect. This effectively ensures the integrity of the packet header control information at the hardware level. By independently checking the control field, bit flipping or disturbance errors that may occur during transmission can be detected and shielded in a timely manner. This avoids triggering erroneous subarray power-on or power-off operations due to incorrect control information, thereby reducing the risk of accidental activation or shutdown and improving the reliability of the activation control process and the safety of system operation.

[0043] In some embodiments, the control field further includes: an x-coordinate field and a y-coordinate field of the target processing unit. The activation controller includes: a power gating driver, used to determine the target processing unit based on the x-coordinate field and the y-coordinate field of the target processing unit after receiving a verification pass signal. Each bit of the subarray activation mask field is input to the corresponding inverter for inversion processing to obtain a sleep control signal for each subarray. The corresponding target subarray is powered on or off according to the subarray sleep control signal. Here, the x-coordinate is the X-coordinate, and the y-coordinate is the Y-coordinate.

[0044] In this embodiment of the invention, as shown in Table 1, the X-coordinate field of the target processing unit is used to represent the X-coordinate in the wafer physical coordinate system, and its value range is 0 to 255. The Y-coordinate field of the target processing unit is used to represent the Y-coordinate in the wafer physical coordinate system, and its value range is 0 to 319. The subarray activation mask field is used to indicate the subarrays that need to be activated. Specifically, when Bit[i] = 1 in the subarray activation mask field, it indicates that the i-th subarray (i = 0 to 7) is activated; when Bit[i] = 0 in the subarray activation mask field, it indicates that the i-th subarray is deactivated.

[0045] For example, when the subarray activation mask field is 0x01 (i.e., binary 0000 0001), it indicates that only subarray 0 is activated. When the subarray activation mask field is 0x03 (i.e., binary 0000 0011), it indicates that subarray 0 and subarray 1 are activated. When the subarray activation mask field is 0xFF (i.e., binary 1111 1111), it indicates that all 8 subarrays are activated.

[0046] After receiving the verification pass signal, the power gating driver determines the target processing unit's X-coordinate field from the control field. and the Y-coordinate field of the target processing unit Determine the coordinate position of the target processing unit and activate the subarray mask field in the control field. Each bit The signals are input to the corresponding inverters for inversion to generate the subarray sleep control signals for each subarray. The power-gated driver operates according to the subarray sleep control signal (). This controls the gate switching of the corresponding P-type metal-oxide-semiconductor field-effect transistor (PMOS). Each subarray corresponds to a set of PMOS transistors. In this embodiment, the eight subarrays each correspond to eight sets of PMOS transistors.

[0047] In some embodiments, the power gate driver is specifically used to control the gate of the corresponding transistor to turn on when the subarray sleep control signal is low, so as to power on the corresponding target subarray. Conversely, if the subarray sleep control signal is high, it controls the gate of the corresponding transistor to turn off, so as to power off the corresponding target subarray.

[0048] When the subarray sleep control signal is low (i.e.) When the power supply gate driver controls the gate of the corresponding PMOS transistor to turn on, the corresponding target subarray is powered on. When the subarray sleep control signal is low ( When the power gate driver controls the gate of the corresponding PMOS transistor to open, the corresponding subarray is powered off.

[0049] According to the above embodiments, by setting an activation token field and a subarray activation mask field in the packet header, the packet carries control fields for the target processing unit and its internal subarrays while carrying computational data, thereby constructing a data-as-instruction hardware autonomous control method. After the activation controller passes the verification, it directly sends each bit to the corresponding inverter according to the subarray activation mask field, and the inverter drives the gate of the high-threshold transistor to form a power gating path. This allows the subarray activation mask field to directly act on the subarray power switch without going through intermediate control logic, thereby achieving fine-grained power supply control at the subarray level. In this way, only the subarrays that actually participate in the computation are powered on, while the other subarrays remain powered off. This suppresses the leakage current of non-working subarrays to an extremely low level (e.g., less than 1nA), effectively avoiding the ineffective energy consumption caused by power supply methods at the granularity of the entire processing unit, and achieving a precise suppression effect on static power consumption.

[0050] In some embodiments, it further includes: a data stream interface for transmitting computation result data packets to an on-chip network.

[0051] The activation controller also includes a sleep trigger, used to monitor whether the target subarray has generated a computation result data packet. If a computation result data packet has been generated and the on-chip network's transmit valid signal is a rising edge, a power-down request signal is generated, and the subarray sleep control signal of the target subarray is set to a high level, so that the target subarray enters a sleep state.

[0052] In this embodiment of the invention, after the target subarray powers on, it performs corresponding computational processing based on the data carried in the data packet and generates computational result data. The target subarray reuses the aforementioned activation token field and encapsulates the computational result data, along with the preset downstream target processing unit X-coordinate field, downstream target processing unit Y-coordinate field, and subarray activation mask field, into a data packet, which is then sent to the on-chip network via the data stream interface. The on-chip network forwards this data packet to the downstream target processing unit.

[0053] The sleep trigger monitors the processing of the target subarray in real time. When it detects that the computation result data has been generated, it further determines whether the valid transmission signal of the on-chip network is a rising edge (i.e., If the on-chip network's valid transmit signal is a rising edge, it indicates that the data packet has been successfully transmitted, and the sleep trigger generates a power-off request signal. And send a power-off request signal to the power gating driver.

[0054] Upon receiving the power-down request signal, the power gating driver sets the subarray sleep control signal corresponding to the target subarray to a high level (i.e., This is used to control the target subarray to enter a sleep state.

[0055] According to the above embodiment, after completing the computation, the target subarray sends the computation result data packet to the on-chip network via the data flow interface. The computation result data packet reuses the activation token field and carries control information for the downstream target processing unit and its subarray. This triggers the activation operation of the corresponding processing unit while the result data is being transmitted to the downstream processing unit, constructing a chain-like computing pipeline structure driven by the data flow. The sleep trigger in the activation controller monitors the processing of the target subarray. Only after detecting that the computation result data packet has been generated and the on-chip network's transmit valid signal has a rising edge, confirming that the result data has been successfully transmitted, does it generate a power-off request signal and control the corresponding subarray to enter a sleep state. This avoids the risk of data loss due to premature power-off before the result data has been safely transmitted. Through this mechanism, seamless pipeline connection between processing units is achieved without additional software scheduling or global synchronization control, forming a self-triggering computing link driven by the control information carried in the result data packet, ensuring the continuity and reliability of the computing process.

[0056] The technical solution of this application will be described below through a specific embodiment, but the scope of protection of this application is not limited thereto.

[0057] In one embodiment, such as Figure 2 As shown, taking the Conv1 layer computation task of a neural network as an example, the parameter scale of the Conv1 layer is 7×7×3×64, and its computation task is mapped to 8 processing units for execution. Among them, the processing unit PE_0x0001 includes subarrays 0 to 7.

[0058] The corresponding data packet template is generated based on the above mapping relationship. Among them, the header control field of the input data packet is set to

[10]

[00]

[01]

[01]

[000] [000000][0][A3], the activation token field is set to 10b, the target processing unit coordinate field points to the processing unit PE_0x0001, and the subarray activation mask field is set to 0x01 to indicate that only subarray 0 is activated.

[0059] The header control field of the operation result data packet is set to

[10]

[00]

[02]

[02]

[040] [000100][0][F7]. The operation result data packet reuses the activation token field of the input data packet and points the target processing unit coordinate field to the downstream processing unit PE_0x0002. The subarray activation mask field is set to 0x02, which is used to trigger the activation of subarray 1 in the downstream processing unit after the operation result data is sent.

[0060] During operation, when the activation controller receives the input data packet via the on-chip network, it acquires the header control field

[10]

[00]

[01]

[01]

[000] [000000][0][A3] of the input data packet at time T = 0 ns. Subsequently, at time T = 0.8 ns, the token parser parses the header control field and identifies the activation token field, thereby generating an activation token valid signal (token_valid = 1). At time T = 1.5 ns, the verifier performs CRC8 verification on the header control field and outputs a verification pass signal (crc_ok = 1) after successful verification. At time T = 2.3 ns, the power gating driver generates the subarray sleep control signal (SLEEP_0 = 0) corresponding to subarray 0 based on the subarray activation mask field 0x01, and sets the subarray sleep control signals corresponding to the remaining subarrays to SLEEP_1 to SLEEP_7 = 1. The power gating path controls subarray 0 to power on according to the subarray sleep control signal and controls subarrays 1 to 7 to enter the power-off state.

[0061] At time T = 87.3 ns, the power supply voltage of subarray 0 reaches a stable state, for example, VDD_subarray0 = 0.9 × VDD. At time T = 146.0 ns, subarray 0 completes the convolution operation and generates the corresponding calculation result data 0x1A3F. At time T = 147.5 ns, the target processing unit PE_0x0001 generates the operation result data packet, whose header control field is set to

[10]

[00]

[02]

[02]

[040] [000100][0][F7], and reuses the activation token field in the above header control field, while carrying control information pointing to the downstream processing unit PE_0x0002 and its subarray 1. The target processing unit PE_0x0001 injects the operation result data packet into the on-chip network for transmission through the data stream interface.

[0062] At time T = 151.2 ns, the on-chip network confirms that the computation result data packet has been sent. The sleep trigger monitors the above process. After detecting that the computation result data packet has been generated and the on-chip network's transmit valid signal is rising, i.e., confirming that the computation result data packet has been successfully sent, it generates a power-off request signal (power_off_req = 1) and sets the subarray sleep control signal corresponding to subarray 0 to 1 (SLEEP_0 = 1). At time T = 152.0 ns, the power gating driver controls subarray 0 to enter the power-off state according to the subarray sleep control signal, thereby suppressing its leakage current to an extremely low level. At time T = 155.0 ns, the downstream processing unit PE_0x0002 is triggered and activated after receiving the computation result data packet, so as to realize the chain-like self-driving and pipeline-like seamless connection between adjacent processing units.

[0063] This application provides a wafer-level SRAM in-memory computing array activation control method, applied to the aforementioned wafer-level SRAM in-memory computing array activation control system. This wafer-level SRAM in-memory computing array activation control method is based on the same inventive concept as the wafer-level SRAM in-memory computing array activation control system in one embodiment of this application, and the principle of solving the problem is similar. Therefore, the implementation of the wafer-level SRAM in-memory computing array activation control method is the same as the implementation of the wafer-level SRAM in-memory computing array activation control system in one embodiment of this application, and repeated details will not be described again. As used below, the terms "unit" or "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the system described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0064] The wafer-level SRAM in-memory computing array activation control method includes: SRAM in-memory computing arrays consist of multiple subarrays.

[0065] The activation controller acquires the control field of the data packet header. If the activation token field in the control field equals a preset encoded value, an activation token validity signal is generated. Based on the activation token validity signal, the target processing unit is determined according to the control field. Based on the subarray activation mask field in the control field, a subarray sleep control signal is generated for the target subarray corresponding to the target processing unit. The target subarray is powered on or off according to the subarray sleep control signal.

[0066] In some embodiments, the method further includes: a token resolver receiving a data packet, reading a control field from the packet header, and determining whether the activation token field is equal to a preset encoded value. If so, generating an activation token valid signal.

[0067] In some embodiments, the control field further includes a cyclic redundancy check (CRUD) field. The method further includes: after receiving a valid activation token signal, the verifier performs verification processing on the control field to obtain a verification value. The CRUD field is then matched with the verification value. If the CRUD field and the verification value match successfully, a verification pass signal is generated.

[0068] In some embodiments, the control field further includes: a target processing unit horizontal coordinate field and a target processing unit vertical coordinate field. The method further includes: after receiving a verification pass signal, the power gating driver determines the target processing unit based on the target processing unit horizontal coordinate field and the target processing unit vertical coordinate field. Each bit of the subarray activation mask field is input to the corresponding inverter for inversion processing to obtain a sleep control signal for each subarray. The corresponding target subarray is powered on or off according to the subarray sleep control signal.

[0069] In some embodiments, the method further includes: if the subarray sleep control signal is low, the power gate driver controls the gate of the corresponding transistor to turn on, so as to power on the corresponding target subarray. If the subarray sleep control signal is high, the power gate driver controls the gate of the corresponding transistor to turn off, so as to power off the corresponding target subarray.

[0070] In some embodiments, the method further includes: a sleep trigger, which monitors whether the target subarray has generated a computation result data packet. If a computation result data packet has been generated and the on-chip network's transmit valid signal is a rising edge, a power-down request signal is generated, and the subarray sleep control signal of the target subarray is set to a high level, so that the target subarray enters a sleep state.

[0071] In some embodiments, the method further includes: a data stream interface transmitting the computation result data packet to an on-chip network.

[0072] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0073] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0074] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0075] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0076] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0077] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A wafer-level SRAM in-memory computing array activation control system, characterized in that, include: Activate the controller and SRAM-based computing array; The SRAM in-memory computing array includes multiple sub-arrays; The activation controller is used to obtain the control field of the data packet header. If the activation token field in the control field is equal to the preset encoding value, an activation token valid signal is generated. Based on the activation token validity signal, the target processing unit is determined according to the control field; Based on the subarray activation mask field in the control field, a subarray sleep control signal is generated for the target subarray corresponding to the target processing unit; the target subarray is powered on or off according to the subarray sleep control signal.

2. The system according to claim 1, characterized in that, The activation controller includes a token parser, which receives data packets, reads the control field from the header of the data packets, determines whether the activation token field is equal to a preset encoded value, and generates an activation token valid signal if so.

3. The system according to claim 1, characterized in that, The control field further includes a cyclic redundancy check field; the activation controller further includes a verifier, used to perform verification processing on the control field after receiving the activation token valid signal to obtain a verification value; match the cyclic redundancy check field with the verification value; if the cyclic redundancy check field and the verification value match successfully, generate a verification pass signal.

4. The system according to claim 3, characterized in that, The control field further includes: a target processing unit horizontal coordinate field and a target processing unit vertical coordinate field; the activation controller includes: a power gating driver, used to determine the target processing unit according to the target processing unit horizontal coordinate field and the target processing unit vertical coordinate field after receiving the verification pass signal; input each bit of the subarray activation mask field to the corresponding inverter for inversion processing to obtain the sleep control signal of each subarray; control the corresponding target subarray to power on or power off according to the subarray sleep control signal.

5. The system according to claim 4, characterized in that, The power gate driver is specifically used to control the gate of the corresponding transistor to turn on when the subarray sleep control signal is low, so as to power on the corresponding target subarray; and to control the gate of the corresponding transistor to turn off when the subarray sleep control signal is high, so as to power off the corresponding target subarray.

6. The system according to claim 1, characterized in that, The activation controller further includes a sleep trigger, used to monitor whether the target subarray has generated a computation result data packet; if the computation result data packet has been generated and the on-chip network's transmit valid signal is a rising edge, a power-off request signal is generated, and the subarray sleep control signal of the target subarray is set to a high level, so that the target subarray enters a sleep state.

7. The system according to claim 6, characterized in that, Also includes: A data stream interface is used to transmit the data packets containing the computation results to the on-chip network.

8. A wafer-level SRAM in-memory computing array activation control method, characterized in that, include: SRAM in-memory computing arrays consist of multiple subarrays; The activation controller obtains the control field of the data packet header. If the activation token field in the control field is equal to the preset encoding value, an activation token valid signal is generated. Based on the activation token validity signal, the target processing unit is determined according to the control field; Based on the subarray activation mask field in the control field, a subarray sleep control signal is generated for the target subarray corresponding to the target processing unit; the target subarray is powered on or off according to the subarray sleep control signal.

9. A chip, characterized in that, The wafer-level SRAM in-memory computing array activation control system includes any one of claims 1 to 7.

10. A circuit board, characterized in that, Includes the chip described in claim 9.

11. An electronic device, characterized in that, Includes the board as described in claim 10.

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