Power failure processing method of storage chip, electronic equipment and storage medium
By monitoring and slowing down the rate of voltage drop in the storage chip through the power-down control unit, the data integrity problem caused by abnormal power loss of the storage chip is solved, thereby achieving data reliability and optimization of storage space.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI LONGSYS MICROELECTRONICS TECH CO LTD
- Filing Date
- 2024-11-06
- Publication Date
- 2026-05-15
AI Technical Summary
Storage chips may experience abnormal power loss during the execution of control commands, which may lead to a loss of data integrity. Existing technologies such as dual data backup and hardware power detection mechanisms have problems such as high space consumption or unreliability.
The power-down control unit monitors the voltage of the memory chip in real time and slows down its rate of decline, so that the voltage drops to the minimum operating voltage after the controller reset time, ensuring that the control command is completed within an appropriate time.
This effectively avoids data anomalies caused by incomplete execution of control commands, reduces storage space requirements and the risk of data loss, and improves data reliability.
Smart Images
Figure CN122050447A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of memory chip technology, and in particular to power-down handling methods for memory chips, electronic devices, and storage media. Background Technology
[0002] During the execution of control instructions (such as erase instructions), memory chips may experience abnormal power outages. Since the execution of control instructions requires a certain amount of operation time, if a power outage occurs during the operation cycle, the execution of control instructions by the memory chip will not be completed completely, and the correctness of the data in the memory chip cannot be guaranteed. Summary of the Invention
[0003] This application provides a power-down processing method for a memory chip, an electronic device, and a storage medium. The power-down control unit can monitor the voltage of the memory chip in real time, and when the memory chip loses power, the power-down control unit controls the rate of voltage drop of the memory chip, so that the time when the voltage of the memory chip drops to the minimum operating voltage is after the reset time of the controller, and the time interval between the two times is sufficient to execute the controller's control command once, thus avoiding data anomalies due to incomplete execution of the control command.
[0004] To address the aforementioned technical problems, this application provides a power-down processing method for a memory chip. The memory chip is coupled to a controller and a power-down control unit. The power-down processing method includes: monitoring the target operating voltage of the memory chip using the power-down control unit; and, in response to a decrease in the target operating voltage of the memory chip, delaying the rate of decrease of the target operating voltage so that the target time point when the target operating voltage decreases to the minimum operating voltage is after the reset time point of the controller, and the time length between the target time point and the reset time point is at least sufficient for the memory chip to execute one control instruction from the controller.
[0005] In some embodiments, the power-down control unit and the controller are respectively coupled to the power supply unit, which is configured to supply power to the controller and to supply power to the memory chip through the power-down control unit.
[0006] In some embodiments, the power-down control unit generates a voltage signal with a first falling slope in response to a decrease in the target operating voltage provided by the power supply unit, and provides the voltage signal to the memory chip; wherein the first falling slope is less than the default falling slope of power-down.
[0007] In some embodiments, the power supply unit includes a first power supply unit and a second power supply unit, wherein the first power supply unit is configured to supply power to the memory chip through a power-down control unit, and the second power supply unit is configured to supply power to the controller.
[0008] In some embodiments, a first power supply unit is coupled to a first terminal of a power-down control unit, and a memory chip is coupled to a second terminal of a power-down control unit; the power-down control unit generates a voltage signal with a first falling slope in response to a decrease in the target operating voltage provided by the first power supply unit, and provides the voltage signal to the memory chip; wherein the first falling slope is less than the default falling slope of power-down.
[0009] In some embodiments, the memory chip receives a control command sent by the controller when the controller's operating voltage drops to the reset voltage or before the controller's operating voltage drops to the reset voltage, and executes the completion control command before the target time point.
[0010] In some embodiments, the control instructions are erase instructions or programming instructions, and the time required for the memory chip to complete the execution of erase instructions and programming instructions is different.
[0011] In some embodiments, the time to complete an erase instruction is less than or equal to 10 ms, and the time to complete a programming instruction is less than or equal to 750 μs.
[0012] To address the aforementioned technical problems, this application also provides an electronic device, which includes a controller, a memory chip, and a power-down control unit. The memory chip is coupled to the controller and the power-down control unit and is used to implement the aforementioned power-down processing method.
[0013] To address the aforementioned technical problems, this application also provides a computer-readable and writable storage medium storing a computer program, which, when executed by a controller, is used to implement the aforementioned power-off processing method.
[0014] The power-down handling method for memory chips provided in some embodiments of this application utilizes a power-down control unit to monitor the target operating voltage of the memory chip. When the target operating voltage of the memory chip decreases, the power-down control unit slows down the rate of decrease of the target operating voltage, ensuring that the target time point when the target operating voltage drops to the minimum operating voltage is after the reset time point of the controller, and the time interval between the target time point and the reset time point is sufficient for the memory chip to execute the controller's control command at least once. This allows for real-time monitoring of the memory chip voltage, controlling the rate of voltage decrease when the memory chip experiences a power failure, ensuring that the time corresponding to the minimum operating voltage drops is after the controller's reset time, and that the time interval between the two times satisfies the requirement to execute the controller's control command once, thus avoiding data anomalies due to incomplete execution of control commands. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0016] Figure 1 These are schematic diagrams of the electronic devices in some embodiments of this application;
[0017] Figure 2 This is a linear relationship graph of voltage versus time in some embodiments of this application;
[0018] Figure 3 This is a flowchart illustrating the power-down handling method of a memory chip in some embodiments of this application;
[0019] Figure 4 This is a linear relationship graph of voltage versus time in some embodiments of this application;
[0020] Figure 5 These are schematic diagrams of the electronic devices in some embodiments of this application;
[0021] Figure 6 These are schematic diagrams of the electronic devices in some embodiments of this application;
[0022] Figure 7 This is a schematic diagram of the structure of a computer-readable and writable storage medium in some embodiments of this application. Detailed Implementation
[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0024] A memory chip may experience an abnormal power outage during the execution of control instructions. Since the execution of control instructions requires a certain amount of operation time, if a power outage occurs during the operation cycle, the memory chip will not be able to complete the execution of control instructions, and thus the correctness of the data in the memory chip cannot be guaranteed.
[0025] To address the aforementioned technical issues, related technologies include: 1) performing dual data backup. However, dual data backup requires significant space on the storage chip, and it cannot completely eliminate the risk of data errors; 2) the controller verifies the correctness of data read from the memory. However, the error checking and correction within the storage chip are unreliable and may not report errors when they occur, leading to the inability to detect errors; 3) adding a power detection unit and signal control circuit in the hardware. The power detection unit detects the voltage, and the signal control circuit prevents the controller from sending erase / write commands to the storage chip during power failure, thereby avoiding data operations and ensuring data reliability. However, since the hardware controls the sending of control commands during power failure, there is a possibility that the control commands may have already been sent before the power failure occurs.
[0026] To address the aforementioned technical problems, this application proposes a power-off handling method for electronic devices and memory chips.
[0027] See Figure 1 , Figure 1 This is a schematic diagram of the structure of an electronic device in some embodiments of this application. The electronic device 10 includes a controller 101, a storage chip 102, and a power-down control unit 103. The controller 101 and the power-down control unit 103 are respectively coupled to the storage chip 102.
[0028] The memory chip 102 can be any erasable and rewritable non-volatile memory (such as NOR Flash, NAND Flash or others), and there are no restrictions here.
[0029] In some embodiments, the controller 101 and the memory chip 102 operate at the same voltage during normal operation. If a power failure occurs, the operating voltage of the controller 101 and the target operating voltage of the memory chip 102 decrease from the same voltage until they reach 0. Furthermore, the operating voltage of the controller 101 and the target operating voltage of the memory chip 102 decrease at the same rate, that is, both the operating voltage of the controller 101 and the target operating voltage of the memory chip 102 decrease at a first rate until they reach 0.
[0030] However, it is worth noting that the controller 101 stops sending control commands after its operating voltage reaches the reset voltage. Therefore, when the operating voltage of the controller 101 drops to or before it drops to the reset voltage, the controller 101 may send a control command to the memory chip 102 once, so that the memory chip 102 can execute the control command during the drop of the target operating voltage. However, after the target operating voltage of the memory chip 102 reaches the minimum operating voltage (less than the reset voltage), the memory chip 102 will stop working. Therefore, if the time between the sending of the control command and the time during which the memory chip 102 stops working is not sufficient for the memory chip 102 to execute the control command, the control command will not be executed normally, resulting in an instruction execution error and potentially causing data loss.
[0031] like Figure 2 As shown, the linear relationships between the voltage and time of the controller 101 and the memory chip 102 are v1(t) and v2(t), respectively. v1(t) and v2(t) coincide, meaning that the voltage of both the controller 101 and the memory chip 102 is V1 when they are working normally. When a power failure occurs, the operating voltage of the controller 101 and the memory chip 102 begins to decrease. When the operating voltage of the controller 101 drops to the reset voltage V2 corresponding to time T1, the controller 101 sends a control command. If the voltage drop process of the controller 101 and / or the memory chip 102 is not processed before the operating voltage of the memory chip 102 drops to the lowest operating voltage corresponding to time T2, the time period T1-T2 is insufficient to support the memory chip 102 to execute a control command, and the memory chip 102 will not be able to execute the control command normally.
[0032] Therefore, in order to avoid problems such as the memory chip 102 failing to execute the control commands sent by the controller 101 and related data loss during power failure, the process of the drop in the operating voltage of the controller 101 and / or the target operating voltage of the memory chip 102 can be processed during power failure.
[0033] In some embodiments, the operating voltage of the memory chip 102 is processed in the event of a power failure. Specifically, as shown in the following examples... Figure 3 As shown, the power-down handling method for memory chip 102 may include the following steps:
[0034] Step 11: Monitor the target operating voltage of the memory chip using the power-down control unit.
[0035] It is understood that the target operating voltage of the memory chip 102 is the voltage required for the normal operation of the memory chip 102, and can be determined according to the actual situation. If the target operating voltage of the memory chip 102 decreases, it can be determined that the memory chip 102 is in an abnormal state such as power failure.
[0036] Step 12: In response to the decrease in the target operating voltage of the memory chip, the power-down control unit slows down the rate of decrease of the target operating voltage so that the target time point when the target operating voltage decreases to the minimum operating voltage is after the reset time point of the controller, and the time length between the target time point and the reset time point is at least sufficient for the memory chip to execute the controller's control command once.
[0037] In some embodiments, the memory chip 102 receives a control command sent by the controller 101 when the operating voltage of the controller 101 drops to the reset voltage or before the operating voltage of the controller 101 drops to the reset voltage, and executes the completion control command before the target time point.
[0038] Specifically, when the operating voltage of the controller 101 drops to the reset voltage, or before the operating voltage of the controller 101 drops to the reset voltage, the controller 101 sends a control command to the memory chip 102, and the memory chip 102 begins to execute the control command. In order to ensure the smooth completion of the control command, the control command needs to be completed before the target operating voltage of the memory chip 102 drops to the target time point of the minimum operating voltage.
[0039] Based on this, it is only necessary to ensure that the time interval between the reset time point when the operating voltage of the controller 101 drops to the reset voltage and the target time point when the target operating voltage of the memory chip 102 drops to the minimum operating voltage satisfies the time required to execute one control command.
[0040] In some embodiments, when a power failure occurs, the operating voltage of the controller 101 and the target operating voltage of the memory chip 102 decrease from the same voltage value. By processing the rate of decrease of the target operating voltage of the memory chip 102, the operating voltage of the controller 101 decreases at a first rate and the target operating voltage of the memory chip 102 decreases at a second rate until it decreases to 0.
[0041] Furthermore, the second rate is less than the first rate, so that the target time point when the target operating voltage of the memory chip 102 drops to the minimum operating voltage is after the reset time point when the operating voltage of the controller 101 drops to the reset voltage, so as to ensure that the control command sent by the controller 101 when or before the reset voltage can be executed by the memory chip 102 when or before the target operating voltage drops to the minimum operating voltage.
[0042] like Figure 4As shown, the linear relationships between the voltage and time of controller 101 and memory chip 102 are v1(t) and v2(t), respectively. The voltages of controller 101 and memory chip 102 during normal operation are V1, meaning v1(t) and v2(t) partially overlap. During a power outage, the operating voltages of both controller 101 and memory chip 102 begin to decrease, but the rate of decrease differs between the operating voltage of controller 101 and the target operating voltage of memory chip 102. When controller 101 drops to the reset voltage V2 corresponding to time T1, controller 101 sends a control command, which memory chip 102 executes. The execution of the control command is completed before or when the target operating voltage of memory chip 102 drops to the minimum operating voltage corresponding to time T2. In other words, memory chip 102 completes one control command execution within the T1-T2 time period, with the control command being sent at time T1 or before time T1.
[0043] In some embodiments, the control instructions are erase instructions or programming instructions, and the time required for the memory chip 102 to complete the execution of erase instructions and programming instructions is different.
[0044] In one application scenario, the time taken for the memory chip 102 to complete one erase instruction is less than or equal to 10ms, and the time taken to complete one programming instruction is less than or equal to 750us. Specifically, when the control instruction is an erase instruction, the time interval T1-T2 is greater than or equal to 10ms, such as 10ms, 10.5ms, 11ms, 15ms, or 20ms; when the control instruction is a programming instruction, the time interval T1-T2 is greater than or equal to 750us, such as 750us, 760us, 770us, or 800us.
[0045] In some embodiments, the control instructions are erase instructions, read instructions, or write instructions, and the time required for the memory chip 102 to complete the execution of erase instructions, read instructions, and write instructions is different.
[0046] The power-down processing method for the memory chip 102 provided in some embodiments of this application can utilize the power-down control unit 103 to monitor the voltage of the memory chip 102 in real time. When the memory chip 102 loses power, the power-down control unit 103 controls the rate of voltage drop of the memory chip 102, so that the time when the voltage of the memory chip 102 drops to the minimum operating voltage is after the reset time of the controller 101, and the time interval between the two times satisfies the requirement to execute the control command of the controller 101 once, thus avoiding problems such as data loss due to incomplete execution of the control command.
[0047] In some embodiments, to ensure the normal operation of the controller 101 and the memory chip 102, the electronic device 10 further includes a power supply unit, such as... Figure 5 and Figure 6 As shown, Figure 5 and Figure 6 These are schematic diagrams of the electronic devices in some embodiments of this application.
[0048] exist Figure 5 In this device 10, there are a controller 101, a memory chip 102, a power-down control unit 103, and a power supply unit 104. The controller 101 and the power-down control unit 103 are respectively coupled to the memory chip 102, and the power-down control unit 103 and the controller 101 are respectively coupled to the power supply unit 104. The power supply unit 104 is configured to supply power to the controller 101 and to supply power to the memory chip 102 through the power-down control unit 103, so that the power-down control unit 103 can monitor the target operating voltage of the memory chip 102 to achieve, for example... Figure 3 The power-down handling method of the memory chip 102 shown.
[0049] The power supply unit 104 can be a battery, external DC power, or other sources.
[0050] In some embodiments, in response to a reduction in the target operating voltage provided by the power supply unit 104, the power-down control unit 103 may generate a voltage signal with a first falling slope and provide the voltage signal to the memory chip 102, so that the memory chip 102 reduces the target operating voltage according to the first falling slope (corresponding to the second rate mentioned above) of the received voltage signal; wherein, the first falling slope is less than the default power-down falling slope (corresponding to the first rate mentioned above).
[0051] exist Figure 6 In this device 10, there are a controller 101, a memory chip 102, a power-down control unit 103, a first power supply unit 1041, and a second power supply unit 1042. The controller 101 and the power-down control unit 103 are respectively coupled to the memory chip 102. The power-down control unit 103 is coupled to the first power supply unit 1041, and the controller 101 is coupled to the second power supply unit 1042. The first power supply unit 1041 is configured to supply power to the memory chip 102 through the power-down control unit 103, and the second power supply unit 1042 is configured to supply power to the controller 101. This allows the power-down control unit 103 to monitor the target operating voltage of the memory chip 102 to achieve the desired effect. Figure 3 The power-down handling method of the memory chip 102 shown.
[0052] The first power supply unit 1041 and the second power supply unit 1042 can be batteries, external DC power, or other sources.
[0053] In some embodiments, in response to a reduction in the target operating voltage provided by the first power supply unit 1041, the power-down control unit 103 may generate a voltage signal with a first falling slope and provide the voltage signal to the memory chip 102, so that the memory chip 102 reduces the target operating voltage according to the first falling slope corresponding to the received voltage signal; wherein the first falling slope is less than the default falling slope of power-down.
[0054] In some embodiments of this application, the electronic device 10 can use a power-down control unit 103 to monitor the target operating voltage of the memory chip 102, and when the target operating voltage drops, use the power-down control unit 103 to slow down the rate of decrease of the target operating voltage of the memory chip 102, so as to realize the power-down processing method of the memory chip 102.
[0055] See Figure 7 , Figure 7 This is a schematic diagram of the structure of a computer-readable and writable storage medium in some embodiments of this application. The computer-readable and writable storage medium 100 stores a computer program 1001. When the computer program 1001 is executed under the control of the controller 101, it is used to implement the power-down processing method described above, which will not be described in detail here.
[0056] The controller 101 involved in this application may be referred to as a CPU (Central Processing Unit), which may be an integrated circuit chip, or a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component.
[0057] The computer-readable and writable storage medium 100 used in this application includes various media such as USB flash drives and portable hard drives that can store program code and can be repeatedly rewritten.
[0058] In summary, the power-down processing method of the memory chip 102 provided in some embodiments of this application can significantly improve the probability of data errors caused by abnormal power failure. That is, it can reduce the situation where ECC (Error Checking and Correcting) does not report errors due to incomplete execution of control instructions, and can avoid the situation of reading erroneous data.
[0059] In addition, the power-down processing method of the storage chip 102 provided in some embodiments of this application can reduce the storage space requirement. That is, the requirement for dual data backup will be reduced, and only temporary storage during the data migration process needs to be done.
[0060] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A method for handling power-down events in a memory chip, wherein the memory chip is coupled to a controller, characterized in that, The memory chip is coupled to a power-down control unit, and the power-down processing method includes: The target operating voltage of the memory chip is monitored using the power-down control unit. The power-down control unit responds to a decrease in the target operating voltage of the memory chip by delaying the rate of decrease of the target operating voltage, so that the target time point when the target operating voltage decreases to the minimum operating voltage is after the reset time point of the controller, and the time length between the target time point and the reset time point is at least sufficient for the memory chip to execute the control command of the controller once.
2. The power-off handling method according to claim 1, characterized in that, The power-down control unit and the controller are respectively coupled to the power supply unit, which is configured to supply power to the controller and to supply power to the memory chip through the power-down control unit.
3. The power-off handling method according to claim 2, characterized in that, The power-down control unit, in response to a decrease in the target operating voltage provided by the power supply unit, generates a voltage signal with a first falling slope and provides the voltage signal to the memory chip; wherein the first falling slope is less than the default power-down falling slope.
4. The power-off handling method according to claim 2, characterized in that, The power supply unit includes a first power supply unit and a second power supply unit. The first power supply unit is configured to supply power to the memory chip through the power-down control unit, and the second power supply unit is configured to supply power to the controller.
5. The power-off handling method according to claim 4, characterized in that, The first power supply unit is coupled to the first terminal of the power-down control unit, and the memory chip is coupled to the second terminal of the power-down control unit; The power-down control unit, in response to a decrease in the target operating voltage provided by the first power supply unit, generates a voltage signal with a first falling slope and provides the voltage signal to the memory chip; wherein the first falling slope is less than the default power-down falling slope.
6. The power-off handling method according to claim 1, characterized in that, The memory chip receives the control command sent by the controller when the controller's operating voltage drops to the reset voltage or before the controller's operating voltage drops to the reset voltage, and executes the control command before the target time point.
7. The power-off handling method according to claim 1, characterized in that, The control command is either an erase command or a programming command, and the memory chip requires different execution times for the erase command and the programming command.
8. The power-off handling method according to claim 7, characterized in that, The time to complete one erase instruction is less than or equal to 10ms, and the time to complete one programming instruction is less than or equal to 750us.
9. An electronic device, characterized in that, The electronic device includes a controller, a memory chip, and a power-down control unit, wherein the memory chip is coupled to the controller and the power-down control unit, and the memory chip is used to implement the method according to any one of claims 1-8.
10. A computer-readable and writable storage medium, characterized in that, The computer-readable and writable storage medium stores a computer program, which, when executed by the controller, is used to implement the method described in any one of claims 1-8.