Clock synchronization device, optical transmitter and optical receiver

Abstract

Provided in an embodiment of the present invention are a clock synchronization device, an optical transmitter, and an optical receiver, which relate to the technical field of optical transmission networks, the clock synchronization device comprising: a phase discrimination module for obtaining first total phase error information based on a service recovery clock and a first phase-locked clock, the first phase-locked clock is obtained by a first phase lock of a digital-to-analog converter; the loop filter is used for obtaining first adjustment information based on the first total phase error information, so that the first phase lock obtains a second phase-locked clock based on the first adjustment information, and the digital-to-analog converter converts service data into analog data based on the second phase-locked clock, the service recovery clock is a sampling clock of the service data. According to the invention, the problem that the service transmission rate in the ODSP is not synchronous is solved, and the effect of improving the transmission performance of the system is further achieved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of optical transmission networks, and more specifically, to a clock synchronization device, an optical transmitter, and an optical receiver. Background Technology

[0002] With the explosive growth of data traffic, especially driven by technologies such as 5G, cloud computing, big data, and artificial intelligence, the demand for high capacity, high reliability, and large bandwidth in fiber optic communication is increasing day by day.

[0003] Among them, ODSP (Optical Digital Signal Processor) can effectively shape, compensate and optimize optical signals through advanced digital signal processing algorithms, thereby improving the transmission quality and efficiency of signals.

[0004] Accurate clock recovery and data synchronization in ODSP are crucial for maintaining network stability and reliability. However, a problem exists in related technologies where service transmission rates are out of sync within ODSP. Summary of the Invention

[0005] This invention provides a clock synchronization device, an optical transmitter, and an optical receiver to at least solve the problem of asynchronous service transmission rates in ODSP.

[0006] According to an embodiment of the present invention, a clock synchronization device is provided, comprising: a phase detection module, configured to obtain first total phase error information based on a service recovery clock and a first phase-locked clock, wherein the first phase-locked clock is obtained by a first phase-locked unit of a digital-to-analog converter; and a loop filter, configured to obtain first adjustment information based on the first total phase error information, so that the first phase-locked unit obtains a second phase-locked clock based on the first adjustment information, so that the digital-to-analog converter converts service data into analog data based on the second phase-locked clock, wherein the service recovery clock is a sampling clock for the service data.

[0007] According to another embodiment of the present invention, an optical transmitter is also provided, including a clock synchronization device as described in any of the preceding claims; a transmitter digital signal processor for inputting a service recovery clock to the clock synchronization device; and a digital-to-analog converter for inputting a first phase-locked clock to the clock synchronization device and converting service data into analog data based on a second phase-locked clock, wherein the second phase-locked clock is obtained by the clock synchronization device based on the first phase-locked clock.

[0008] According to another embodiment of the present invention, a clock synchronization device is also provided, comprising: a phase detection module, used to obtain second total phase error information based on a service recovery clock and a third phase-locked clock, wherein the third phase-locked clock is obtained by the second phase-locked unit of a serializer / deserializer;

[0009] A loop filter is used to obtain second adjustment information based on the second total phase error information, so that the second phase-locked loop (PLL) obtains a fourth phase-locked clock based on the second adjustment information, so that the serializer / deserializer converts the service data into serial data based on the fourth phase-locked clock, wherein the service recovery clock is the sampling clock of the service data.

[0010] According to another embodiment of the present invention, an optical receiver is also provided, comprising a clock synchronization device as described in any of the preceding claims; a framer for inputting a service recovery clock to the clock synchronization device; a serializer / deserializer for inputting a fourth phase-locked clock to the clock synchronization device, and for converting service data into serial data based on a fifth phase-locked clock, wherein the fifth phase-locked clock is obtained by the clock synchronization device based on the fourth phase-locked clock.

[0011] In one embodiment of the present invention, a phase detection module calculates a first total phase error based on the service recovery clock (i.e., the sampling clock of the service data) and a first phase-locked clock (obtained from the first phase-locked unit of the digital-to-analog converter). This enables the detection and quantification of the rate inconsistency between the ODSP output data and the received service data. The first phase-locked unit receives first adjustment information generated by the loop filter and adjusts its output accordingly to obtain a second phase-locked clock. This adjustment process aims to make the phase-locked clock more accurately match the service recovery clock, thereby avoiding data stream rate inconsistency. The digital-to-analog converter (DAC) uses the adjusted second phase-locked clock to convert the service data into analog data. Because the phase error between the second phase-locked clock and the service recovery clock is reduced, the sampling clock of the digital-to-analog converter is more accurately synchronized with the service recovery clock, thereby improving data transmission performance. Therefore, this application solves the rate inconsistency problem of ODSP during data transmission through precise clock synchronization technology, thereby improving data transmission performance. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a clock synchronization device and a digital-to-analog converter applied to an optical transmitter according to an embodiment of the present invention.

[0013] Figure 2 This is a schematic diagram of the phase detection module according to an embodiment of the present invention;

[0014] Figure 3This is a schematic diagram of the phase detector according to an embodiment of the present invention;

[0015] Figure 4 This is a schematic diagram of the structure of the first processing module according to an embodiment of the present invention;

[0016] Figure 5 This is a schematic diagram of the structure of the second processing module according to an embodiment of the present invention;

[0017] Figure 6 This is a schematic diagram of the structure of a loop filter according to an embodiment of the present invention;

[0018] Figure 7 This is a schematic diagram of the structure of the second filter according to an embodiment of the present invention;

[0019] Figure 8 This is a schematic diagram of the waterline adjustment module according to an embodiment of the present invention;

[0020] Figure 9 This is a schematic diagram of the structure of an optical transmitter according to an embodiment of the present invention;

[0021] Figure 10 This is a schematic diagram of the structure of an optical receiver according to an embodiment of the present invention. Detailed Implementation

[0022] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0024] A clock synchronization device is provided in this embodiment of the invention. Figure 1 This is a schematic diagram of a clock synchronization device and a digital-to-analog converter applied to an optical transmitter according to an embodiment of the present invention, as shown below. Figure 1 As shown, the clock synchronization device includes: a phase detector module and a loop filter. Among them,

[0025] The phase detection module is used to obtain the first total phase error information based on the service recovery clock and the first phase-locked clock, wherein the first phase-locked clock is obtained by the first phase-locked unit of the digital-to-analog converter;

[0026] A loop filter is used to obtain first adjustment information based on first total phase error information, so that a first phase-locked loop (PLL) obtains a second phase-locked clock based on the first adjustment information, so that a digital-to-analog converter converts service data into analog data based on the second phase-locked clock, wherein the service recovery clock is the sampling clock of the service data.

[0027] In one exemplary embodiment, the clock synchronization device can be applied to an optical transmitter. The clock synchronization device receives and analyzes the phase error between the service recovery clock and the first phase-locked clock using a phase detection module to obtain first total phase error information. Based on the first total phase error information, a loop filter obtains first adjustment information, thereby enabling the first phase-locked unit to synchronize the phase of the obtained second phase-locked clock with the phase of the service recovery clock based on the first adjustment information, thus achieving clock synchronization and ensuring consistent service rates.

[0028] In summary, through the above embodiments of the present invention, by utilizing the phase detection module to calculate the first total phase error information based on the service recovery clock (i.e., the sampling clock of the service data) and the first phase-locked clock (obtained from the first phase-locked unit of the digital-to-analog converter), the rate inconsistency problem between the ODSP output data and the received service data can be detected and quantified. The first phase-locked unit receives the first adjustment information generated by the loop filter and adjusts its output accordingly to obtain the second phase-locked clock. This adjustment process is to make the phase-locked clock more accurately match the service recovery clock, thereby avoiding data stream rate inconsistency. The digital-to-analog converter (DAC) uses the adjusted second phase-locked clock to convert the service data into analog data. Because the phase error between the second phase-locked clock and the service recovery clock is reduced, the sampling clock of the digital-to-analog converter is more accurately synchronized with the service recovery clock, thereby improving data transmission performance. Therefore, this application solves the rate inconsistency problem of ODSP during data transmission through precise clock synchronization technology, thereby improving data transmission performance. In one embodiment, Figure 2 This is a schematic diagram of the phase detection module according to an embodiment of the present invention, as shown below. Figure 2 As shown, the phase detection module includes: a phase detector, a waterline adjustment module, and a first adder. Among them,

[0029] A phase detector is used to obtain first phase error information based on the service recovery clock and the first phase-locked clock;

[0030] The waterline adjustment module is used to obtain the second phase error information based on the waterline of the cache container according to the business data flow;

[0031] The first adder is used to obtain the first total phase error information based on the first error information and the second error information.

[0032] In one exemplary implementation, a phase detector uses the service recovery clock as a reference signal and the first phase-locked clock as the signal to be synchronized. The phase difference between the service recovery clock and the first phase-locked clock is compared to obtain first phase error information. A waterline adjustment module compares the waterline of the service data stream's buffer container with a preset normal waterline range to obtain second phase error information based on the comparison result. A first adder accumulates the first and second error information to obtain first total phase error information, thereby determining the overall phase error between the service recovery clock and the first phase-locked clock.

[0033] In one implementation, Figure 3 This is a schematic diagram of the phase detector according to an embodiment of the present invention, as shown below. Figure 3 As shown, the phase detector includes: a first processing module and a second processing module. Among them,

[0034] The first processing module is used to obtain the third phase error information based on the service recovery clock and the first phase-locked clock.

[0035] The second processing module is used to merge integer data and decimal data to obtain the first phase error information, wherein the integer data and decimal data are obtained based on the third phase error information.

[0036] In one exemplary embodiment, the first processing module uses the service recovery clock and the first phase-locked clock to obtain the third phase error information, and obtains the pre-processed data. Then, the second processing module uses the third phase error information to process it again based on digital signal processing, so as to make the obtained first phase error information data more accurate.

[0037] In one implementation, Figure 4 This is a schematic diagram of the structure of the first processing module according to an embodiment of the present invention, as shown below. Figure 4 As shown, the first processing module includes: a first counter, a first multiplier, a second counter, a second multiplier, and a subtractor. Among them,

[0038] The first counter is used to count the service recovery clock and obtain the first count result;

[0039] The first multiplier is used to multiply the first counting result by a first preset multiple to obtain the second counting result;

[0040] The second counter is used to count the first phase-locked clock to obtain the third counting result;

[0041] The second multiplier is used to multiply the third counting result by a second preset multiple to obtain the fourth counting result;

[0042] The subtractor obtains the third phase error information based on the second and fourth count results;

[0043] The first preset multiple and the second preset multiple are obtained based on the frequency of the service recovery clock and the frequency of the first phase-locked clock.

[0044] In one exemplary implementation, the clock frequencies of the first counter and the second counter typically differ, for example, the ratio of their clock frequencies is L:M. A first multiplier multiplies the first count result obtained from the first counter by M to obtain a second count result. A second multiplier multiplies the third count result obtained from the second counter by L to obtain a fourth count result. This ensures that the counts from the first and second counters are consistent, facilitating comparison. A subtractor subtracts the second and fourth count results to obtain the third phase error information between the service recovery clock and the first phase-locked clock.

[0045] In one implementation, Figure 5 This is a schematic diagram of the structure of the second processing module according to an embodiment of the present invention, as shown below. Figure 5 As shown, the second processing module includes: a differential converter, a first integrator, a shifter, and a merging module. Among them,

[0046] The differential unit is used to perform differential operations on the third phase error information to obtain the differential operation result;

[0047] The first integrator is used to accumulate the results of the difference operation to obtain integer data;

[0048] A shifter is used to obtain fractional data based on third phase error information;

[0049] The merging module is used to merge integer and decimal data to obtain the first phase error information.

[0050] In one exemplary embodiment, a differential operation is performed on the third phase error information based on a differential converter to obtain the differential operation result. For example, the third phase error information of the previous cycle is subtracted from the third phase error information of the current cycle to obtain the operation result as the differential operation result. The differential operation result is then rounded to produce an output result of 0, 1, or -1. Within a preset time period, the differential operation results of 0, 1, or -1 output by the differential converter are accumulated based on the first integrator to obtain integer data. The third phase error information is shifted by a preset bit width using a shifter to obtain decimal data. The integer data and decimal data are merged using a merging module to obtain the first phase error information. Regarding the bit width of the clock counter, it is usually determined based on the bandwidth range of the clock following loop and the magnitude of the clock frequency deviation. The smaller the bandwidth of the clock following loop and the larger the clock frequency deviation, the larger the bit width of the counter. Based on the combination of the differential converter and the first integrator, the bit width of the first counter and the second counter can be effectively reduced. In one embodiment, Figure 6 This is a schematic diagram of the loop filter according to an embodiment of the present invention, as shown below. Figure 6 As shown, the loop filter includes: a first filter and a second filter. Wherein,

[0051] The first filter is used to smooth the first total phase error information to obtain a smoothing result;

[0052] The second filter is used to process the smoothing result using an algorithm to obtain the first adjustment information.

[0053] In one exemplary embodiment, the first filter may be an alpha filter to reduce noise and smooth the first total phase error information to obtain a smoothed result. The smoothed result is then processed by a preset algorithm based on the second filter to generate first adjustment information.

[0054] In one implementation, Figure 7 This is a schematic diagram of the structure of the second filter according to an embodiment of the present invention, as shown below. Figure 7 As shown, the second filter includes: a second integrator, a proportionalizer, and a second adder. Among them,

[0055] The second integrator is used to multiply the smoothing result by the integration factor and perform accumulation to obtain the integration result.

[0056] The scaler is used to multiply the smoothing result by a scaling factor to obtain the scaled result.

[0057] The second adder is used to obtain the first adjustment information based on the integral processing result and the proportional processing result.

[0058] In one exemplary implementation, the smoothing result is multiplied by an integration factor ki based on a second integrator to obtain a proportional processing result, and the smoothing result is multiplied by a proportional factor kp based on a proportionalizer to obtain another proportional processing result. The integral processing result and the proportional processing result are accumulated based on a second adder to obtain first adjustment information, such as a frequency control word fcode.

[0059] The reference formula for setting the integration factor ki can be: The reference formula for setting the scaling factor kp can be: The reference formula for setting the alpha filter parameter α can be:

[0060] Where K is the bandwidth of the clock follower loop, fs is the operating clock frequency of the phase detector and loop filter, kv is the gain of the phase-locked loop, m is a number greater than 1, indicating that the bandwidth of the alpha filter is greater than the bandwidth of the clock follower loop, L is the coefficient of the phase detector, which is set based on the actual situation, and floor(x) is the floor function.

[0061] In one implementation, Figure 8 This is a schematic diagram of the waterline adjustment module according to an embodiment of the present invention, as shown below. Figure 8 As shown, the waterline adjustment module includes: a comparator and a third processing module. Among them,

[0062] The comparator is used to compare the buffer waterline of the business data stream with a preset threshold to obtain the comparison result;

[0063] The third processing module is used to multiply the comparison result by the bandwidth factor and perform cumulative processing to obtain the second phase error information.

[0064] In one exemplary embodiment, a waterline adjustment module can be used to adjust the service rate between the service recovery clock domain and the phase-locked loop (PLL) clock domain. For example, when the entire clock synchronization device is in a convergent state, if the buffer container waterline in the waterline adjustment module deviates from a preset normal waterline range by more than a preset error range, the buffer container waterline can be adjusted to within the preset error range of the normal waterline range based on the waterline adjustment module. The waterline adjustment module compares the buffer container waterline with the preset normal waterline range to obtain a comparison result, which can be an indication signal updn. The indication signal updn can be 1, 0, or -1. A third processing module multiplies the comparison result by a bandwidth factor and performs accumulation processing to obtain second phase error information. The bandwidth configuration of the waterline adjustment module can be at least 5 to 10 times lower than the bandwidth configuration of the loop filter.

[0065] An optical transmitter is also provided in this embodiment of the invention. Figure 9 This is a schematic diagram of the structure of an optical transmitter according to an embodiment of the present invention, such as... Figure 9 As shown, the optical transmitter includes a clock synchronization device, a transmitting digital signal processor, and a digital-to-analog converter as described above. Among them,

[0066] The transmitter digital signal processor is used to input the service recovery clock to the clock synchronization device;

[0067] A digital-to-analog converter is used to input a first phase-locked clock to a clock synchronization device and to convert service data into analog data based on a second phase-locked clock, wherein the second phase-locked clock is obtained by the clock synchronization device based on the first phase-locked clock.

[0068] In one exemplary embodiment, the clock synchronization device receives service data and service recovery clock sent by the digital signal processor at the transmitting end, and receives a first phase-locked clock fed back by the first phase-locker of the digital-to-analog converter. The first adjustment information is obtained through the combined action of the phase detection module and the loop filter of the clock synchronization device, so that the first phase-locker obtains a second phase-locked clock based on the first adjustment information, and the digital-to-analog converter converts the service data into analog data based on the second phase-locked clock.

[0069] In one exemplary embodiment, the optical transmitter may further include a serializer / deserializer and a framer. The serializer / deserializer converts the high-speed serial data stream into parallel service data; the framer performs mapping and encapsulation operations on the parallel service data to the OTN (Optical Transport Network) frame structure. The transmitting end digital signal processor performs forward error correction (FEC) encoding, frame encapsulation, constellation mapping, shaping filtering, pre-compensation, and upsampling operations on the received OTN frames. The processed digital signal is then converted into an analog signal by a digital-to-analog converter to control the optical module to generate an optical signal, which is then transmitted into the optical fiber channel.

[0070] Because a frequency offset may exist between the client-side service recovery clock and the digital-to-analog converter clock within the transmitter's digital signal processor (DSP), prolonged use can cause abnormal states such as the waterline in the asynchronous waterline adjustment module within the transmitter's DSP being either empty or full, leading to data transmission errors. Therefore, employing any of the aforementioned clock synchronization devices can dynamically adjust the DSP clock based on the service recovery clock, ensuring no sampling frequency offset between the transmitter's DSP clock and the DSP clock, thus achieving consistent service rates.

[0071] This invention also provides a clock synchronization device, including a phase detection module and a loop filter.

[0072] The phase detection module is used to obtain the second total phase error information based on the service recovery clock and the third phase-locked clock, wherein the third phase-locked clock is obtained by the second phase-locked unit of the serializer / deserializer;

[0073] A loop filter is used to obtain second adjustment information based on second total phase error information, so that the second phase-locked loop (PLL) obtains a fourth phase-locked clock based on the second adjustment information, so that the serializer / deserializer converts service data into serial data based on the fourth phase-locked clock. The service recovery clock is the sampling clock of the service data.

[0074] In one exemplary embodiment, the clock synchronization device can be applied to an optical receiver. The clock synchronization device receives and analyzes the phase error between the service recovery clock and the third phase-locked clock using a phase detection module to obtain second total phase error information. Based on the second total phase error information, a loop filter obtains second adjustment information, thereby enabling the second phase-locked unit to synchronize the phase of the obtained fourth phase-locked clock with the phase of the service recovery clock based on the second adjustment information, thus achieving clock synchronization and ensuring consistent service rates.

[0075] In summary, through the above embodiments of the present invention, by utilizing the phase detection module to calculate the second total phase error information based on the service recovery clock (i.e., the sampling clock of the service data) and the third phase-locked clock (obtained from the second phase-locked unit of the serializer / deserializer), the rate inconsistency problem between the ODSP output data and the received service data can be detected and quantified. The second phase-locked unit receives the second adjustment information generated by the loop filter and adjusts its output accordingly to obtain the fourth phase-locked clock. This adjustment process is to make the phase-locked clock more accurately match the service recovery clock, thereby avoiding data flow rate inconsistency. The serializer / deserializer uses the adjusted fourth phase-locked clock to convert multiple parallel service data into serial service data. Because the phase error between the fourth phase-locked clock and the service recovery clock is reduced, the sampling clock of the serializer / deserializer is more accurately synchronized with the service recovery clock, thereby improving data transmission performance. Therefore, this application solves the rate inconsistency problem of ODSP during data transmission through precise clock synchronization technology, thereby improving data transmission performance.

[0076] In one embodiment, the phase detection module includes: a phase detector, a waterline adjustment module, and a first adder.

[0077] A phase detector is used to obtain fourth phase error information based on the service recovery clock and the third phase-locked clock;

[0078] The waterline adjustment module is used to obtain the fifth phase error information based on the waterline of the cache container according to the business data flow;

[0079] The first adder is used to obtain the second total phase error information based on the fourth and fifth error information.

[0080] In one exemplary implementation, a phase detector uses the service recovery clock as a reference signal and the third phase-locked clock as the signal to be synchronized. The phase difference between the service recovery clock and the third phase-locked clock is compared to obtain fourth phase error information. A waterline adjustment module compares the waterline of the service data stream's buffer container with a preset normal waterline range to obtain fifth phase error information based on the comparison result. A first adder accumulates the fourth and fifth error information to obtain second total phase error information, thus determining the overall phase error between the service recovery clock and the third phase-locked clock.

[0081] In one embodiment, the phase detector includes: a first processing module and a second processing module.

[0082] The first processing module is used to obtain the sixth phase error information based on the service recovery clock and the third phase-locked clock.

[0083] The second processing module is used to merge integer data and decimal data to obtain the fourth phase error information, wherein the integer data and decimal data are obtained based on the sixth phase error information.

[0084] In one exemplary embodiment, the first processing module uses the service recovery clock and the third phase-locked clock to obtain the sixth phase error information, and obtains the pre-processed data. Then, the second processing module uses the sixth phase error information to process it again based on digital signal processing, so that the obtained fourth phase error information data is more accurate.

[0085] In one embodiment, the first processing module includes: a first counter, a first multiplier, a second counter, a second multiplier, and a subtractor.

[0086] The first counter is used to count the service recovery clock and obtain the fifth count result;

[0087] The first multiplier is used to multiply the fifth count result by the third preset multiple to obtain the sixth count result;

[0088] The second counter is used to count the fourth phase-locked clock to obtain the seventh count result;

[0089] The second multiplier is used to multiply the seventh counting result by the fourth preset multiple to obtain the eighth counting result;

[0090] The subtractor obtains the sixth phase error information based on the sixth and eighth count results;

[0091] The third and fourth preset multiples are obtained based on the frequency of the service recovery clock and the frequency of the fourth phase-locked clock.

[0092] In one exemplary implementation, the clock frequencies of the first counter and the second counter typically differ; for example, the ratio of their clock frequencies is L:M. A first multiplier multiplies the fifth count result obtained from the first counter by M to obtain a sixth count result. A second multiplier multiplies the seventh count result obtained from the second counter by L to obtain an eighth count result. This ensures that the counts from the first and second counters are consistent, facilitating comparison. A subtractor subtracts the sixth and eighth count results to obtain the sixth phase error information between the service recovery clock and the first phase-locked clock.

[0093] In one embodiment, the second processing module includes: a differential converter, a first integrator, a shifter, and a merging module.

[0094] The differential unit is used to perform differential operations on the sixth phase error information to obtain the differential operation result;

[0095] The first integrator is used to accumulate the results of the difference operation to obtain integer data;

[0096] A shifter is used to obtain fractional data based on the sixth phase error information;

[0097] The merging module is used to merge integer and decimal data to obtain the fourth phase error information.

[0098] In one exemplary implementation, the sixth phase error information is differentially processed using a differential converter to obtain a differential operation result. For example, the sixth phase error information of the previous cycle is subtracted from the sixth phase error information of the current cycle to obtain the differential operation result. This result is then rounded to an output of 0, 1, or -1. Within a preset time period, the differential operation results (0, 1, or -1) output by the differential converter are accumulated using a first integrator to obtain integer data. The sixth phase error information is shifted by a preset bit width using a shifter to obtain decimal data. The integer and decimal data are then merged using a merging module to obtain the fourth phase error information. The bit width of the clock counter is typically determined based on the bandwidth range of the clock follower loop and the magnitude of the clock frequency offset. The smaller the bandwidth of the clock follower loop and the larger the clock frequency offset, the larger the bit width of the counter. The combination of the differential converter and the first integrator can effectively reduce the bit width of both the first and second counters.

[0099] In one embodiment, the loop filter includes: a first filter and a second filter.

[0100] The first filter is used to smooth the second total phase error information to obtain a smoothing result;

[0101] The second filter is used to process the smoothing result using an algorithm to obtain the second adjustment information.

[0102] In one exemplary embodiment, the first filter may be an alpha filter to reduce noise and smooth the second total phase error information to obtain a smoothed result. The smoothed result is then processed by a preset algorithm based on the second filter to generate second adjustment information.

[0103] In one embodiment, the second filter includes a second integrator, a proportionalizer, and a second adder. The second integrator is used to multiply the smoothing result by an integration factor and perform accumulation processing to obtain the integral processing result.

[0104] The scaler is used to multiply the smoothing result by a scaling factor to obtain the scaled result.

[0105] The second adder is used to obtain the second adjustment information based on the integral processing result and the proportional processing result.

[0106] In one exemplary implementation, the smoothing result is multiplied by an integration factor ki based on a second integrator to obtain a proportional processing result, and the smoothing result is multiplied by a proportional factor kp based on a proportionalizer to obtain another proportional processing result. The integral processing result and the proportional processing result are accumulated based on a second adder to obtain second adjustment information, such as a frequency control word fcode.

[0107] The reference formula for setting the integration factor ki can be: The reference formula for setting the scaling factor kp can be: The reference formula for setting the alpha filter parameter α can be:

[0108] Where K is the bandwidth of the clock follower loop, fs is the operating clock frequency of the phase detector and loop filter, kv is the gain of the phase-locked loop, m is a number greater than 1, indicating that the bandwidth of the alpha filter is greater than the bandwidth of the clock follower loop, L is the coefficient of the phase detector, which is set based on the actual situation, and floor(x) is the floor function.

[0109] In one embodiment, the waterline adjustment module includes: a comparator and a third processing module.

[0110] The comparator is used to compare the buffer waterline of the business data stream with a preset threshold to obtain the comparison result;

[0111] The third processing module is used to multiply the comparison result by the bandwidth factor and perform cumulative processing to obtain the fifth phase error information.

[0112] In one exemplary embodiment, a waterline adjustment module can be used to adjust the service rate between the service recovery clock domain and the phase-locked loop (PLL) clock domain. For example, when the entire clock synchronization device is in a convergent state, if the buffer container waterline in the waterline adjustment module deviates from a preset normal waterline range by more than a preset error range, the buffer container waterline can be adjusted to within the preset error range of the normal waterline range based on the waterline adjustment module. The waterline adjustment module compares the buffer container waterline with the preset normal waterline range to obtain a comparison result, which can be an indication signal updn. The indication signal updn can be 1, 0, or -1. A third processing module multiplies the comparison result by a bandwidth factor and performs accumulation processing to obtain second phase error information. The bandwidth configuration of the waterline adjustment module can be at least 5 to 10 times lower than the bandwidth configuration of the loop filter.

[0113] This embodiment also provides an optical receiver. Figure 10 This is a schematic diagram of the structure of an optical receiver according to an embodiment of the present invention, as shown below. Figure 10 As shown, the optical receiver includes a clock synchronization device, a framer, and a serializer / deserializer as described above.

[0114] in,

[0115] A framer is used to input the service recovery clock into the clock synchronization device;

[0116] The serializer / deserializer is used to input the fourth phase-locked clock to the clock synchronization device and to convert service data into serial data based on the fifth phase-locked clock, wherein the fifth phase-locked clock is obtained by the clock synchronization device based on the fourth phase-locked clock.

[0117] In one exemplary embodiment, the clock synchronization device receives service data and service recovery clock sent by the framer, and receives a fourth phase-locked clock fed back by the second phase-locked unit of the serializer / deserializer. The second adjustment information is obtained through the combined action of the phase detection module and the loop filter of the clock synchronization device, so that the second phase-locked unit obtains a fifth phase-locked clock based on the second adjustment information, so that the serializer / deserializer converts the multiple parallel service data sent by the framer into serial service data based on the fifth phase-locked clock.

[0118] In one exemplary embodiment, the optical receiver may further include: an analog-to-digital converter (ADC) and a receiving-end digital signal processor (DSP). The optical receiver receives an optical signal from the optical fiber channel and converts the optical signal into an analog electrical signal. The ADC samples the analog electrical signal into a digital signal. The DSP performs optical channel impairment compensation on the digital signal, which may include delay compensation, dispersion compensation, polarization demultiplexing, carrier recovery, etc., and then performs FEC decoding to extract the OTN frame structure. A framer deframes the OTN frame to obtain multiple parallel service data streams. A serializer / deserializer converts the multiple parallel service data streams into high-speed serial service data.

[0119] Since the operating clock of the framer and the operating clock of the serializer / deserializer are not from the same source, there will be a frequency offset between them. Therefore, by using any of the above-mentioned clock synchronization devices, the operating clock of the serializer / deserializer is adjusted to follow the service recovery clock decoded by the framer, so as to achieve the effect of consistent data rate.

[0120] In one embodiment, the clock synchronization device is further equipped with an automatic bandwidth switching mechanism to reduce clock jitter and improve clock accuracy.

[0121] In one exemplary embodiment, when the clock synchronization device is first powered on, the loop filter is configured with a first bandwidth to enable rapid convergence of the clock synchronization device. The smoothing result obtained after smoothing by the first filter can be identified and analyzed to determine the convergence state of the clock synchronization device. For example, if the smoothing result for a consecutive preset number of beats is determined to be less than a threshold value, the clock synchronization device is determined to be in a convergent state, and the loop filter is configured with a second bandwidth to reduce clock jitter. At a certain moment, if the smoothing result for a consecutive preset number of beats is determined to be greater than or equal to the threshold value, the clock synchronization device is determined to transition from a convergent state to a non-convergent state, and the loop filter is configured with the first bandwidth to accelerate clock following. The first bandwidth is greater than the second bandwidth.

[0122] In summary, configuring an automatic bandwidth switching mechanism for the clock synchronization device can quickly and adaptively track the first total phase error information or the second total phase error information, and effectively reduce the clock jitter of the first phase-locked loop and the second phase-locked loop, thereby improving the cascade performance of the optical transmitter and the optical receiver.

[0123] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0124] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A clock synchronization device, characterized in that, include: The phase detection module is used to obtain first total phase error information based on the service recovery clock and the first phase-locked clock, wherein the first phase-locked clock is obtained by the first phase-locked unit of the digital-to-analog converter; A loop filter is used to obtain first adjustment information based on the first total phase error information, so that the first phase-locked loop (PLL) obtains a second phase-locked clock based on the first adjustment information, so that the digital-to-analog converter converts service data into analog data based on the second PLL, wherein the service recovery clock is the sampling clock of the service data.

2. The clock synchronization device according to claim 1, characterized in that, The phase detection module includes: A phase detector is used to obtain first phase error information based on the service recovery clock and the first phase-locked clock; The waterline adjustment module is used to obtain the second phase error information based on the waterline of the cache container according to the business data flow; A first adder is used to obtain the first total phase error information based on the first error information and the second error information.

3. The clock synchronization device according to claim 2, characterized in that, The phase detector includes: The first processing module is used to obtain third phase error information based on the service recovery clock and the first phase-locked clock; The second processing module is used to merge integer data and decimal data to obtain the first phase error information, wherein the integer data and decimal data are obtained based on the third phase error information.

4. The clock synchronization device according to claim 3, characterized in that, The first processing module includes: A first counter is used to count the service recovery clock to obtain a first counting result; A first multiplier is used to multiply the first counting result by a first preset multiple to obtain a second counting result; The second counter is used to count the first phase-locked clock to obtain a third counting result; The second multiplier is used to multiply the third counting result by a second preset multiple to obtain the fourth counting result; The subtractor obtains the third phase error information based on the second counting result and the fourth counting result; The first preset multiple and the second preset multiple are obtained based on the frequency of the service recovery clock and the frequency of the first phase-locked clock.

5. The clock synchronization device according to claim 3, characterized in that, The second processing module includes: A differential converter is used to perform differential operations on the third phase error information to obtain the differential operation result; A first integrator is used to accumulate the difference operation results to obtain the integer data; A shifter is used to obtain the fractional data based on the third phase error information; The merging module is used to merge the integer data and the decimal data to obtain the first phase error information.

6. The clock synchronization device according to claim 1, characterized in that, The loop filter includes: The first filter is used to smooth the first total phase error information to obtain a smoothing result. The second filter is used to process the smoothing result using an algorithm to obtain the first adjustment information.

7. The clock synchronization device according to claim 6, characterized in that, The second filter includes: The second integrator is used to multiply the smoothing result by an integration factor and perform accumulation processing to obtain the integration result. A scaler is used to multiply the smoothing result by a scaling factor to obtain a scaling result. The second adder is used to obtain the first adjustment information based on the integral processing result and the proportional processing result.

8. The clock synchronization device according to claim 2, characterized in that, The waterline adjustment module includes: A comparator is used to compare the buffer container waterline of the business data stream with a preset threshold to obtain a comparison result; The third processing module is used to multiply the comparison result by a bandwidth factor and perform accumulation processing to obtain the second phase error information.

9. An optical transmitter, characterized in that, include: The clock synchronization device as described in any one of claims 1 to 8; The transmitting end digital signal processor is used to input the service recovery clock to the clock synchronization device; A digital-to-analog converter is used to input a first phase-locked clock to the clock synchronization device and to convert service data into analog data based on a second phase-locked clock, wherein the second phase-locked clock is obtained by the clock synchronization device based on the first phase-locked clock.

10. A clock synchronization device, characterized in that, include: The phase detection module is used to obtain the second total phase error information based on the service recovery clock and the third phase-locked clock, wherein the third phase-locked clock is obtained by the second phase-locked unit of the serializer / deserializer; A loop filter is used to obtain second adjustment information based on the second total phase error information, so that the second phase-locked loop (PLL) obtains a fourth phase-locked clock based on the second adjustment information, so that the serializer / deserializer converts the service data into serial data based on the fourth phase-locked clock, wherein the service recovery clock is the sampling clock of the service data.

11. The clock synchronization device according to claim 10, characterized in that, The phase detection module includes: A phase detector is used to obtain fourth phase error information based on the service recovery clock and the third phase-locked clock; The waterline adjustment module is used to obtain the fifth phase error information based on the waterline of the cache container according to the business data flow; A first adder is used to obtain the second total phase error information based on the fourth error information and the fifth error information.

12. The clock synchronization device according to claim 11, characterized in that, The phase detector includes: The first processing module is used to obtain the sixth phase error information based on the service recovery clock and the third phase-locked clock; The second processing module is used to merge integer data and decimal data to obtain the fourth phase error information, wherein the integer data and decimal data are obtained based on the sixth phase error information.

13. The clock synchronization device according to claim 12, characterized in that, The first processing module includes: The first counter is used to count the service recovery clock to obtain the fifth count result; The first multiplier is used to multiply the fifth counting result by a third preset multiple to obtain the sixth counting result; The second counter is used to count the fourth phase-locked clock to obtain the seventh counting result; The second multiplier is used to multiply the seventh counting result by a fourth preset multiple to obtain the eighth counting result; The subtractor obtains the sixth phase error information based on the sixth counting result and the eighth counting result; The third preset multiple and the fourth preset multiple are obtained based on the frequency of the service recovery clock and the frequency of the fourth phase-locked clock.

14. The clock synchronization device according to claim 12, characterized in that, The second processing module includes: A differential converter is used to perform differential operations on the sixth phase error information to obtain the differential operation result; A first integrator is used to accumulate the difference operation results to obtain the integer data; A shifter is used to obtain the fractional data based on the sixth phase error information; The merging module is used to merge the integer data and the decimal data to obtain the fourth phase error information.

15. The clock synchronization device according to claim 10, characterized in that, The loop filter includes: The first filter is used to smooth the second total phase error information to obtain a smoothing result; The second filter is used to perform algorithmic processing on the smoothing result to obtain the second adjustment information.

16. The clock synchronization device according to claim 15, characterized in that, The second filter includes: The second integrator is used to multiply the smoothing result by an integration factor and perform accumulation processing to obtain the integration result. A scaler is used to multiply the smoothing result by a scaling factor to obtain a scaling result. A second adder is used to obtain the second adjustment information based on the integral processing result and the proportional processing result.

17. The clock synchronization device according to claim 11, characterized in that, The waterline adjustment module includes: A comparator is used to compare the buffer container waterline of the business data stream with a preset threshold to obtain a comparison result; The third processing module is used to multiply the comparison result by the bandwidth factor and perform accumulation processing to obtain the fifth phase error information.

18. An optical receiver, characterized in that, include: The clock synchronization device as described in any one of claims 10 to 17; A framer is used to input a service recovery clock into the clock synchronization device; A serializer / deserializer is used to input a fourth phase-locked clock to the clock synchronization device and to convert service data into serial data based on a fifth phase-locked clock, wherein the fifth phase-locked clock is obtained by the clock synchronization device based on the fourth phase-locked clock.

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