Clock fault interference suppression method and related device

Abstract

The embodiment of the invention provides a clock fault interference suppression method and a related device, after a clock node detects a clock fault, the clock node sends clock fault suppression information to a corresponding slave clock node so as to suppress the slave clock node from generating indication information corresponding to the clock fault. And interference on maintenance and processing of clock faults due to generation of excessive indication information is avoided.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a method and related apparatus for suppressing clock fault interference. Background Technology

[0002] With the continuous development of communication networks, the requirements for time synchronization accuracy are becoming increasingly stringent, leading to the emergence of more and more precise time synchronization protocols. For example, the G.8275.1 protocol is a telecommunications application protocol defined by the International Telecommunication Union-Telecommunication Standardization Sector (ITU-T) based on the IEEE 1588 protocol. To meet the needs of different scenarios, clock nodes typically have a master-slave hierarchical structure. In this structure, the master clock node sends synchronization information to its corresponding slave clock node, and the slave clock node adjusts its clock according to the received synchronization information to achieve time synchronization.

[0003] However, in real-world scenarios, each clock node typically has multiple slave clock nodes. For example, clock node 1 has two slave clock nodes: clock node 2 and clock node 3, and clock node 2 has two slave clock nodes: clock node 4 and clock node 5. If a clock fault occurs at clock node 1, since its multiple slave clock nodes are all time-synchronized based on clock node 1, multiple slave clock nodes will also generate corresponding clock faults. This results in multiple fault alarms due to the same clock fault, which interferes with the maintenance of clock faults and affects the speed and efficiency of clock fault location and resolution. Summary of the Invention

[0004] This application provides a clock fault interference suppression method and related apparatus, which sends clock fault suppression information to its slave clock nodes to suppress the generation of indication information by the slave clock nodes, thereby avoiding multiple indication information generated by multiple clock nodes and reducing interference of indication information.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] In a first aspect, a clock fault interference suppression method is provided, applied to a clock node. The method includes: after detecting a clock fault, sending first clock fault suppression information to a slave clock node of the clock node, wherein the first clock fault suppression information is used to suppress the generation of indication information, and the indication information is used to indicate that a clock fault has occurred in the slave clock node.

[0007] For multiple clock nodes, when one clock node detects a clock fault, clock fault suppression information is sent to its slave clock nodes to suppress the generation of multiple indication information by multiple slave clock nodes, so as to avoid multiple clock nodes generating multiple indication information and affecting the location of the clock fault.

[0008] Optionally, after detecting a clock fault, the clock node can generate indication information and send clock fault suppression information to its slave clock nodes to suppress the generation of indication information by the slave clock nodes. Thus, for a specific clock fault, the first clock node to detect the fault generates indication information, and its slave clock nodes are suppressed from generating indication information, allowing users or network management to quickly locate and maintain the clock fault based on the indication information.

[0009] Optionally, the clock fault suppression information is also used to instruct the slave clock node of the clock node to send clock fault suppression information to the corresponding slave clock node, thereby realizing the successive suppression of multiple slave clock nodes in the master-slave relationship structure. For example, if clock node 1 is the master clock node of clock node 2 and clock node 2 is the master clock node of clock node 3, then clock node 1 can suppress clock node 2 from generating indication information, and clock node 2 can suppress clock node 3 from generating indication information.

[0010] In some implementations of the first aspect, after sending the first clock fault suppression information to the slave clock node, the method further includes: sending clock fault suppression release information to the slave clock node, the clock fault suppression release information being used to release the suppression on generating the indication information. Thus, a clock node releases the suppression on its slave clock node generating indication information by sending the clock fault suppression release information to its slave clock node. After the slave clock node is released, it detects a clock fault and can generate indication information.

[0011] Optionally, after detecting clock fault recovery, a clock fault suppression release message is sent to the slave clock node to avoid the clock node being unable to report clock fault indication information due to excessive suppression time.

[0012] In some implementations of the first aspect, the method further includes: sending suppression enable information to the second clock node, the suppression enable information being used to enable the suppression of the function of generating indication information, first clock fault suppression information.

[0013] Thus, the function of suppressing the generation of indication information can be configured for multiple clock nodes according to user needs. The function of suppressing the generation of indication information of a clock node can be enabled by suppressing the information. That is, after receiving the suppression enable information, the clock node can suppress the generation of the indication information according to the received first clock fault suppression information; if the clock node does not receive the suppression enable information, it cannot suppress the generation of the indication information according to the received first clock fault suppression information.

[0014] In some implementations of the first aspect, the method further includes: sending suppression shutdown information to the second clock node, the suppression shutdown information being used to disable the function of suppressing the generation of indication information. Thus, the function of suppressing the generation of indication information by multiple clock nodes can be disabled according to user needs. After disabling the function of suppressing the generation of indication information by a clock node, the generation of the indication information cannot be suppressed based on the received first clock fault suppression information, or the indication information can be generated after a clock fault is detected; if a clock node does not receive suppression shutdown information, the generation of the indication information can be suppressed based on the received first clock fault suppression information.

[0015] In some implementations of the first aspect, the method further includes: sending a set time to the slave clock node, the set time indicating that the function of suppressing the generation of indication information is deactivated after a set time has elapsed. The set time limits the time during which the clock node enables the function of suppressing the generation of indication information.

[0016] In some implementations of the first aspect, the detection of a clock fault includes at least one of the following three: failure to receive synchronization information from the master clock node within a preset time period; receiving synchronization information from the master clock node and detecting an anomaly in the synchronization information; or detecting a node fault in the clock node, preventing the clock node from performing time synchronization. The clock node receives synchronization information from its corresponding master clock node and performs time synchronization based on the received synchronization information. If the communication link between the clock node and its corresponding master clock node fails, the clock node cannot receive synchronization information from its master clock node. If the master clock node fails, it may cause the clock to receive abnormal synchronization information, such as discontinuous timestamps in the synchronization information, preventing the clock node from performing time synchronization based on the synchronization information. If the clock node experiences a hardware fault related to time synchronization, such as a clock chip failure, a clock chip failure will also prevent the clock node from performing time synchronization.

[0017] In some implementations of the first aspect, sending the first clock fault suppression information to the slave clock node of the clock node includes: sending a Precision Time Protocol (PTP) message to the slave clock node, wherein the PTP message includes a Type Length Value (TLV) and the TLV includes the first clock fault suppression information, or the PTP message includes a PTP message header and the PTP message header includes a message type, the message type being used to indicate the first clock fault suppression information. Clock nodes can transmit the first clock fault suppression information through PTP messages. This can be achieved by extending the TLV in the PTP message to carry the first clock fault suppression information, or by extending the message type of the PTP message to indicate that the PTP message is used to suppress the generation of indication information; that is, the function of the first clock fault suppression information is implemented through PTP messages.

[0018] In some implementations of the first aspect, the first clock fault suppression information includes a clock fault identifier, and the first clock fault suppression information is used to suppress the generation of indication information corresponding to the clock fault identifier. Thus, by using the clock fault identifier, the generation of indication information corresponding to the clock fault identifier from the clock node is suppressed, while other types of indication information are not suppressed, thereby achieving precise suppression.

[0019] Secondly, a clock fault interference suppression method is provided, applied to a clock node, the method comprising: receiving first clock fault suppression information sent by the master clock node of the clock node, the first clock fault suppression information being used to suppress the generation of indication information, the indication information being used to indicate that the clock node has experienced a clock fault.

[0020] In some implementations of the second aspect, the method further includes: receiving first clock fault suppression release information sent by the master clock node, wherein the first clock fault suppression release information is used to release the suppression of generating the indication information.

[0021] In some implementations of the second aspect, the method further includes: receiving suppression enable information sent by the master clock node, the suppression enable information being used to enable the function of suppressing the generation of indication information.

[0022] In some implementations of the second aspect, the method further includes: receiving suppression shutdown information sent by the master clock node, the suppression shutdown information being used to disable the function of suppressing the generation of indication information.

[0023] In some implementations of the second aspect, the method further includes: sending second clock fault suppression information to the slave clock node, the second clock fault suppression information being used to suppress the generation of indication information.

[0024] In some implementations of the second aspect, the method further includes: sending a second clock fault suppression release information to the slave clock node, the second clock fault suppression release information being used to release the suppression of generating the indication information.

[0025] In some implementations of the second aspect, the method further includes: receiving a set time sent by the master clock node, the set time being used to indicate that after the set time has elapsed, the function of suppressing the generation of indication information is de-enabled.

[0026] In some implementations of the second aspect, receiving the first clock fault suppression information sent by the master clock node of the clock node includes:

[0027] The system receives a Precision Time Protocol (PTP) message sent by the master clock node. The PTP message includes a Type Length Value (TLV), and the TLV includes first clock fault suppression information. Alternatively, the PTP message includes a PTP message header, and the PTP message header includes a message type, which is used to indicate the first clock fault suppression information.

[0028] Thirdly, a clock fault interference suppression method is provided, applied to a management node. The method includes: receiving indication information sent by at least two clock nodes, the indication information indicating a clock fault in the clock nodes; presenting the indication information of a target clock node among the at least two clock nodes according to clock tracking path information, and suppressing the presentation of indication information of slave clock nodes of the target clock node. The clock tracking path information describes the master-slave relationship between the at least two clock nodes, and the target clock node is the master clock node of the other clock nodes among the at least two clock nodes. Thus, if the management node receives missing fault indication information sent by multiple clock nodes, it can suppress the indication information of other missing nodes according to the clock tracking path and present the indication information of the master clock node, thereby avoiding interference from clock fault indications of multiple slave clock nodes to fault maintenance.

[0029] Fourthly, a clock fault interference suppression device is provided, the device comprising a unit for performing any of the methods described in the first aspect or a unit for performing any of the methods described in the second aspect.

[0030] Fifthly, a network device is provided, comprising: a memory including computer-readable instructions; and a processor communicating with the memory, the processor being configured to execute the computer-readable instructions, causing the network device to perform the clock fault interference suppression method described in any one of the first, second, or third aspects.

[0031] A sixth aspect provides a computer-readable storage medium including a program or instructions that, when executed by a processor, implement the clock fault interference suppression method as described in any one of the first, second, or third aspects.

[0032] In a seventh aspect, a chip is provided, including a processor for retrieving and executing instructions stored in a memory, causing a network device on which the chip is installed to perform the clock fault interference suppression method described in any one of the first, second, or third aspects.

[0033] Eighthly, a computer program product is provided, the computer program product including instructions that, when executed by a computer, implement the method as described in any one of the first, second, or third aspects.

[0034] The beneficial effects of each possible implementation of the clock fault interference suppression method provided in the second aspect, the clock fault interference suppression method provided in the third aspect, the clock fault interference suppression device provided in the fourth aspect, the network device provided in the fifth aspect, the computer-readable storage medium provided in the sixth aspect, the chip provided in the seventh aspect, and the computer program product provided in the eighth aspect of the embodiments of this application can be referred to the descriptions of the various possible implementations in the first aspect, and will not be repeated here. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a master-slave hierarchical structure;

[0036] Figure 2 A flowchart illustrating a clock fault interference suppression method provided in an embodiment of this application;

[0037] Figure 3 This is a schematic diagram of a PTP message format;

[0038] Figure 4 A flowchart illustrating a clock fault interference suppression method provided in an embodiment of this application;

[0039] Figure 5 This is a schematic diagram of another master-slave hierarchical structure;

[0040] Figure 6 This is a schematic diagram of a clock fault interference suppression device provided in an embodiment of this application.

[0041] Figure 7 This is a schematic diagram of a clock fault interference suppression device provided in an embodiment of this application.

[0042] Figure 8 This is a schematic diagram of the structure of a network device provided in an embodiment of this application. Detailed Implementation

[0043] The technical solutions in this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments in this specification, and not all of them.

[0044] With the continuous development of communication networks, the requirements for the accuracy of time synchronization are becoming increasingly stringent, leading to the emergence of more and more precise time synchronization protocols, such as the G.8275.1 protocol. To meet the needs of different scenarios, clock nodes have a master-slave hierarchical structure. In this hierarchy, the master clock node provides synchronization information to its corresponding slave clock node, and the slave clock node adjusts its clock based on the received synchronization information to achieve time synchronization.

[0045] Figure 1 This is a schematic diagram of a master-slave hierarchical structure. Figure 1 The master-slave hierarchy in the system includes multiple clock nodes. In this hierarchy, the node that publishes synchronization information is called the master node or master clock node (hereinafter referred to as the master clock node), while the node that receives synchronization information is called the slave node or slave clock node (hereinafter referred to as the slave clock node). The slave clock nodes synchronize their time based on the received synchronization information. The clock on the master clock node is called the master clock, and the clock on the slave clock node is called the slave clock.

[0046] Figure 1 In this system, clock node 1 serves as the master clock node for clock nodes 2 and 3, while clock nodes 2 and 3 are slave clock nodes of clock node 1. That is, the clock of clock node 1 is the master clock of clock nodes 2 and 3, and the clocks of clock nodes 2 and 3 are slave clocks of clock node 1. Clock node 3 serves as the master clock node for clock nodes 4 and 5, and clock node 4 serves as the master clock node for clock nodes 6 and 7.

[0047] If a clock fault is detected at clock node 3, such as incorrect clock data configuration or failure to load, or an incorrect clock frame DIP switch setting, causing clock node 3 to lose lock, a clock fault alarm will be generated. The synchronization information received by the slave clock nodes from clock node 3 will become inaccurate or unstable, leading to a decrease in the clock quality of the slave clock nodes and subsequent lock loss. Clock nodes 4, 5, 6, and 7 will also generate clock fault alarms. If there are many slave clock nodes in the master-slave hierarchy, a large number of clock fault alarms will be generated successively. This large number of alarms will interfere with clock fault maintenance, affecting the speed and efficiency of clock fault location and resolution.

[0048] To address the aforementioned problems, this application provides a clock fault interference suppression method. After a clock node detects a clock fault, it sends clock fault suppression information to its slave clock nodes. This suppression information suppresses the generation of indication information, which in turn indicates a clock fault has occurred at a slave clock node. Thus, for multiple clock nodes, when one clock node detects a clock fault, sending clock fault suppression information to its slave clock nodes suppresses the generation of indication information by multiple slave clock nodes, preventing multiple clock nodes from generating multiple indication messages due to the same clock fault, thereby affecting the location and maintenance of the clock fault.

[0049] Optionally, the clock node in this application may be a network device that supports time synchronization protocols, such as a router, terminal, base station, or clock server.

[0050] Please see Figure 2 , Figure 2 This is a flowchart illustrating a clock fault interference suppression method provided in an embodiment of this application. Figure 2 The methods for suppressing clock fault interference include: S201 to S202.

[0051] S201. After a clock fault is detected, the first clock node sends a first clock fault suppression information to the second clock node. The first clock fault suppression information is used to suppress the generation of indication information. The indication information is used to indicate that a clock fault has occurred in the second clock node. The first clock node is the master clock node of the second clock node.

[0052] Optionally, the first clock node detecting a clock fault includes: the first clock node not receiving synchronization information from its master clock node within a preset time period. This synchronization information is used to instruct the first clock node to perform time synchronization. If the first clock node does not receive the synchronization information, it cannot perform time synchronization based on it. For example, a link failure between the first clock node and its corresponding master clock node may prevent the first clock node from receiving the synchronization information from the master clock node, thus preventing accurate time synchronization based on the master clock node's synchronization information.

[0053] Optionally, the first clock node detecting a clock fault includes: if the first clock node receives synchronization information sent by its master clock node and detects that the synchronization information is abnormal, then the first clock node cannot perform time synchronization based on the abnormal synchronization information. The abnormal synchronization information may be due to discontinuous timestamps in the synchronization information or a deviation between the timestamps and the reference clock exceeding a preset range, causing the first clock node to be unable to perform accurate time synchronization based on the abnormal synchronization information.

[0054] Optionally, the first clock node detecting a clock fault includes: the first clock node detecting a node fault that prevents the clock node from performing time synchronization. The node fault may be a failure in a time-synchronization-related module within the clock node, such as a fault in the clock chip of the first clock node or a fault in clock-related circuitry, resulting in the first clock node's inability to perform accurate time synchronization.

[0055] Optionally, when a clock node detects a clock fault, it can generate indication information to notify the user or management node that the clock node has experienced a clock fault. For example, the clock node can issue an alarm based on the indication information. The alarm can be an audible and visual prompt, or an alarm message sent to the management node. After generating the indication information, the first clock node can also send the alarm indication information to the management node so that administrators can locate and maintain the clock fault. The management node can be a network management device or other management equipment.

[0056] Since the first clock node is the master clock node of the second clock node, the second clock node is the slave clock node of the first clock node; since the clock in the first clock node is the master clock of the clock in the second clock node, the clock in the second clock node is the slave clock of the clock in the first clock node.

[0057] Optionally, if the first clock fault suppression information is used to suppress the generation of indication information, then after the second clock node receives the first clock fault suppression information, the second clock node will no longer generate indication information. In other embodiments, after the second clock node receives the first clock fault suppression information, the second clock node will not generate indication information for a preset time period, for example, after receiving the first clock fault suppression information, the second clock node will not generate indication information for 30 minutes. In other embodiments, the frequency or other characteristics of the generation of indication information are suppressed by the first clock fault suppression information to reduce interference from multiple indication information generated by the clock nodes, for example, reducing the flickering frequency of the indication information generated by the clock nodes.

[0058] Optionally, the indication information is used to indicate that a clock failure has occurred at the clock node. The indication information may be an alarm message or a fault indication message, etc., used to remind the user or management node that the clock node has failed.

[0059] Optionally, after detecting a clock fault, the first clock node may send first clock fault suppression information to the second clock node to suppress the generation of indication information. Alternatively, in other scenarios, such as when the first clock node receives suppression indication information from a user and sends clock fault suppression information to the second clock node based on that information, or when a synchronization anomaly is detected or other scenarios may occur where multiple clock nodes generate multiple indication messages, the first clock node may send first clock fault suppression information to the second clock node.

[0060] S202, the second clock node receives the first clock fault suppression information sent by the first clock node.

[0061] Optionally, after receiving the first clock fault suppression information, the second clock node suppresses the generation of indication information based on the first clock fault suppression information.

[0062] Thus, after a clock node detects a clock fault, it sends a first clock fault suppression message to its slave clock nodes to suppress the slave clock nodes from generating indication messages, thereby preventing multiple slave clock nodes from generating too many indication messages due to the same clock fault, which would interfere with the maintenance and handling of the clock fault.

[0063] Optionally, after the first clock node detects a clock fault, it is also used to generate indication information, which is used to indicate that the first clock node has a clock fault. The generation of indication information from the node is suppressed by the first clock fault suppression information, and the first clock node generates indication information so that the faulty clock node can be quickly located through the indication information, thereby improving the maintenance efficiency of clock faults.

[0064] Optionally, clock faults can include various types, such as physical connection failures, network congestion, or clock failures themselves. Different types of clock faults have different effects. Therefore, after detecting a clock fault, the first clock node is also used to determine the fault type in order to suppress the generation of indication information corresponding to that fault type from the clock node, but not to suppress the generation of indication information for other fault types from the clock node.

[0065] Optionally, the first clock fault suppression information includes a clock fault identifier, which identifies the fault type of the clock fault generated by the first clock node. The first clock fault suppression information is used to suppress the generation of indication information corresponding to the fault type of the clock fault identifier. Thus, the first clock node sends the first clock fault suppression information to the second clock node to suppress the generation of indication information corresponding to its clock fault identifier, and does not suppress indication information for other fault types, so as to avoid affecting clock faults of other fault types.

[0066] Optionally, the first clock fault suppression information is further used to instruct the second clock node to generate indication information for its slave clock node, thereby suppressing the generation of indication information by the second clock node. Thus, if the second clock node has slave clock nodes, after receiving the first clock fault suppression information sent by the first clock node, the second clock node is also used to send clock fault suppression information to its slave clock node to suppress the generation of indication information by its slave clock node.

[0067] Optionally, after S202, the method further includes: the second clock node sending second clock fault suppression information to the third clock node, the second clock fault suppression information being used to suppress the generation of indication information, and the second clock node being the master clock node of the third clock node. Thus, after a clock node receives the clock fault suppression information, if the clock node has slave clock nodes, the clock node also sends clock fault suppression information to its slave clock nodes to suppress the generation of indication information by the slave clock nodes, avoiding multiple clock nodes generating a large amount of indication information due to the same clock fault, thus preventing interference with clock fault maintenance. Furthermore, each clock node that receives the clock fault suppression information suppresses the generation of indication information by its slave clock nodes, simplifying the deployment of the suppression function and reducing implementation difficulty.

[0068] Optionally, after the clock fault of the clock node is repaired, the clock node is also used to send clock fault suppression release information to its source clock nodes to release the suppression of the generation of indication information.

[0069] Optionally, after S202, the method further includes: the first clock node sending a first clock fault suppression release information to the second clock node, the first clock fault suppression release information being used to release the suppression of generating indication information. Thus, after the second clock node receives the first clock fault suppression release information, it releases the suppression of generating indication information. Then, after the second clock node detects a clock fault, the second clock node can generate indication information corresponding to that clock fault.

[0070] Optionally, if the first clock node detects a clock fault recovery, it can send a first clock fault suppression release information to the second clock node. Of course, the first clock node can also send the first clock fault suppression release information to the second clock node in other scenarios. For example, if the first clock node receives a user's release instruction, it can send the first clock fault suppression release information to the second clock node according to the release instruction; or, for example, after the first clock node sends the first clock fault suppression information to the second clock node, after a preset time period, once the release period arrives, the first clock node sends the first clock fault suppression release information to the second clock node to release the suppression of the generation instruction information.

[0071] Optionally, when the first clock node detects a clock fault recovery, it also generates clock fault recovery information to notify the user or management node that the clock fault has been repaired.

[0072] Optionally, after the second clock node receives the first clock fault suppression release information, the method further includes: the second clock node sending second clock fault suppression release information to the third clock node, the second clock fault suppression release information being used to release the suppression of the generation indication information. Thus, after the second clock node receives the first clock fault suppression release information, the second clock node sends the second clock fault suppression release information to its slave clock nodes to release the suppression of the generation indication information.

[0073] A master-slave hierarchy may include multiple clock nodes, each of which may have multiple slave clock nodes. These multiple clock nodes may have different suppression requirements, for example... Figure 1 In this configuration, clock node 3 serves as the master clock node for clock nodes 4 and 5. Due to user requirements, when clock node 4 receives clock fault suppression information from clock node 3, clock node 4 suppresses the generation of indication information; when clock node 5 receives clock fault suppression information from clock node 3, clock node 5 does not suppress the generation of indication information. This can be achieved by configuring clock nodes 4 and 5 in advance to enable or disable the suppression of indication information generation, thus meeting diverse user needs.

[0074] Optionally, the method further includes: sending suppression enable information to the second clock node, the suppression enable information being used to enable the function of suppressing the generation of indication information. Thus, by sending suppression enable information to the clock node, the function of suppressing the generation of indication information is enabled. The clock node can then suppress the generation of indication information based on the received clock fault suppression information. If the clock node does not receive suppression enable information, i.e., the function of suppressing the generation of indication information is not enabled, it will not suppress the generation of indication information based on the clock fault suppression information when it receives clock fault suppression information. That is, when the clock node detects a clock fault, it can generate indication information; the suppression enable information is used to enable the function of suppressing the generation of indication information. If the clock node does not receive suppression enable information, it does not enable the function of suppressing the generation of indication information and therefore cannot suppress the generation of indication information based on the received clock fault suppression information. If the clock node receives suppression enable information, it enables the function of suppressing the generation of indication information and can suppress the generation of indication information based on the received clock fault suppression information.

[0075] Optionally, the method further includes: a first clock node sending a set time to a second clock node, the set time indicating that after the set time has elapsed, the function of suppressing the generation of indication information will be deactivated. After receiving the suppression activation information, the clock node enables the function of suppressing the generation of indication information. After receiving the suppression activation information, the clock node deactivates the function of suppressing the generation of indication information after the set time has elapsed.

[0076] Optionally, the suppression enable information includes a set time, which indicates that the function of suppressing the generation of indication information will be deenabled after the set time has elapsed. The set time is transmitted to the slave clock node via the suppression enable information.

[0077] Optionally, the suppression enable information is also used to instruct the second clock node to send suppression enable information to its slave clock node so as to enable the function of suppressing the generation of indication information.

[0078] Optionally, the suppression enable information is sent by the master clock node to the corresponding slave clock node. For example, the first clock node sends the suppression enable information to the second clock node, and the second clock node sends the suppression enable information to the third clock node. Alternatively, the management node can send the information to the corresponding clock node in the master-slave hierarchy. For example, the network management system sends the suppression enable information to the second and third clock nodes.

[0079] Optionally, after the second clock node receives the suppression enable information, the method further includes: the first clock node sending suppression disable information to the second clock node, the suppression disable information being used to disable the function of suppressing the generation of indication information. Thus, after the second clock node receives the suppression disable information, the function of suppressing the generation of indication information is disabled. If the second clock node receives the first clock fault suppression information, the second clock node does not suppress the generation of indication information or generates indication information when the clock node detects a clock fault.

[0080] Optionally, the suppression shutdown information is also used to instruct the second clock node to send suppression shutdown information to its slave clock node to disable the function of suppressing the generation of indication information.

[0081] Optionally, the suppression and shutdown information can be sent by the master clock node to the corresponding slave clock node. For example, the first clock node sends the suppression and shutdown information to the second clock node, and the second clock node sends the suppression and shutdown information to the third clock node. Alternatively, the management node can send the information to the corresponding clock node in the master-slave hierarchy. For example, the network management system sends the suppression and shutdown information to the second clock node.

[0082] Optionally, the clock node can send suppression enable information, suppression disable information, clock fault suppression information, and fault suppression release information to its slave clock nodes. The suppression enable and disable information configure the slave clock node to suppress the generation of indication information. Upon detecting a clock fault, the clock node sends clock fault suppression information to its slave clock nodes; upon detecting clock fault recovery, it sends clock fault suppression release information to its slave clock nodes. That is, the suppression enable and disable information enables the static configuration of the clock node's suppression function. The clock fault suppression information and fault suppression release information enable the dynamic configuration of the clock node's suppression function; that is, when the suppression function's triggering conditions are met, such as each time a clock fault is detected, the clock node can be triggered to send clock fault suppression information to its slave clock nodes.

[0083] Optionally, clock nodes can transmit the above information via Precision Time Protocol (PTP) messages, such as transmitting suppression enable information, suppression disable information, clock fault suppression information, or fault suppression release information via PTP messages. The PTP message is defined by the Precision Clock Synchronization Protocol for Networked Measurement and Control Systems (IEEE 1588v2 and IEEE 1588v2.1). The PTP message formats defined by IEEE 1588v2 and 1588v2.1 include common PTP message encapsulation headers (such as Ethernet encapsulation, Internet Protocol version 4 (IPv4), Internet Protocol version 6 (IPv6), etc.).

[0084] Optionally, the PTP message can be an event message or a general message. For example, if the PTP message is an event message, it can be a message such as Sync; if the PTP message is a general message, it can be a message such as Announce or Management.

[0085] The PTP message includes a header, a payload, and message extension bytes. In this embodiment, information between clock nodes can be transmitted either through the PTP message header or through the PTP message extension bytes.

[0086] Optionally, in S201, the first clock node sending first clock fault suppression information to the second clock node includes: the first clock node sending a PTP message to the second slave clock node. The PTP message includes a Type-Length-Value (TLV), which contains the first clock fault suppression information. For example, the TLV includes a Value field, and the value of the Value field identifies the first clock fault suppression information. In other embodiments, other information can also be transmitted via the PTP message. For example, if clock nodes transmit fault suppression release information via the PTP message, the value of the Value field of the TLV in the PTP message indicates fault suppression release information; if clock nodes transmit suppression enable information via the PTP message, the value of the Value field of the TLV in the PTP message indicates suppression enable information; if clock nodes transmit suppression disable information via the PTP message, the value of the Value field of the TLV in the PTP message indicates suppression disable information. In other implementations, the value of the Value field can be pre-defined to correspond to different information. For example, a value of 1 in the Value field indicates suppression enabled information; a value of 2 in the Value field indicates suppression disabled information; a value of 3 in the Value field indicates first clock fault suppression information; and a value of 4 in the Value field indicates fault suppression deactivated information.

[0087] Optionally, different information can be indicated by the Value field in the TLV of the PTP message, and the message type or message type can also be indicated by the Type field in the TLV. For example, the Type field can be used to indicate that the current message is a message related to the suppression function.

[0088] Optionally, the TLV includes suppression enable information, which includes a set time. The set time is used to indicate that the function of suppressing the generation of indication information is de-enabled after the set time has elapsed.

[0089] Optionally, the TLV can be located in a reserved field in the header of the PTP message or in the message extension bytes of the PTP message.

[0090] Optionally, in S201, the first clock node sends first clock fault suppression information to the second clock node, including: the first clock node sending a PTP message to the second slave clock node. The PTP message includes a message type, which is used to indicate the first clock fault suppression information. For example, the message type value indicates the first clock fault suppression information. Of course, the message type value can also indicate other information, such as a message type value of 1 indicating suppression enabled; a message type value of 2 indicating suppression disabled; a message type value of 3 indicating first clock fault suppression information; and a message type value of 4 indicating fault suppression deactivated.

[0091] Optionally, the PTP message includes a PTP message header, which includes a message type. The message type indicates the type of the PTP message. Thus, by adding a message type to the PTP message header, information such as first clock fault suppression information can be transmitted via the PTP message.

[0092] Please see Figure 3 , Figure 3 This is a schematic diagram of a PTP message format defined by IEEE 1588v2. Figure 3 MsgType identifies the message type. TranSpec is related to transmission and indicates the protocol associated with the PTP message. If TranSpec is 0, it indicates that the PTP message is defined by the IEEE 1588 protocol. VerPTP indicates the version of the 1588 protocol. Reserved1 is a 4-bit reserved field. MsgLength indicates the length of the PTP message. DomainNumber identifies the domain number, indicating the domain to which the message was sent. Reserved2 is a 1-byte reserved field. FlagField represents the flag field. CorrectionField represents the correction field. Reserved3 is a 4-byte reserved field. SourcePortIdentity identifies the source port identifier. SequenceID identifies the sequence number ID, indicating the message sequence number. ControlField identifies the control field. LogMsgInterval indicates the log message interval. PTPSpecifiedMessageField identifies the PTP message body and message extension bytes.

[0093] If the relevant information (suppression enable information, suppression disable information, clock fault suppression information, fault suppression release information) in this application embodiment is transmitted through the TLV in the PTP message, then the TLV can be located in a reserved field in the PTP message, such as in Figure 3The fields corresponding to Reserved1, Reserved2, or Reserved3 in the message can also be located in the fields corresponding to the message extension bytes, such as in... Figure 3 In the PTPSpecified Message Field. If the relevant information (such as suppression enable information, suppression disable information, clock fault suppression information, and fault suppression release information) in the embodiments of this application is transmitted through the message type in the PTP message, then it can be... Figure 3 The MsgType in the function is expanded to include message types, such as message type 1 indicating suppression enabled information; message type 2 indicating suppression disabled information; message type 3 indicating first clock fault suppression information; and message type 4 indicating fault suppression deactivated information.

[0094] Optionally, the clock in the first clock node can be a boundary clock, and the clock in the second clock node can be an ordinary clock or a boundary clock. Of course, the clocks in the first and second clock nodes can also be other types of clocks, and this application does not limit them.

[0095] Please see Figure 4 , Figure 4 This is a flowchart illustrating a clock fault interference suppression method provided in an embodiment of this application. Figure 4 It includes three clock nodes: clock node A, clock node B, and clock node C, where clock node A is the master clock node of clock node B, and clock node B is the master clock node of clock node C.

[0096] S401, Clock node A sends synchronization information 1 to clock node B, and clock node B performs time synchronization based on the received clock information 1;

[0097] S402, Clock node B sends synchronization information 2 to clock node C, and clock node C performs time synchronization based on the received clock information 2;

[0098] S403, Clock node A sends suppression enable information 1 to clock node B. Suppression enable information 1 is used to enable the function of suppressing the generation of indication information.

[0099] S404, Clock node B sends suppression enable information 2 to clock node C. Suppression enable information 2 is used to enable the function of suppressing the generation of indication information.

[0100] S405. If clock node A detects a clock fault, then clock node A generates an indication message.

[0101] S406. Clock node A sends clock fault suppression information 1 to clock node B. Clock fault suppression information 1 is used to suppress clock node B from generating indication information.

[0102] S407. Clock node B sends clock fault suppression information 2 to clock node C. Clock fault suppression information 2 is used to suppress clock node C from generating indication information.

[0103] S408. If clock node A detects that a clock fault has been recovered, then clock node A generates clock fault recovery information.

[0104] S409. Clock node A sends clock fault suppression release information 1 to clock node B. Clock fault suppression release information 1 is used to release the suppression of generating indication information.

[0105] S410, Clock node B sends clock fault suppression release information 2 to clock node C. Clock fault suppression release information 2 is used to release the suppression of generating indication information.

[0106] S411, Clock node A sends suppression off information 1 to clock node B. Suppression off information 1 is used to disable the function of suppressing the generation of indication information.

[0107] S412, Clock node B sends suppression shutdown information 2 to clock node C. Suppression shutdown information 2 is used to disable the function of suppressing the generation of indication information.

[0108] Please see Figure 5 , Figure 5 This is a schematic diagram of a master-slave hierarchical structure provided in an embodiment of this application. Figure 5 It includes multiple clock node hierarchical structures and Figure 1 The similarities and differences are, Figure 5 It also includes management nodes, which are connected to multiple clock nodes in the clock node hierarchy. For example... Figure 5 In this system, the management node is connected to clock nodes 4, 6, and 7, and can also connect to other clock nodes. The management node is a node with management functions, such as a network management system.

[0109] Optionally, in the master-slave hierarchy, at least two clock nodes generate clock failure alert information based on the clock failure and send the clock failure alert information to the management node.

[0110] After receiving clock failure alerts from at least two clock nodes, the management node presents the indication information of the target clock node among the at least two clock nodes based on the clock tracking path information of the at least two clock nodes, and suppresses the presentation of the indication information of the slave clock nodes of the target clock node. The clock tracking path information describes the master-slave relationship of the at least two clock nodes, and the target clock node is the master clock node of the other clock nodes among the at least two clock nodes.

[0111] Optionally, the management node can suppress the presentation of the slave clock node's indication information by not presenting it, or it can differentiate between the master and slave clock nodes' indication information by using different presentation methods. The presentation methods may include presentation frequency, presentation color, etc.

[0112] Optionally, the clock tracking path information can be a master-slave relationship between multiple clock nodes, where clock node 4 is the master clock node of clock node 6, or it can be a topological relationship between multiple clock nodes, from which the master clock node among the multiple clock nodes can be determined. Alternatively, by identifying the first clock node that detects a clock fault (or the master clock node among multiple clock nodes) and displaying the indication information of that clock node while not displaying the indication information of other clock nodes, the indication information of other clock nodes can be suppressed.

[0113] Optionally, the clock fault notification information sent by at least two clock nodes can be clock fault notification information sent by at least two clock nodes within a preset time, such as multiple clock fault notification information sent within 1 second. Of course, the clock fault notification information sent by at least two clock nodes can also be indication information generated by at least two clock nodes based on the same clock fault, in which case the at least two clock fault notification information indicates the same clock fault.

[0114] Optionally, the indication information includes a clock fault identifier. The clock node is instructed to generate the clock fault corresponding to the indication information by the clock fault identifier in the indication information. In this way, if the clock fault indication information sent by at least two clock nodes is based on the same clock fault identifier, the clock faults of multiple slave clock nodes can be suppressed to avoid the multiple indication information from interfering with the clock fault.

[0115] like Figure 5In the process, clock nodes 4, 6, and 7 generate indication information and send it to the management node. After receiving the indication information from clock nodes 4, 6, and 7, the management node displays the indication information sent by clock node 4, but not the indication information sent by clock nodes 6 and 7, since clock node 4 is the master clock node of clock nodes 6 and 7, or in other words, clock node 4 is the first clock node in the clock tracking path among the three received indication information. This is to avoid interference from other indication information in locating the clock fault and to facilitate the user to quickly locate the location of the clock fault from the display interface.

[0116] Please see Figure 6 , Figure 6 This is a schematic diagram of a clock fault interference suppression device provided in an embodiment of this application. The clock fault interference suppression device includes a first processing unit and a first communication unit. The first processing unit is used to detect clock faults and generate first clock fault suppression information after detecting the clock fault. The first communication unit is used to send the first clock fault suppression information to other clock nodes (or from clock nodes). That is, the first processing unit and the first communication unit cooperate to achieve... Figure 2 The clock fault interference suppression method included in S201 of the corresponding embodiment.

[0117] Optionally, after sending the first clock fault suppression information, the first processing unit is further configured to generate fault suppression release information, and the first communication unit is further configured to: send the fault suppression release information to the slave clock node, wherein the fault suppression release information is used to release the suppression of the generation of indication information.

[0118] Optionally, the first processing unit is further configured to generate suppression enable information, and the first communication unit is further configured to send suppression enable information to the slave clock node, the suppression enable information being used to enable the function of suppressing the generation of indication information.

[0119] Optionally, the first processing unit is further configured to generate suppression shutdown information, and the first communication unit is further configured to: send suppression shutdown information to the slave clock node, wherein the suppression shutdown information is used to disable the function of suppressing the generation of indication information.

[0120] Optionally, the first communication unit is further configured to: send a set time to the slave clock node, the set time being used to indicate that after the set time has elapsed, the function of suppressing the generation of indication information is de-enabled.

[0121] Optionally, a clock fault detection includes at least one of the following three: no synchronization information is received from the master clock node of the clock node within a preset time period; synchronization information is received from the master clock node of the clock node and an anomaly is detected in the synchronization information; a node fault is detected in the clock node, making it unable to perform time synchronization.

[0122] Optionally, sending first clock failure suppression information to a slave clock node of a clock node includes: sending a Precision Time Protocol (PTP) message to the slave clock node, wherein the PTP message includes a Type Length Value (TLV) and the TLV includes the first clock failure suppression information, or the PTP message includes a PTP message header and the PTP message header includes a message type, wherein the message type is used to indicate the first clock failure suppression information.

[0123] Optionally, if the first clock fault suppression information includes a clock fault identifier, then the first clock fault suppression information is used to suppress the generation of indication information corresponding to the clock fault identifier.

[0124] Please see Figure 7 , Figure 7 This is a schematic diagram of a clock fault interference suppression device provided in an embodiment of this application. The clock fault interference suppression device includes a second processing unit and a second communication unit. The second communication unit is used to obtain first clock fault suppression information from its master clock node, and the first processing unit is used to suppress the generation of indication information based on the first clock fault suppression information. The first communication unit implements... Figure 2 The clock fault interference suppression method included in S202 of the corresponding embodiment.

[0125] Optionally, the second communication unit is further configured to receive first clock fault suppression release information sent by the master clock node, the first clock fault suppression release information being used to release the suppression of generating the indication information.

[0126] Optionally, the second communication unit is further configured to receive suppression enable information sent by the master clock node, the suppression enable information being used to enable the function of suppressing the generation of indication information.

[0127] Optionally, the second communication unit is further configured to receive suppression shutdown information sent by the master clock node, the suppression shutdown information being used to disable the function of suppressing the generation of indication information.

[0128] Optionally, the second communication unit is further configured to send second clock fault suppression information to the slave clock node of the clock node, the second clock fault suppression information being used to enable the function of suppressing the generation of indication information.

[0129] Optionally, the second communication unit is further configured to send a second clock fault suppression release information to the slave clock node, the second clock fault suppression release information being used to enable the function of suppressing the generation of indication information.

[0130] Optionally, the second communication unit is further configured to receive a set time sent by the master clock node, the set time being used to indicate that after the set time is reached, the function of suppressing the generation of indication information is deactivated.

[0131] Optionally, receiving the first clock fault suppression information sent by the master clock node of the clock node includes: receiving a Precision Time Protocol (PTP) message sent by the master clock node, wherein the PTP message includes a Type Length Value (TLV) and the TLV includes the first clock fault suppression information, or the PTP message includes a PTP message header and the PTP message header includes a message type, wherein the message type is used to indicate the first clock fault suppression information.

[0132] It should be understood that the above description is merely to help those skilled in the art better understand the embodiments of this application, and is not intended to limit the scope of the embodiments of this application. Based on the examples given above, those skilled in the art can obviously make various equivalent modifications or changes. For example, some steps in the various methods described above may be unnecessary, or new steps may be added. Alternatively, any combination of two or more of the above embodiments may be used. Such modifications, changes, or combinations also fall within the scope of the embodiments of this application.

[0133] It should also be understood that the methods, situations, categories, and classifications of embodiments in this application are for the convenience of description only and should not constitute a special limitation. Various methods, categories, situations, and features in embodiments can be combined without contradiction.

[0134] It should also be understood that the various numerical designations used in the embodiments of this application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application. The order of the process numbers described above does not imply the order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0135] It should also be understood that the above description of the embodiments of this application focuses on highlighting the differences between the various embodiments. Any similarities or differences not mentioned can be referred to each other. For the sake of brevity, they will not be repeated here.

[0136] The above combination Figures 2 to 7 The embodiments of the methods and systems provided in this application have been described. The network device provided in the embodiments of this application is described below.

[0137] This embodiment can divide the network device into functional modules according to the above method. For example, it can be divided into functional modules corresponding to each function, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0138] It should be noted that the relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0139] The network device provided in this application embodiment is used to execute the clock fault interference suppression method provided in the above method embodiment, and thus can achieve the same effect as the above implementation method.

[0140] In other embodiments, when using integrated units, the network device may include a processing module, a storage module, and a communication module. The processing module can be used to control and manage the operations of the network device. For example, it can be used to support the network device in executing the steps performed by the processing unit. The storage module can be used to store program code and data, etc. The communication module can be used to support communication between the network device and other network devices.

[0141] The processing module can be a processor or a controller. It can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc. The storage module can be a memory. The communication module can specifically be a radio frequency circuit, a Bluetooth chip, a Wi-Fi chip, or other devices that interact with other network devices.

[0142] Based on the same concept, embodiments of this application also provide a network device, see [link to relevant documentation]. Figure 8 , Figure 8 A schematic diagram of the structure of an exemplary network device of this application is shown. Figure 8 The network device shown can execute the steps in the clock fault interference suppression method performed by any of the clock nodes (e.g., the first clock node or the second clock node) or management nodes provided in the embodiments of this application.

[0143] The network device 800 includes at least one processor 801, a memory 803, and at least one network interface 804.

[0144] The processor 801 is, for example, a general-purpose CPU, a digital signal processor (DSP), a network processor (NP), a GPU, a neural network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits or application-specific integrated circuits (ASICs) used to implement the scheme of this application, a programmable logic device (PLD), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute the various logic blocks, modules, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0145] Optionally, network device 800 also includes bus 802. Bus 802 is used to transmit information between the components of network device 800. Bus 802 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. Bus 802 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 8 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0146] Memory 803 may be, for example, read-only memory (ROM) or other types of storage devices capable of storing static information and instructions; random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions; electrically erasable programmable read-only memory (EEPROM); compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile optical discs, Blu-ray discs, etc.); magnetic disk storage media or other magnetic storage devices; or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. Memory 803 may exist independently and be connected to processor 801 via bus 802. Memory 803 may also be integrated with processor 801.

[0147] Network interface 804 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), or wireless local area network (WLAN). Network interface 804 can include wired network interfaces and wireless network interfaces. Specifically, network interface 804 can be an Ethernet interface, such as Fast Ethernet (FE), Gigabit Ethernet (GE), Asynchronous Transfer Mode (ATM), WLAN, cellular network, or combinations thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In some embodiments of this application, network interface 804 can be used for network device 800 to communicate with other devices.

[0148] In specific implementations, as some embodiments, processor 801 may include one or more CPUs. Each of these processors may be a single-core processor or a multi-core processor. Here, "processor" may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0149] In specific implementations, as some methods, network device 800 may include multiple processors. Each of these processors may be a single-core processor or a multi-core processor. Here, a processor may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0150] In some embodiments, memory 803 is used to store program instructions for executing the present application's solution, and processor 801 can execute the program instructions stored in memory 803. That is, network device 800 can implement the method provided in the above embodiments through processor 801 and the program instructions in memory 803. The program instructions may include one or more software modules. Optionally, processor 801 itself may also store program instructions for executing the present application's solution.

[0151] In specific implementation, the processor 801 in the network device 800 of this application reads instructions from the memory 803, causing... Figure 8 The network device 800 shown can perform all or part of the steps in the clock fault interference suppression method performed by the network device in the above embodiments.

[0152] In the above embodiments, each step of the method is implemented through integrated logic circuits in the hardware of the processor of the network device 800 or through software instructions. The steps of the method embodiments disclosed in this application can be directly implemented by the hardware processor, or implemented by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. Since the storage medium is located in memory, the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method embodiments; to avoid repetition, these will not be described in detail here.

[0153] It should be understood that the aforementioned processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. General-purpose processors can be microprocessors or any conventional processor. It is worth noting that the processor can be a processor supporting the Advanced Reduced Instruction Set Computing (RISC) machine (ARM) architecture.

[0154] Furthermore, in an alternative embodiment, the memory described above may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may also include non-volatile random access memory. For example, the memory may also store device type information.

[0155] The memory can be volatile or non-volatile, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which serves as an external cache. Many forms of RAM are available by way of example, but not limitation. Examples include static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0156] The network device provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, so they will not be described again here.

[0157] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the methods described in the above-described method embodiments.

[0158] This application also provides a computer program product that, when run on a network device, enables the network device to implement the methods described in the above-described method embodiments.

[0159] This application provides a chip, including a processor, for calling and executing instructions stored in a memory, causing a communication device with the chip installed to execute the method described in the above-described method embodiments of any network device provided in this application.

[0160] This application also provides a chip system including a processor coupled to a memory. The processor executes a computer program stored in the memory to implement the method described in the above-described method embodiments. The chip system may be a single chip or a chip module composed of multiple chips.

[0161] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, or magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0162] Those skilled in the art will understand that implementing all or part of the processes in the above embodiments can be accomplished by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium can include various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0163] The naming or numbering of steps in this application does not mean that the steps in the method flow must be executed in the time / logical order indicated by the naming or numbering. The execution order of the named or numbered process steps can be changed according to the technical purpose to be achieved, as long as the same or similar technical effect can be achieved.

[0164] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0165] In the embodiments provided in this application, it should be understood that the disclosed apparatus / devices and methods can be implemented in other ways. For example, the apparatus / device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0166] It should be understood that in the description of this application and the appended claims, the terms "comprising," "including," "having," and any variations thereof are intended to cover a non-exclusive inclusion and mean "including but not limited to," unless otherwise specifically emphasized. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not necessarily limited to those steps or modules that are explicitly listed, but may include other steps or modules that are not explicitly listed or that are inherent to such process, method, product, or apparatus.

[0167] In the description of this application, unless otherwise stated, " / " indicates that the objects before and after are in an "or" relationship. For example, A / B can mean A or B. "And / or" in this application is used to describe the mapping relationship of the related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural.

[0168] Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0169] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0170] Furthermore, in the description of this application and the appended claims, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, nor should they be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein; features defined as "first" or "second" may explicitly or implicitly include at least one of those features.

[0171] In the embodiments of this application, the words "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of the words "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0172] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0173] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for suppressing clock malfunction interference, characterized in that, Applied to a clock node, the method includes: Upon detecting a clock fault, a first clock fault suppression information is sent to the slave clock node of the clock node. The first clock fault suppression information is used to suppress the generation of indication information, which is used to indicate that a clock fault has occurred in the slave clock node.

2. The method according to claim 1, characterized in that, After sending the first clock fault suppression information to the slave clock node of the clock node, the method further includes: A clock fault suppression release information is sent to the slave clock node, the clock fault suppression release information being used to release the suppression of generating the indication information.

3. The method according to claim 1 or 2, characterized in that, The method further includes: The suppression enable information is sent to the slave clock node, which enables the function of suppressing the generation of indication information.

4. The method according to claim 3, characterized in that, The method further includes: A suppression shutdown message is sent to the slave clock node, the suppression shutdown message being used to disable the function of suppressing the generation of indication information.

5. The method according to claim 3 or 4, characterized in that, The method further includes: A set time is sent to the slave clock node, the set time being used to indicate that the function of suppressing the generation of indication information will be de-enabled after the set time has elapsed.

6. The method according to any one of claims 1 to 5, characterized in that, The detected clock fault includes at least one of the following three: If the clock node does not receive synchronization information from the master clock node within a preset time period, the clock node performs time synchronization based on the synchronization information. The system receives synchronization information sent by the master clock node of the clock node and detects that the synchronization information is abnormal. A node failure was detected in the clock node, preventing it from synchronizing time.

7. The method according to any one of claims 1 to 6, characterized in that, Sending the first clock fault suppression information to the slave clock node of the clock node includes: Send a Precision Time Protocol (PTP) message to the slave clock node. The PTP message includes a Type Length Value (TLV) and the TLV includes first clock fault suppression information. Alternatively, the PTP message includes a PTP message header and the PTP message header includes a message type that indicates the first clock fault suppression information.

8. The method according to any one of claims 1 to 7, characterized in that, If the first clock fault suppression information includes a clock fault identifier, then the first clock fault suppression information is used to suppress the generation of indication information corresponding to the clock fault identifier.

9. A method for suppressing clock malfunction interference, characterized in that, Applied to a clock node, the method includes: The clock node receives first clock fault suppression information sent by its master clock node. The first clock fault suppression information is used to suppress the generation of indication information, which is used to indicate that the clock node has experienced a clock fault.

10. The method according to claim 9, characterized in that, The method further includes: The system receives a first clock fault suppression release information sent by the master clock node, which is used to release the suppression of the generation of the indication information.

11. The method according to claim 9 or 10, characterized in that, The method further includes: The system receives suppression enable information sent by the master clock node, which enables the function of suppressing the generation of indication information.

12. The method according to claim 11, characterized in that, The method further includes: The system receives suppression shutdown information sent by the master clock node, which is used to disable the function of suppressing the generation of indication information.

13. The method according to claim 9 or 10, characterized in that, The method further includes: Send a second clock fault suppression information to the slave clock node of the clock node. The second clock fault suppression information is used to enable the function of suppressing the generation of indication information.

14. The method according to claim 13, characterized in that, The method further includes: Send a second clock fault suppression release information to the slave clock node, the second clock fault suppression release information being used to enable the function of suppressing the generation of indication information.

15. The method according to claim 11 or 12, characterized in that, The method further includes: The system receives a set time sent by the master clock node. The set time is used to indicate that the function of suppressing the generation of indication information will be de-enabled after the set time has elapsed.

16. The method according to any one of claims 9 to 15, characterized in that, The first clock fault suppression information received from the master clock node of the clock node includes: The system receives a Precision Time Protocol (PTP) message sent by the master clock node. The PTP message includes a Type Length Value (TLV), and the TLV includes first clock fault suppression information. Alternatively, the PTP message includes a PTP message header, and the PTP message header includes a message type, which is used to indicate the first clock fault suppression information.

17. A clock malfunction interference suppression device, characterized in that, The apparatus includes a unit for performing the method of any one of claims 1 to 8 or a unit for performing the method of any one of claims 9 to 16.

18. A network device, characterized in that, include: The memory includes computer-readable instructions; A processor communicating with the memory, the processor being configured to execute the computer-readable instructions causing the network device to perform the clock fault interference suppression method according to any one of claims 1-16.

19. A computer-readable storage medium, characterized in that, Includes a program or instruction that, when executed by a processor, implements the clock fault interference suppression method as described in any one of claims 1-16.

20. A computer program product, characterized in that, The computer program product includes instructions that, when executed by a computer, implement the clock fault interference suppression method as described in any one of claims 1-16.

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