Embedded firmware PQC and SM2 digital signature mixed verification method

Abstract

The invention relates to the technical field of digital information transmission security, and discloses an embedded firmware PQC and SM2 digital signature hybrid verification method, which comprises the following steps of: analyzing an SM2 public key and a signature value from a message, retrieving a PQC signature data block, constructing a cascade anchoring abstract, responding to the retrieved PQC signature data block, extracting the data block, executing hash operation to generate a PQC abstract, and verifying the PQC abstract. After the load abstract and the PQC abstract are cascaded according to bits, a final verification abstract is calculated; elliptic curve verification is executed based on the SM2 public key, the signature value and the final verification abstract, PQC enhanced verification is executed when verification passes, the integrity of post-quantum signature data is internalized into a mathematical precondition of signature verification of a national cryptographic algorithm through a nested abstract anchoring mechanism, and the risk that a mixed signature protocol is degraded and attacked is avoided.

Description

Technical Field

[0001] This invention relates to a hybrid verification method combining embedded firmware PQC and SM2 digital signature, belonging to the field of digital information transmission security technology. Background Technology

[0002] In current industrial internet edge computing and embedded device firmware upgrade scenarios, ensuring the integrity and authenticity of transmitted data is fundamental to guaranteeing system security. Current mainstream solutions generally employ the SM2 elliptic curve cryptography algorithm (a national standard) to generate digital signatures, preventing malicious firmware tampering. However, with the development of quantum computing technology, traditional public-key cryptography faces potential security threats. Introducing quantum-resistant quantum cryptographic algorithms into existing systems to construct hybrid signature verification architectures has become an inevitable trend in industry evolution. To adapt to the limited storage and computing resources of industrial embedded devices, existing technologies primarily focus on improving the execution efficiency of single cryptographic algorithms at the software control level through code simplification and instruction set adaptation. For example, Chinese invention patent CN103020530A discloses an optimization method for the SM2 encryption algorithm based on an embedded platform. By extracting open-source library APIs, writing underlying drivers, and optimizing core multiplication and division instructions, the method reduces the memory footprint of the SM2 algorithm on the embedded platform and improves the parallelism of operations. However, such technical solutions focus on solving the problem of running efficiency of a single algorithm on hardware that is limited. The system architecture still uses the traditional single-channel verification logic. When facing complex application scenarios of post-quantum hybrid signatures, the simple algorithm-level optimization does not involve the design of strong logical correlation between multi-signature data and lacks a mathematical binding mechanism for signature data of different security levels, resulting in security shortcomings at the system protocol level.

[0003] However, existing hybrid signature schemes often employ loosely coupled serial or parallel verification logic. The receiving end typically determines whether to trigger the post-quantum signature verification process based on the plaintext extended field or protocol header identifier in the digital certificate. This uncontrolled channel based on explicit identifier scheduling mechanism has inherent security flaws and lacks resistance to protocol degradation. A man-in-the-middle attacker can intercept the transmitted message, physically strip the post-quantum signature data block, and simultaneously erase the corresponding indicator. At this time, the receiving device, based on the characteristics of the tampered message, mistakenly identifies it as only needing to perform traditional SM2 verification of old versions of the protocol or low-security data. Since the traditional SM2 signature verification logic only calculates the digest for the firmware payload itself, even if the post-quantum signature data is lost, SM2 verification can still pass, causing the system to fall back to a low security level without being aware of it in high-risk environments, thus bypassing the protocol negotiation phase of the anti-quantum protection mechanism. In addition, simply adding a complex handshake negotiation mechanism or establishing a high-strength encrypted tunnel to prevent such tampering increases the communication latency and energy consumption of embedded devices with limited computing resources, and it is difficult to maintain backward compatibility with existing old devices without breaking the existing communication protocol stack.

[0004] Therefore, the technical problem to be solved by this invention is how to establish a strong mathematical dependence of traditional signature algorithms on the existence of post-quantum signature data from the cryptographic operation level without introducing additional communication overhead and hardware modification, so as to avoid the risk of downgrade attacks in hybrid signature protocols. Summary of the Invention

[0005] To address the problems mentioned in the background art, the technical solution of the present invention is as follows: A hybrid verification method for embedded firmware PQC and SM2 digital signature, the method comprising the following steps: Step S1, data stream parsing and feature extraction: Separate the firmware payload to be verified and digital certificate data from the received communication message, parse the digital certificate data to extract the SM2 public key and SM2 signature value, and traverse the extended field of the digital certificate data to search for the existence of PQC signature data block. Step S2: Construct a cascaded anchored digest. Perform a first hash operation on the firmware payload to be verified to generate a payload digest. If a PQC signature data block is found, extract the PQC signature data block and perform a second hash operation on it to generate a PQC digest. Concatenate the payload digest and the PQC digest bit by bit to form an input sequence. Perform a third hash operation on the input sequence to obtain the final verification digest. If no PQC signature data block is found, construct a substitution sequence containing the payload digest and preset padding bits and calculate the hash value of the substitution sequence as the final verification digest. Step S3: Perform SM2 anchor verification. Based on the SM2 public key, SM2 signature value and final verification digest, perform elliptic curve verification operation. When the operation result confirms that the final verification digest and SM2 signature value satisfy the preset algebraic matching relationship, the first level of verification is determined to be passed, confirming that there is a mathematical binding relationship between the firmware payload to be verified and the retrieval status of the PQC signature data block. Step S4: Perform PQC enhanced verification. In response to the pass determination in step S3, call the preset lattice cryptography algorithm parameters, take the payload digest as the message input, perform lattice basis vector operation on the PQC signature data block, calculate the verification norm, and generate a verification pass instruction when the verification norm is less than the preset rejection threshold.

[0006] Preferably, in step S2, if no PQC signature data block is found, the step of constructing a substitution sequence containing a payload digest and preset padding bits and calculating the hash value of the substitution sequence as the final verification digest includes: detecting the current security policy configuration state of the system; if the security policy configuration state is a forced post-quantum protection mode, then the construction of the substitution sequence is prohibited and a verification blocking instruction is directly generated; if the security policy configuration state is a compatibility mode, then a preset zero-value bit stream is called as a preset padding bit, the payload digest and the zero-value bit stream are linearly concatenated to generate a substitution sequence, and the SM3 hash algorithm is called to calculate the substitution sequence to output the final verification digest; wherein, if the sending end uses an input sequence containing a PQC digest when generating the SM2 signature value, and the receiving end uses a substitution sequence in step S2 because no PQC signature data block is found, then the final verification digest calculated in this way will cause the elliptic curve verification operation result in step S3 to be invalid.

[0007] Preferably, in step S3, performing the elliptic curve verification operation includes the following sub-steps: parsing the SM2 signature value to obtain the first component. Second component Using the SM2 public key and the second component and elliptic curve base points Calculate the points of the elliptic curve And obtain the elliptic curve points. x-coordinate ; using the final verification digest and x-axis Calculate verification parameters Validate parameters The calculation follows the following formula: ,in, Base point of elliptic curve The order will be used to verify the parameters. With the first component A numerical comparison is performed. If the two values ​​are equal, the result of the operation confirms that the final verification digest and the SM2 signature value satisfy the preset algebraic matching relationship.

[0008] Preferably, in step S4, the step of performing lattice basis vector operation includes: loading the public key matrix and polynomial coefficients pre-placed in the protected storage area; mapping the payload digest to a message vector on the polynomial ring; performing polynomial matrix multiplication operation based on the signature vector and message vector contained in the PQC signature data block; extracting high-order bits or low-order bits based on the result of the polynomial matrix multiplication operation, and calculating the verification norm; wherein the verification norm is an infinite norm or an Euclidean norm.

[0009] Preferably, in step S1, the step of separating the firmware payload to be verified and the digital certificate data from the received communication message includes: establishing a physically isolated payload buffer and signature buffer in the trusted memory area of ​​the embedded device; writing the firmware payload to be verified into the payload buffer and writing the digital certificate data into the signature buffer through a direct memory access channel; locking the write permission of the payload buffer until the verification pass instruction is generated or the process terminates.

[0010] Preferably, in step S2, the first hash operation, the second hash operation, and the third hash operation all use the SM3 cryptographic hash algorithm; the step of concatenating the payload digest and the PQC digest bit by bit to form the input sequence includes: taking the 256-bit payload digest as the high-order data and the 256-bit PQC digest as the low-order data, performing a direct concatenation without padding in the register to generate a 512-bit input sequence.

[0011] Preferably, in step S1, the step of traversing the extended field of the digital certificate data to search for the existence of a PQC signature data block includes: parsing the ASN.1 encoding structure of the digital certificate data in sequence to locate the extended field area; reading the object identifier of the extended item item by item and comparing the read object identifier with a preset list of post-quantum algorithm identifiers in binary; when the comparison results are consistent, parsing the eight-bit byte string value corresponding to the extended item, identifying it as a PQC signature data block and recording its memory address offset.

[0012] Preferably, the method further includes step S5: in response to the determination of first-level verification failure in step S3 or in response to the verification norm not being less than the rejection threshold in step S4, a security blocking process is executed; the security blocking process includes: sending a termination signal to the bootloader, clearing the cached data of the firmware payload to be verified in memory, and recording the verification failure type code in the security log area, the type code being used to distinguish whether it is SM2 anchoring verification failure or PQC enhanced verification failure.

[0013] Preferably, the method is applied to firmware upgrade scenarios for industrial internet edge computing nodes or industrial controllers; the firmware payload to be verified is executable binary machine code or a configuration file of a field-programmable gate array; the digital certificate data follows the X.509v3 standard format, and the PQC signature data block is encapsulated in a custom extension of the standard format.

[0014] Preferably, after generating the verification pass instruction, the method further includes: removing write protection on the non-volatile memory storing the old firmware, writing the verified firmware payload to be verified in memory to the non-volatile memory; updating the system boot pointer and performing a device soft reboot to load and run the new firmware.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. In embedded firmware PQC and SM2 digital signature, a cascaded digest anchoring mechanism is constructed. The integrity verification of post-quantum signature data is established as a mathematical prerequisite for the national cryptographic algorithm signature verification. When generating the verification digest, the hash value of the firmware payload is linearly concatenated with the hash value of the post-quantum signature data block. This makes the input parameters of the national cryptographic algorithm signature verification directly dependent on the existence of the post-quantum signature data. When the post-quantum signature data block is stripped or tampered with during transmission, the anchor digest undergoes an irreversible change, causing the national cryptographic algorithm signature verification to fail. Based on the strongly coupled logic of cryptographic primitives, the verification system does not need to rely on easily tampered plaintext identifiers or external negotiation protocols. This eliminates the risk of hybrid signature protocols being downgraded by man-in-the-middle attacks from the perspective of operational principles, ensuring the protocol security of industrial Internet edge devices in uncontrolled channels.

[0016] 2. While ensuring dual security, it minimizes the consumption of computing resources and communication bandwidth. It performs hash operations and bit string concatenation in local memory, replacing the overhead of establishing independent encryption channels or multi-round handshake negotiation in traditional solutions. For industrial embedded devices with limited computing resources, it uses existing hash instructions to complete multi-signature strong binding verification. It triggers high-computing lattice cryptographic operations only when the anchor verification is successful, and calls cascade verification strategies as needed. It avoids the increase in system latency or unnecessary energy consumption due to the introduction of post-quantum protection, and meets the real-time and low-power requirements of industrial control systems.

[0017] 3. It has the ability to adapt to the system architecture based on standard cryptographic primitives, retains the standard digital certificate encoding structure and the basic elliptic curve underlying operation logic, and only adjusts the application layer data digest assembly rules to achieve quantum resistance integration. This allows existing industrial equipment to gain resistance to quantum computing-assisted attacks without replacing dedicated hardware acceleration modules or reconstructing the underlying communication protocol stack. It solves the problem of deploying new cryptographic algorithms on existing industrial infrastructure and reduces the hardware transformation costs and system compatibility risks in the long-cycle technology iteration process of industrial network security systems. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the embedded firmware PQC and SM2 cascaded anchoring verification logic flow of the present invention; Figure 2 This is a comparison chart of the time overhead of signature generation and verification under different PQC algorithm parameter sets of this invention; Figure 3 This is a diagram illustrating the firmware verification hardware architecture and data flow of the present invention based on a physical isolation mechanism. Detailed Implementation

[0019] The present invention will be described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are merely for explaining the present invention and are not intended to limit the scope of protection of the present invention.

[0020] This invention discloses a hybrid verification method for embedded firmware PQC and SM2 digital signatures, applicable to embedded device environments with limited computing resources, such as industrial internet edge computing nodes, industrial firewalls, and industrial controllers. This method introduces post-quantum cryptography (PQC signature data hash fingerprint) into the traditional SM2 elliptic curve cryptography verification process, constructing a cascaded digest anchoring mechanism. It establishes the integrity verification of the post-quantum signature data as a mathematical precondition for successful SM2 signature verification, thereby eliminating the risk of downgrade attacks caused by the stripping of post-quantum data in the hybrid signature protocol without changing the underlying cryptographic primitive logic. In the verification environment construction and data parsing stages, the system allocates contiguous physical address space in the trusted memory region of the embedded device, establishing a payload buffer for storing the firmware payload to be verified and a signature buffer for storing digital certificate data. The receiving end splits the packets received by the communication interface through a direct memory access channel, writing the firmware payload to the payload buffer and the digital certificate data to the signature buffer, and locking the write permission of the payload buffer. The processor parses the signature buffer data according to the encoding rules defined by the X.509v3 standard format or industrial control protocols, extracting the SM2 public key point coordinates from a specific offset position. and including the first component Second component The processor retrieves the SM2 signature value and simultaneously iterates through the object identifiers in the certificate extension field, comparing them with a pre-defined list of post-quantum algorithm identifiers. If a match is found, the processor locates the eight-bit byte string value corresponding to that extension item and identifies it as a PQC signature data block. Extract the data; if no matching item is found after the traversal ends, mark the current state as no PQC data.

[0021] During the digest construction and anchoring phase, the processor performs a hash operation based on cascaded logic. The system calls the SM3 cryptographic hash algorithm to perform the first hash operation on the data in the payload buffer, generating a payload digest of 256 bits in length. In the case where a PQC signature data block is retrieved, the processor... Perform the second hash operation to generate a 256-bit PQC digest. and in the register As high-level data, Perform bitwise concatenation without padding as the low-order data to construct a 512-bit input sequence. That is, following the relational formula If no PQC signature data block is found, the processor calls a preset 256-bit zero-value bit stream. Constructing alternative sequences The processor processes the input sequence constructed above. or Perform the third hash operation and output the final verification digest. The final verification summary As the sole message input parameter for subsequent elliptic curve verification operations, it ensures that the SM2 signature verification process has a deterministic mathematical dependence on the existence of PQC data.

[0022] In the SM2 anchoring verification phase, the system utilizes the elliptic curve discrete logarithm problem to verify the final verification summary. The processor reads the SM2 public key to verify its validity. The second component of the SM2 signature value and elliptic curve base points The system performs elliptic curve dot multiplication and dot addition operations, and calculates the elliptic curve points according to the SM2 digital signature verification standard logic. and obtain points x-coordinate The processor utilizes the final verification digest and x-axis According to the relation Calculate the verification parameters ,in Based on The system will calculate the resulting verification parameters based on the order. The first component of the signature value extracted from the message Perform numerical comparisons when and If the values ​​are equal, the SM2 anchoring verification is considered successful. Mathematical logic confirms that the received firmware payload and PQC signature data block existed and were not tampered with during signature generation. If the PQC data block is stripped during transmission, it will result in… Changes occurred, which in turn caused and If there is a mismatch, the verification process terminates. During the PQC enhanced verification phase, after successful SM2 anchoring verification, the system triggers a lattice-based verification process. The processor loads the lattice-based cryptographic algorithm parameters, including the public key matrix, pre-stored in the protected storage area. And polynomial coefficients, the system uses the load summary generated in step S2 For message input, the extracted PQC signature data block is parsed into a signature vector. and prompt information And perform matrix multiplication on the polynomial ring to verify the inequalities. Whether it is valid, among which The preset rejection threshold, This is an intermediate variable for hash operations. The system uses a public key vector. If the verification norm meets the threshold requirement, the system generates a final verification pass instruction, removes the write protection of the non-volatile memory, and performs a firmware update. If any verification step fails, the system sends a termination signal to the bootloader, clears the memory cache, and records a security audit log.

[0023] Example 1: This example applies to a firmware upgrade scenario for an industrial internet edge computing node, deployed in a remote unattended substation. It receives firmware updates via a public cellular network and faces the risk of a man-in-the-middle attacker intercepting communication messages and stripping the post-quantum PQC signature data block, attempting to induce the node to revert to a low-security mode that only verifies the SM2 signature. Upon receiving a message containing the firmware payload and digital certificate to be verified, the system uses a direct memory access channel to split the message into physically isolated payload and signature buffers. The processor parses the signature buffer data, extracts the SM2 public key and signature value, and traverses the certificate extension fields to retrieve the PQC signature data block. Regardless of the search results, the system executes the cascading anchored summary construction process.

[0024] For the retrieved In this case, the processor computes a summary , with firmware payload summary Concatenate to generate input sequence ,satisfy For those not found In this case, the processor calls zero-value padding bits to construct the replacement sequence. ,satisfy System calculation final verification summary It is used as message input to perform SM2 signature verification calculation and calculate verification parameters. Because the sender uses a valid signature when generating the signature. The input sequence, if the attacker strips it during transmission The result calculated by the receiving end The discrepancy between the original sequence and the one sent at the end leads to a difference in the final verification digest. The change, this difference, affects the calculated verification parameters. With the signature value component in the message The mismatch caused the SM2 anchor signature verification to fail. The system determined that a downgrade attack existed and blocked firmware writing. The subsequent high-overhead PQC cipher verification process was not triggered. By utilizing the sensitivity of the SM2 algorithm to the input digest, the integrity of the PQC data was established as a mathematical prerequisite for the SM2 signature verification to pass, thus realizing anti-protocol downgrade defense on edge devices with limited computing resources.

[0025] Example 2: This example constructs an experimental platform simulating an industrial edge computing node based on the ARM Cortex-M4 architecture to verify the anti-degradation attack performance and computing resource overhead of the above-mentioned hybrid verification method in a real industrial environment. The platform's main frequency is set to 168MHz, configured with 192KB SRAM and running a real-time operating system to simulate resource-constrained industrial field equipment. A man-in-the-middle attack node with full-traffic interception and tampering capabilities is set in the experimental topology, located between the firmware update server and the edge computing node. This node can perform deep packet inspection, PQC data stripping, and protocol header tampering operations. The firmware payload size is set to 512KB, and the PQC... The C signature algorithm uses the NIST third-round candidate algorithm CRYSTALS-Dilithium2 parameter set, and the SM2 algorithm uses the parameters recommended by the national cryptographic standard. The experimental design includes two independent test groups: a control group and the present invention sample group. The control group uses a serial verification logic based on explicit identification, that is, the receiving end parses the security level field in the communication message header, and only triggers the PQC verification process when the field indicates high. The present invention sample group uses the above-mentioned nested digest anchoring mechanism. Regardless of the external identifier, the PQC data digest is concatenated to the SM2 signature verification input. In the attack scenario, the man-in-the-middle node intercepts the firmware update message and physically strips the PQC signature data block. It then changes the security level field in the message header from High to Low and forwards the modified message to the receiving end, attempting to induce the receiving end to perform downgrade verification.

[0026] Experimental results show that, in the control group, when the receiver parses the tampered low-security-level identifier, the logical decision only requires performing SM2 verification. Because the attacker retains the unmodified firmware payload and SM2 signature, the receiver calculates the firmware payload digest. The SM2 signature verification was completed and deemed successful, resulting in the incorrect loading of firmware lacking PQC protection, thus successfully performing a downgrade attack. However, in the sample of this invention, the receiving end did not detect... This triggers the anchoring logic, which uses preset zero-value padding bits to construct the input sequence. And calculate the final verification digest. Because the sending end uses a valid SM2 signature when generating the signature. The original sequence The receiver calculates The digest generated by the sender based on the original sequence differs fundamentally from the digest generated by the sender. This difference leads to a change in the verification parameters calculated using the SM2 signature verification formula. With the signature value component carried in the message If there is a mismatch, the SM2 anchor verification fails. Based on this, the system determines that there is a potential downgrade attack and immediately blocks the firmware writing process. For a detailed comparison of the verification data, please refer to Table 1.

[0027] Table 1: Data Table on Anti-Degradation Attack Effectiveness Verification

[0028] Quantitative evaluation of computational overhead shows that, compared to the control group, the sample group of this invention only adds one SM3 hash operation and memory concatenation operation for the PQC data block. On the Cortex-M4 platform, the average time of this additional operation is 1.2ms, which accounts for only 2.7% of the total time of SM2 standard signature verification (approximately 45ms), and is far lower than the approximately 150ms required to perform a complete Dilithium2 signature verification. This indicates that the mechanism achieves deterministic defense against degradation attacks at extremely low time cost. In summary, this embodiment confirms that the nested digest anchoring mechanism can effectively utilize the mathematical characteristics of the SM2 algorithm to bind the integrity of PQC data in resource-constrained industrial embedded environments. This scheme avoids the security risks of man-in-the-middle attacks implementing protocol degradation by stripping data without increasing additional communication handshake overhead and with almost no impact on real-time performance.

[0029] Example 3: This example combines Figures 1 to 3 This section describes a hybrid verification method combining embedded firmware PQC and SM2 digital signatures, as follows: Figure 1 As shown, the process begins at the communication message input stage. After receiving the firmware update request, the system enters the data stream parsing and feature extraction stage, separating the firmware payload to be verified and the digital certificate from the message, and extracting the SM2 public key. The logical flow then enters the critical branch judgment node, which traverses the extended field of the digital certificate to confirm whether the PQC signature data block has been retrieved. If the retrieval result is yes, the process proceeds to the PQC digest generation step, where the system extracts... It then performs a hash operation to construct a cascaded anchored digest, which is formed by bitwise concatenation of the payload digest and the PQC digest. If the search result is negative, the process proceeds to the step of constructing an alternative sequence, which generates an alternative sequence using the payload summary and pre-set zero-value padding bits. The two paths mentioned above eventually converge, and the system processes the generated input sequence. or Perform a third hash operation to compute the final verification digest. Based on this, the system executes the SM2 anchoring verification step, that is, based on Perform elliptic curve verification operations and determine whether the algebraic matching relationship holds, specifically by verifying the parameters. Is it strictly equal to the signature component? If the judgment result is negative or the first-level verification fails, the process directly proceeds to execute the security blocking procedure, including sending a termination signal, clearing the memory cache, and recording the security log. If the judgment result is positive, that is, the first-level verification is confirmed to be passed, the system will immediately trigger the PQC enhanced verification step, perform lattice basis vector operation and calculate the verification norm. When the verification norm is less than the preset rejection threshold, the system will generate a verification pass instruction, thereby removing the memory write protection and updating the system boot pointer. Otherwise, the process will also switch to the security blocking procedure to ensure system security.

[0030] like Figure 2 As shown, the horizontal axis represents the PQC parameter set, covering algorithm configurations with different security strengths such as Dilithium2, Dilithium3, Dilithium5, Falcon-512, and Falcon-1024. The vertical axis represents the computation time in milliseconds (ms), ranging from 0 to 300. Solid lines represent signature generation time, and dashed lines represent signature verification time. The trends of the two lines clearly depict the increasing computation time as the complexity of the parameter set increases, for example, from Dilithium2 to Dilithium5. Dilithium5 reaches its peak signature verification time, while Falcon-512 shows a relative advantage in verification efficiency. Figure 3 As shown, the system hardware architecture is logically divided into three parts: an untrusted area, a physically isolated trusted memory and computing area, and a core storage area. The data flow originates from the cloud publishing center located in the untrusted area, is transmitted to the trusted memory and computing area via the communication interface, and is written to the payload buffer in physical isolation A and the signature buffer in physical isolation B, respectively. The payload buffer is specifically responsible for caching the firmware to be verified, while the signature buffer is used to extract and store PQC data blocks. The data flow from these two buffers eventually converges at the central anchoring logic module. Combined with the rejection threshold parameter from the root of trust OTP storage, the data is input to the hybrid verification engine SM2+PQC for processing. Only data that has passed verification is allowed to be written to the system boot partition Flash located in the core storage area.

[0031] Example 4: This example supplements the verification parameters for the algebraic matching relationship verification process in step S3 of the SM2 anchoring verification. With signature value components The principle-based deduction and verification procedure of the mathematical correlation between them is used to eliminate potential algorithmic logic black boxes and confirm that the matching relationship is not an empirical setting, but a necessary algebraic result of the SM2 algorithm signature generation and verification process under PQC data constraints. The core of SM2 signature verification lies in verifying whether the signer holds the public key. corresponding private key And verification message If the data is not tampered with during transmission, the signer calculates the digest during the standard SM2 signature generation process. Generate random numbers Calculate the points of the elliptic curve ,calculate ,calculate The signature value is In this invention, the message Defined as a concatenated sequence containing PQC signature data (e.g. Therefore, the abstract That is, corresponding to the formula above. .

[0032] In the verification logic at the receiving end, the steps described in the specific implementation are used to calculate... (Note: here) For the received signature value component, if (Then verification fails), calculate the point. Let's expand on the calculation process: because Substituting, we get: The signature generation formula will contain... Substitute: ,therefore: This indicates that if the message digest The digest used when generating the signature Consistency (i.e.) ), and signature value If valid, then the points reconstructed by the receiving end It must be related to the random point during signature generation. Overlap, that is x-coordinate equal According to the SM2 standard, the verification equation is as follows: At the receiving end, the verification parameters are calculated. ,like and Then there must be Conversely, if the PQC data is stripped or tampered with during transmission, causing errors in the receiver's calculations... ,even if and Unchanged, calculated Point (and then) Although mathematically it still satisfies (because (Unchanged), but the final verification equation middle, The change will directly lead to This deduction confirms step S3. The judgment logic is based on a rigorous mathematical proof of the elliptic curve discrete logarithm problem, rather than a simple numerical comparison, thereby ensuring a strong binding relationship between the integrity of PQC data and the SM2 verification results.

[0033] Example 5: To ensure the adaptability and stability of the nested digest anchoring mechanism under different industrial equipment and security scenarios, this example supplements the offline configuration process for the adaptive calibration of PQC algorithm parameters and hash function mapping procedures. Given the differences in the tolerance for security strength and computational latency in different industrial scenarios, the system pre-constructs a parameter configuration lookup table through controlled engineering experiments. During the offline calibration phase, for the target device's CPU frequency (e.g., 48MHz to 1GHz) and available memory (e.g., 64KB to 512MB), the signature generation and verification time under different grid dimensions and moduli are tested. Based on the test data, the system determines whether the real-time constraints are met. The optimal PQC algorithm parameter set is serialized into a binary configuration file and stored in the device's read-only memory. Simultaneously, a hash function mapping rule is explicitly defined to ensure that firmware payloads of different lengths are uniformly mapped to PQC signature data as fixed-length digest values. This adapts to the input requirements of the SM2 algorithm, eliminating the risk of verification failure due to data format mismatch. In the compatibility mode, actual engineering deployment executes a two-way signature generation and verification procedure. When supporting older firmware releases that do not integrate the PQC algorithm, the release device is configured to execute a downgraded signature process. When generating the signature input sequence, the memory area corresponding to the PQC data block is set to zero, based on the firmware payload digest. Cascaded 256-bit all-zero padding When the receiver detects that the local security policy is in compatibility mode and the message extension field is missing a PQC data block, it calculates the SM2 signature value and constructs a replacement sequence by calling a preset zero-value bit stream. Calculate the final verification summary Validate parameters With signature components The firmware payload is verified to be unaltered and the sender's identity conforms to the old protocol specification. If the sender follows the new protocol and generates a valid PQC digest... The signature is generated by the intermediate device in the transmission link stripping the PQC data block, and the receiving end constructs a replacement sequence with all-zero padding based on the missing state in compatibility mode. Leading to the final verification summary Compared with the original digest from the sender Inconsistency, elliptic curve verification parameters Not equal to signature component The system is compatible with legitimate older devices while maintaining the ability to block attacks that strip data from newer devices.

[0034] Furthermore, to address calculation errors that may arise during field deployment due to equipment aging or environmental interference, a pre-deployment calibration procedure is established. Upon initial power-on of the equipment or after major maintenance, the system automatically initiates a self-test program. This program calls preset standard test vectors, including known firmware digests, PQC signature blocks, and expected SM2 verification results. It executes a complete anchoring verification process under the current hardware environment. The system monitors intermediate variables during the signature verification process, such as the elliptic curve dot product result and the norm of the operation. If the deviation between the calculated result and the expected value exceeds the preset safety tolerance, an alarm is triggered and the system is prohibited from entering the working state. Only after the self-test passes and confirms that the hardware computing power and algorithm logic are operating normally under the current environment does the system activate the formal firmware update verification function, ensuring the stability of the technical solution in actual deployment and preventing security mechanism failures caused by environmental factors.

[0035] Example 6: In a mass production project of an industrial security gateway based on the ARM Cortex-M33 core and with TrustZone security extension enabled, this example supplements a standardized hardware-layer memory protection unit (MPU) configuration and data structure instantiation procedure to address the key technical feature of physically isolated load buffers and signature buffers mentioned in the specification. This eliminates the engineering black box regarding the specific implementation of isolation. During the system boot phase, the bootloader reads the hardware descriptor pre-stored in the one-time programmable (OTP) area, obtains the minimum memory footprint required by the current PQC algorithm (such as Dilithium2), and programs the MPU registers in the processor, dividing the memory into two non-overlapping physical memory regions: starting at address... Size is The load region, and the starting address is Size is The signature area is configured so that the MPU only allows privileged write access to these two areas to the Direct Memory Access (DMA) controller, while strictly limiting the access permissions of application layer software to privileged read or completely prohibiting access. This establishes unidirectional data flow and tamper-proof properties at the hardware physical level. The physical isolation payload buffer and signature buffer are implemented in ARM Cortex-M33 or embedded SoC embodiments with TrustZone architecture by configuring the hardware memory protection unit (MPU) region descriptor. During the system power-on boot phase, the boot program writes to the MPU control register, and the starting address in the physical memory SRAM is... length The contiguous address space is defined as a dedicated region for independent payloads, starting at address length The area is defined as a signature-only area. For the two specific areas, the MPU access permission attributes are set by the hardware to grant privileged write permissions to the Direct Memory Access (DMA) channel, while the CPU core and application software only have privileged read permissions. The hardware configuration instruction set takes effect before the execution cycle. Any operation that writes data to the buffer via CPU instructions will trigger a bus error or memory management error. The SoC internal bus architecture is built to create a physical boundary for unidirectional data flow and tamper-proof protection, independent of software logic.

[0036] For the polynomial matrix multiplication and verification norm calculations involved in the PQC enhanced verification phase, this embodiment defines a set of deterministic arithmetic implementation logic based on number-theoretic transformations (NTT) to solve the problem of ambiguous computation paths during execution. During computation, the system does not directly operate on the polynomial ring. Instead of performing complex convolution operations on the surface, the public key matrix is ​​pre-programmed. and signature vector The coefficients are mapped to the NTT domain. The processor calls assembly-level optimized fixed-point NTT butterfly instructions to perform point-value multiplication and accumulation, calculating the NTT representation of the result vector. An inverse number-theoretic transformation (INTT) is then performed to restore it to a polynomial in the coefficient field. Based on this, the verification norm is concretized by calculating the infinite norm of the restored polynomial coefficient vector. Regarding the rejection threshold In this embodiment, empirical estimation is abandoned, and a theoretical boundary calculation procedure based on lattice cryptography security reduction is adopted. The system calculates the boundary based on the modulus of the selected PQC parameter set. like and the distribution range of small polynomials Combined with the Hamming weight limit output by the hash function Probability analysis leads to the derivation that makes the probability of signature forgery lower than... A strict upper bound, for example, under a selected parameter set, Fixed to a specific integer value that satisfies the security proof, such as The derived values ​​are hard-coded into read-only memory. During runtime, the processor calculates the... Strictly smaller than the curing temperature Only when the value is reached is the PQC verification considered successful.

[0037] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0038] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A hybrid verification method combining embedded firmware PQC and SM2 digital signature, characterized in that, The method performs the following steps: Step S1, data stream parsing and feature extraction: Separate the firmware payload to be verified and digital certificate data from the received communication message, parse the digital certificate data to extract the SM2 public key and SM2 signature value, and traverse the extended field of the digital certificate data to search for the existence of PQC signature data block. Step S2: Construct cascaded anchored digests by performing a first hash operation on the firmware payload to be verified to generate a payload digest. If a PQC signature data block is retrieved, the PQC signature data block is extracted and a second hash operation is performed on it to generate a PQC digest. The payload digest and the PQC digest are concatenated bit by bit to form an input sequence. A third hash operation is performed on the input sequence to obtain the final verification digest. If no PQC signature data block is found, construct an alternative sequence containing the payload digest and preset padding bits, and calculate the hash value of the alternative sequence as the final verification digest. Step S3: Perform SM2 anchor verification. Based on the SM2 public key, SM2 signature value and final verification digest, perform elliptic curve verification operation. When the operation result confirms that the final verification digest and SM2 signature value satisfy the preset algebraic matching relationship, the first level of verification is determined to be passed, confirming that there is a mathematical binding relationship between the firmware payload to be verified and the retrieval status of the PQC signature data block. Step S4: Perform PQC enhanced verification. In response to the pass determination in step S3, call the preset lattice cryptography algorithm parameters, take the payload digest as the message input, perform lattice basis vector operation on the PQC signature data block, calculate the verification norm, and generate a verification pass instruction when the verification norm is less than the preset rejection threshold.

2. The embedded firmware PQC and SM2 digital signature hybrid verification method according to claim 1, characterized in that, In step S2, if no PQC signature data block is found, the step of constructing a substitution sequence containing a payload digest and preset padding bits and calculating the hash value of the substitution sequence as the final verification digest includes: detecting the current security policy configuration state of the system; if the security policy configuration state is a forced post-quantum protection mode, then the construction of the substitution sequence is prohibited and a verification blocking instruction is directly generated; if the security policy configuration state is a compatibility mode, then a preset zero-value bit stream is called as a preset padding bit, the payload digest and the zero-value bit stream are linearly concatenated to generate a substitution sequence, and the SM3 hash algorithm is called to calculate the substitution sequence to output the final verification digest; wherein, if the sending end uses an input sequence containing a PQC digest when generating the SM2 signature value, and the receiving end uses a substitution sequence in step S2 because no PQC signature data block is found, then the final verification digest calculated in this way will cause the elliptic curve verification operation result in step S3 to be invalid.

3. The embedded firmware PQC and SM2 digital signature hybrid verification method according to claim 1, characterized in that, In step S3, performing the elliptic curve verification operation includes the following sub-steps: parsing the SM2 signature value to obtain the first component. Second component Using the SM2 public key and the second component and elliptic curve base points Calculate the points of the elliptic curve And obtain the elliptic curve points. x-coordinate ; Using the final verification digest and x-axis Calculate verification parameters Validate parameters The calculation follows the following formula: ,in, Base point of elliptic curve The order will be used to verify the parameters. With the first component A numerical comparison is performed. If the two values ​​are equal, the result of the operation confirms that the final verification digest and the SM2 signature value satisfy the preset algebraic matching relationship.

4. The embedded firmware PQC and SM2 digital signature hybrid verification method according to claim 1, characterized in that, In step S4, the steps of performing lattice basis vector operations include: loading the public key matrix and polynomial coefficients pre-placed in the protected storage area; mapping the payload digest to a message vector on the polynomial ring; performing polynomial matrix multiplication operations based on the signature vector and message vector contained in the PQC signature data block; extracting high-order bits or low-order bits based on the result of the polynomial matrix multiplication operations, and calculating the verification norm; wherein the verification norm is an infinite norm or an Euclidean norm.

5. The embedded firmware PQC and SM2 digital signature hybrid verification method according to claim 1, characterized in that, In step S1, the steps of separating the firmware payload to be verified and the digital certificate data from the received communication message include: establishing physically isolated payload buffers and signature buffers in the trusted memory area of ​​the embedded device; writing the firmware payload to be verified into the payload buffer and writing the digital certificate data into the signature buffer through a direct memory access channel; locking the write permission of the payload buffer until the verification pass instruction is generated or the process terminates.

6. The embedded firmware PQC and SM2 digital signature hybrid verification method according to claim 1, characterized in that, In step S2, the first hash operation, the second hash operation, and the third hash operation all use the SM3 cryptographic hash algorithm; the step of concatenating the payload digest and the PQC digest bit by bit to form the input sequence includes: taking the 256-bit payload digest as the high-order data and the 256-bit PQC digest as the low-order data, performing a direct concatenation without padding in the register to generate a 512-bit input sequence.

7. The embedded firmware PQC and SM2 digital signature hybrid verification method according to claim 1, characterized in that, In step S1, the step of traversing the extended field of the digital certificate data to search for the existence of a PQC signature data block includes: parsing the ASN.1 encoding structure of the digital certificate data in sequence to locate the extended field area; reading the object identifier of the extended item item by item and comparing the read object identifier with the preset post-quantum algorithm identifier list in binary; when the comparison result is consistent, parsing the eight-bit byte string value corresponding to the extended item, identifying it as a PQC signature data block and recording its memory address offset.

8. The embedded firmware PQC and SM2 digital signature hybrid verification method according to claim 1, characterized in that, The method also includes step S5: in response to the determination of first-level verification failure in step S3 or in response to the verification norm not being less than the rejection threshold in step S4, a security blocking process is executed; The security blocking process includes: sending a termination signal to the bootloader, clearing the cached data of the firmware payload to be verified in memory, and recording the verification failure type code in the security log area. The type code is used to distinguish whether it is an SM2 anchoring verification failure or a PQC enhanced verification failure.

9. The embedded firmware PQC and SM2 digital signature hybrid verification method according to claim 1, characterized in that, The method is applied to firmware upgrade scenarios for industrial internet edge computing nodes or industrial controllers; the firmware payload to be verified is executable binary machine code or a configuration file of a field-programmable gate array. Digital certificate data follows the X.509v3 standard format, and the PQC signature data block is encapsulated in a custom extension of this standard format.

10. The embedded firmware PQC and SM2 digital signature hybrid verification method according to claim 1, characterized in that, The steps following the generation of the verification pass instruction also include: removing write protection on the non-volatile memory storing the old firmware, writing the verified firmware payload to be verified from memory to the non-volatile memory; updating the system boot pointer and performing a device soft reboot to load and run the new firmware.

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