Ethernet message transmission method, device, system and equipment and storage medium

Abstract

The invention discloses an Ethernet message transmission method, device and system, equipment and a storage medium. The method comprises the following steps: an FPGA chip obtains a first Ethernet sending message, wherein the first Ethernet sending message comprises a virtual local area network identifier; analyzing the first Ethernet sending message to obtain a virtual local area network identifier and message data without the virtual local area network identifier, and packaging the message data into a second Ethernet sending message; and transmitting the second Ethernet sending message to the outside through an Ethernet port corresponding to the virtual local area network identifier. The FPGA chip obtains a first Ethernet receiving message received through the Ethernet port, wherein the first Ethernet receiving message carries a virtual local area network identifier of the Ethernet port; forming a second Ethernet receiving message according to the first Ethernet receiving message and the virtual local area network identifier; and the message received by the second Ethernet is transmitted to the processor, the processor is supported to receive and send the message through a plurality of Ethernet ports, and more message transmission scenes are met.

Description

Technical Field

[0001] This invention relates to the field of computer network technology, and in particular to an Ethernet packet transmission method, apparatus, system, device, and storage medium. Background Technology

[0002] In current network equipment design, multi-port technology is increasingly widely used to meet the needs of different scenarios regarding the number, performance, and flexibility of network interfaces. However, existing multi-port technology architectures have certain limitations, leading to increased design complexity and cost, or failing to meet practical application requirements.

[0003] Currently, multi-port network solutions mainly employ two technical architectures. One is a one-to-one correspondence between the Ethernet controller (Media Access Control, MAC) peripheral and the physical layer (PHY) driver, with each network port requiring an independent MAC and PHY; however, most mainstream central processing units (CPUs) typically have no more than two MACs. If a project requires more network ports, a high-end CPU chip integrating more MACs must be selected, which not only increases the difficulty of chip selection but also significantly increases hardware costs.

[0004] Another approach involves expanding multiple network ports using an Ethernet switching chip, but all of these ports share the same MAC address, which cannot meet the needs of many application scenarios (such as port isolation requiring independent MAC addresses, multi-network access, or support for specific protocols). Summary of the Invention

[0005] This invention provides an Ethernet message transmission method, apparatus, system, device, and storage medium to solve the problem that traditional Ethernet communication cannot support message transmission across multiple network ports.

[0006] In a first aspect, embodiments of the present invention provide an Ethernet packet transmission method, including:

[0007] Acquire a first Ethernet transmission message, wherein the first Ethernet transmission message contains a virtual LAN identifier;

[0008] Parse the first Ethernet transmission message to obtain the virtual local area network identifier and message data without the virtual local area network identifier, and encapsulate the message data into a second Ethernet transmission message;

[0009] The second Ethernet message is transmitted outward through the Ethernet port corresponding to the virtual LAN identifier.

[0010] Secondly, embodiments of the present invention provide an Ethernet packet transmission method, including:

[0011] Acquire a first Ethernet receive packet received through the Ethernet port, wherein the first Ethernet receive packet carries the virtual LAN identifier of the Ethernet port;

[0012] The second Ethernet receive message is formed by combining the first Ethernet receive message and the virtual LAN identifier;

[0013] The second Ethernet received message is transmitted to the processor.

[0014] Thirdly, embodiments of the present invention provide an Ethernet packet transmission device, comprising:

[0015] A message transmission module and / or a message transmission module; wherein the message transmission module includes: a message acquisition submodule, a message encapsulation submodule, and a message transmission submodule;

[0016] The message acquisition submodule is used to acquire a first Ethernet message, which contains a virtual local area network identifier.

[0017] The message encapsulation submodule is used to parse the first Ethernet message to obtain the virtual local area network identifier and message data without the virtual local area network identifier, and encapsulate the message data into a second Ethernet message;

[0018] The message transmission submodule is used to transmit the second Ethernet message to the outside through the Ethernet port corresponding to the virtual LAN identifier;

[0019] The message receiving and transmission module includes: a message receiving acquisition submodule, a message receiving composition submodule, and a message receiving transmission submodule; the message receiving acquisition submodule is used to acquire a first Ethernet received message received through the Ethernet port, wherein the first Ethernet received message carries the virtual local area network identifier of the Ethernet port.

[0020] A message receiving submodule is used to compose a second Ethernet message based on the first Ethernet message and the virtual LAN identifier.

[0021] The receive message transmission submodule is used to transmit the second Ethernet receive message to the processor.

[0022] Fourthly, embodiments of the present invention provide an Ethernet packet transmission system, comprising:

[0023] The processor, a field-programmable gate array chip executing the message transmission method described in any embodiment, and a preset number of physical layer drivers;

[0024] The processor includes an Ethernet controller, and the field-programmable gate array chip includes an Ethernet control module and the preset number of Ethernet ports; the Ethernet controller is connected to the Ethernet control module, and the preset number of physical layer drivers are connected one-to-one with the preset number of Ethernet ports;

[0025] The data transmission rate of the Ethernet control module is on the first order of magnitude, and the data transmission rate of the Ethernet port is on the second order of magnitude, wherein the first order of magnitude is greater than the second order of magnitude.

[0026] Fifthly, embodiments of the present invention provide an electronic device, the electronic device comprising:

[0027] At least one processor;

[0028] At least one

[0029] and a memory communicatively connected to the at least one processor;

[0030] The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the Ethernet packet transmission method according to any embodiment of the present invention.

[0031] In a sixth aspect, embodiments of the present invention provide a computer-readable storage medium storing computer instructions that are used to cause a processor to execute and implement the Ethernet packet transmission method described in any embodiment of the present invention.

[0032] The technical solution of this invention involves acquiring a first Ethernet transmission message via an FPGA chip. This first Ethernet transmission message includes a Virtual LAN (VLAN) identifier. The first Ethernet transmission message is parsed to obtain the VLAN identifier and message data without the VLAN identifier. The message data is then encapsulated into a second Ethernet transmission message. The second Ethernet transmission message is transmitted outward through the Ethernet port corresponding to the VLAN identifier. Additionally, the FPGA chip acquires a first Ethernet reception message received through an Ethernet port. This first Ethernet reception message carries the VLAN identifier of the Ethernet port. A second Ethernet reception message is formed based on the first Ethernet reception message and the VLAN identifier. The second Ethernet reception message is then transmitted to the processor. This supports the processor receiving and sending messages through multiple Ethernet ports, solving the problem in traditional Ethernet communication where multi-port message transmission is not supported, and thus meeting more message transmission scenarios.

[0033] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a flowchart of an Ethernet packet transmission method provided in Embodiment 1 of the present invention;

[0036] Figure 2 This is a flowchart of an Ethernet packet transmission method provided in Embodiment 2 of the present invention;

[0037] Figure 3 This is a schematic diagram of the structure of an Ethernet packet transmission device including a packet transmission module provided in Embodiment 3 of the present invention;

[0038] Figure 4 This is a schematic diagram of an Ethernet packet transmission device including a packet receiving and transmission module, provided in Embodiment 3 of the present invention.

[0039] Figure 5 This is a schematic diagram of the structure of an Ethernet packet transmission device including a packet transmission module and a packet transmission module, provided in Embodiment 3 of the present invention.

[0040] Figure 6 This is a schematic diagram of the structure of an Ethernet packet transmission system provided in Embodiment 4 of the present invention;

[0041] Figure 7 A schematic diagram illustrating the process of sending Ethernet packets to the outside world;

[0042] Figure 8 A schematic diagram illustrating the principle of receiving Ethernet receive messages sent from the outside.

[0043] Figure 9 A schematic diagram of the structure of an electronic device for implementing the Ethernet packet transmission method of this invention. Detailed Implementation

[0044] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0045] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0046] Example 1

[0047] Figure 1 This is a flowchart of an Ethernet packet transmission method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where a processor sends Ethernet packets to the outside through multiple network ports. The method can be executed by an Ethernet packet transmission device, which can be implemented in hardware and / or software and can be configured in an electronic device.

[0048] This Ethernet packet transmission method can be implemented using an Ethernet packet transmission system, which includes a processor, a preset number of physical layer driver PHYs, and a field-programmable gate array (FPGA) chip. The FPGA chip enables the processor to send Ethernet packets to the outside world through multiple Ethernet ports.

[0049] like Figure 1 As shown, the method includes:

[0050] S110. Obtain the first Ethernet transmission message, which contains a virtual LAN identifier.

[0051] In this embodiment, the first Ethernet transmission message can be considered as an Ethernet transmission message sent by the processor to the FPGA chip. The processor can be, for example, a Central Processing Unit (CPU). An Ethernet transmission message can be understood as an Ethernet message generated by the processor and sent externally. An Ethernet frame is the basic transmission unit of the data link layer in a computer network, used to transmit data between devices in a local area network (LAN), and generally exists in the form of data frames. Ethernet messages need to conform to the format and rules defined by the Ethernet protocol to ensure compatibility and reliable communication between devices. This embodiment will not elaborate on the format and rules that the first Ethernet transmission message must follow.

[0052] The first Ethernet packet sent carries a Virtual Local Area Network (VLAN) identifier. The VLAN identifier can be understood as a unique identifier for a VLAN, also known as a VLAN number. A VLAN allows multiple logical subnets to be divided on the same physical network, thereby improving network security, management flexibility, and traffic isolation.

[0053] Specifically, during the process of sending Ethernet packets to the outside, the FPGA chip receives the first Ethernet packet carrying the VLAN number sent by the processor. The VLAN number is used to determine which Ethernet port to forward the Ethernet packet to.

[0054] For example, in an Ethernet packet transmission system, the FPGA chip can receive the first Ethernet packet carrying the VLAN number sent by the processor by generating the first Ethernet packet carrying the VLAN number through the processor, and sending the first Ethernet packet carrying the VLAN number to the Ethernet control module of the FPGA chip through the Ethernet controller in the processor, so that the FPGA chip can receive the first Ethernet packet carrying the VLAN number through the Ethernet control module.

[0055] S120. Parse the first Ethernet transmission message to obtain the virtual LAN identifier and the message data without the virtual LAN identifier, and encapsulate the message data into a second Ethernet transmission message.

[0056] The second Ethernet transmission message can be considered as an Ethernet transmission message sent out by the FPGA chip, for example, it could be sent to the PHY. The second Ethernet transmission message can be understood as the result of reassembling the first Ethernet transmission message.

[0057] Specifically, the FPGA chip parses the first Ethernet transmission packet to obtain the VLAN number contained in the first Ethernet transmission packet, as well as the packet data without the VLAN number. The packet data may include, for example, the data to be transmitted, length, type, and checksum sequence. The parsed packet data without the VLAN number is then re-encapsulated into a second Ethernet transmission packet for data transmission.

[0058] Understandably, the re-encapsulated second Ethernet transmission message still needs to conform to the format and rules defined by the Ethernet protocol, such as frame structure and frame data length. If these cannot be met, certain adaptation adjustments to the message data are required.

[0059] S130: Transmit the second Ethernet message to the outside through the Ethernet port corresponding to the virtual LAN identifier.

[0060] In an Ethernet packet transmission system, there can be multiple Ethernet ports, each configured with a unique virtual local area network (VLAN) identifier.

[0061] Specifically, the Ethernet port corresponding to the virtual LAN identifier is determined as the target Ethernet port, and the second Ethernet transmission message is transmitted outward through the target Ethernet port. This enables the FPGA chip to send Ethernet transmission messages to the outside through the specified Ethernet port.

[0062] The FPGA chip can transmit a second Ethernet message by sending the second Ethernet message to the physical layer driver PHY corresponding to the Ethernet port through the virtual LAN identifier. The physical layer driver is responsible for processing the second Ethernet message and transmitting it through a physical medium (such as twisted pair or optical fiber).

[0063] For example, for Gigabit Ethernet, an FPGA chip can theoretically expand to a maximum of 10 100 Mbps Ethernet ports, and for reliable expansion, it can expand to a maximum of 8 Ethernet ports. The VLAN number contained in the first Ethernet transmission packet sent by the processor can be in the range of 00 to 07.

[0064] When the VLAN number is 00, the second Ethernet packet is sent from the first Ethernet port; when the VLAN number is 01, the second Ethernet packet is sent from the second Ethernet port; when the VLAN number is 02, the second Ethernet packet is sent from the third Ethernet port; when the VLAN number is 03, the second Ethernet packet is sent from the fourth Ethernet port; when the VLAN number is 04, the second Ethernet packet is sent from the fifth Ethernet port; when the VLAN number is 05, the second Ethernet packet is sent from the sixth Ethernet port; when the VLAN number is 06, the second Ethernet packet is sent from the seventh Ethernet port; and when the VLAN number is 07, the second Ethernet packet is sent from the eighth Ethernet port.

[0065] The technical solution of this invention involves acquiring a first Ethernet transmission packet via an FPGA chip. This first Ethernet transmission packet includes a Virtual LAN (VLAN) identifier. The first Ethernet transmission packet is parsed to obtain the VLAN identifier and packet data without the VLAN identifier. The packet data is then encapsulated into a second Ethernet transmission packet. The second Ethernet transmission packet is then transmitted externally through the Ethernet port corresponding to the VLAN identifier. By determining the Ethernet port for packet transmission using the VLAN identifier in the first Ethernet transmission packet, it is possible to send Ethernet packets externally through a specified Ethernet port, providing a feasible foundation for supporting Ethernet packet transmission across multiple network ports.

[0066] As an optional embodiment, in S120, the message data is encapsulated into a second Ethernet transmission message, including:

[0067] If the length of the message data is less than the preset length, placeholders are padded to the end of the message data and it is encapsulated into a second Ethernet transmission message; the message length of the second Ethernet transmission message is determined based on the Ethernet protocol.

[0068] If the length of the message data is equal to or greater than the preset length, the message data is encapsulated into a second Ethernet transmission message.

[0069] The preset length is the message data length specified by the Ethernet protocol. In the Ethernet protocol, the message data length ranges from 64 bytes (minimum) to 1526 bytes (including the preamble), therefore, the preset length can be 64 bytes. Placeholders can be zero data or other symbols.

[0070] Specifically, the length of the first Ethernet transmission message is 64 to 1526 bytes, with the Virtual LAN identifier occupying 4 bytes. Therefore, the minimum length of the message data without the Virtual LAN identifier parsed from the first Ethernet transmission message is 60 bytes, which is less than the minimum message data length specified in the Ethernet protocol. In this embodiment, the length of the message data without the Virtual LAN identifier parsed from the first Ethernet transmission message is obtained. If the data length is greater than or equal to a preset length, no additional processing is required, and it can be directly encapsulated into a second Ethernet transmission message. If the data length is less than the preset length, placeholders need to be padded at the end of the message data to make the data length reach the preset length. The message data after padding with placeholders is then encapsulated into a second Ethernet transmission message.

[0071] For example, if the message data length is greater than or equal to 64, no placeholders are needed; it can be encapsulated directly. If the message data length is 63, 1 byte of placeholders is needed. If the message data length is 58, 2 bytes of placeholders are needed. If the message data length is 57, 3 bytes of placeholders are needed. If the message data length is 56, 4 bytes of placeholders are needed.

[0072] This embodiment fills or leaves blank placeholders on the parsed packet data that does not contain a virtual LAN identifier and encapsulates it into a second Ethernet transmission packet so that the packet data can be transmitted in subsequent packets.

[0073] As an optional embodiment, in S110, obtaining the first Ethernet transmission message includes:

[0074] Receive the first Ethernet transmission message;

[0075] The first received Ethernet transmission message is written into the buffer, and the number of messages written into the buffer is counted.

[0076] If the count value is greater than zero, the first Ethernet transmission message is read from the cache.

[0077] The cache can be a first-in-first-out (FIFO) cache.

[0078] Specifically, after receiving the first Ethernet transmission packet from the processor, the Ethernet control module of the FPGA chip writes the first Ethernet transmission packet into a buffer and counts the packets written to the buffer, incrementing the count by 1 for each packet written. It continuously checks if the count is zero. If the count is zero, it means no packet has been written to the buffer, and no processing is performed. If the count is greater than zero, it means the first transmission packet has been written to the buffer, and a first Ethernet transmission packet frame is read from the buffer.

[0079] Example 2

[0080] Figure 2 This is a flowchart of an Ethernet packet transmission method provided in Embodiment 2 of the present invention. This embodiment is applicable to situations where a processor receives Ethernet packets sent by other devices through multiple network ports. The method can be executed by an Ethernet packet transmission device, which can be implemented in hardware and / or software and can be configured in an electronic device.

[0081] This Ethernet packet transmission method can be implemented using an Ethernet packet transmission system, which includes a processor, a preset number of physical layer driver PHYs, and a field-programmable gate array (FPGA) chip. The FPGA chip enables the processor to receive Ethernet packets sent by other devices through multiple Ethernet ports.

[0082] like Figure 2 As shown, the method includes:

[0083] S210. Obtain the first Ethernet receive message received through the Ethernet port. The first Ethernet receive message carries the virtual LAN identifier of the Ethernet port.

[0084] In this context, an Ethernet port can be understood as a port in the FPGA chip used for network data connection. In this embodiment, multiple Ethernet ports can be deployed in the FPGA chip, each with a unique virtual local area network (VLAN) identifier. The first Ethernet received message can be considered an Ethernet received message transmitted from an external source to the FPGA chip; this external source could be the PHY. An Ethernet received message can be understood as an Ethernet message received from an external source and transmitted to the processor; this external source could be another device or another module within that device.

[0085] Specifically, the FPGA chip receives the first Ethernet receive message through the Ethernet port, and obtains the virtual LAN identifier (i.e., VLAN number) of the corresponding Ethernet port carried in the first Ethernet receive message.

[0086] For example, the number of Ethernet ports can be determined based on the order of magnitude of the data transmission rate of the Ethernet ports and the order of magnitude of the data transmission rate of the Ethernet controller in the processor. For Gigabit Ethernet, the FPGA chip can theoretically expand to a maximum of 10 100 Mbps Ethernet ports. For reliable expansion, a maximum of 8 Ethernet ports can be added, with each of the 8 Ethernet ports connected one-to-one to 8 physical layer driver (PHY) packets. The VLAN number carried in the first Ethernet receive packet received by the Ethernet port can be in the range of 00 to 07. The physical layer driver (PHY) receives the first Ethernet receive packet and sends it to the corresponding Ethernet port.

[0087] S220. The second Ethernet receive message is formed based on the first Ethernet receive message and the virtual LAN identifier.

[0088] The second Ethernet received message can be considered as an Ethernet received message transmitted from the FPGA chip to the processor. The second Ethernet received message can be understood as the message reassembly result of the first Ethernet received message.

[0089] Specifically, the first Ethernet receive message and the carried virtual LAN identifier are reassembled to obtain a second Ethernet receive message containing the virtual LAN identifier.

[0090] S230: Transmit the second Ethernet received message to the processor.

[0091] Specifically, the FPGA chip transmits the second Ethernet receive message to the processor through the Ethernet controller, thereby processing Ethernet receive messages that can be received from different Ethernet ports.

[0092] The technical solution of this invention uses an FPGA chip to acquire a first Ethernet received message received via an Ethernet port. This first Ethernet received message carries the virtual LAN identifier of the Ethernet port. A second Ethernet received message is then transmitted to the processor. This enables the reception of externally sent Ethernet messages through different Ethernet ports, providing a feasible foundation for supporting Ethernet message transmission across multiple network ports.

[0093] As an optional embodiment, in S210, obtaining the first Ethernet received message received through the Ethernet port includes:

[0094] Receive the first Ethernet receive message through the Ethernet port and obtain the virtual LAN identifier configured on the Ethernet port.

[0095] Write the first Ethernet received message and the virtual LAN identifier into the buffer corresponding to the Ethernet port;

[0096] The first Ethernet receive packet carrying the virtual local area network identifier is read from the cache using a periodic polling method.

[0097] Specifically, each Ethernet port corresponds to a buffer used to write the first Ethernet received packet transmitted through that Ethernet port. The FPGA chip receives the first Ethernet received packet transmitted externally through the Ethernet port and obtains the VLAN number configured on the Ethernet port that transmitted the first Ethernet received packet. It then writes the first Ethernet received packet and the VLAN number together into the buffer corresponding to the Ethernet port. The FPGA chip periodically polls the buffers corresponding to each Ethernet port. When packet data exists in the polled buffer, it reads a frame of packet data carrying a virtual LAN identifier from the buffer.

[0098] In addition, for the first Ethernet receive packet carrying the virtual LAN identifier, the first Ethernet receive packet can be written into the RAM cache, and the VLAN number can also be written into the cache, waiting to be used in the subsequent packet reassembly process.

[0099] For example, a first Ethernet packet is received from the first Ethernet port, with the VLAN number of the first Ethernet port configured as 00. The VLAN number and the first Ethernet packet are written together into FIFO buffer 1. A first Ethernet packet is received from the second Ethernet port, with the VLAN number of the second Ethernet port configured as 01. The VLAN number and the first Ethernet packet are written together into FIFO buffer 2. A first Ethernet packet is received from the third Ethernet port, with the VLAN number configured as 02. The VLAN number and the first Ethernet packet are written together into FIFO buffer 3. A first Ethernet packet is received from the fourth Ethernet port, with the VLAN number of the fourth Ethernet port configured as 03. The VLAN number and the first Ethernet packet are written together into FIFO buffer 4. The first Ethernet receive packet is input from the fifth Ethernet port. The VLAN number of the fifth Ethernet port is configured as 04. The VLAN number and the first Ethernet receive packet are written together into FIFO buffer 5. The first Ethernet receive packet is input from the sixth Ethernet port. The VLAN number of the sixth Ethernet port is configured as 05. The VLAN number and the first Ethernet receive packet are written together into FIFO buffer 6. The first Ethernet receive packet is input from the seventh Ethernet port. The VLAN number of the seventh Ethernet port is configured as 06. The VLAN number and the first Ethernet receive packet are written together into FIFO buffer 7. The first Ethernet receive packet is input from the eighth Ethernet port. The VLAN number of the eighth Ethernet port is configured as 07. The VLAN number and the first Ethernet receive packet are written together into FIFO buffer 8.

[0100] As an optional embodiment, in S220, a second Ethernet receive message is formed based on the first Ethernet receive message and the virtual LAN identifier, including:

[0101] The virtual LAN identifier is inserted into the first Ethernet receive packet to obtain the second Ethernet receive packet.

[0102] Specifically, the virtual LAN identifier is inserted into a preset position in the first Ethernet received packet, and the packet is reassembled to obtain the second Ethernet received packet. The preset position can be specified by the Ethernet protocol.

[0103] As an optional embodiment, in S230, transmitting the second Ethernet received message to the processor includes:

[0104] Generate the checksum of the second Ethernet received message;

[0105] The checksum is placed at the end of the second Ethernet received message and transmitted to the processor.

[0106] Specifically, the second Ethernet received packet, encapsulated with the VLAN number, is verified, for example using CRC32 checksum, to generate a checksum. This checksum is then placed at the end of the second Ethernet received packet and transmitted to the processor. Upon receiving the second Ethernet received packet, the processor can verify the packet based on the checksum, ensuring the data integrity of the second Ethernet received packet.

[0107] Example 3

[0108] Embodiment 3 of the present invention provides an Ethernet packet transmission device, which includes: a packet transmission module 310 and / or a packet transmission module 320; Figure 3 This is a schematic diagram of an Ethernet packet transmission device including a packet transmission module according to Embodiment 3 of the present invention. Figure 4 This is a schematic diagram of an Ethernet packet transmission device including a packet receiving and transmission module, provided in Embodiment 3 of the present invention. Figure 5 This is a schematic diagram of an Ethernet packet transmission device including a message transmission module and a message transmission module, provided in Embodiment 3 of the present invention.

[0109] Among them, such as Figure 3 or Figure 5 As shown, the message transmission module 30 includes: a message acquisition module 310, a message encapsulation submodule 320, and a message transmission submodule 330;

[0110] The message acquisition submodule 310 is used to acquire a first Ethernet message, which contains a virtual local area network identifier.

[0111] The message encapsulation submodule 320 is used to parse the first Ethernet message to obtain the virtual local area network identifier and message data without the virtual local area network identifier, and encapsulate the message data into a second Ethernet message.

[0112] The message transmission submodule 330 is used to transmit the second Ethernet message to the outside through the Ethernet port corresponding to the virtual LAN identifier;

[0113] like Figure 4 or Figure 5 As shown, the message receiving and transmission module 40 includes: a message receiving acquisition submodule 410, a message receiving composition submodule 420, and a message receiving and transmission submodule 430; wherein:

[0114] The received message acquisition submodule 410 is used to acquire a first Ethernet received message received through the Ethernet port, wherein the first Ethernet received message carries the virtual local area network identifier of the Ethernet port.

[0115] The receiving message composition submodule 420 is used to compose a second Ethernet receiving message based on the first Ethernet receiving message and the virtual LAN identifier.

[0116] The received message transmission submodule 430 is used to transmit the second Ethernet received message to the processor.

[0117] Optionally, the message encapsulation submodule 320 is specifically used for:

[0118] If the length of the message data is less than the preset length, placeholders are padded to the end of the message data and it is encapsulated into a second Ethernet transmission message; the message length of the second Ethernet transmission message is determined based on the Ethernet protocol.

[0119] If the length of the message data is equal to or greater than the preset length, the message data is encapsulated into a second Ethernet transmission message.

[0120] Optionally, the message acquisition submodule 310 is specifically used for:

[0121] Receive the first Ethernet transmission message;

[0122] The first received Ethernet transmission message is written into the buffer, and the number of messages written into the buffer is counted.

[0123] If the count value is greater than zero, the first Ethernet transmission message is read from the cache.

[0124] Optionally, the received message acquisition submodule 410 includes:

[0125] Receive the first Ethernet receive message through the Ethernet port and obtain the virtual LAN identifier configured on the Ethernet port.

[0126] Write the first Ethernet received message and the virtual LAN identifier into the buffer corresponding to the Ethernet port;

[0127] The first Ethernet receive packet carrying the virtual local area network identifier is read from the cache using a periodic polling method.

[0128] Optionally, the received message composition submodule 420 is specifically used for:

[0129] The virtual LAN identifier is inserted into the first Ethernet receive packet to obtain the second Ethernet receive packet.

[0130] Optionally, the message receiving and transmission submodule 430 is specifically used for:

[0131] Generate the checksum of the second Ethernet received message;

[0132] The checksum is placed at the end of the second Ethernet received message and transmitted to the processor.

[0133] The Ethernet packet transmission device provided in the embodiments of the present invention can execute the Ethernet packet transmission method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0134] Example 4

[0135] Figure 6 This is a schematic diagram of an Ethernet packet transmission system provided in Embodiment 4 of the present invention. Figure 6 As shown, the Ethernet packet transmission system 50 includes: a processor 51, a field-programmable gate array (FPGA) chip 52 that executes the packet transmission method described in any of the above embodiments, and a preset number (n) of physical layer drivers 53; the processor 51 includes an Ethernet controller 511, the FPGA chip 52 includes an Ethernet control module 521 and the preset number of Ethernet ports 522; the Ethernet controller 511 is connected to the Ethernet control module 521, and the preset number of physical layer drivers 53 are connected one-to-one with the preset number of Ethernet ports 522;

[0136] The data transmission rate of the Ethernet control module 521 is on the first order of magnitude, and the data transmission rate of the Ethernet port 522 is on the second order of magnitude, where the first order of magnitude is greater than the second order of magnitude. The preset quantity is determined based on the proportional relationship between the first and second orders of magnitude.

[0137] In this embodiment, a preset number of physical layer drivers 53 and a preset number of Ethernet ports 522 in the FPGA chip 52 can be connected one-to-one via the MII interface. The Ethernet control module 521 of the FPGA chip 52 and the Ethernet controller 511 of the processor 51 can be connected via the RGMII interface using a direct MAC-to-MAC connection.

[0138] Optionally, the field-programmable gate array (FPGA) chip 52 may also include a buffer module 523 for buffering Ethernet packets and / or virtual LAN identifiers. A preset number of Ethernet ports 522 can be used with a multi-channel data combiner module, and a multi-channel data combiner module can also be connected between the preset number of Ethernet ports 522 and the buffer module 523. Figure 6 (not shown in the image) and the corresponding buffer for each Ethernet port 522 ( Figure 6 (Not shown in the image), the buffer corresponding to each Ethernet port 522 is used to buffer the first Ethernet received message received by the Ethernet port, and the multi-channel data combining module is used to periodically poll the buffers corresponding to each Ethernet port 522 and send Ethernet transmit messages to the corresponding Ethernet port 522.

[0139] For example, if the processor's Ethernet controller 511 is a gigabit MAC with a data transmission rate on the gigabit order, and the field-programmable gate array (FPGA) chip 52's Ethernet port 522 is a 100-megabit MAC with a data transmission rate on the 100-megabit order, then theoretically, the FPGA chip 52 can be configured with approximately 10 Ethernet ports 522. Furthermore, to ensure transmission reliability, 8 Ethernet ports 522 can be configured to support multi-port packet transmission. It should be understood that the FPGA chip 52 can be configured with different numbers of ports depending on data transmission requirements and hardware limitations.

[0140] For example, an Ethernet message transmission system can realize a bidirectional Ethernet transmission process in which the processor sends Ethernet transmission messages to the outside through multiple Ethernet ports and receives Ethernet reception messages sent from the outside through multiple Ethernet ports.

[0141] Optionally, the field-programmable gate array chip 52 also includes a message reassembly module 524 for reassembling Ethernet transmit and receive messages.

[0142] Figure 7A schematic diagram illustrating the process of sending Ethernet packets to the outside world. (For example...) Figure 7 As shown, during the process of the processor 51 sending Ethernet transmission messages to the outside through the field-programmable gate array (FPGA) chip 52, the processor 51 generates a first Ethernet transmission message carrying a virtual local area network (VLAN) identifier, and sends the first Ethernet transmission message to the Ethernet control module 521 of the FPGA chip 52 through the Ethernet controller 511. After receiving the first Ethernet transmission message through the Ethernet control module 521, the FPGA chip 52 writes it into a FIFO buffer. The FPGA chip 52 reads a frame of the first Ethernet transmission message from the buffer, parses the first Ethernet transmission message through the message reassembly module 524 to obtain the VLAN identifier and the message data without the VLAN identifier, and encapsulates the message data into a second Ethernet transmission message. The FPGA chip 52 determines the Ethernet port 522 corresponding to the VLAN identifier through the multi-channel data combining module, and sends the second Ethernet transmission message to the physical layer driver 53 connected to the Ethernet port 522.

[0143] Figure 8 A schematic diagram illustrating the principle of receiving Ethernet receive messages sent from the outside, as shown below. Figure 8 As shown, during the process of the processor 51 receiving externally transmitted Ethernet receive packets through the field-programmable gate array (FPGA) chip 52, the physical layer driver 53 receives the first externally transmitted Ethernet receive packet and sends it to the Ethernet port 522 connected to the physical layer driver 53. After receiving the first Ethernet receive packet, the Ethernet port 522 writes the first Ethernet receive packet and the virtual local area network (VLAN) identifier of the Ethernet port 522 into the corresponding buffer of the Ethernet port 522. The multi-channel data combining module in the FPGA chip 52 periodically polls the FIFO buffers corresponding to each Ethernet port 522, reads the first Ethernet receive packet carrying the VLAN identifier from the FIFO buffer, and writes the first Ethernet receive packet into the buffer module 523. The FPGA chip 52 reads the first Ethernet receive packet from the buffer module 523 through the packet reassembly module 524, inserts the VLAN identifier into the preset position of the first Ethernet receive packet, and obtains the second Ethernet receive packet. The FPGA chip 52 sends the second Ethernet receive packet to the Ethernet controller 511 of the processor 51 through the Ethernet control module 521.

[0144] Example 5

[0145] Figure 9A schematic diagram of an electronic device 60 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0146] like Figure 9 As shown, the electronic device 60 includes at least one processor 61 and a memory, such as a read-only memory (ROM) 62 and a random access memory (RAM) 63, communicatively connected to the at least one processor 61. The memory stores computer programs executable by the at least one processor. The processor 61 can perform various appropriate actions and processes based on the computer program stored in the ROM 62 or loaded into the RAM 63 from storage unit 68. The RAM 63 may also store various programs and data required for the operation of the electronic device 60. The processor 61, ROM 62, and RAM 63 are interconnected via a bus 64. An input / output (I / O) interface 65 is also connected to the bus 64.

[0147] Multiple components in electronic device 60 are connected to I / O interface 65, including: input unit 66, such as keyboard, mouse, etc.; output unit 67, such as various types of monitors, speakers, etc.; storage unit 68, such as disk, optical disk, etc.; and communication unit 69, such as network card, modem, wireless transceiver, etc. Communication unit 69 allows electronic device 60 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0148] Processor 61 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 61 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 61 performs the various methods and processes described above, such as Ethernet packet transmission methods.

[0149] In some embodiments, the Ethernet packet transmission method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 68. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 60 via ROM 62 and / or communication unit 69. When the computer program is loaded into RAM 63 and executed by processor 61, one or more steps of the Ethernet packet transmission method described above may be performed. Alternatively, in other embodiments, processor 61 may be configured to perform the Ethernet packet transmission method by any other suitable means (e.g., by means of firmware).

[0150] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0151] In some embodiments, the Ethernet packet transmission method may be implemented as a computer program, which is implicitly included in a computer program product. When executed by a processor, the computer program implements the Ethernet packet transmission method of the present invention. The computer program product can be understood as a software product that primarily implements its solution through a computer program. The computer program used to implement the method of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer program causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer program may be executed entirely on a machine, partially on a machine, partially on a remote machine as a standalone software package, or entirely on a remote machine or server.

[0152] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0153] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0154] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0155] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0156] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0157] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for transmitting Ethernet packets, characterized in that, include: Acquire a first Ethernet transmission message, wherein the first Ethernet transmission message contains a virtual LAN identifier; Parse the first Ethernet transmission message to obtain the virtual local area network identifier and message data without the virtual local area network identifier, and encapsulate the message data into a second Ethernet transmission message; The second Ethernet message is transmitted outward through the Ethernet port corresponding to the virtual LAN identifier.

2. The method according to claim 1, characterized in that, The step of encapsulating the message data into a second Ethernet transmission message includes: If the length of the message data is less than the preset length, placeholders are padded to the end of the message data and it is encapsulated into a second Ethernet transmission message; the message length of the second Ethernet transmission message is determined based on the Ethernet protocol. If the length of the message data is equal to or greater than the preset length, the message data is encapsulated into a second Ethernet transmission message.

3. The method according to any one of claims 1-2, characterized in that, The acquisition of the first Ethernet transmission message includes: Receive the first Ethernet transmission message; The first received Ethernet transmission message is written into the buffer, and the number of messages written into the buffer is counted. If the count value is greater than zero, the first Ethernet transmission message is read from the cache.

4. An Ethernet message transmission method, characterized in that, include: Acquire a first Ethernet receive packet received through the Ethernet port, wherein the first Ethernet receive packet carries the virtual LAN identifier of the Ethernet port; The second Ethernet receive message is formed by combining the first Ethernet receive message and the virtual LAN identifier; The second Ethernet received message is transmitted to the processor.

5. The method according to claim 4, characterized in that, The step of acquiring the first Ethernet received message received through the Ethernet port includes: Receive the first Ethernet receive message through the Ethernet port and obtain the virtual LAN identifier configured on the Ethernet port. Write the first Ethernet received message and the virtual LAN identifier into the buffer corresponding to the Ethernet port; The first Ethernet receive packet carrying the virtual local area network identifier is read from the cache using a periodic polling method.

6. The method according to any one of claims 4-5, characterized in that, The step of composing a second Ethernet receive message based on the first Ethernet receive message and the virtual LAN identifier includes: The virtual LAN identifier is inserted into the first Ethernet receive packet to obtain the second Ethernet receive packet.

7. The method according to any one of claims 4-5, characterized in that, The step of transmitting the second Ethernet received message to the processor includes: Generate the checksum of the second Ethernet received message; The checksum is placed at the end of the second Ethernet received message and transmitted to the processor.

8. An Ethernet packet transmission device, characterized in that, include: A message transmission module and / or a message transmission module; The message transmission module includes: a message acquisition submodule, a message encapsulation submodule, and a message transmission submodule; the message acquisition submodule is used to acquire a first Ethernet message, wherein the first Ethernet message contains a virtual local area network identifier. The message encapsulation submodule is used to parse the first Ethernet message to obtain the virtual local area network identifier and message data without the virtual local area network identifier, and encapsulate the message data into a second Ethernet message; The message transmission submodule is used to transmit the second Ethernet message to the outside through the Ethernet port corresponding to the virtual LAN identifier; The message receiving and transmission module includes: a message receiving acquisition submodule, a message receiving composition submodule, and a message receiving transmission submodule; the message receiving acquisition submodule is used to acquire a first Ethernet received message received through the Ethernet port, wherein the first Ethernet received message carries the virtual local area network identifier of the Ethernet port. The received message composition submodule is used to compose a second Ethernet received message based on the first Ethernet received message and the virtual LAN identifier. The received message transmission submodule is used to transmit the second Ethernet received message to the processor.

9. An Ethernet message transmission system, characterized in that, include: A processor, a field-programmable gate array chip that executes the message transmission method according to any one of claims 1-7, and a predetermined number of physical layer drivers; The processor includes an Ethernet controller, and the field-programmable gate array chip includes an Ethernet control module and the preset number of Ethernet ports; The Ethernet controller is connected to the Ethernet control module, and the preset number of physical layer drivers are connected one-to-one with the preset number of Ethernet ports; The data transmission rate of the Ethernet control module is on the first order of magnitude, and the data transmission rate of the Ethernet port is on the second order of magnitude, wherein the first order of magnitude is greater than the second order of magnitude.

10. The system according to claim 9, characterized in that, The preset quantity is determined based on the metric ratio between the first order of magnitude and the second order of magnitude.

11. An electronic device, characterized in that, The electronic device includes: Processor, field-programmable gate array chip, and a predetermined number of physical layer drivers; And a memory that is communicatively connected to the field-programmable gate array chip; The memory stores a computer program that can be executed by the field-programmable gate array (FPGA) chip, and the computer program is executed by the FPGA chip to enable the FPGA chip to perform the Ethernet packet transmission method according to any one of claims 1-7.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that are used to cause a processor to execute the Ethernet packet transmission method according to any one of claims 1-7.

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