Slave station data processing method and system of process field bus based on FPGA, storage medium, electronic equipment and computer program product
By receiving and processing fieldbus data through an FPGA module, combined with a priority judgment and parsing module, the problem of high-speed transmission that a single-chip microcomputer cannot meet is solved, and efficient data acquisition and processing are achieved.
Patent Information
- Application Number
- CN202411620335.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2026-05-15
AI Technical Summary
In existing technologies, using a microcontroller to acquire fieldbus data cannot meet the requirements of high-speed transmission, resulting in untimely data acquisition, increased packet loss rate, and affecting the real-time performance and functionality of data acquisition.
An FPGA module is used to receive slave data, and the data priority is determined by the first processing module. The second processing module is used for high-speed bus transmission, and the data is parsed by a preset parsing module to achieve efficient processing of slave data.
It enables high-speed transmission and efficient acquisition of process fieldbus data, ensuring priority processing of important data and improving the real-time performance and reliability of data transmission.
Smart Images
Figure CN122053530A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data processing of process fieldbuses, and more specifically, to a slave data processing method, system, storage medium, electronic device, and computer program product based on an FPGA-based process fieldbus. Background Technology
[0002] PROFIBUS (Process Field Bus) is a process fieldbus widely used in industrial automation, building control, transportation, power and other automation control fields due to its completeness, openness and transparency as a standard, as well as its impartiality in not relying on manufacturers.
[0003] Currently, the main approach to acquiring data via fieldbus is to use embedded devices, which can be microcontrollers. However, the inventors of this application have discovered that using microcontrollers to acquire or receive data transmitted by the process fieldbus cannot fully meet the high-speed transmission requirements of the process fieldbus.
[0004] For example, in the field of automation control, the data acquisition and processing cycle is typically on the order of milliseconds, which places high demands on data processing speed. Furthermore, the data acquired via process fieldbus is often large in volume. Microcontrollers may be unable to meet the data processing requirements, leading to untimely data acquisition, increased packet loss rates, and impacting the real-time performance and functionality of the data acquisition. Summary of the Invention
[0005] According to one aspect of this application, a slave data processing method for an FPGA-based fieldbus is provided. The slave data processing method includes: receiving slave data with a preset rate from a slave station of a process fieldbus via an FPGA module; acquiring the slave data from the FPGA module through a first processing module; determining the priority of the slave data in the first processing module based on preset rules; receiving the slave data from the first processing module through a second processing module according to the priority of the slave data and a preset high-speed bus; and acquiring and parsing the slave data from the second processing module through a preset parsing module.
[0006] According to some embodiments of this application, the step of receiving slave data with a preset rate from a process fieldbus via an FPGA module may include: filtering the slave data. This filtering step may include: performing high-frequency sampling of the waveform of the slave data using a high-frequency clock unit built into the FPGA module within a preset sampling time to obtain a sampled signal of the slave data within the preset sampling time; and acquiring the slave data within the preset sampling time if the sampled signals of the slave data within the preset sampling time are consistent.
[0007] According to some embodiments of this application, the FPGA module receives slave data from the process fieldbus via a communication chip; the above-mentioned step of receiving slave data with a preset rate from the process fieldbus via the FPGA module may include: acquiring the storage state of the transmission storage unit in the FPGA module based on a preset period; controlling the working state of the communication chip according to the data storage state of the transmission storage unit; and receiving data collected by the communication chip according to the working state.
[0008] According to some embodiments of this application, the step of obtaining slave data in the FPGA module through the first processing module may include: obtaining slave data through the first processing module based on the SPI interface.
[0009] According to some embodiments of this application, the above-mentioned step of receiving slave data from the first processing module through the second processing module according to the priority of the slave data and the preset high-speed bus may include: sending slave data through the first processing module based on the first preset serial port; and receiving slave data through the second processing module based on the second preset serial port.
[0010] According to some embodiments of this application, the steps of obtaining and parsing slave data in the second processing module through the preset parsing module may include: determining the corresponding preset configuration file according to the slave type corresponding to the slave data; and parsing the slave data according to the preset configuration file through the preset parsing module.
[0011] According to one aspect of this application, a slave data processing system based on an FPGA-based process fieldbus is provided. The slave data processing system is connected to at least one slave station via the process fieldbus. The slave data processing system includes an FPGA module, a first processing module, a second processing module, and a preset parsing module. The FPGA module receives slave data with a preset rate from the slave station on the process fieldbus. The first processing module acquires the slave data from the FPGA module, determines the priority of the slave data according to preset rules, and sends the slave data according to the priority of the slave data and a preset high-speed bus. The second processing module acquires the slave data from the first processing module. The preset parsing module acquires and parses the slave data.
[0012] According to some embodiments of this application, the FPGA module performs high-frequency sampling of the waveform of the slave data based on the high-frequency clock unit built into the FPGA module within a preset sampling time to obtain the sampling signal of the slave data within the preset sampling time; if the sampling signal of the slave data within the preset sampling time is consistent, the FPGA module acquires the slave data within the preset sampling time.
[0013] According to some embodiments of this application, the FPGA module receives slave data from the process fieldbus through the communication chip; the FPGA module also acquires the storage status of the transmitting storage unit within the FPGA module based on a preset period; the FPGA module controls the working state of the communication chip according to the current storage status of the transmitting storage unit; and the FPGA module receives data collected by the communication chip according to the working state.
[0014] According to some embodiments of this application, the first processing module acquires slave data from the FPGA module based on the SPI interface.
[0015] According to some embodiments of this application, the first processing module sends slave data to the second processing module via a first preset serial port; the second processing module receives slave data from the first processing module via a second preset serial port.
[0016] According to some embodiments of this application, the preset parsing module determines the corresponding preset configuration file based on the slave type corresponding to the slave data; the preset parsing module parses the slave data according to the preset configuration file.
[0017] According to another aspect of this application, this application also provides a non-volatile computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is capable of implementing the slave data processing method based on FPGA process fieldbus as described above.
[0018] According to another aspect of this application, this application also provides an electronic device, including: one or more processors; and a storage device for storing one or more programs, which, when executed by one or more processors, enable the one or more processors to implement the FPGA-based process fieldbus slave data processing method described above.
[0019] According to another aspect of this application, this application also provides a computer program product, including: a computer program stored on a computer-readable storage medium; the computer program includes program instructions, which, when executed by a computer, cause the computer to perform the slave data processing method based on FPGA process fieldbus as described above.
[0020] Through the above technical solution, the slave data processing method provided in this application receives slave data from the process fieldbus via an FPGA module, which can meet the requirements of high-speed slave data transmission. This application uses a first processing module to determine the priority of slave data, prioritizing the transmission of higher-priority slave data, thus ensuring that more important slave data receives priority processing. This application uses a preset parsing module to parse and process the transmitted slave data, thereby determining the operating status of the corresponding slave or generating corresponding response commands. This application can achieve high-speed data acquisition from the process fieldbus. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 A schematic flowchart of a slave data processing method 1000 according to an embodiment of this application is shown;
[0023] Figure 2 A flowchart illustrating step S110 according to an embodiment of this application is shown;
[0024] Figure 3 Another flowchart illustrating step S110 according to an embodiment of this application is shown;
[0025] Figure 4 A flowchart illustrating step S120 according to an embodiment of this application is shown;
[0026] Figure 5 A flowchart illustrating step S140 according to an embodiment of this application is shown;
[0027] Figure 6 A flowchart illustrating step S150 according to an embodiment of this application is shown;
[0028] Figure 7 This diagram illustrates the structure of a slave data processing system according to an embodiment of the present application.
[0029] Figure 8 A schematic diagram showing the connection between a first processing module and a second processing module according to an embodiment of this application is provided.
[0030] Figure 9 This diagram illustrates a slave data sampling process using an FPGA module according to an embodiment of this application.
[0031] Figure label:
[0032] Slave Data Processing System 200.
[0033] FPGA module 21; first processing module 22; second processing module 23; preset parsing module 24.
[0034] The first preset serial port is 221.
[0035] The second preset serial port is 231. Detailed Implementation
[0036] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.
[0037] The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of these specific details, or other methods, components, materials, devices, etc. In these cases, well-known structures, methods, devices, implementations, materials, or operations will not be shown or described in detail.
[0038] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.
[0039] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order.
[0040] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0041] According to one aspect of this application, this application provides a slave data processing method 1000 based on an FPGA-based process fieldbus. See also Figure 1 The slave data processing method 1000 includes steps S110-S150. The slave data processing method 1000 can be executed by a slave data processing system. The slave data processing system can be a client device (such as a host) with data processing capabilities.
[0042] In step S110, the slave data processing system receives slave data with a preset rate from the slave station of the process fieldbus based on the FPGA module.
[0043] According to the example embodiment, the FPGA module is a Field Programmable Gate Array (FPGA) module. The slave data processing system can connect to at least one slave station via a process fieldbus to receive the slave station's operating status data.
[0044] For example, the slave station can be different types of field devices, such as power transmission protection devices, control devices, etc.
[0045] According to the example embodiment, slave data includes, but is not limited to, slave operating status data, fault data, and other data.
[0046] For example, the process fieldbus can support data transmission rates of 12 Mb / s or less for slave stations. Specifically, transmission rates can include: 4.8 kb / s, 9.6 kb / s, 19.2 kb / s, 31.25 kb / s, 38.4 kb / s, 45.45 kb / s, 57.6 kb / s, 93.75 kb / s, 115.2 kb / s, 187.5 kb / s, 500 kb / s, 1.5 Mb / s, 3 Mb / s, 6 Mb / s, and 12 Mb / s. This improves the compatibility of process fieldbus transmission rates.
[0047] In step S120, the slave data processing system obtains slave data from the FPGA module through the first processing module.
[0048] For example, the first processing module may be a microcontroller unit (MCU).
[0049] In step S130, the slave data processing system determines the priority of the slave data in the first processing module based on preset rules.
[0050] According to the example embodiment, the preset rules can be user-preset rules that prioritize slave data based on its status or type. The preset rules can be preset according to different slave data statuses, and this application does not impose any limitations.
[0051] For example, the slave data processing system can categorize slave data into control data, business data, and debugging data based on its type. Preset rules can assign control data as the first priority, business data as the second priority, and debugging data as the third priority. The slave data processing system determines the priority level of slave data based on these preset rules.
[0052] In step S140, the slave data processing system receives slave data from the first processing module through the second processing module according to the priority of the slave data and the preset high-speed bus.
[0053] According to the example embodiment, after determining the priority level of the slave data based on preset rules, the slave data processing system will prioritize sending the first-level slave data through the first processing module (such as the MCU module). After the first-level slave data is sent, the slave data processing system will send the second-level slave data through the first processing module. After the second-level slave data is sent, the slave data processing system will send the third-level slave data through the first processing module.
[0054] For example, the second processing module can be a central processing unit (CPU) module. The first processing module and the second processing module can be connected via a preset high-speed bus. The preset high-speed bus can be a communication line for data transmission between the first processing module and the second processing module. The preset high-speed bus can support hierarchical data transmission protocols.
[0055] According to an example embodiment, the slave data processing system receives slave data from the first processing module through a second processing module (such as a CPU module) based on the priority of the slave data and a preset high-speed bus.
[0056] For example, the slave data processing system prioritizes receiving first-level slave data through a second processing module (such as a CPU module). After receiving the first-level slave data, the slave data processing system receives second-level slave data through the second processing module. After receiving the second-level slave data, the slave data processing system receives third-level slave data through the second processing module.
[0057] In step S150, the slave data processing system obtains and parses the slave data in the second processing module through the preset parsing module.
[0058] According to the example embodiment, the preset parsing module can be a module with parsing function, such as a parsing tool or parsing application. The preset parsing module can be preset inside the second processing module or set outside the second processing module.
[0059] The slave data processing system parses and processes slave data through a preset parsing module to determine the operating status of the corresponding slave or generate response commands based on the data. The slave data processing system can also send the generated response commands to the first processing module via a second processing module. Furthermore, the slave data processing system can send the response commands to the FPGA module via the first processing module, and then, via the FPGA module, send the response commands to the process fieldbus. The slave receives the response commands via the process fieldbus.
[0060] Through the above embodiments, the slave data processing method provided in this application receives slave data from the process fieldbus via an FPGA module, which can meet the requirements of high-speed slave data transmission. This application uses a first processing module to determine the priority of the slave data and prioritizes the transmission of higher-priority slave data, thereby ensuring that more important slave data receives priority processing. This application uses a preset parsing module to parse and process the transmitted slave data, thereby determining the operating status of the corresponding slave or generating corresponding response commands. This application can achieve high-speed data acquisition from the process fieldbus.
[0061] Existing embedded devices can also use dedicated process fieldbus communication chips. However, the inventors also found that although dedicated process fieldbus communication chips have relatively complete functions, they cannot perform interference filtering on the received bus data, and their cost is high, with limited flexibility in hardware interface adaptation.
[0062] Optionally, see Figure 2 Step S110 may include step S111.
[0063] In step S111, the slave data processing system performs filtering processing on the slave data.
[0064] See Figure 2 Step S111 may include steps S111a and S111b.
[0065] In step S111a, the slave data processing system performs high-frequency sampling of the waveform of the slave data based on the high-frequency clock unit built into the FPGA module within a preset sampling time to obtain the sampled signal of the slave data within the preset sampling time.
[0066] According to an example embodiment, the FPGA module includes a high-frequency clock unit. For example, the sampling frequency of the high-frequency clock unit can be 80 Mb / s.
[0067] The preset sampling time can be the effective sampling window time for the FPGA module to perform effective sampling. For example, the sampling frequency of the high-frequency clock unit can be 80Mb / s, and the data transmission rate of the process fieldbus slave station is 12Mb / s. In order for the slave station data processing system to effectively sample based on the FPGA module, the slave station data processing system can sample no more than 7 data points of slave station data based on the FPGA module within the preset sampling time.
[0068] In step S111b, the slave data processing system acquires slave data for the preset sampling time if the sampling signals of the slave data within the preset sampling time are consistent.
[0069] According to the example embodiment, if the signals of the data points sampled by the slave data processing system are all the same within a preset sampling time, then the sampling signals of the slave data within the preset sampling time are consistent.
[0070] For example, if all data points of the slave data collected by the slave data processing system through the FPGA module are at a high level within the preset sampling time, then the slave data processing system determines that the input data of the slave data is "1".
[0071] If, within the preset sampling time, all data points acquired by the slave data processing system through the FPGA module are at a low level, the slave data processing system determines that the input data of the slave data is "0". Otherwise, the slave data processing system maintains the previous sampling result unchanged.
[0072] Through the above embodiments, this application can effectively filter external circuit noise interference by judging the consistency of data points of slave data within a preset sampling time, thereby avoiding waveform glitches in slave data that could lead to misjudgment of slave data by the slave data processing system.
[0073] Optionally, see Figure 3 Step S110 may also include steps S112, S113, and S114. Steps S112-S114 may be executed in no particular order with respect to step S111.
[0074] In step S112, the slave data processing system acquires the storage status of the transmission storage unit in the FPGA module based on a preset period.
[0075] According to an example embodiment, the FPGA module can receive slave data from the process fieldbus via a communication chip. The communication chip can convert the signal transmission type of the slave data.
[0076] For example, the communication chip can be an RS-485 chip. An RS-485 chip can convert differential signals from a process fieldbus into single-ended signals.
[0077] According to an example embodiment, the FPGA module includes a receive storage unit and a transmit storage unit. After receiving slave data from the process fieldbus via the FPGA module, the slave data processing system can cache it in the receive storage unit. After receiving a response instruction from the first processing module via the FPGA module, the slave data processing system can cache it in the transmit storage unit.
[0078] The slave data processing system can periodically acquire the storage status of the transmit storage unit within the FPGA module based on a preset period. The preset period can be a predefined time interval for the slave data processing system to acquire the storage status of the transmit storage unit.
[0079] For example, the slave data processing system can periodically acquire the signal of the data bit stored in the transmitting storage unit based on a preset period. When the signal of the data bit stored in the transmitting storage unit is high, the storage state of the transmitting storage unit is that there is data to be transmitted; when the signal of the data bit stored in the transmitting storage unit is low, the storage state of the transmitting storage unit is that there is no data to be transmitted.
[0080] In step S113, the slave data processing system controls the working state of the communication chip according to the data storage status of the transmission storage unit.
[0081] For example, if the slave data processing system receives a high-level signal from the data bit stored in the transmission storage unit, the slave data processing system will change the working state of the communication chip (such as an RS-485 chip) to the transmission state based on the FPGA module.
[0082] When the slave data processing system receives a low-level signal from the transmitting storage unit, the slave data processing system changes the working state of the communication chip (such as an RS-485 chip) to the receiving state based on the FPGA module.
[0083] In step S114, the slave data processing system receives data collected by the communication chip according to its working status.
[0084] For example, when the communication chip (such as an RS-485 chip) is in the transmit state, the slave data processing system sends a response command to the process fieldbus through the communication chip (such as an RS-485 chip).
[0085] When the communication chip (such as the RS-485 chip) is in the receiving state, the slave data processing system waits to receive response instructions from the FPGA module through the communication chip (such as the RS-485 chip).
[0086] After the slave data processing system finishes sending a response command to the process fieldbus via a communication chip (such as an RS-485 chip), the signal of the data bit stored in the transmission storage unit changes from high level to low level. Then, the slave data processing system changes the working state of the communication chip (such as an RS-485 chip) from the transmitting state to the receiving state based on the FPGA module, so that the communication chip (such as an RS-485 chip) waits for data to be received.
[0087] Optionally, see Figure 4 Step S120 may also include step S121.
[0088] In step S121, the slave data processing system acquires slave data through the first processing module based on the SPI interface.
[0089] According to the example embodiment, the SPI interface is a Serial Peripheral Interface (SPI).
[0090] The slave data processing system can also acquire slave data through the first processing module based on the CAN interface (Controller Area Network Interface) or the EMIF interface (External Memory Interface), and this application does not limit this.
[0091] When the slave data processing system obtains slave data through the SPI interface, only 4 configuration buses are needed. Compared with traditional interfaces (such as the EMIF interface), the number of buses is reduced, and the convenience and flexibility of slave data transmission are greatly improved.
[0092] Optionally, see Figure 5 Step S140 may also include steps S141 and S142.
[0093] In step S141, the slave data processing system sends slave data through the first processing module based on the first preset serial port.
[0094] According to the example embodiment, the first preset serial port is the serial port connecting the first processing module and the second processing module.
[0095] For example, the first preset serial port can be a Universal Asynchronous Receiver / Transmitter (UART).
[0096] In step S142, the slave data processing system receives slave data through the second processing module based on the second preset serial port.
[0097] According to the example embodiment, the second preset serial port is the serial port connecting the first processing module and the second processing module.
[0098] For example, the second preset serial port can also be a UART.
[0099] Optionally, see Figure 6 Step S150 may also include steps S151 and S152.
[0100] In step S151, the slave data processing system determines the corresponding preset configuration file based on the slave type corresponding to the slave data.
[0101] According to the example embodiment, the preset configuration file can be a file that includes slave configuration information and configuration parameter data. The preset configuration file can be flexibly configured according to the type of slave. Each type of slave can correspond to one preset configuration file. Each preset configuration file is an independent file.
[0102] The slave data processing system can determine the type of slave data based on the slave data, and thus determine the preset configuration file corresponding to the slave data.
[0103] In step S152, the slave data processing system parses the slave data according to the preset configuration file through the preset parsing module.
[0104] For example, after the slave data processing system determines the type of slave data and its corresponding preset configuration file based on the slave data, the system uses a preset parsing module to parse the slave data according to the preset configuration file. This allows the system to determine the operating status of the corresponding slave or generate response commands based on the slave data.
[0105] Understandably, the microcontroller solution lacks flexibility in parsing and processing data received from the process fieldbus.
[0106] Through the above embodiments, this application enables the slave data processing method to flexibly and independently parse slave data by flexibly and independently setting preset configuration files according to the type of slave station, thereby improving the parsing flexibility of slave data transmitted by the process fieldbus.
[0107] According to one aspect of this application, a slave data processing system 200 based on an FPGA-based process fieldbus is provided. See also... Figure 7The slave data processing system 200 can be connected to at least one slave station via a process fieldbus. The slave data processing system 200 includes an FPGA module 21, a first processing module 22, a second processing module 23, and a preset parsing module 24. The FPGA module 21 and the first processing module 22 can be mounted on the serial port board of the slave data processing system 200, while the second processing module 23 and the preset parsing module 24 can be mounted on the processing board of the slave data processing system 200.
[0108] According to an example embodiment, FPGA module 21 receives slave data with a preset rate from a slave station of the process fieldbus.
[0109] According to the example embodiment, FPGA module 21 is a field programmable gate array (FPGA) module that receives the operating status data of the slave station.
[0110] For example, the slave station can be different types of field devices, such as power transmission protection devices, control devices, etc.
[0111] According to the example embodiment, slave data includes, but is not limited to, slave operating status data, fault data, and other data.
[0112] For example, the process fieldbus can support data transmission rates of 12 Mb / s or less for slave stations. Specifically, transmission rates can include: 4.8 kb / s, 9.6 kb / s, 19.2 kb / s, 31.25 kb / s, 38.4 kb / s, 45.45 kb / s, 57.6 kb / s, 93.75 kb / s, 115.2 kb / s, 187.5 kb / s, 500 kb / s, 1.5 Mb / s, 3 Mb / s, 6 Mb / s, and 12 Mb / s. This improves the compatibility of process fieldbus transmission rates.
[0113] According to the example embodiment, the first processing module 22 obtains slave data from the FPGA module 21, determines the priority of the slave data according to preset rules, and sends the slave data to the second processing module 23 according to the priority of the slave data and the preset high-speed bus.
[0114] For example, the first processing module 22 can be a microcontroller unit (MCU).
[0115] According to the example embodiment, the preset rules can be user-preset rules that prioritize slave data based on its status or type. The preset rules can be preset according to different slave data statuses, and this application does not impose any limitations.
[0116] For example, the first processing module 22 (such as the MCU module) can classify slave data into control data, service data, and debugging data based on the type of slave data. A preset rule can be that control data is at the first level, service data at the second level, and debugging data at the third level. The first processing module 22 determines the priority level of the slave data based on the preset rule.
[0117] According to the example embodiment, see Figure 8 After determining the priority level of the slave data based on preset rules, the first processing module 22 can store the slave data in the storage unit of the first processing module 22. The first processing module 22 can send the slave data to the second processing module 23 through a hierarchical data transmission protocol.
[0118] For example, the first processing module 22 will prioritize sending the first-level slave data based on the priority of the slave data. After the first-level slave data is sent, the first processing module 22 will send the second-level slave data. After the second-level slave data is sent, the first processing module 22 will send the third-level slave data.
[0119] When the first processing module 22 sends second-level slave data, after receiving the first-level slave data, the first processing module 22 sends the first-level slave data after completing the transmission of the second-level slave data. After completing the transmission of the first-level slave data, the first processing module 22 continues to send second-level slave data.
[0120] When the first processing module 22 sends third-level slave data, after receiving first-level (or second-level) slave data, it sends first-level (or second-level) slave data after completing the transmission of the third-level slave data. After completing the transmission of first-level (or second-level) slave data, the first processing module 22 continues to send third-level slave data.
[0121] According to the example embodiment, the second processing module 23 acquires slave data from the first processing module 22.
[0122] For example, the second processing module 23 can be a central processing unit (CPU) module. The first processing module 22 and the second processing module 23 can be connected via a preset high-speed bus. The preset high-speed bus can be a communication line for transmitting data between the first processing module 22 and the second processing module 23. The preset high-speed bus can support hierarchical data transmission protocols.
[0123] According to an example embodiment, the second processing module 23 (such as a CPU module) receives slave data from the first processing module 22 according to the priority of the slave data and a preset high-speed bus.
[0124] For example, the second processing module 23 (such as a CPU module) prioritizes receiving the first-level slave data. After receiving the first-level slave data, the second processing module 23 sends the second-level slave data. After receiving the second-level slave data, the slave data processing system 200 receives the third-level slave data through the second processing module 23.
[0125] According to the example embodiment, the preset parsing module 24 acquires and parses the slave station data.
[0126] According to the example embodiment, the preset parsing module 24 can be a module with parsing functions, such as a parsing tool or parsing application. The preset parsing module 24 can be preset inside the second processing module 23, or it can be located outside the second processing module 23.
[0127] The pre-defined parsing module 24 parses and processes the slave data to determine the operating status of the corresponding slave or to generate a response command based on the slave data. The second processing module 23 sends the generated response command to the first processing module 22. The first processing module 22 sends the response command to the FPGA module 21, and then the FPGA module 21 sends the response command to the process fieldbus. The slave receives the response command through the process fieldbus.
[0128] Through the above embodiments, this application receives slave data from the process fieldbus via the FPGA module 21, which can meet the requirements for high-speed slave data transmission. This application uses the first processing module 22 to determine the priority of the slave data, prioritizing the transmission of higher-priority slave data, thus ensuring that more important slave data receives priority processing. This application uses a preset parsing module 24 to parse and process the transmitted slave data, thereby determining the operating status of the corresponding slave or generating corresponding response commands. This application can achieve high-speed data acquisition from the process fieldbus.
[0129] Optionally, within a preset sampling time, the FPGA module 21 performs high-frequency sampling on the waveform of the slave data based on the high-frequency clock unit built into the FPGA module 21 to obtain the sampled signal of the slave data within the preset sampling time.
[0130] According to an example embodiment, FPGA module 21 includes a high-frequency clock unit. For example, the sampling frequency of the high-frequency clock unit can be 80 Mb / s.
[0131] The preset sampling time can be the effective sampling window time for the FPGA module 21 to perform effective sampling. For example, the sampling frequency of the high-frequency clock unit can be 80Mb / s, and the data transmission rate of the process fieldbus slave station is 12Mb / s. In order for the FPGA module 21 to perform effective sampling, the FPGA module 21 will sample no more than 7 data points of slave station data within the preset sampling time.
[0132] For example, see Figure 9 Within the preset sampling time, FPGA module 21 samples data points from 4 slave stations.
[0133] According to the example embodiment, the FPGA module 21 acquires the slave data within the preset sampling time when the sampling signals of the slave data within the preset sampling time are consistent.
[0134] According to the example embodiment, if the signals of the data points sampled by the FPGA module 21 are all the same within a preset sampling time, then the sampling signals of the slave data within the preset sampling time are consistent.
[0135] For example, if all data points of the slave station data acquired by FPGA module 21 are at a high level within the preset sampling time, then FPGA module 21 determines that the input data of the slave station data is "1". If all data points of the slave station data acquired by FPGA module 21 are at a low level within the preset sampling time, then FPGA module 21 determines that the input data of the slave station data is "0". Otherwise, FPGA module 21 maintains the previous sampling result unchanged.
[0136] Through the above embodiments, this application can effectively filter external circuit noise interference by judging the consistency of data points of slave data within a preset sampling time, thereby avoiding waveform glitches in slave data that could lead to misjudgment of slave data by the slave data processing system 200.
[0137] Optionally, the FPGA module 21 receives slave data from the process fieldbus via a communication chip.
[0138] According to the example embodiment, FPGA module 21 can receive slave data from the process fieldbus via a communication chip. The communication chip can convert the transmission signal type of the slave data.
[0139] For example, the communication chip can be an RS-485 chip. An RS-485 chip can convert differential signals from a process fieldbus into single-ended signals.
[0140] According to the example embodiment, FPGA module 21 includes a receive storage unit and a transmit storage unit. After receiving slave data from the process fieldbus, FPGA module 21 can buffer it in the receive storage unit. After receiving a response instruction from the first processing module 22, FPGA module 21 can buffer it in the transmit storage unit.
[0141] According to the example embodiment, the FPGA module 21 also acquires the storage status of the transmission storage unit within the FPGA module 21 based on a preset period. The preset period can be a preset time period for the FPGA module 21 to acquire the storage status of the transmission storage unit.
[0142] For example, the FPGA module 21 can periodically acquire the signal of the data bit stored in the transmission storage unit based on a preset period. When the signal of the data bit stored in the transmission storage unit is high, the storage state of the transmission storage unit is that there is data to be transmitted; when the signal of the data bit stored in the transmission storage unit is low, the storage state of the transmission storage unit is that there is no data to be transmitted.
[0143] According to the example embodiment, the FPGA module 21 controls the working state of the communication chip based on the current storage state of the transmission storage unit.
[0144] For example, when the FPGA module 21 receives a high-level signal indicating that the data bit stored in the transmission storage unit is high, the FPGA module 21 changes the operating state of the communication chip (such as an RS-485 chip) to the transmission state.
[0145] When the FPGA module 21 receives a low-level signal from the data bit stored in the transmission storage unit, the FPGA module 21 changes the working state of the communication chip (such as an RS-485 chip) to the receiving state.
[0146] According to the example embodiment, FPGA module 21 receives data collected by the communication chip based on its operating status.
[0147] For example, when the communication chip (such as the RS-485 chip) is in the transmit state, the communication chip (such as the RS-485 chip) sends a response command to the process fieldbus.
[0148] When the communication chip (such as the RS-485 chip) is in the receiving state, the communication chip (such as the RS-485 chip) waits to receive a response command from the FPGA module 21.
[0149] When the communication chip (such as the RS-485 chip) finishes sending the response command to the process fieldbus, the signal of the data bit stored in the transmission storage unit changes from high level to low level. Then, the FPGA module 21 changes the working state of the communication chip (such as the RS-485 chip) from the transmitting state to the receiving state, so that the communication chip (such as the RS-485 chip) waits for the data to be received.
[0150] Optionally, the first processing module 22 acquires slave data from the FPGA module 21 via the SPI interface.
[0151] According to the example embodiment, the SPI interface is a Serial Peripheral Interface (SPI).
[0152] The first processing module 22 can also acquire slave data based on the CAN interface (Controller Area Network Interface) or the EMIF interface (External Memory Interface), and this application does not impose any restrictions on this.
[0153] When the first processing module 22 obtains slave data through the SPI interface, only 4 configuration buses are needed. Compared with traditional interfaces (such as the EMIF interface), the number of buses is reduced, and the convenience and flexibility of slave data transmission are greatly improved.
[0154] Optionally, the first processing module 22 sends slave data to the second processing module 23 based on the first preset serial port 221.
[0155] The second processing module 23 receives slave data from the first processing module 22 via the second preset serial port 231.
[0156] According to the example embodiment, the first preset serial port 221 is the serial port connecting the first processing module 22 and the second processing module 23. The second preset serial port 231 is the serial port connecting the first processing module 22 and the second processing module 23.
[0157] For example, both the first preset serial port 221 and the second preset serial port 231 can be Universal Asynchronous Receiver / Transmitter (UART).
[0158] Optionally, the preset parsing module 24 determines the corresponding preset configuration file based on the slave type corresponding to the slave data.
[0159] According to the example embodiment, the preset configuration file can be a file that includes slave configuration information and configuration parameter data. The preset configuration file can be flexibly configured according to the type of slave. Each type of slave can correspond to one preset configuration file. Each preset configuration file is an independent file.
[0160] The preset parsing module 24 can determine the type of slave data based on the slave data, thereby determining the preset configuration file corresponding to the slave data.
[0161] The preset parsing module 24 parses the slave station data according to a preset configuration file. For example, after determining the type of slave station data and the corresponding preset configuration file based on the slave station data, the preset parsing module 24 parses the slave station data according to the preset configuration file. This determines the operating status of the corresponding slave station or generates response instructions based on the slave station data.
[0162] Through the above embodiments, this application enables the slave data processing system 200 to flexibly and independently parse slave data by flexibly and independently setting preset configuration files according to the type of slave station, thereby improving the parsing flexibility of slave data transmitted by the process fieldbus.
[0163] According to another aspect of this application, this application also provides a non-volatile computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is capable of implementing the slave data processing method based on FPGA process fieldbus as described above.
[0164] According to another aspect of this application, this application also provides an electronic device, including: one or more processors; and a storage device for storing one or more programs, which, when executed by one or more processors, enable the one or more processors to implement the FPGA-based process fieldbus slave data processing method described above.
[0165] According to another aspect of this application, this application also provides a computer program product, including: a computer program stored on a computer-readable storage medium; the computer program includes program instructions, which, when executed by a computer, cause the computer to perform the slave data processing method based on FPGA process fieldbus as described above.
[0166] Finally, it should be noted that the above description is merely a preferred embodiment of this application and is not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions of the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A slave data processing method based on FPGA-based process fieldbus, characterized in that, The slave data processing method includes: The FPGA module receives slave data with a preset rate from the slave station of the process fieldbus. The slave data in the FPGA module is obtained through the first processing module; The priority of the slave data is determined in the first processing module based on preset rules; The second processing module receives the slave data from the first processing module according to the priority of the slave data and the preset high-speed bus. The slave data in the second processing module is obtained and parsed through a preset parsing module.
2. The slave data processing method according to claim 1, characterized in that, The FPGA-based module receives slave data with a preset rate from the process fieldbus slave station, including: The filtering process for the slave station data includes: Within a preset sampling time, the waveform of the slave data is sampled at high frequency by the high-frequency clock unit built into the FPGA module to obtain the sampled signal of the slave data within the preset sampling time. If the sampling signals of the slave data within the preset sampling time are consistent, the slave data within the preset sampling time is acquired.
3. The slave data processing method according to claim 1, characterized in that, The FPGA module receives slave data from the process fieldbus via a communication chip; The FPGA-based module receiving slave data with a preset rate from the process fieldbus also includes: The storage status of the transmission storage unit within the FPGA module is obtained based on a preset period. The operating state of the communication chip is controlled according to the data storage state of the transmission storage unit; Receive data collected by the communication chip according to the operating status.
4. The slave data processing method according to claim 1, characterized in that, The step of obtaining the slave data in the FPGA module through the first processing module includes: The slave data is obtained by the first processing module based on the SPI interface.
5. The slave data processing method according to claim 1, characterized in that, The step of receiving the slave data from the first processing module through the second processing module according to the priority of the slave data and the preset high-speed bus includes: The slave station data is sent via the first processing module based on the first preset serial port; The second processing module receives the slave station data via the second preset serial port.
6. The slave data processing method according to claim 1, characterized in that, The step of acquiring and parsing the slave data in the second processing module through the preset parsing module includes: The corresponding preset configuration file is determined based on the slave type corresponding to the slave data; The preset parsing module parses the slave data according to the preset configuration file.
7. A slave data processing system based on an FPGA-based process fieldbus, wherein the slave data processing system is connected to at least one slave station via the process fieldbus, characterized in that, The slave data processing system includes: The FPGA module receives slave data with a preset rate from the slave station of the process fieldbus; The first processing module acquires the slave data from the FPGA module, determines the priority of the slave data according to preset rules, and sends the slave data according to the priority of the slave data and a preset high-speed bus. The second processing module acquires the slave data from the first processing module; A pre-defined parsing module is used to acquire and parse the slave station data.
8. The slave data processing system according to claim 7, characterized in that, Within a preset sampling time, the FPGA module performs high-frequency sampling on the waveform of the slave data based on the high-frequency clock unit built into the FPGA module, so as to obtain the sampling signal of the slave data within the preset sampling time. If the sampling signals of the slave data within the preset sampling time are consistent, the FPGA module acquires the slave data within the preset sampling time.
9. The slave data processing system according to claim 7, characterized in that, The FPGA module receives slave data from the process fieldbus via a communication chip; The FPGA module also acquires the storage status of the transmission storage unit within the FPGA module based on a preset period; The FPGA module controls the working state of the communication chip according to the current storage state of the transmission storage unit; The FPGA module receives data collected by the communication chip based on the operating status.
10. The slave data processing system according to claim 7, characterized in that, The first processing module acquires the slave data from the FPGA module via the SPI interface.
11. The slave data processing system according to claim 7, characterized in that, The first processing module sends the slave data to the second processing module via a first preset serial port; The second processing module receives the slave data from the first processing module via a second preset serial port.
12. The slave data processing system according to claim 7, characterized in that, The preset parsing module determines the corresponding preset configuration file based on the slave type corresponding to the slave data; The preset parsing module parses the slave data according to the preset configuration file.
13. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the slave data processing method based on FPGA process fieldbus as described in any one of claims 1-6.
14. An electronic device, characterized in that, include: One or more processors; Storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the FPGA-based process fieldbus slave data processing method as described in any one of claims 1-6.
15. A computer program product, characterized in that, The method includes a computer program stored on a computer-readable storage medium, the computer program including program instructions that, when executed by a computer, cause the computer to perform the slave data processing method based on an FPGA process fieldbus as described in any one of claims 1-6.