Image processing system, image processing method and image sensor testing device

Abstract

The invention provides an image processing system, an image processing method and an image sensor testing device, and belongs to the technical field of data processing. The image processing system comprises: a first type interface for receiving image data output by an image sensor; the video recording module is electrically connected to the first type of interface, and the video recording module carries out continuous frame caching on the image data received by the first type of interface; the storage module is electrically connected to the video recording module and stores the image data cached by the video recording module; the frame extraction module is electrically connected to the first type of interface, and the frame extraction module performs frame extraction on the image data received by the first type of interface at a preset frequency; and the second type interface is electrically connected to the storage module and the frame extraction module, and the second type interface transmits the image data extracted by the frame extraction module or the image data stored by the storage module to the host. Through the image processing system provided by the invention, data storage and preview can be realized at the same time.

Description

Technical Field

[0001] This invention belongs to the field of data processing technology, and specifically relates to an image processing system and method, and an image sensor testing device. Background Technology

[0002] When testing high-speed image sensors, image data needs to be stored and a preview function on the host computer is required. This involves using multiple processing boards to distribute the high-resolution, high-frame-rate image data and then merging the image data on the host computer.

[0003] However, using multiple processing boards to split and merge image data presents several challenges. First, it requires multiple boards, increasing the potential for failure and raising hardware costs and maintenance difficulties. Second, the host computer cannot adjust the frame extraction process in real time based on the frame rate and bandwidth of the high-speed image sensor. Furthermore, relying on host-side memory for data caching can easily lead to data loss due to insufficient memory. Summary of the Invention

[0004] The purpose of this invention is to provide an image processing system and method that can solve the problems of high hardware cost, high maintenance cost and difficulty in maintenance, fixed frame extraction strategy and loss of cached data when storing and previewing image data.

[0005] To achieve the above objectives, the present invention provides an image processing system comprising at least: The first type of interface receives image data output from the image sensor; The recording module is electrically connected to the first type of interface, and the recording module performs continuous frame buffering of the image data received by the first type of interface; A storage module is electrically connected to the recording module, and the storage module stores the image data cached by the recording module; A frame extraction module, electrically connected to the first type of interface, performs frame extraction on the image data received from the first type of interface at a preset frequency; and The second type of interface is electrically connected to the storage module and the frame extraction module. The second type of interface transmits the image data extracted by the frame extraction module or the image data stored in the storage module to the host.

[0006] In one embodiment of the present invention, the image processing system further includes a command communication module, which receives control commands issued by the host and transmits the status information of the image processing system back to the host.

[0007] In one embodiment of the present invention, the image processing system further includes a clock module, which provides a synchronization clock signal for the recording module, the storage module, the frame extraction module and the command communication module.

[0008] In one embodiment of the present invention, the frame extraction module includes multiple sub-buffers and two indexes, wherein one index indicates the sub-buffer where the image data is written, and the other index indicates the sub-buffer where the image data is read.

[0009] In one embodiment of the present invention, when the frame extraction module is in normal mode, the frame extraction module performs equal-interval frame extraction on the image data received per unit time at a preset frequency.

[0010] In one embodiment of the present invention, when the frame extraction module is in an abnormal mode, the frame extraction module obtains the frame difference between adjacent image data, and extracts multiple image data in descending order of frame difference at a preset frequency.

[0011] In one embodiment of the present invention, the frame difference between adjacent image data is obtained by the following formula: ; Among them, D i Let K1 be the frame difference of the i-th frame of image data, K2 be the weighting coefficient in the vertical direction, and K1 be the weighting coefficient in the horizontal direction. Let be the standard deviation of the vertical direction of the i-th frame image data. Let be the standard deviation of the horizontal direction of the i-th frame image data. Let be the standard deviation of the image data in the vertical direction of the (i-1)th frame. denoted as the standard deviation of the horizontal direction of the image data in the (i-1)th frame.

[0012] In one embodiment of the present invention, when the frame extraction module is in verification mode, the frame extraction module continuously extracts frames from the image data received per unit time at a preset frequency.

[0013] The present invention also provides an image processing method, comprising at least the following steps: Use the first type interface to receive image data output from the image sensor; The image data received by the first type of interface is buffered frame by frame using the recording module; The image data cached by the recording module is stored using a storage module; The image data received from the first type of interface is frame-sampling using a frame-sampling module at a preset frequency; and The image data extracted by the frame extraction module or stored by the storage module is transmitted to the host using the second type interface.

[0014] In one embodiment of the present invention, the working mode of the frame extraction module is controlled according to the host command. When the frame extraction module is in normal mode, the frame extraction module performs equal-interval frame extraction on the image data received per unit time at a preset frequency. When the frame extraction module is in an abnormal mode, the frame extraction module obtains the frame difference between adjacent image data, and extracts multiple image data in descending order of frame difference at a preset frequency. When the frame extraction module is in verification mode, the frame extraction module continuously extracts frames from the image data received per unit time at a preset frequency.

[0015] The present invention also provides an image sensor testing device, including any of the above-mentioned image processing systems.

[0016] In summary, the image processing system and method, and image sensor testing device provided by this invention enable the storage and preview of image data through an image processing system. This reduces both hardware and subsequent maintenance costs, simplifying a complex system. By using a recording module to cache image data and then writing the image data in blocks into the storage module, this application avoids bandwidth bottlenecks caused by continuous writing to a single address, ensuring no data loss under high input bandwidth and enabling continuous storage of high-frequency data. Furthermore, the frame extraction module in this application is compatible with both high-frequency and low-frequency image data, allowing the host to preview image data at a preset frequency. This ensures smooth, uninterrupted image data reception, avoiding high-frequency stuttering and low-frequency frame drops. Additionally, the frame extraction module can be configured with different frame extraction modes to meet various testing requirements and scenarios. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a structural block diagram of an image processing system according to an embodiment of the present invention.

[0019] Figure 2 This is a structural block diagram of multiple sub-cache areas and two indexes in one embodiment of the present invention.

[0020] Figure 3 This is a flowchart of an image processing method according to an embodiment of the present invention.

[0021] Figure 4This is a structural block diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0022] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0024] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," and "right," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] Please combine Figure 1 As shown, the high-speed image sensor 201 has wide applications in industrial visual inspection, high-speed motion imaging, medical image acquisition, and high-definition security monitoring. When testing the high-speed image sensor 201, it is necessary to use the high-speed image sensor 201 to acquire data and transmit the acquired data to the host 203 for analysis and processing. The high-speed image sensor 201 acquires, for example, 92 pairs of Low Voltage Differential Signaling (LVDS) image data, which is transmitted to the host 203. The image data has, for example, a resolution of 5016×3080, a pixel depth of 10 bits, and a frame rate of 700 fps, with an image data bandwidth of approximately 105 Gbps. Therefore, this application provides an image sensor testing device, including a host 203 and an image processing system 100. That is, when using the host 203 to test the high-speed image sensor 201, an image processing system 100 is set between the high-speed image sensor 201 and the host 203 to store the images acquired by the high-speed image sensor 201 and to enable the host 203 to preview the image data.

[0026] Please see Figure 1As shown, the image processing system 100 provided in this application includes at least a first type interface 101, a recording module 102, a storage module 103, a frame extraction module 104, and a second type interface 107. The first type interface 101 receives image data output from an image sensor. The recording module 102 is electrically connected to the first type interface 101 and continuously buffers the image data received by the first type interface 101. The storage module 103 is electrically connected to the recording module 102 and stores the buffered image data. The frame extraction module 104 is electrically connected to the first type interface 101 and performs frame extraction on the image data received by the first type interface 101 at a preset frequency. The second type interface 107 is electrically connected to the storage module 103 and the frame extraction module 104, and transmits the image data extracted by the frame extraction module 104 or the image data stored in the storage module 103 to the host 203.

[0027] Please see Figure 1 As shown, in one embodiment of the present invention, a first type interface 101 is electrically connected to the output interface of a high-speed image sensor 201 for receiving image data output by the image sensor. The type of the first type interface 101 is selected according to the transmission characteristics between the high-speed image sensor 201 and the image processing system 100, and can be any one of a parallel differential interface, a serial differential interface, and a dedicated high-speed interface. In this embodiment, low-voltage differential signals are used for data transmission between the high-speed image sensor 201 and the image processing system 100, so a parallel differential interface can be used as the first type interface 101, i.e., an LVDS interface. Furthermore, the ordinary input / output (In / Out, IO) pairs in the Field Programmable Gate Array (FPGA) 108 can be configured as differential pairs as the first type interface 101, and channel delay compensation and image data deserialization can be performed to achieve image data synchronization.

[0028] Please see Figure 1As shown, in one embodiment of the present invention, the recording module 102 is electrically connected to the first type interface 101, and the recording module 102 performs continuous frame buffering of the image data received by the first type interface 101. The storage module 103 is electrically connected to the recording module 102, and the storage module 103 stores the image data buffered by the recording module 102. The recording module 102 and the storage module 103 are the core functional modules for carrying out continuous frame image data storage, image data management, and batch export of image data. The recording module 102 is integrated inside the field-programmable gate array 108, and the storage module 103 is implemented using a double data rate synchronous dynamic random access memory (DDR) externally connected to the field-programmable gate array 108. The size of the DDR is set according to requirements, and can be 4GB DDR, 8GB DDR, or 16GB DDR, etc.

[0029] Please see Figure 1 As shown, in one embodiment of the present invention, after the recording module 102 receives the deserialized image data from the first type interface 101, it encapsulates the image data frame by frame and adds frame header data. The frame header data includes, for example, frame sequence number, timestamp, resolution, and frame rate parameters. After encapsulating the image data, the encapsulated image data is cached in the recording module 102. When the cached image data reaches a set capacity, the encapsulated image data is written in blocks to the storage module 103 for storage. Caches the image data in the recording module 102 first, and then writes the image data in blocks to an independent address range of DDR, which avoids the bandwidth bottleneck caused by continuous writing to a single address, ensures no data loss under large input bandwidth, and achieves continuous data storage of, for example, 700 frames / s.

[0030] Please see Figure 1 As shown, in one embodiment of the present invention, a capacity calculation logic can also be built into the field programmable gate array 108 to automatically calculate the total number of frames that can be stored based on the amount of data in a single frame, monitor the occupancy rate of the storage module 103 in real time, and feed back the remaining storage time to the host 203.

[0031] Please see Figure 1 As shown, in one embodiment of the present invention, after each frame of image data is written to the storage module 103, a checksum is automatically obtained and stored in the frame header. When the host 203 reads the image data, it verifies whether the data has been corrupted due to transmission or storage errors using the checksum. When invalid frame image data occurs due to abnormal sensor output or data misalignment, the invalid frame image data can be detected and marked as invalid, thus preventing invalid frame image data from affecting subsequent testing processes.

[0032] Please see Figure 1As shown, in one embodiment of the present invention, after the image data is stored in the storage module 103, the image data can be exported from the storage module 103 according to the read command issued by the host 203. The read rate of the image data matches the bandwidth of the 10 Gigabit network card 202 between the image processing system 100 and the host 203 interface, without needing to match the input bandwidth of the image processing system 100, for example, 105 Gbps, thus reducing the requirements on the receiving performance of the host 203.

[0033] Please see Figure 1 As shown, in one embodiment of the present invention, the recording module 102 receives external trigger signals such as control commands or test commands from the host 203 to precisely start and stop recording, thereby capturing frame data under specific test scenarios and reducing invalid data storage. Simultaneously, the recording module 102 sends other control commands to the receiving host 203 and provides real-time feedback to the host 203 on the module's operating status, including recording progress, buffer occupancy rate, data verification results, and whether frame loss has occurred, facilitating user monitoring of the data storage process.

[0034] Please see Figure 1 As shown, in one embodiment of the present invention, the recording module 102 and the frame extraction module 104 share the image data received by the first type interface 101, but use independent DDR read / write channels to avoid bandwidth conflicts between storage and preview. Specifically, the real-time performance of the frame extraction module 104 can be prioritized through the internal bus arbitration mechanism of the field-programmable gate array 108, without affecting the write efficiency of the storage module 103.

[0035] Please see Figure 1 As shown, in one embodiment of the present invention, the frame extraction module 104 is electrically connected to the first type interface 101, and the frame extraction module 104 performs frame extraction on the image data received from the first type interface 101 at a preset frequency. The frame extraction module 104 can be integrated into the field-programmable gate array 108. By performing frame extraction at a preset frequency and configuring the buffer within the frame extraction module 104, the adaptive frequency of image data input and output can be ensured, and the output image data can be output without tearing or regression.

[0036] Please see Figure 1 and Figure 2As shown, in one embodiment of the present invention, the frame extraction module 104 includes multiple sub-buffers 1041 and two indices, that is, the frame extraction module 104 includes at least three sub-buffers 1041 and two indices. One index indicates the sub-buffer 1041 where the image data is written, and the other index indicates the sub-buffer 1041 where the image data is read. For example, the index indicating the sub-buffer 1041 where the image data is written is defined as the first index, and the index indicating the sub-buffer 1041 where the image data is read is defined as the second index. Then, the sub-buffer 1041 indicated by the first index is in a state where image data received from the first type interface 101 is written to the sub-buffer 1041, and the sub-buffer 1041 indicated by the second index is in a full buffer state, and the host 203 is reading image data from this sub-buffer 1041. One, two, or more sub-buffers 1041 not indicated by the first or second index are in an idle state, waiting for the sub-buffer 1041 indicated by the first index to be full of image data before writing the image data input from the first type interface 101. This application completely separates the write buffer and the read buffer by setting multiple sub-buffers 1041 and two indices in the frame extraction module 104, thereby eliminating image tearing at the hardware level.

[0037] Please see Figure 1 As shown, in one embodiment of the present invention, the frame extraction module 104 performs frame extraction at a preset frequency. That is, frame recognition logic is built into the frame extraction module 104, and the frame extraction strategy is dynamically adjusted based on the frame rate input from the image data received by the first type interface 101, ensuring that the frame extraction module 104 outputs a preset number of image data per unit time. In some embodiments, the preset frame extraction frequency is set to, for example, 30fps. In other embodiments, the preset frame extraction frequency can also be set to 25fps, 35fps, 40fps, or 50fps, etc. In this case, the frame extraction module 104 transmits image data to the host 203 at a fixed frequency, ensuring that the image data received by the host 203 is smooth and uninterrupted throughout the process.

[0038] Please see Figure 1As shown, in one embodiment of the present invention, the frame extraction module 104 is provided with multiple frame extraction modes. During the frame extraction process, the frame extraction mode of the frame extraction module 104 can be adjusted according to the needs of the host 203 to meet the image testing requirements of the host 203. The frame extraction modes of the frame extraction module 104 include, for example, a normal mode, an abnormal mode, and a verification mode. When the frame extraction module 104 is in normal mode, it performs equal-interval frame extraction on the image data received per unit time at a preset frequency. When the frame extraction module 104 is in abnormal mode, it acquires the frame difference between adjacent image data and extracts multiple image data according to the frame difference from largest to smallest at a preset frequency. When the frame extraction module 104 is in verification mode, it performs continuous frame extraction on the image data received per unit time at a preset frequency.

[0039] For details, please refer to Figure 1 As shown, in one embodiment of the present invention, when the frame extraction module 104 is in normal mode, the frame extraction module 104 can be compatible with high-frequency data, ensuring the integrity of the output of the frame extraction module 104. When the frame extraction module 104 is in normal mode, the frame extraction module 104 performs equal-interval frame extraction on the image data received per unit time at a preset frequency. At this time, the write frame rate of the frame extraction module 104 is, for example, 900fps, and the preset frame extraction frequency is, for example, 30fps, then the frame extraction interval N = input frame rate / 30 = 30. That is, one frame of image data is extracted to the host 203 every 30 frames.

[0040] Please see Figure 1 As shown, in one embodiment of the present invention, when the image scene changes significantly or abnormal frames appear, the frame extraction module 104 is set to an abnormal mode, which can make the image changes more prominent and show whether there is a problem with the image in the preview. When the frame extraction module 104 is in abnormal mode, the frame extraction module 104 obtains the frame difference between adjacent image data and extracts multiple image data in descending order of frame difference at a preset frequency. At this time, the write frame rate of the frame extraction module 104 is, for example, 900fps, and the preset frame extraction frequency is, for example, 30fps. After receiving 900 frames of image data, the frame difference between adjacent image data is obtained according to the writing order of the image data, and the 30 frames of image data with the largest frame difference are obtained in descending order of frame difference, and the 30 frames of image data with the largest frame difference are transmitted to the host 203 in the writing order of the image data.

[0041] Specifically, the frame difference between adjacent image data is obtained using the following formula: ; Among them, D i Let K1 be the frame difference of the i-th frame of image data, K2 be the weighting coefficient in the vertical direction, and K1 be the weighting coefficient in the horizontal direction. Let be the standard deviation of the vertical direction of the i-th frame image data. Let be the standard deviation of the horizontal direction of the i-th frame image data. Let be the standard deviation of the image data in the vertical direction of the (i-1)th frame. Let K1 be the standard deviation of the horizontal direction of the image data in the (i-1)th frame, where K1 + K2 1.

[0042] Please see Figure 1 As shown, in one embodiment of the present invention, when performing image evaluation on a scene, the frame extraction module 104 is set to verification mode to facilitate the statistical analysis of image standard deviation and noise, and to easily observe the noise fluctuations in the time domain. When the frame extraction module 104 is in verification mode, it continuously extracts frames from the image data received per unit time at a preset frequency. At this time, the write frame rate of the frame extraction module 104 is, for example, 900 fps, and the preset frame extraction frequency is, for example, 30 fps. Then, after the first type interface 101 begins receiving image data, 30 frames of image data are extracted to the host 203 at any time within each 1-second interval.

[0043] Please see Figure 1 As shown, in one embodiment of the present invention, when the write frame rate of the frame extraction module 104 is less than the preset frame extraction frequency, the frame extraction function is turned off, and all image data is written to the sub-buffer 1041. Based on the preset frame extraction frequency, image data is copied within the image data, so that the frame extraction module 104 outputs image data at the preset frequency. At this time, if the write frame rate of the frame extraction module 104 is, for example, 25fps, and the preset frame extraction frequency is, for example, 30fps, then all image data is written to the sub-buffer. Furthermore, when writing image data, every 5 frames of image data are written, for example, the 5th frame of image data is copied, thereby ensuring that the frame extraction module 104 still outputs image data to the host 203 at 30fps.

[0044] Please see Figure 1 As shown, in one embodiment of the present invention, when using the sub-buffer 1041 to store each frame of image data, the data format of each frame of image data is converted so that the image data output by the frame extraction module 104 conforms to the data format requirements of the second type interface 107. In this application, for example, the image data input to the first type interface 101 is converted from LVDS data format to a data packet format suitable for optical fiber transmission. Furthermore, for each frame of image data, information such as frame header, frame sequence number, timestamp, and resolution needs to be added to meet the requirements of the second type interface 107.

[0045] Please see Figure 1As shown, in one embodiment of the present invention, a command communication module 106 is also provided in the image processing system 100. The command communication module 106 receives control commands issued by the host 203 and sends back the status information of the image processing system 100 to the host 203, thereby realizing information exchange between the host 203 and the image processing system 100.

[0046] Please see Figure 1 As shown, in one embodiment of the present invention, a clock module 105 is also provided in the image processing system 100. The clock module 105 provides a synchronous clock signal for the recording module 102, the storage module 103, the frame extraction module 104 and the command communication module 106 to ensure that the timing of each module is consistent.

[0047] Please see Figure 1 As shown, in one embodiment of the present invention, the second type interface 107 connects the host 203 and the storage module 103 and frame extraction module 104 in the image processing system 100, transmitting the image data extracted by the frame extraction module 104 or the image data stored in the storage module 103 to the host 203. In this application, the second type interface 107 is, for example, a Gigabit Interface Converter (GBIC) interface, which is an interface device that converts gigabit electrical signals into optical signals, specifically, for example, a Small Form Pluggable (SFP) interface. Furthermore, a 10 Gigabit Ethernet card 202 can also be provided between the image processing system 100 and the host 203. The second type interface 107 is connected to the 10 Gigabit Ethernet card 202 via optical fiber, and interacts with the host 203 through the 10 Gigabit Ethernet card 202. The 10 Gigabit Ethernet card 202 and the host 203 are connected, for example, via a PCIe port or a USB Thunderbolt port.

[0048] Please see Figure 1 and Figure 3 As shown, the present invention also provides an image processing method using the image processing system 100 provided above, and the image processing method includes steps S101 to S105.

[0049] S101. Receive image data output by the image sensor using the first type interface.

[0050] S102. Use the recording module to buffer the image data received from the first type interface in consecutive frames.

[0051] S103. Use the storage module to store the image data cached by the recording module.

[0052] S104. Use the frame extraction module to extract frames from the image data received by the first type interface at a preset frequency.

[0053] S105. Use the second type interface to transfer the image data extracted by the frame extraction module or the image data stored by the storage module to the host.

[0054] Please see Figure 1 and Figure 3 As shown, in one embodiment of the present invention, during image processing, the host 203 sends control commands to control the recording module 102, storage module 103, and frame extraction module 104 to work simultaneously. The frame extraction module 104 enables image preview while simultaneously buffering consecutive frames of image data locally. After the image data is stored in the storage module 103, the host 203 also queries the image data stored in the storage module 103 according to control instructions.

[0055] Please see Figure 1 and Figure 3 As shown, in one embodiment of the present invention, during image processing, the working mode of the frame extraction module 104 can be controlled according to the host command. When the frame extraction module 104 is in normal mode, it performs equal-interval frame extraction on the image data received per unit time at a preset frequency. When the frame extraction module 104 is in abnormal mode, it acquires the frame difference between adjacent image data and extracts multiple image data according to the frame difference from largest to smallest at a preset frequency. When the frame extraction module 104 is in verification mode, it performs continuous frame extraction on the image data received per unit time at a preset frequency.

[0056] Please see Figure 4 As shown, the present invention also provides an electronic device, which includes a memory 302 and a processor 301. The memory 302 stores program instructions, and the processor 301 executes the program instructions in the memory 302 to implement the image processing method described above.

[0057] Please see Figure 4 As shown, the memory 302 includes at least one type of readable storage medium, including flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory can be an internal storage unit of an electronic device, such as a portable hard drive. In other embodiments, the memory can be an external storage device of the electronic device, such as a plug-in portable hard drive, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc. Furthermore, the memory can include both internal and external storage units of the electronic device. The memory can be used not only to store application software and various types of data installed on the electronic device, but also to temporarily store data that has been output or will be output.

[0058] Please see Figure 4 As shown, in some embodiments, the processor 301 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits packaged with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor is the control unit of the host computer, executing programs or modules stored in the memory and accessing data stored in the memory to perform various functions of the host computer and process data.

[0059] The processor executes the host's operating system and various installed applications. The processor executes the applications to implement the steps in the above method embodiments.

[0060] For example, the program can be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules can be a series of program instruction segments capable of performing a specific function, which describe the execution process of the program on the host.

[0061] The integrated unit implemented as a software functional module described above can be stored in a computer-readable storage medium. This software functional module, stored in a storage medium, includes several instructions to cause a computer device (which may be a personal computer, computer equipment, or network device, etc.) or processor to execute some functions of the image processing methods of the various embodiments of the present invention.

[0062] In summary, the present invention provides an image processing system and method, and an image sensor testing device. The image processing system includes at least a first type interface, a recording module, a storage module, a frame extraction module, and a second type interface. The first type interface receives image data output from the image sensor. The recording module is electrically connected to the first type interface and continuously buffers the image data received by the first type interface. The storage module is electrically connected to the recording module and stores the buffered image data. The frame extraction module is electrically connected to the first type interface and extracts frames from the image data received by the first type interface at a preset frequency. The second type interface is electrically connected to the storage module and the frame extraction module, and transmits the image data extracted by the frame extraction module or the image data stored in the storage module to the host computer.

[0063] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An image processing system, characterized in that, At least including: The first type of interface receives image data output from the image sensor; The recording module is electrically connected to the first type of interface, and the recording module performs continuous frame buffering of the image data received by the first type of interface; A storage module is electrically connected to the recording module, and the storage module stores the image data cached by the recording module; A frame extraction module is electrically connected to the first type of interface. The frame extraction module extracts frames from the image data received by the first type of interface at a preset frequency. as well as The second type of interface is electrically connected to the storage module and the frame extraction module. The second type of interface transmits the image data extracted by the frame extraction module or the image data stored in the storage module to the host.

2. The image processing system according to claim 1, characterized in that, The image processing system also includes a command communication module, which receives control commands issued by the host and sends the status information of the image processing system back to the host.

3. The image processing system according to claim 2, characterized in that, The image processing system also includes a clock module, which provides a synchronization clock signal for the recording module, the storage module, the frame extraction module, and the command communication module.

4. The image processing system according to claim 1, characterized in that, The frame extraction module includes multiple sub-buffers and two indices, wherein one index indicates the sub-buffer where the image data is written, and the other index indicates the sub-buffer where the image data is read.

5. The image processing system according to claim 1, characterized in that, When the frame extraction module is in normal mode, the frame extraction module performs equal-interval frame extraction on the image data received per unit time at a preset frequency.

6. The image processing system according to claim 1, characterized in that, When the frame extraction module is in an abnormal mode, the frame extraction module obtains the frame difference between adjacent image data and extracts multiple image data in descending order of frame difference at a preset frequency.

7. The image processing system according to claim 5, characterized in that, The frame difference between adjacent image data is obtained using the following formula: ； Among them, D i Let K1 be the frame difference of the i-th frame of image data, K2 be the weighting coefficient in the vertical direction, and K1 be the weighting coefficient in the horizontal direction. Let be the standard deviation of the vertical direction of the i-th frame image data. Let be the standard deviation of the horizontal direction of the i-th frame image data. Let be the standard deviation of the image data in the vertical direction of the (i-1)th frame. denoted as the standard deviation of the horizontal direction of the image data in the (i-1)th frame.

8. The image processing system according to claim 1, characterized in that, When the frame extraction module is in verification mode, the frame extraction module continuously extracts frames from the image data received per unit time at a preset frequency.

9. An image processing method, characterized in that, At least the following steps are included: Use the first type interface to receive image data output from the image sensor; The image data received by the first type of interface is buffered frame by frame using the recording module; The image data cached by the recording module is stored using a storage module; The frame-sampling module is used to extract frames from the image data received by the first type of interface at a preset frequency. as well as The image data extracted by the frame extraction module or stored by the storage module is transmitted to the host using the second type interface.

10. An image sensor testing device, characterized in that, Includes the image processing system as claimed in any one of claims 1 to 8.

Images