Heterogeneous computing task scheduling method and device, equipment, storage medium and product

Abstract

The invention relates to the field of integrated circuit design and computer systems, and discloses a heterogeneous computing task scheduling method, device and equipment, a storage medium and a product, the method comprises the following steps: S1, task graph construction and feature extraction: analyzing an application program to construct a directed acyclic graph reflecting a task dependency relationship, generating a task feature vector containing multi-dimensional attributes for each atomic task; and S2, dependency elasticity dynamic analysis: monitoring the dependency relationship and address access behavior between tasks in real time, and quantitatively calculating a reordering elasticity value representing the adjustability degree of the dependency relationship. According to the method, through a hardware-assisted dependency elastic analysis and speculative out-of-order execution mechanism and in cooperation with a full-dimensional resource state perception and closed-loop feedback model, the technical problems of pipeline blockage caused by weak dependency of tasks and unbalanced resource allocation under a complex load in an existing heterogeneous computing system are effectively solved.

Description

Technical Field

[0001] This application relates to the fields of integrated circuit design and computer architecture, and for example to a heterogeneous computing task scheduling method, apparatus, device, storage medium, and product. Background Technology

[0002] With the rapid development of artificial intelligence and edge computing technologies, modern System-on-Chip (SoC) has evolved into a heterogeneous computing platform integrating a general-purpose processor (CPU), a neural network processing unit (NPU), a digital signal processor (DSP), and various dedicated accelerators. Such platforms typically employ a task scheduling mechanism based on a directed acyclic graph (DAG), allocating tasks through static analysis by the compiler or simple dynamic scheduling at runtime.

[0003] However, existing heterogeneous computing task scheduling technologies face severe instruction pipeline blocking problems when dealing with strong data dependencies and dynamic loads. Traditional scheduling strategies, in order to ensure the correctness of program execution results (i.e., data consistency), often employ conservative blocking mechanisms when handling dependencies such as Write-After-Read (WAR) or Write-After-Write (WAW). For example, when a subsequent task needs to write to a buffer that is being read by a preceding task, the scheduler will force the subsequent task to wait, even if the computing resources (such as the CPU) required by the subsequent task are idle. This forced waiting due to dependencies creates a persistent "pipeline bubble" at the hardware level, causing expensive computing cores to idle for extended periods, severely limiting the chip's peak performance. This is especially problematic in scenarios with complex inter-task dependencies and significant differences in execution time, where system throughput will decrease significantly.

[0004] Furthermore, existing technologies suffer from resource status awareness issues, leading to allocation imbalances. Current schedulers typically only consider the "busy / idle" status of computing cores when dispatching tasks, neglecting cache locality, on-chip network (NoC) congestion, and the chip's real-time power consumption and temperature distribution. This "blind" scheduling easily triggers a series of performance degradation phenomena: for example, assigning high memory access intensive tasks to cores with extremely high cache miss rates leads to severe memory wall bottlenecks; or assigning high-computing-power tasks to cores with temperatures approaching thresholds triggers hardware-forced throttling, causing system stuttering. Due to the lack of a comprehensive awareness and feedback mechanism for real-time system health (such as hotspots, routing congestion, and energy efficiency ratio), existing architectures struggle to maintain optimal energy efficiency ratio (Performance / Watt) under varying loads, failing to meet the stringent requirements of edge devices for both real-time performance and low power consumption.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0007] This disclosure provides a heterogeneous computing task scheduling method based on adaptive reordering and dynamic resource allocation. This method effectively solves the technical problems of pipeline blockage caused by weak task dependencies and resource allocation imbalance under complex loads in existing heterogeneous computing systems by using hardware-assisted dependency elasticity analysis and speculative out-of-order execution mechanism, combined with full-dimensional resource status awareness and closed-loop feedback model.

[0008] In some embodiments, a heterogeneous computing task scheduling method is provided, including the following steps: S1: Task graph construction and feature extraction, parsing the application to construct a directed acyclic graph that reflects task dependencies, and generating a task feature vector containing multi-dimensional attributes for each atomic task; S2: Dependency elasticity dynamic analysis, real-time monitoring of dependencies and address access behavior between tasks, and quantitative calculation of reordering elasticity values ​​that represent the degree of adjustability of dependencies; S3: Resource status awareness, collects raw operational data of various physical sensing layers in heterogeneous computing systems, and constructs a multi-dimensional resource status vector that reflects the real-time health of the system; S4: Multi-target matching and scheduling: Based on the task feature vector and the multi-dimensional resource state vector, a weighted similarity algorithm is used to calculate the matching score and determine the target resource combination, and a scheduling instruction is generated. S5: Speculative out-of-order launch and submission. When a weak dependency is detected between tasks and the reordering elasticity value is higher than a preset threshold, an out-of-order launch mechanism is triggered. The execution results of subsequent tasks are written into an intermediate buffer for temporary storage until the preceding dependency is resolved, and then the results are submitted to the main memory. S6: Closed-loop feedback and model update. After the task is completed, the actual running data is recorded to calculate the prediction error, and the error is used to update the weight parameters used for scheduling decisions.

[0009] In step S1, the task feature vector is configured as a descriptor containing multiple fields, the fields including at least: computational intensity quantized as the ratio of floating-point numbers to memory access bytes, memory access mode identifier indicating the degree of memory access dispersion, data reuse rate calculated based on reuse distance, real-time level indicating task priority, and energy consumption sensitive bit indicating performance priority or energy efficiency priority.

[0010] In step S2, the quantization calculation of the reordering elasticity value, which represents the degree of adjustability of the dependency relationship, specifically includes: real-time capture of the address conflict probability between tasks; Get the number of cycles that downstream tasks are in the queue; Obtain the percentage of idle time slots for the target functional unit; Based on preset weighting coefficients, the address conflict probability, the number of dwell periods, and the proportion of idle time slots are weighted and calculated to obtain the reordering elasticity value, and this value is written into the dependency elasticity table.

[0011] In step S3, the data sources of the multidimensional resource state vector include at least: the idle queue depth of various computing cores, the missing counter value of the L2 cache, the virtual channel occupancy rate of the on-chip network router, and the current power consumption reading provided by the power management unit. The construction of a multidimensional resource state vector reflecting the real-time health of the system includes: using normalization logic to map physical data of different dimensions to a unified numerical range.

[0012] In step S4, determining the target resource combination includes executing multi-level arbitration logic: prioritizing the scheduling of tasks with high real-time requirements; If the real-time performance levels are the same, prioritize scheduling the task with the higher reordering elasticity value; If the reordering elasticity values ​​are similar, the task with the largest predicted energy efficiency gain will be scheduled first.

[0013] In step S5, the intermediate buffer is a flexible reordering buffer with content addressing characteristics. This step specifically includes: allocating entries in the flexible reordering buffer, recording task identifiers, data pointers pointing to the internal data area, and a previous task completion bitmap; updating the previous task completion bitmap by listening for completion signals; and triggering data transfer and releasing the corresponding entries when the bitmap indicates that all dependencies have been resolved. If an address alias conflict is detected during runtime, the corresponding entry in the elastic reordering buffer is discarded, and the task is re-added to the ready queue for execution in its original order.

[0014] In some embodiments, a heterogeneous computing device is provided, characterized in that it includes: a core control layer component, including a dependency elasticity analyzer, a resource state aggregator, and a scheduler; The dependency elasticity analyzer is configured as described in step S2 to provide the scheduler with real-time reordering elasticity values. The resource state aggregator is configured as described in step S3, providing a multi-dimensional resource state vector to the scheduler. The scheduler is configured as described in steps S1, S4 and S6, and has a built-in storage unit for storing model weights and a vector processing unit. Execution and storage layer components, including heterogeneous compute pools, resilient reordering buffers, and interconnect and storage systems; The heterogeneous computing pool includes a general-purpose processor, a neural network processing unit, and a matrix operation accelerator. The elastic reordering buffer, configured as described in step S5, is used to temporarily store data during out-of-order execution and commit data when dependencies are resolved.

[0015] In some embodiments, a computer device is provided, including: a processor and a memory storing program instructions, wherein the processor is configured to execute the above-described heterogeneous computing task scheduling method based on adaptive reordering and dynamic resource allocation when running the program instructions.

[0016] On another front, a computer-readable storage medium is provided, on which program instructions are stored, which, when executed, perform the above-described heterogeneous computing task scheduling method based on adaptive reordering and dynamic resource allocation.

[0017] On another front, a computer program product is provided, which, when run by the processor of a computer device, executes the above-mentioned heterogeneous computing task scheduling method based on adaptive reordering and dynamic resource allocation.

[0018] The method provided in this disclosure achieves the following technical effects: By working collaboratively with the Dependency Elastic Analyzer (DEA) and the Elastic Reorder Buffer (ERB), it effectively fills the "false dependency" bubbles in the instruction pipeline and improves throughput. Addressing the forced waiting problem caused by weak dependencies such as WAR / WAW mentioned in the background art, this application does not employ the traditional passive blocking strategy. Instead, it innovatively utilizes the DEA to quantify the adjustability (RE value) of dependencies in real time. When it detects that a downstream task has an address conflict risk but current computing resources (such as CPU) are idle and the RE value is high, the system decisively triggers speculative out-of-order launches. At this time, the ERB, as a highly intelligent hardware middleware layer, plays a crucial role: it provides a temporary, isolated "sandbox" space (i.e., ERB entry) for the pre-executed subsequent tasks, temporarily storing the computation results there instead of directly writing them back to main memory. This mechanism ensures that the data read by the preceding task (such as a heavy-load task running on the NPU) is not overwritten or corrupted, thus physically guaranteeing data consistency. Simultaneously, the subsequent task utilizes the CPU idle time that would otherwise be wasted. The computation is completed in time, achieving deep overlap and parallelism on the time axis between different heterogeneous units (CPU and NPU). Once the preceding task is completed, the ERB instantly completes the sequential submission of data by listening to the bus signal. This mechanism transforms serial waiting time into effective computation time, significantly improving the overall throughput of the system in resource-constrained scenarios. Furthermore, this application combines a Resource State Aggregator (RSA) and a Closed-Loop Feedback Scheduler (ARA) to solve the problem of blind resource allocation. Unlike existing technologies that only focus on "busy / idle" states, RSA constructs a multi-dimensional resource state vector (MDRSV) that includes cache miss rate, NoC virtual channel occupancy rate, and power consumption and temperature readings. The scheduler uses this panoramic view to accurately avoid computationally intensive tasks from cores with excessively high temperatures, or schedules memory-intensive tasks to nodes with better data locality, thereby avoiding frequency reduction and stuttering caused by local hotspots. This ensures that high-efficiency units (such as NPU) always operate under optimal conditions. With the online learning mechanism that updates weights based on prediction errors, the chip can dynamically adapt to constantly changing load characteristics, achieving a globally optimal balance between performance and power consumption.

[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1This is a schematic diagram of the heterogeneous computing task scheduling method provided in the embodiments of this disclosure; Figure 2 This is a block diagram of the internal logical structure of the Dependency Elastic Analyzer (DEA) and Elastic Reordering Buffer (ERB) provided in the embodiments of this disclosure; Figure 3 This is a general flowchart of the heterogeneous computing task scheduling method provided in the embodiments of this disclosure; Figure 4 This is a timing waveform diagram of speculative out-of-order launch and secure commit in a weakly dependent scenario provided by an embodiment of this disclosure; Figure 5 This is a logical schematic diagram of the multi-dimensional resource status perception and closed-loop feedback update mechanism provided in the embodiments of this disclosure; Figure 6 This is a schematic diagram of the hardware structure of a computing processing device provided in an embodiment of this disclosure. Detailed Implementation

[0021] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0022] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0023] Unless otherwise stated, the term "multiple" means two or more.

[0024] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0025] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0026] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0027] Combination Figure 1 , Figure 3 and Figure 5 As shown, this disclosure provides a heterogeneous computing task scheduling method, which is applied to a multi-core system-on-a-chip (SoC) containing heterogeneous computing units (CPU, NPU, GEMM), and specifically includes the following steps: S1: Task Graph Construction and Multidimensional Feature Extraction Steps Task Graph Construction: During the compilation or runtime loading phase, the front-end parser abstracts the application as a directed acyclic graph (DAG). Each node represents an atomic task, and each directed edge represents a data dependency.

[0028] Feature Vector Generation: The system generates a Task Feature Vector (TFV) for each task. The TFV is specifically configured as a vector with a bit width of [missing information]. N A descriptor (e.g., 128-bit) contains the following fields: Computational intensity: quantified as the ratio of floating-point operations to the number of bytes accessed (FLOPs / Byte). Memory access mode identifier: 2-bit code, 00 indicates random access, 01 indicates sequential streaming access, 10 indicates tiered access. Data reuse rate: a normalized score calculated based on reuse distance; Real-time performance level: an integer range from 0 to 10, where 10 represents a hard real-time task; Energy consumption sensitive bit: 1 bit identifier, 0 represents performance priority, 1 represents energy efficiency priority.

[0029] S2: Dependency Elasticity Dynamic Analysis Steps Based on Hardware Probes A hardware-based Dependency Resilience Analyzer (DEA) monitors and quantifies the adjustability (RE value) of dependencies in real time.

[0030] Address range monitoring: The address monitoring unit in DEA captures task data in real time by listening to the system bus. Ti and Tj The read / write address range (Base_Addr, Size).

[0031] Elasticity value calculation: DEA's internal elasticity calculation engine performs a calculation every 100 clock cycles, based on the formula... The elasticity value is obtained.

[0032] in, The probability of conflict is determined by the following formula;

[0033] This represents the number of cycles that downstream tasks remain in the queue. The percentage of idle time slots for the target functional unit; These are the weighting coefficients stored in the configuration register, with default values ​​of 0.4, 0.4, and 0.2.

[0034] Result storage: The calculated RE value is written to the Dependency Elasticity Table (DET) implemented in on-chip SRAM, with the index key (Task_ID_src, Task_ID_dst).

[0035] S3: Steps for Comprehensive Resource Status Awareness and Modeling A multidimensional resource state vector (MDRSV) reflecting the real-time health of the system is constructed using a resource state aggregator (RSA).

[0036] Data Acquisition: RSA connects to the physical sensing layer via side-band signals to collect the following raw data: the idle queue depth of various computing cores, the Miss Counter register value of the L2 cache, the virtual channel occupancy rate of the NoC router, and the current power consumption reading provided by the PMU (Power Management Unit).

[0037] Normalization processing: RSA has a built-in normalization logic circuit that maps physical data of different dimensions to the [0, 1] interval, splices them to generate a 64-dimensional MDRSV vector, and stores it in a shared register group visible to the scheduler.

[0038] S4: Multi-objective weighted matching and scheduling arbitration steps The ARA scheduler reads the TFV of the task to be scheduled and the current MDRSV, and performs dynamic resource allocation.

[0039] Similarity matching: The task is calculated using a weighted cosine similarity algorithm. T With resource combination Match score:

[0040] in, These are the weight parameters that are dynamically adjusted by the online prediction model.

[0041] Conflict arbitration: When multiple tasks compete for the same resource When (e.g., in an NPU unit), the scheduler executes cascaded comparison logic: 1. Prioritize scheduling tasks with high real-time requirements; 2. If the levels are the same, prioritize scheduling tasks with higher dependency edge RE values ​​(to maximize pipeline masking effect). 3. If the RE values ​​are similar, prioritize scheduling based on the predicted energy efficiency gain. The biggest task.

[0042] S5: Speculative Out-of-Order Launch and Secure Submission Procedures Reordering decision: The scheduler queries the DET table. If it finds that task pair (T_{prev}, T_{next}) satisfies: (1) The dependency type is weak dependency (WAR / WAW); (2) ; (3) If there are free entries in the Elastic Reorder Buffer (ERB), the out-of-order firing mechanism is triggered.

[0043] If the Elastic Reorder Buffer (ERB) has free entries, the out-of-order launch mechanism is triggered. . The execution results are not written back to main memory, but are instead written to an entry allocated in the ERB via a dedicated bus. This entry records: Task_ID, Data_Ptr (pointing to the internal data area of ​​the ERB), Dep_Mask (previous task completion bitmap), and Status (set to Pending).

[0044] Dependency Resolution and Commit: The ERB updates the Dep_Mask of each entry by listening to the Completion Bus. When the Dep_Mask of an entry is all zeros, the ERB sets the Status to Committed and triggers the DMA controller to move the data to the target SRAM or DRAM address, and then releases the entry.

[0045] Abnormal rollback: If the DEA detects an address alias conflict during execution (i.e., the previous determination that there was no conflict was wrong), the ERB immediately discards the corresponding entry, and the scheduler puts the task back into the ready queue for execution in the original order.

[0046] S6: Closed-loop feedback and model update steps After the task is completed, the system records its actual running time, energy consumption, and cache behavior, and calculates the prediction error. This error is used as a backpropagation signal to update the weight parameters of the lightweight MLP (Multilayer Perceptron) model inside the scheduler. This allows for the calibration of subsequent matching strategies.

[0047] Combination Figure 1 , Figure 2 and Figure 5Based on the above-mentioned heterogeneous computing task scheduling method with adaptive reordering and dynamic resource allocation, this disclosure provides a heterogeneous computing task scheduling device (chip), comprising: 1. Core control layer components Dependency Elastic Analyzer (DEA): Configured to execute step S2, it integrates an address comparator array (implementing the address monitoring unit) and an arithmetic logic unit based on adders and multipliers (implementing the elastic computing engine). The DEA provides the scheduler with real-time RE values ​​through a dedicated interface.

[0048] Resource State Aggregator (RSA): Configured to execute step S3, it includes a multiplexer (MUX) and normalization logic circuitry, with its input connected to the performance counters of each subsystem of the chip and its output connected to the MDRSV register group.

[0049] ARA scheduler: configured to execute steps S1, S4 and S6. The scheduler includes a microcontroller or finite state machine (FSM), an SRAM with built-in storage of MLP model weights, and a vector processing unit for calculating weighted similarity.

[0050] 2. Execution and storage layer components Heterogeneous computing pool: Contains general-purpose processors (CPUs), neural network processing units (NPUs), and matrix operation accelerators (GEMMs). Each unit is equipped with an independent instruction queue and completion signal transmitter.

[0051] Elastic Reordering Buffer (ERB): Configured to execute step S5. The ERB is physically implemented as a multi-port SRAM with content-addressable memory (CAM) characteristics, supporting fast lookups based on Task_ID. The ERB includes comparison logic circuitry for real-time checking whether the dependency mask (Dep_Mask) has returned to zero to generate a commit signal.

[0052] Interconnection and storage system: Includes a network-on-chip (NoC) router and an L2 cache controller. The NoC router is configured to support virtual channels (VCs) with different priorities and receives QoS configuration signals from the scheduler to reserve bandwidth.

[0053] The heterogeneous computing chip device based on adaptive reordering and dynamic resource allocation provided in the embodiments of this disclosure is adopted.

[0054] By using hardware-assisted DEA and ERB mechanisms, the instruction pipeline blocking problem in heterogeneous multi-core systems is solved: DEA can accurately identify dynamic weak dependencies (such as read-after-write WARs) that traditional compilers cannot determine. Combined with the temporary storage mechanism of ERB, subsequent tasks can be executed in advance using idle computing resources before the preceding tasks are completed, thereby significantly improving the overall system throughput in resource-constrained scenarios.

[0055] By using the closed-loop feedback of the MDRSV model and the ARA scheduler, the problem of resource allocation imbalance under complex loads is solved: Unlike traditional round-robin scheduling or static partitioning, this device uses a full-dimensional resource state vector (covering computing, storage, interconnection, and power consumption) to make decisions and continuously corrects the scheduling weights through online learning, ensuring that high-efficiency units (such as NPUs) are always assigned computing tasks that best suit their characteristics, thereby optimizing the system's performance ratio (Performance / Watt).

[0056] The correctness of speculative execution is ensured through an exception rollback mechanism: the speculative execution and safe commit mechanism provided by ERB enables the chip to actively perform aggressive scheduling optimization, and can still roll back to the correct state in the rare case of address conflicts, thus ensuring the semantic correctness of the program.

[0057] Given that the solutions and methods for solving the problem are similar, the specific implementation of the device in the embodiments of this specification can be referred to the foregoing method embodiments, and will not be repeated here.

[0058] To further enhance the persuasiveness of this technical solution in practical application scenarios and demonstrate how it solves specific engineering problems, a specific embodiment based on an edge-based intelligent video analysis scenario is provided below. This embodiment demonstrates how the present invention can ensure real-time performance in resource-constrained and dynamically changing embedded environments through adaptive reordering and dynamic resource allocation.

[0059] Reference Figure 4 Example 5: Specific Applications of Edge Intelligent Video Analytics This embodiment describes the specific workflow of the chip architecture applied to a high-performance smart security camera. In this scenario, the chip needs to simultaneously process image signal processing (ISP), deep learning-based target detection (such as the YOLO model), and target tracking algorithms, facing challenges of limited computing resources and extremely high real-time requirements.

[0060] 1. Scene Prediction and Task Feature Extraction (S1) Assume the chip is processing the Nth frame of a high-definition video stream. The system generates the following three key task sequences: Task (Preprocessing): The CPU performs image normalization and writes the data into buffer Buf_1.

[0061] TFV characteristics: Memory access mode = sequential, real-time performance = 8, computational intensity = low.

[0062] Task (Inference): The NPU reads Buf_1, performs convolution operations, and outputs a feature map.

[0063] TFV characteristics: Memory access mode = block, real-time performance = 10, computational intensity = high.

[0064] Task (Next frame prefetch): The CPU prepares to read the data of frame N+1 and plans to overwrite the write buffer Buf_1 to reuse memory.

[0065] TFV characteristics: Memory access mode = sequential, real-time = 6.

[0066] 2. Resource Status Awareness and Dependency Analysis (S2-S3) Dependency conflict detection: Task Need to read Buf_1, task It needs to be written to Buf_1.

[0067] DEA analysis: DEA detected... There is a read-after-write (WAR) dependency. This is a typical example of a weak dependency.

[0068] RE value calculation: DEA is calculated according to the formula. An evaluation is performed. Assuming complete address overlap ( =0), but downstream waiting time High (pipeline congestion), and execution The required general-purpose processor (CPU) is currently idle. =1.0).

[0069] The calculation result is: RE = 0.4(1) + 0.4(0.8) + 0.2(1.0) = 0.92. This value is much higher than the default threshold of 0.5, indicating that it has great value for reordering.

[0070] Hardware status awareness: RSA monitoring: Display of MDRSV generated by Resource Status Aggregator (RSA); NPU status: Busy (processing residual calculations from the previous frame), estimated to take another 500 cycles.

[0071] CPU status: Idle.

[0072] ERB status: Ample space.

[0073] Scheduling decisions and speculative execution (S4-S5) The traditional scheduling dilemma: In traditional architectures, due to... Attempt to modify The scheduler must force a block for the required data. ,until (NPU) complete. This causes the CPU to idle and delays the acquisition of the next frame, which can easily lead to frame drops.

[0074] ARA scheduler decision: RE=0.92 was detected and the resource and ERB conditions are met.

[0075] Command Launch: The scheduler decides to launch the mission ahead of schedule. Despite the prerequisite tasks Not yet completed.

[0076] Results are temporarily saved: Instead of directly overwriting Buf_14, the data of frame N+1 is written to the entry Entry_X allocated by the Elastic Reorder Buffer (ERB) and executed on the CPU.

[0077] Data protection: At this time, Buf_1 in main memory still holds the data of frame N, for use by the busy NPU (task power supply). The data was read safely without any corruption.

[0078] Dependency resolution and resource feedback (S5-S6) Sequential submission: When the NPU completes its task Then, send a completion signal.

[0079] ERB detected Pre-dependencies ( The issue has been resolved (Dep_Mask has been reset to zero).

[0080] ERB automatically commits the N+1th frame data in Entry_X to Buf_1, completing the memory state update.

[0081] Dynamic power consumption coordination: During execution, RSA detected that the NPU's temperature was approaching the threshold due to continuous high load operation.

[0082] The power consumption dimension of MDRSV triggers an alarm.

[0083] Online adjustment: When allocating resources for the next stage of the "target tracking task", the ARA scheduler uses the MLP model to predict and automatically avoid the NPU core in the high-temperature area, and instead schedules it to the backup DSP unit or reduces the frequency to prevent system lag caused by overheating and frequency reduction.

[0084] In this embodiment, the technical solution of the present invention brings significant beneficial effects: Eliminates pipeline bubbles: By utilizing DEA and ERB to handle WAR dependencies, the CPU does not need to wait when the NPU is busy, and completes the data preparation for the next frame in advance, achieving fully parallel and overlapping execution of the CPU and NPU.

[0085] Avoid memory data contention: ERB acts as a hardware-level "version controller," ensuring data consistency under aggressive out-of-order scheduling without the need for complex software locking mechanisms.

[0086] System stability is ensured: MDRSV-based thermal sensing scheduling prevents sudden performance degradation of edge devices due to local overheating, ensuring the frame rate stability (FPS Stability) of video stream analysis.

[0087] Combination Figure 6 As shown, this disclosure provides a computing device including a processor 904 and a memory 901. Optionally, the device may further include a communication interface 902 and a bus 903. The processor 904, communication interface 902, and memory 901 can communicate with each other via the bus 903. The communication interface 902 can be used for information transmission. The processor 904 can call logical instructions in the memory 901 to execute the heterogeneous computing task scheduling method based on adaptive reordering and dynamic resource allocation described in the above embodiments.

[0088] Furthermore, the logic instructions in the aforementioned memory 901 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0089] The memory 901, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 904 executes functional applications and data processing by running the program instructions / modules stored in the memory 901, thereby implementing the heterogeneous computing task scheduling method based on adaptive reordering and dynamic resource allocation in the above embodiments.

[0090] The memory 901 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 901 may include high-speed random access memory and may also include non-volatile memory.

[0091] This disclosure provides a computer program product, which is a software product that mainly implements the methods described in this specification through a computer program.

[0092] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to perform the above-described method.

[0093] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0094] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0095] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0096] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0097] The methods and products disclosed in the embodiments herein (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0098] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks, and the operations or steps corresponding to different blocks in the flowchart and block diagram descriptions, may occur in a different order than indicated in the drawings or descriptions. For example, two consecutive blocks or operation steps may actually be executed substantially in parallel, or sometimes in reverse order, depending on the functions involved. Sometimes there is no specific order between different operations or steps. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A heterogeneous computing task scheduling method, characterized in that, Includes the following steps: S1: Task graph construction and feature extraction, parsing the application to construct a directed acyclic graph that reflects task dependencies, and generating a task feature vector containing multi-dimensional attributes for each atomic task; S2: Dependency elasticity dynamic analysis, real-time monitoring of dependencies and address access behavior between tasks, and quantitative calculation of reordering elasticity values ​​that represent the degree of adjustability of dependencies; S3: Resource status awareness, collects raw operational data of various physical sensing layers in heterogeneous computing systems, and constructs a multi-dimensional resource status vector that reflects the real-time health of the system; S4: Multi-target matching and scheduling: Based on the task feature vector and the multi-dimensional resource state vector, a weighted similarity algorithm is used to calculate the matching score and determine the target resource combination, and a scheduling instruction is generated. S5: Speculative out-of-order launch and submission. When a weak dependency is detected between tasks and the reordering elasticity value is higher than a preset threshold, an out-of-order launch mechanism is triggered. The execution results of subsequent tasks are written into an intermediate buffer for temporary storage until the preceding dependency is resolved, and then the results are submitted to the main memory. S6: Closed-loop feedback and model update. After the task is completed, the actual running data is recorded to calculate the prediction error, and the error is used to update the weight parameters used for scheduling decisions.

2. The heterogeneous computing task scheduling method according to claim 1, characterized in that, In step S1, the task feature vector is configured as a descriptor containing multiple fields, the fields including at least: computational intensity quantized as the ratio of floating-point numbers to memory access bytes, memory access mode identifier indicating the degree of memory access dispersion, data reuse rate calculated based on reuse distance, real-time level indicating task priority, and energy consumption sensitive bit indicating performance priority or energy efficiency priority.

3. The heterogeneous computing task scheduling method according to claim 1, characterized in that, In step S2, the quantization calculation of the reordering elasticity value, which represents the degree of adjustability of the dependency relationship, specifically includes: real-time capture of the address conflict probability between tasks; Get the number of cycles that downstream tasks are in the queue; Obtain the percentage of idle time slots for the target functional unit; Based on preset weighting coefficients, the address conflict probability, the number of dwell periods, and the proportion of idle time slots are weighted and calculated to obtain the reordering elasticity value, and this value is written into the dependency elasticity table.

4. The heterogeneous computing task scheduling method according to claim 1, characterized in that, In step S3, the data sources of the multidimensional resource state vector include at least: the idle queue depth of various computing cores, the missing counter value of the L2 cache, the virtual channel occupancy rate of the on-chip network router, and the current power consumption reading provided by the power management unit. The construction of a multidimensional resource state vector reflecting the real-time health of the system includes: using normalization logic to map physical data of different dimensions to a unified numerical range.

5. The heterogeneous computing task scheduling method according to claim 1, characterized in that, In step S4, determining the target resource combination includes executing multi-level arbitration logic: prioritizing the scheduling of tasks with high real-time requirements; If the real-time performance levels are the same, prioritize scheduling the task with the higher reordering elasticity value; If the reordering elasticity values ​​are similar, the task with the largest predicted energy efficiency gain will be scheduled first.

6. The heterogeneous computing task scheduling method according to claim 1, characterized in that, In step S5, the intermediate buffer is a flexible reordering buffer with content addressing characteristics. This step specifically includes: allocating entries in the flexible reordering buffer, recording task identifiers, data pointers pointing to the internal data area, and a previous task completion bitmap; updating the previous task completion bitmap by listening for completion signals; and triggering data transfer and releasing the corresponding entries when the bitmap indicates that all dependencies have been resolved. If an address alias conflict is detected during runtime, the corresponding entry in the elastic reordering buffer is discarded, and the task is re-added to the ready queue for execution in its original order.

7. A heterogeneous computing task scheduling device, characterized in that, include: The core control layer components include a dependency resilience analyzer, a resource state aggregator, and a scheduler. The dependency elasticity analyzer is configured to provide the scheduler with real-time reordering elasticity values ​​in step S2 as described in claim 1. The resource state aggregator is configured to provide a multi-dimensional resource state vector to the scheduler as described in step S3 of claim 1. The scheduler, configured as described in steps S1, S4 and S6 of claim 1, has a built-in storage unit for storing model weights and a vector processing unit. Execution and storage layer components, including heterogeneous compute pools, resilient reordering buffers, and interconnect and storage systems; The heterogeneous computing pool includes a general-purpose processor, a neural network processing unit, and a matrix operation accelerator. The elastic reordering buffer, configured as described in step S5 of claim 1, is used to temporarily store data during out-of-order execution and commit data when dependencies are resolved.

8. A computing processing device, characterized in that, The device includes a processor and a memory storing program instructions, characterized in that the processor is configured to execute the heterogeneous computing task scheduling method as described in any one of claims 1 to 6 when running the program instructions.

9. A computer-readable storage medium storing program instructions, characterized in that, When the program instructions are executed, they perform the heterogeneous computing task scheduling method as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, When the computer program product is run by the processor of the computer device, it executes the heterogeneous computing task scheduling method according to any one of claims 1-6.

Images