Triangular matrix calculation method based on folding compression, computer equipment and storage medium

Abstract

The invention relates to the field of computer hardware acceleration, and discloses a triangular matrix calculation method based on folding compression, computer equipment and a storage medium, and the method comprises the steps: building a streaming load quantification model, and obtaining the load distribution characteristics of all calculation nodes of a triangular matrix algorithm in a streaming calculation architecture; a collaborative compression operation is executed, and a calculation task mapping scheme is generated; performing alignment processing on the combined multiple paths of input data streams; the computer equipment comprises a processor, a memory and a computer program which is stored on the memory and can run on the processor; a computer program is stored in the storage medium. Through a folding compression method, the utilization rate of the processing unit is improved, and hardware resource occupation is reduced; through systematic load quantification and optimization space search, the design efficiency is improved; and reliable implementation of the scheme on hardware is ensured through a special micro-architecture and a data alignment mechanism.

Description

Technical Field

[0001] This invention relates to the field of computer hardware acceleration technology, specifically to a triangular matrix calculation method, computer device, and storage medium based on folded compression. Background Technology

[0002] Triangular matrix algorithms, such as Cholesky decomposition, QR decomposition, triangular matrix inversion and multiplication, are fundamental to solving linear systems and eigenvalue problems, playing an indispensable role in cutting-edge technologies such as radar signal processing, 5G / 6G wireless communication, and artificial intelligence model computation. To meet the ever-increasing demand for real-time high-performance computing, academia and industry have developed various acceleration solutions. While highly optimized function libraries such as Intel MKL, LAPACK, and cuSOLVER exist on general-purpose computing platforms (CPU / GPU), their inherent SIMD / SIMT execution modes struggle to efficiently handle the data recursive dependencies and irregular memory accesses inherent in triangular matrix algorithms. Therefore, Field-Programmable Gate Arrays (FPGAs), with their customizable hardware architecture and deep pipeline capabilities, have become an ideal platform for implementing high-performance computing of such algorithms. Currently, mainstream FPGA-based implementations typically employ streaming computing architectures such as systolic arrays, efficiently mapping the triangular matrix computation process through the construction of fine-grained hardware pipelines.

[0003] However, existing methods for calculating triangular matrices based on FPGA pulsating arrays suffer from a series of deep-seated technical bottlenecks, which severely restrict the improvement of hardware resource utilization and design efficiency.

[0004] First, there is a fundamental problem of unbalanced workload. On the one hand, within a single computation iteration, the vast differences in task complexity among different processing units (PEs) lead to uneven workload distribution; on the other hand, between different computation iterations, the sharp decrease in computational load in later iterations results in a large number of PEs being idle for extended periods. These two types of problems directly lead to a huge waste of hardware resources and low overall utilization.

[0005] Secondly, existing technical solutions typically lack theoretical models for precise quantitative analysis of computational load, and even more so, they lack a framework for systematically and automatically exploring and generating optimal resource allocation. This makes the hardware optimization process heavily reliant on engineers' manual experience and repeated trial and error, which is not only inefficient and time-consuming, but also makes it difficult to guarantee finding the globally optimal solution for a specific matrix dimension.

[0006] Finally, even if a solution is devised to merge multiple logical tasks into a single physical unit, existing technologies fail to provide corresponding microarchitecture support. More importantly, existing technologies lack mature alignment and scheduling mechanisms to address the timing conflicts that inevitably arise from merging multiple data streams. This makes it difficult to implement advanced optimization ideas correctly and stably at the hardware level, posing a significant risk to functional correctness. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a triangular matrix calculation method, computer device, and storage medium based on folded compression. This solves the problems of low hardware resource utilization caused by the inherent load imbalance characteristics of triangular matrix algorithms in streaming computing architectures such as FPGAs, as well as the lack of systematic optimization and reliable hardware implementation solutions.

[0008] To achieve the above objectives, the first aspect of the present invention provides a method for calculating a triangular matrix based on folded compression, the method comprising:

[0009] Step 1: Establish a streaming load quantization model to obtain the load distribution characteristics of all computing nodes in the streaming computing architecture using the triangular matrix algorithm.

[0010] Step 2: Based on the load distribution characteristics, perform a collaborative compression operation to generate a computing task mapping scheme that merges multiple logical computing tasks into a smaller number of physical processing units.

[0011] Step 3: Align the merged multi-input data streams to ensure that there are no data conflicts when the multiple logical computation tasks are executed on the physical processing unit.

[0012] Preferably, the step of establishing the streaming load quantization model may specifically include:

[0013] First, the algorithm for processing the triangular matrix is ​​decomposed to obtain a set of basic computational operations, such as multiplication, addition, or multiply-addition.

[0014] Secondly, the loop structure in the triangular matrix algorithm is analyzed to determine the execution conditions for each basic computational operation. These execution conditions define which computational cycles the operation is active in.

[0015] Finally, based on the execution conditions, a theoretical utilization function is established for the computing node corresponding to each basic computing operation. This function is used to quantitatively characterize the working state (active or idle) of the computing node under different computing cycles. The execution conditions and the theoretical utilization function together constitute the streaming load quantization model.

[0016] Preferably, after establishing the streaming load quantization model, a data flow graph with utilization annotations can also be constructed. Specifically, the basic computational operations are abstracted into computational nodes, and data dependencies are abstracted into directed edges, thereby constructing a basic data flow graph. Subsequently, for each computational node in this basic data flow graph, its corresponding theoretical utilization function is associated, thus forming a data flow graph with utilization annotations that can intuitively display the time-varying load characteristics of each node.

[0017] Preferably, the step of performing the collaborative compression operation may specifically include:

[0018] Identify and pair computational tasks that exhibit complementary utilization characteristics in the early and late stages of the computation process. For example, one task may have high utilization in the early stages and low utilization in the later stages, while another task may have the opposite. Combine these tasks into a collaborative task group with a relatively flat overall load.

[0019] Then, the multiple logical computing tasks in the collaborative task group are compressed and uniformly mapped to a single physical processing unit for execution through time-division multiplexing scheduling. This forms a computing task mapping scheme that maps multiple logical tasks to a single physical hardware, thereby reducing the total number of physical processing units required.

[0020] Preferably, the collaborative compression operation may further include constructing a folded tree model. This model uses the dimension of the matrix to be processed as the root node and the number of folds and fold positions as child nodes for hierarchical decision-making. In this folded tree model, a complete path from the root node to any leaf node corresponds to a specific pairing scheme for a collaborative task group.

[0021] Preferably, after the computation task mapping scheme is formed, it also includes verifying its load effectiveness. The verification steps are as follows:

[0022] Calculate the combined utilization of the individual processing unit. This combined utilization is the sum of the theoretical utilizations of all logical computation tasks carried by the processing unit.

[0023] Then, it is determined whether the combined utilization rate exceeds a preset load threshold (typically 1 for a single-issue processing unit) in any given computation cycle. If the combined utilization rate is less than or equal to 1 in any cycle, the scheme is valid; if there is at least one cycle in which the combined utilization rate is greater than 1, the computation task mapping scheme is determined to be invalid, because this means that multiple tasks need to use the physical processing unit at the same time, resulting in hardware resource conflicts.

[0024] Preferably, the alignment process may specifically include: First, analyzing the data validity sequence of each input data stream to determine its validity status (i.e., whether the data is valid) in each clock cycle. Second, detecting whether there exists at least one clock cycle in which the validity status of two or more input data streams is simultaneously true. If so, a data stream access conflict is determined to have occurred. Finally, if a data stream access conflict is determined to have occurred, the minimum latency required to resolve the conflict is calculated.

[0025] Preferably, after alignment, the process also includes handling data stream access conflicts. The specific steps are as follows:

[0026] Based on the calculated minimum delay period, a data buffer circuit (such as a FIFO or shift register) is configured in the corresponding data flow path to precisely delay the data timing, ensuring that conflicting data does not arrive at the processing unit input in the same cycle.

[0027] Meanwhile, a data selection logic (such as a multiplexer) is configured at the input of the single processing unit. This logic selects a currently valid data stream from multiple data streams that have been delayed and aligned according to the current clock cycle and sends it to the computing core.

[0028] A second aspect of the present invention provides a computer device comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements any of the folded compression-based triangular matrix calculation methods described in the first aspect of the present invention.

[0029] A third aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the triangular matrix calculation methods based on folded compression as described in the first aspect of the present invention.

[0030] This invention provides a triangular matrix calculation method, computer device, and storage medium based on folded compression. It offers the following advantages:

[0031] 1. This invention utilizes a folding compression method to merge multiple logical tasks with complementary load characteristics within a computation cycle into a single physical processing unit (PSU). This time-division multiplexing mechanism improves the average utilization rate of the PSU throughout the workflow, thereby effectively reducing the total number of PSUs required to implement triangular matrix operations and directly lowering the area and power consumption of the hardware circuitry. Conversely, with fixed hardware resources, this method can handle more complex calculations and achieve higher processing performance.

[0032] 2. This invention establishes a streaming load quantization model, firstly providing a precise mathematical characterization of the load on each computing node. Based on this, a folded tree model defines a complete optimization exploration space. By traversing this space, all feasible folding and compression schemes are systematically generated and evaluated, thereby quickly searching for the optimal mapping strategy for a specific matrix dimension. This avoids the blindness and inefficiency of relying on manual experience in traditional hardware design.

[0033] 3. This invention clarifies the specific microarchitecture support for its hardware implementation. Through load validity verification, invalid mapping schemes that could lead to resource conflicts can be pre-screened. Simultaneously, by analyzing, delaying, and selecting alignment processes for the merged data streams, the physical layer data access conflict problem is resolved. This complete process, from scheme generation and verification to hardware conflict handling, ensures that the folding compression method can be executed correctly and stably in actual hardware. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the streaming load quantization model of the present invention;

[0035] Figure 2 This is a schematic diagram of the folding exploration space of the present invention;

[0036] Figure 3 This is a schematic diagram of compression based on the folding path according to the present invention;

[0037] Figure 4 This is a schematic diagram of the microarchitecture design of the present invention. Detailed Implementation

[0038] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] Please see the appendix Figure 1 - Appendix Figure 4 This invention provides a method for calculating a triangular matrix based on folded compression, comprising the following steps:

[0040] S1. Establish a streaming load quantization model to obtain the load distribution characteristics of all computing nodes in the streaming computing architecture using the triangular matrix algorithm.

[0041] This step aims to formally and quantitatively analyze the computational process of specific triangular matrix algorithms (such as Cholesky decomposition and triangular matrix inversion). First, based on the algorithm's high-level language description (its analysis process), its inherent loop structure and data dependencies are analyzed. For each basic computational operation in the algorithm, based on its corresponding loop boundary conditions, a theoretical utilization function characterizing its working state in different computational iteration cycles is derived.

[0042] Subsequently, the various basic computational operations in the algorithm are abstracted into computation nodes, and the data dependencies between operations are abstracted into directed edges, thereby constructing a formal data flow graph. Based on this data flow graph, the theoretical utilization function derived above is used to label each computation node, forming a data flow graph model with load characteristic information.

[0043] Finally, the data flow graph model is extended to cover the entire iteration space required to process a complete matrix. By expanding all iterations, the precise load variation of each computing node throughout its entire computational lifecycle is obtained for a given matrix dimension, forming a quantitative distribution map of the global node load. This distribution map reveals the load imbalance between different computing nodes and at different iteration stages of the same node.

[0044] S2. Based on the load distribution characteristics, perform a collaborative compression operation to generate a load-balanced computing task mapping scheme.

[0045] This step utilizes the load distribution characteristics obtained in step S1 to reorganize and merge computing tasks, thereby improving the overall utilization of computing resources. Analysis of the global node load quantization distribution map reveals that node utilization exhibits a strictly monotonically increasing or decreasing characteristic during the iteration process. Based on this characteristic, computing nodes whose utilization changes with time exhibit complementary patterns (e.g., a node with high load in early iterations and low load in later iterations, and another node with low load in early iterations and high load in later iterations) are identified as candidate nodes for merging.

[0046] To systematically generate all feasible merging schemes, a folded tree model is constructed. The folded tree model uses the dimension information of the matrix to be processed as the root node, the number of folding operations as the second-level child nodes, and subsequent child nodes have the same level as the number of folds. Each level represents a decision on the folding position. Therefore, a complete path from the root node to any leaf node corresponds to a complete folding compression scheme.

[0047] Based on a selected path in the folded tree model, a folding and compression operation is performed. This operation spatially transforms the logical one-dimensional systolic array (where each physical processing unit corresponds to an original computational iteration task), folding and compressing it into a new one-dimensional systolic array with fewer physical resources. In the new systolic array, a single physical processing unit (i.e., the processing unit physically implemented on the hardware chip responsible for performing the core computational task) carries the computational tasks of the original multiple logical processing units (i.e., an independent logical computational task defined in the algorithm flow before being merged and optimized).

[0048] Before determining the final compression scheme, the effectiveness of candidate schemes needs to be verified. Using the streaming load quantization model established in step S1, the total load of the new node after merging is calculated. If, in any calculation cycle, the theoretical load rate of the new node exceeds the upper limit threshold of the hardware processing capacity (e.g., 100%), the scheme is deemed invalid and discarded.

[0049] S3. Align the merged multi-input data streams to ensure that there are no data conflicts during the calculation process.

[0050] This step ensures that the hardware correctly executes the computational task mapping scheme generated in step S2. When multiple original computational tasks are merged into the same physical processing unit, if the input data streams corresponding to these tasks are directly fed in, their data arrival times may overlap, leading to computational resource access conflicts.

[0051] Given the deterministic nature of the triangular matrix algorithm's computation process, it can accurately predict the data requirements of each original computational task in each clock cycle. Based on this prediction, the multiple merged tasks are scheduled. Specifically, using the data flow of one task as a baseline, the number of delay cycles required for the data flows of other tasks relative to that baseline is calculated to stagger their data arrival times.

[0052] The calculated delay period is achieved by inserting an appropriate number of registers or equivalent data buffer units (i.e., hardware circuits used only to temporarily store data to achieve a specific clock cycle delay, which do not perform calculations themselves) into the data flow path that requires delay. After alignment processing, multiple data streams enter the same physical processing unit sequentially in a time-division multiplexing manner for calculation, thereby ensuring the logical correctness of data processing and the absence of timing conflicts.

[0053] Please see the appendix Figure 1 , attached Figure 1 The streaming load quantization model proposed in this invention includes:

[0054] 'a' represents the Cholesky code analysis, which is expressed within the hardware module. The matrix elements are divided, and each operation may not be able to handle all operations. Figures 1-7 show the content of the code analysis. Then, the operations are classified according to their utilization rate, specifically into Sqrt (square root), Div (layer), Mul, and Sub (multiplication and subtraction instructions).

[0055] b represents node extraction using a dimension of 6 as an example, which involves two steps:

[0056] Step 1: Add utilization rate;

[0057] Step 2: Merge adjacent nodes of the same type;

[0058] c represents load quantization with a dimension of 6 as an example.

[0059] To establish a streaming load quantization model, it is necessary to analyze the load of various computing nodes that constitute the triangular matrix algorithm.

[0060] In this embodiment, the principle behind this analysis is that the execution mode of any deterministic triangular matrix algorithm on a streaming hardware architecture is also deterministic. When each independent computational operation is activated and when it is idle is entirely determined by the algorithm's own loop control structure. Therefore, by analyzing this control structure, the load on each physical processing unit can be accurately predicted.

[0061] S111: Decompose the triangular matrix algorithm to be processed to obtain a set of basic computational operations.

[0062] A specific triangular matrix algorithm, such as Cholesky decomposition or QR decomposition, can be viewed as a combination of various types of computational operations (such as dot product, vector scalar multiplication, matrix-vector multiplication, etc.) based on specific data dependencies.

[0063] These basic computational operations are the fundamental units for load analysis (i.e., the smallest indivisible computational steps or basic operations in the algorithm flow during load analysis). For the decomposition of a specific algorithm, those skilled in the art can do so based on its mathematical definition or code implementation; such methods are well-known in the field and will not be elaborated upon here.

[0064] S112. Analyze the loop structure in the high-level language description of the algorithm to determine the execution conditions of each basic computational operation. In a streaming computing architecture, a basic computational operation is typically mapped to a dedicated computing node.

[0065] Whether a corresponding computation node is activated depends on whether the algorithm needs to execute this operation in the current computation iteration cycle. This execution condition is strictly defined by the boundary conditions of the nested loop structure in the algorithm implementation code.

[0066] Specifically, in one embodiment, for a variable from arrive For algorithms that perform outer iterations, an operation located inside an inner loop executes only if the current outer iteration index value is met. and inner iteration index value Satisfying inequalities .

[0067] S113. Based on the execution conditions, establish a theoretical utilization function for each computing node. This theoretical utilization function is used to quantitatively describe the working state of the computing node under different computing cycles. In this embodiment, under the ideal condition of not considering pipeline bubbles, the theoretical utilization of the computing node in a specific iteration cycle can be defined as a binary function, the expression of which is:

[0068] ;

[0069] In the formula, For a specific compute node, indexed by the outer loop The theoretical utilization rate of the computation iteration cycle uniquely determined by other inner loop indices (represented here by ...); This indicates that the node is in a computational state during this iteration cycle. This indicates that the node is idle during this iteration cycle. The execution conditions of the node are logical combinations of inequalities of one or more loop variables, derived from the analysis in step S112, such as those mentioned above. .

[0070] Therefore, by establishing the aforementioned utilization function, the control flow characteristics of the algorithm can be accurately transformed into a quantitative description of the timing load characteristics of each computing node. For example, for a processing... The matrix algorithm, one in the first... The utilization function of a node that only starts working in the next outer iteration is at the outer iteration index. The time is always 0, while The value is then set to 0 or 1 based on the inner loop condition. This analysis method provides a data foundation for subsequently identifying and quantifying the degree of load imbalance across the entire computing array.

[0071] After independently analyzing the load characteristics of each computing node, the method of this embodiment further includes transforming the triangular matrix algorithm into a formalized data flow graph with load characteristic information. This transformation process provides a structured and analyzable model foundation for subsequent global load quantization and compression optimization, and its specific process may include:

[0072] S121. The basic computational operations and data dependencies in the algorithm are abstracted into computational nodes and directed edges, respectively, to construct a basic data flow graph.

[0073] In this embodiment, a basic computational operation refers to the smallest indivisible unit of computation in the algorithm (i.e., an atomic computational operation considered indivisible in the algorithm), such as scalar multiplication, addition, division, or square root operations. Data dependency refers to the output of one operation serving as the input of another operation.

[0074] This step maps the computational flow of the algorithm to a directed acyclic graph. For constructing this graph, those skilled in the art can use intermediate representation generation methods from compiler front-end technologies; the construction process is well-known in the field and will not be elaborated upon here.

[0075] S122. In order to enable the data flow graph to reflect the characteristics of computing load changing over time, the method of this embodiment associates each computing node in the basic data flow graph with a theoretical utilization function obtained in step S11, thereby constructing a data flow graph with utilization labeling.

[0076] A data flow graph with utilization labels It can be formally defined by a triple:

[0077] ;

[0078] In the formula, Let be the set of computational nodes, where each node... This corresponds to a basic computational operation; Let be a set of directed edges, where each edge This represents the data flow direction between nodes; This is a set of node utilization functions; This is a data flow graph with utilization labels.

[0079] gather Each function in With node set Nodes in One-to-one correspondence. This function. The specific form has been determined in step S11, and its function is to describe the node. In the Working state under each calculation iteration.

[0080] In this embodiment, the function can output discrete values, such as 1 representing that the node is in a computational state during the current iteration cycle, and 0 representing that it is in an idle state, but it is not limited to this. Through this formal definition, the static computational structure and dynamic load characteristics of the algorithm are uniformly described, providing a complete mathematical model for subsequent quantitative analysis.

[0081] S123. Perform fusion optimization on data flow graphs with utilization rate labels to reduce model complexity.

[0082] After obtaining the data flow graph with utilization annotations, adjacent isomorphic nodes that meet the preset fusion conditions in the graph can be merged to improve the efficiency of subsequent analysis steps.

[0083] In one specific implementation, preset merging conditions are defined as a set of criteria used to determine whether nodes can be merged. For example, these conditions may require that the nodes to be merged satisfy the following:

[0084] In a data flow graph, this represents a direct adjacent relationship;

[0085] The type of computational operation performed is isomorphic;

[0086] Furthermore, their theoretical utilization functions are completely identical.

[0087] When a group of adjacent nodes simultaneously meet the above conditions of isomorphism and consistent utilization function, it is determined that they meet the preset fusion conditions.

[0088] Once a node group that meets the preset merging conditions is identified, a merging operation can be performed, merging them into an equivalent single computing node. This new single node inherits the computing operation type and theoretical utilization function of the original node, and updates the connection relationships, redirecting edges pointing to the original input node to the new node, and redirecting the outgoing edges of the original output node to originate from the new node.

[0089] This optimization step reduces the total number of nodes in the data flow graph without losing any load information, thus reducing the computational overhead for the global iterative spatial load quantization analysis in step S13.

[0090] After obtaining the theoretical utilization function characterizing the load characteristics of a single computing node and the data flow graph model of the algorithm as a whole, step S13 aims to instantiate this abstract model to apply it to computational tasks that process matrices of a specific dimension, thereby obtaining a global computational load distribution that can guide subsequent optimization operations.

[0091] In one specific embodiment of the present invention, this step is based on the dimension of the triangular matrix to be processed. The previously constructed data flow graph model with utilization annotations is instantiated to cover the entire iteration space required by the algorithm. First, the computational nodes related to iteration in the data flow graph are categorized according to the matrix dimensions. The determined top-level loop boundary (e.g., from iteration) arrive The process is fully expanded. This expansion operation creates a set of corresponding computation node instances for each logical iteration (e.g., the calculation process of processing a row or column of a matrix).

[0092] Subsequently, for each instantiated computing node, the theoretical utilization function established in the preceding steps is applied. The value is evaluated. The parameter is... This is the specific iteration index value of the current node. The output of this function is the load state of the node in the corresponding iteration cycle. In this embodiment, the state is binary, for example, a value of 1 represents that the physical processing unit is in a working state, and a value of 0 represents that it is in an idle state.

[0093] Finally, the load state values ​​of all instantiated computing nodes in their respective iteration cycles are organized to construct a global load matrix. The dimension of this matrix is ​​related to the total number of computing nodes and the total number of computing cycles. Specifically, the elements in the matrix... Indicates the first The computing node at the in the ... The load status under each calculation cycle, the value of which is determined by the aforementioned utilization function. The calculation results are determined under the corresponding period.

[0094] The global node load quantization distribution generated through the above steps accurately reflects, in data form, the two inherent load imbalance characteristics of the triangular matrix algorithm under the streaming computing architecture. The first is the horizontal imbalance within the same iteration cycle, manifested in significant differences in load between computing nodes performing different types of tasks such as point operations, vector operations, and matrix operations. The second is the vertical imbalance between different iteration cycles, manifested in obvious fluctuations in the computing load of the same computing node in the early and later stages of algorithm execution, for example, gradually decreasing from a fully loaded state to completely idle, or vice versa. This quantization distribution map provides direct and necessary data basis for the subsequent folding and compression optimization in step S2.

[0095] Please see the appendix Figure 2 and attached Figure 3 , attached Figure 2The figure illustrates the folding exploration space proposed in this invention, using a matrix dimension of 6 as an example. Here, Matrix Dimensions represents the matrix size; Fold Count represents the fold count; and FoldingPosition represents the folding position.

[0096] Appendix Figure 3 This is the process of compressing the folding path according to the embodiment of the present invention. It expresses the folding case path. The folding case 1 path is (6)-(1)-(-1), and the folding case 2 path is (6)-(2)-(-2)-(+2).

[0097] To systematically generate and evaluate all feasible computational task merging schemes, this invention proposes a method for constructing a folded exploration space. In this embodiment, the folded exploration space is embodied by a folded tree model, which transforms the problem of finding the optimal compression scheme into a traversal problem of a structured search space.

[0098] S211. This method is based on a key load characteristic: in the complete process of processing a single triangular matrix, the utilization rate of computing nodes responsible for handling the early iterations of the algorithm (e.g., processing the first few rows or columns of the matrix) shows a monotonically decreasing trend, while the utilization rate of computing nodes responsible for handling the later iterations (e.g., processing the last few rows or columns of the matrix) shows a monotonically increasing trend. These two trends are complementary in time.

[0099] S212. Based on this complementary utilization characteristic, this embodiment proposes a folding operation, which pairs a computational task from an earlier iteration with a computational task from a later iteration and merges their computational loads into the same physical processing unit. In this way, a combined computational task with a flatter load and higher utilization can be formed throughout the entire computation cycle.

[0100] S213. To comprehensively include all possible folding pairing schemes and to manage them systematically, a folding tree model was constructed.

[0101] In principle, any specific folding scheme is essentially an answer to two core questions:

[0102] 1. How many pairs of calculation tasks are needed in total (i.e., the number of folds);

[0103] II. Which specific pairs of computational tasks are folded (i.e., the folding positions)?

[0104] The folded tree model provides a hierarchical and structured representation of the decision-making process for these two problems. The specific construction process of this folded tree model is as follows:

[0105] S213.1, Use the dimension information of the triangular matrix to be processed as the root node of the tree. For example, for a... The matrix, where the root node represents the dimension. .

[0106] S213.2, Number of folds All possible values ​​are used as the set of nodes at the second level of the tree. Number of folds This refers to the total number of folding operations performed in a compression scheme. It is a positive integer, and its range of values ​​is:

[0107] ;

[0108] In the formula, The number of folds; Let be the dimension of the triangular matrix to be processed. This formula limits the expression to a given... The maximum number of dimensional computational tasks that can be performed is... Secondary pairing and merging It is a constant.

[0109] S213.3, Define the subsequent subtree structure. For a given number of folds... The corresponding subtree depth is Starting from the node representing the number of folds and moving downwards, each layer represents a decision on the fold position. A fold position decision refers to selecting a pair of tasks from the set of tasks that have not yet been folded, one from an earlier iteration and one from a later iteration. For example, pairing the first... The iteration task and the first Each iterative task is paired up.

[0110] S213.4. Define the folding scheme path. In a folding tree, any complete path from the root node to a leaf node constitutes a unique folding compression scheme. This path contains information about the total number of folds and the specific task pair selected for each fold. The set of all these paths constitutes the global exploration space for folding compression in this matrix dimension.

[0111] By constructing the aforementioned folded tree model, the previously blind and inefficient manual trial-and-error process is transformed into a systematic search of a bounded, structured space. Subsequent optimization algorithms can traverse this space or employ heuristic searches to find the optimal folding scheme that satisfies specific design objectives (such as minimum resource consumption or maximum performance) while ensuring that the load on the post-processing unit (i.e., the hardware circuitry specifically used to perform format conversion or verification and other finishing operations on the output of the main computation process) does not exceed its physical limit (e.g., 100% utilization). Regarding the selection of search algorithms, those skilled in the art can choose depth-first search, breadth-first search, or other heuristic algorithms according to design requirements. Their specific implementations are well-known technologies in the field and will not be elaborated upon here.

[0112] After determining a specific folding path based on the folded tree model, folding and compression operations are performed, mapping the original computational tasks to an array of physical processing units that require fewer physical resources. The fundamental principle of this operation is to transform an abstract task merging scheme into a specific hardware resource allocation relationship. Its purpose is to allow a single physical processing unit to execute multiple original tasks that were originally handled by different units and whose computational loads are complementary in time.

[0113] In this embodiment, the operation may specifically include:

[0114] S221. Parse the selected folding path to determine the grouping rules for the original computational tasks. A complete path from the root node to a leaf node of the folded tree directly defines a set of rules for grouping all the original computational tasks.

[0115] For example, for a containing Original computing task (in In a scenario where a path indicates a fold at the center point, the grouping rule it represents is to group tasks... With the task They were grouped into the same task group.

[0116] S222. According to the grouping rules, all original computational tasks belonging to the same task group are mapped to the same physical processing unit. This mapping process will change the original plan that required... An array of independent logic processing units is reconstructed into an array with fewer physical processing units.

[0117] This mapping process can be accomplished by a mapping function. Formal description: This function will index the original task. Indexes mapped to a new, compressed physical processing unit :

[0118] ;

[0119] In the formula, This refers to the index of the physical processing unit in the newly generated one-dimensional physical processing array after compression. This is the index of the original computation task, and its value range is... arrive ; The total number of original computational tasks, usually equal to the dimension of the matrix to be processed; A mapping function implemented based on the grouping rules determined by the folding path.

[0120] S223. Based on the mapping results of step S222, generate the final one-dimensional physical processing array.

[0121] Specifically, taking the above-mentioned center point folding as an example, its mapping function can be specifically expressed as:

[0122] ;

[0123] In the formula, This is the index of the target physical processing unit obtained after mapping, that is, the position index in the final generated one-dimensional physical processing array; This is the index of the original processing unit (or computational iteration), and its value range is usually [value range missing]. arrive ; The total number of original computational tasks, usually equal to the dimension of the matrix to be processed; This is a function that takes the smaller of the two values. The function will index... Its index is symmetric about the center Compare the results and take the smaller one as the new index. This achieves the effect of folding a one-dimensional array from its center point.

[0124] Under this mapping rule, the original task and All are mapped to index 1 Physical processing unit Original task and All are mapped to index 1 Physical processing unit And so on. Ultimately, the index of the physical processing unit... The range of values ​​is arrive Therefore, what was originally needed The computational tasks of one physical processing unit were successfully compressed to approximately Executed on each physical processing unit. It should be noted that the specific form of the mapping function defined by more complex folding paths (such as multiple folds) will differ, but its essence of mapping multiple original task indices to the same new physical processing unit index remains unchanged. The specific construction of this mapping function can be directly derived by those skilled in the art based on the folded tree path information; its implementation is well-known in the field and will not be elaborated upon here.

[0125] After obtaining one or more candidate folding compression schemes through the folded tree model, these schemes need to be validated to ensure that when the merged computational task is executed on a physical processing unit, its instantaneous computational load does not exceed the hardware processing capacity limit of that physical processing unit. This validation process ensures that the generated compression scheme is physically feasible.

[0126] In one embodiment of the present invention, the validity verification process may specifically include the following steps:

[0127] S231. Extract the task merging relationship corresponding to the candidate compression schemes. Each candidate compression scheme defines a set of mapping relationships, which clarifies how the original multiple logical computing tasks are allocated to new, fewer physical processing units.

[0128] Extract the set of original logical computation tasks to be carried out by each new physical processing unit from the scheme. For example, a compression scheme might stipulate that the original first iteration task and the hundredth iteration task are merged into the first physical processing unit.

[0129] S232. Calculate the combined load of the merged physical processing unit. When multiple original tasks are assigned to the same physical processing unit, the total computational demand of that physical processing unit at any given time is the sum of the computational demands of all the original tasks it carries at that time.

[0130] Therefore, this step calculates the combined utilization rate by superimposing the utilization functions of each original task. For a combined task... A new processing unit for each original task (i.e., the same physical processing unit shared by multiple logical computation tasks after being merged using the folding compression method of this invention), in the first... Synthetic utilization rate per calculation cycle It can be calculated using the following formula:

[0131] ;

[0132] In the formula, For the merged post-processing unit in the calculation cycle The synthesis utilization rate; This represents the number of original tasks carried by the post-processing unit. For the first The original tasks that were merged were in the computation cycle. The theoretical utilization function. This utilization function is obtained according to the load analysis method in step S1. It is a bivariate function, and in the period... The value can be 1 (indicating that the task is busy) or 0 (indicating that the task is idle).

[0133] S233. Compare the combined load with the hardware constraints. Calculate the combined utilization rate obtained in S232. It is compared with a preset load threshold. This preset load threshold is determined in advance based on the hardware capabilities of the physical processing unit and represents the maximum computational load it can handle in one computation cycle.

[0134] In this embodiment, the load threshold is set to 1, corresponding to 100% utilization. This is achieved by iterating through all computation cycles. (From the start to the end of the algorithm) Check if any cycle exists. This improves the utilization rate of the synthesis. The value is greater than the preset load threshold.

[0135] S234. Determine the effectiveness of the compression scheme. Based on the comparison results, determine the effectiveness of the candidate compression schemes. If, in a compression scheme, the combined utilization rate of all merged physical processing units is within the total computation cycle of the entire computation process, then the effectiveness of the compression scheme is determined. If none of the load values ​​exceed the preset load threshold, the compression scheme is deemed valid.

[0136] Conversely, if at least one physical processing unit in the compression scheme has a synthesis utilization rate exceeding the threshold in at least one computation cycle, the compression scheme is determined to be invalid and removed from the candidate set.

[0137] Through the above verification steps, all folding compression schemes that meet hardware resource constraints can be screened out, providing a reliable and feasible mapping basis for subsequent hardware implementation and avoiding system malfunctions caused by load overflow. The specific derivation and calculation of the utilization function can be directly obtained by those skilled in the art based on the cyclic boundary conditions of a specific triangular matrix algorithm; the derivation process is well-known in the field and will not be elaborated here.

[0138] Please see the appendix Figure 4 , Figure 4 The microarchitecture design proposed in this invention includes:

[0139] a represents the structure of a traditional microarchitecture; b represents the partially folded microarchitecture proposed in this invention; c represents the fully folded microarchitecture proposed in this invention; d represents an aligned multi-path data stream.

[0140] In the diagram, PE stands for Physical Processing Unit, Merge for merging, Matrix Compute for matrix calculation, Vector Compute for vector calculation, Point Compute for point calculation, Delay for delay, and Split for splitting.

[0141] To support the folded compression scheme generated in step S2 at the hardware level, this invention further provides a corresponding folded-based microarchitecture design. The core function of this microarchitecture is to provide physical execution units for the merged computational tasks and to ensure computational correctness through a precise data flow control mechanism. One of the key technologies in this microarchitecture design is the alignment processing of the merged multi-path input data streams.

[0142] In one embodiment of the present invention, when a single physical processing unit carries multiple computing tasks, in order to ensure that these tasks can be executed correctly, it is necessary to perform conflict analysis and timing adjustment on the merged multi-channel input data stream.

[0143] Its core principle lies in leveraging the deterministic nature of the triangular matrix algorithm's calculation pattern to pre-determine the precise activity sequence of all data streams. This allows for time-division multiplexing of the same physical computing resources by introducing a fixed time delay into some data streams. The specific implementation methods for data stream conflict analysis and delay calculation are as follows:

[0144] S310. First, for a physical processing unit that carries multiple computing tasks, identify all its input data streams. These data streams correspond to the data required by each of the original computing tasks being merged. For example, if a physical processing unit merges the original... The iteration task and the first For each iterative task, its input data stream includes the data that originally flowed separately to... and All data.

[0145] S320. Based on the inherent computational determinism of the triangular matrix algorithm, the timing characteristics of each input data stream are analyzed. Since the algorithm's computational pattern is fixed and predictable, for a given matrix dimension, the timing characteristics at any given clock cycle can be known in advance. Whether each raw computation task needs to read valid data from its input port.

[0146] This analysis allows us to establish a data validity sequence for each input data stream. The sequence is a Boolean sequence, when... When true, it indicates that during a clock cycle The data stream contains valid data that needs to be processed; otherwise, it indicates that the data stream is idle.

[0147] S330. To detect data stream conflicts, the data validity sequences of all input data streams in the same physical processing unit are compared periodically.

[0148] If, within a given clock cycle, there are two or more data streams with valid data sequences... If both conditions are true, it indicates that a data stream access conflict has occurred during that clock cycle. This conflict means that the physical processing unit is required to process data from different original tasks at the same time, which is physically infeasible.

[0149] S340. After a collision is detected, the minimum delay period required to resolve the collision needs to be calculated. This process involves delaying a portion of the data stream to stagger their arrival times.

[0150] In this embodiment, the data stream corresponding to the task with the smaller original iteration index number can be selected as the base data stream, and the rest can be used as the data stream to be delayed. The goal of the delay period calculation is to ensure that when the data stream to be delayed arrives at the physical processing unit, all its valid data can fall within the idle time window of the base data stream.

[0151] Specifically, a method for determining the minimum delay period The method uses an iterative, incremental search approach:

[0152] from Begin by testing each non-negative integer.

[0153] For each test The value is used to check whether a conflict still exists between the delayed data stream and the baseline data stream after the delay is applied.

[0154] The testing conditions are:

[0155] In all clock cycles In the above test, the validity status of both data streams cannot be true simultaneously. This test can be performed using the following formula:

[0156] ;

[0157] In the formula, For the reference data stream in the clock cycle Data validity status; For the delayed data stream, an application was applied After a delay of one cycle, in the clock cycle Data validity status; Let be the minimum non-negative delay period to be solved; For logical AND operations. The first one makes the above expression valid for all... Hengcheng The value is the minimum delay period we are looking for.

[0158] Through the above steps, the required latency cycles for each input data stream of each physical processing unit that needs to merge tasks can be accurately calculated, providing a quantitative basis for subsequent hardware-based data stream alignment. This calculation process is entirely based on the determinism of the algorithm, requires no runtime judgment, and can be completed in one go during the compilation or configuration phase.

[0159] After determining the number of delay cycles required for a specific data stream according to the aforementioned steps, the delay needs to be physically implemented by configuring the corresponding hardware structure to ensure that the merged multiple computing tasks can be executed conflict-free on a single physical processing unit. This part is the specific hardware implementation details of the microarchitecture design of this invention. Its core principle is to implement a pre-calculated time delay through physical circuitry, shifting the originally overlapping data streams in time sequence, thereby achieving conflict-free time-division multiplexing of a single physical computing resource.

[0160] This process may specifically include:

[0161] S321. Determine the configuration parameters of the data buffer unit. In this embodiment, the parameter is specifically the number of delay cycles. Delay period number The value is determined based on the results of the aforementioned data flow conflict analysis steps, and its size is equal to the total number of clock cycles that need to be delayed to allow the data flow to avoid all conflicts and reach the first available clock cycle.

[0162] S322. Configure data buffer units in the specified data flow path according to the determined number of delay cycles.

[0163] Specifically, one feasible implementation is to use cascaded shift registers. In this method, the data buffer unit consists of multiple one-bit or multi-bit registers connected end-to-end. The required number of delay cycles is... Then Each register is cascaded along the data flow path.

[0164] In each clock cycle, data is transferred from the previous stage register to the next stage register. A data signal enters from the input of this data buffer unit and needs to pass through... It takes several clock cycles to reach its output, thus precisely achieving the required delay.

[0165] As another alternative implementation, a First-In-First-Out (FIFO) memory can be used. In this method, the data stream to be delayed is written sequentially into the FIFO. By controlling the read enable signal of the FIFO, it is ensured that the data resides in the FIFO after being written. It is read only after several clock cycles. This waiting time can be controlled by a counter that starts when data is written and counts until it reaches a certain value. A read enable signal is generated at that time.

[0166] For implementations on reconfigurable computing devices such as field-programmable gate arrays (FPGAs), the data buffer unit can also utilize on-chip memory resources, such as block random access memory (BRAM), to construct a circular buffer.

[0167] For the circuit design and implementation of the above data buffer unit, those skilled in the art can select a standard cell library or call an IP core according to the design requirements. The specific circuit structure is a well-known technology in this field and will not be described in detail here.

[0168] S323. Configure data selection logic at the input of the physical processing unit. After processing by the aforementioned data buffer unit, multiple data streams that previously had timing conflicts are adjusted into independent data streams that are staggered in time. These aligned data streams are then fed into the input port of the physical processing unit that carries the merged computation task.

[0169] In this embodiment, a data selector (e.g., a multiplexer) is deployed at the input interface of the physical processing unit. Based on the current clock cycle and preset scheduling information, the selector selectively routes a valid data stream to the computing core in each cycle. Thus, the data streams of multiple logical tasks share the same physical processing unit without conflict in a time-division multiplexing manner, ensuring the logical correctness of the entire computing process.

[0170] A computer device includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the aforementioned triangular matrix calculation method based on folded compression.

[0171] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the aforementioned triangular matrix calculation method based on folded compression.

Claims

1. A method for calculating a triangular matrix based on folded compression, characterized in that, include: Establish a streaming load quantization model to obtain the load distribution characteristics of all computing nodes in the streaming computing architecture using the triangular matrix algorithm; Based on the load distribution characteristics, a collaborative compression operation is performed to generate a computing task mapping scheme that merges multiple logical computing tasks into a smaller number of physical processing units. Alignment processing is performed on the multi-path input data streams after merging multiple logical computation tasks to ensure that there are no data conflicts when the multiple logical computation tasks are executed on the physical processing unit.

2. The triangular matrix calculation method based on folded compression according to claim 1, characterized in that, The establishment of the streaming load quantization model includes the following specific steps: The triangular matrix algorithm to be processed is decomposed to obtain a set of basic computational operations; Analyze the loop structure in the triangular matrix algorithm to determine the execution conditions for each basic computational operation; Based on the execution conditions, a corresponding theoretical utilization function is established for each computing node corresponding to the basic computing operation. This function is used to quantitatively characterize the working state of the computing node under different computing cycles. The execution conditions and the theoretical utilization function are combined to form the streaming load quantification model.

3. The triangular matrix calculation method based on folded compression according to claim 2, characterized in that, After establishing the streaming load quantization model, the process also includes constructing a data flow graph with utilization annotations, the specific steps of which are as follows: The basic computational operations are abstracted into computational nodes, and the data dependencies are abstracted into directed edges to construct a basic data flow graph; For each computation node in the basic data flow graph, the theoretical utilization function is associated with it, thereby constructing the data flow graph with utilization annotations.

4. The triangular matrix calculation method based on folded compression according to claim 1, characterized in that, The execution of the collaborative compression operation includes: Identify and pair computing tasks that have complementary utilization characteristics in the early and late stages of the computing process, and combine the computing tasks into a collaborative task group with a relatively flat overall load. Multiple logical computing tasks in the collaborative task group are compressed and uniformly mapped to a single processing unit for execution through time-division multiplexing scheduling, forming a computing task mapping scheme that maps multiple logical tasks to a single physical hardware.

5. The triangular matrix calculation method based on folded compression according to claim 4, characterized in that, The process of performing collaborative compression also includes identifying feasible collaborative task groups: Construct a folded tree model to systematically identify and generate all feasible collaborative task groups; The folded tree model uses the dimension of the matrix to be processed as the root node and the number of folds and the fold position as child nodes for hierarchical decision-making. Any complete path from the root node to the leaf node in the folded tree model corresponds to a specific pairing scheme of a collaborative task group.

6. The triangular matrix calculation method based on folded compression according to claim 1, characterized in that, After the computing task mapping scheme is formed, the method further includes load validity verification of the computing task mapping scheme, which specifically includes the following steps: For any given computation cycle, the theoretical utilization rates of all logical computation tasks carried by the single processing unit in that cycle are summed arithmetically to obtain the combined utilization rate of the single processing unit, which is the sum of the theoretical utilization rates of all logical computation tasks carried by the processing unit. Determine whether the synthesis utilization rate exceeds a preset load threshold in any calculation cycle; When the synthesis utilization rate exceeds the load threshold, the computing task mapping scheme is determined to be an invalid scheme.

7. The triangular matrix calculation method based on folded compression according to claim 5, characterized in that, After the collaborative task group is uniformly mapped to a single processing unit, alignment processing is performed, which specifically includes the following steps: Analyze the data validity sequence of each input data stream to determine the validity status of the input data stream in each clock cycle; Detect whether there is at least one clock cycle in which the validity status of two or more input data streams is true at the same time. If the validity status exists, determine that a data stream access conflict has occurred. When a data stream access conflict is determined to occur, the minimum latency period required to resolve the access conflict is calculated.

8. The triangular matrix calculation method based on folded compression according to claim 7, characterized in that, After the alignment process, the data stream access conflict handling is also included, with the specific steps as follows: Based on the minimum delay period, a data buffer circuit is configured in the corresponding data flow path to delay the timing of the data. Data selection logic is configured at the input of the single processing unit to select a valid data stream from multiple aligned data streams according to the current clock cycle and send it to the computing core.

9. A computer device, characterized in that, It includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the method as described in any one of claims 1-8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1-8.

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