Display device

Abstract

The invention relates to a display device. The display device includes a plurality of transistors including: a driving transistor connected to an anode electrode of a light emitting diode at a first node; a first transistor connected between the second node and the fourth node; a second transistor connected between the data line and the fifth node; a third transistor connected to the first node and configured to receive an anode reset voltage; a fourth transistor connected to the fifth node and configured to receive a reference voltage; a first light emission control transistor connected to the fourth node and configured to receive a high-potential driving voltage; and a second light emission control transistor connected to the fourth node and connected to the driving transistor at a third node, in which the first capacitor is connected between the first node and the second node, and the second capacitor is connected between the fourth node and the fifth node.

Description

Technical Field

[0001] This disclosure relates to an apparatus, and more specifically, for example, but not limited to, a display apparatus. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images has increased in various forms, and in recent years, various flat panel display devices, such as organic light-emitting display devices and liquid crystal display devices, have been used.

[0003] Recently, in organic light-emitting display devices, in order to compensate for the threshold voltage of the driving transistor, threshold voltage sampling is performed during the horizontal period when an input data voltage is applied.

[0004] In this case, due to insufficient sampling time for threshold voltage compensation, there are error components in the sampled voltage, so threshold voltage compensation in the pixel is not fully performed.

[0005] An error occurs during threshold voltage compensation, thus degrading the image quality of the display device. Summary of the Invention

[0006] The advantage of this disclosure is that it provides a display device that can increase the threshold voltage sampling time of the driving transistor and improve threshold voltage compensation.

[0007] Additional features and advantages of this disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of this disclosure. These and other advantages of this disclosure will be realized and obtained by means of the structures particularly pointed out in the written description, its claims, and the accompanying drawings.

[0008] To achieve these and other advantages, and in accordance with the purposes of this disclosure, as specifically implemented and broadly described herein, a display device includes: a display panel including pixels; and light-emitting diodes and a plurality of transistors, a first capacitor and a second capacitor in the pixels, the plurality of transistors and the first and second capacitors being configured to be electrically connected to the light-emitting diodes, wherein the plurality of transistors includes: a driving transistor connected at a first node to the anode electrode of the light-emitting diode; a first transistor connected between a second node and a fourth node, the gate electrode of the driving transistor being connected to the second node; a second transistor connected between a data line and a fifth node; a third transistor connected to the first node and configured to receive an anode reset voltage; a fourth transistor connected to the fifth node and configured to receive a reference voltage; a first light-emitting control transistor connected to the fourth node and configured to receive a high-potential driving voltage; and a second light-emitting control transistor connected to the fourth node and connected to the driving transistor at the third node, wherein the first capacitor is connected between the first and second nodes, and the second capacitor is connected between the fourth and fifth nodes.

[0009] In another aspect, a display device includes: a display panel including pixels; light-emitting diodes (LEDs) in the pixels; a driving transistor connected at a first node to the anode of the LED; a first transistor connected between a second node and a fourth node, the gate electrode of the driving transistor being connected to the second node; a second transistor connected between a data line and a fifth node; a third transistor connected to the first node and configured to receive an anode reset voltage; a fourth transistor connected to the fifth node and configured to receive a reference voltage; a first light-emitting control transistor connected to the fourth node and connected at the third node to the driving transistor; a storage capacitor connected between the first node and the second node; and a pump capacitor connected between the fourth node and the fifth node, wherein during a sampling period, the anode reset voltage and a threshold voltage of the driving transistor are configured to be sampled and reflected to the second node, and wherein during a data writing period following the sampling period, a data voltage is configured to be reflected to the second node.

[0010] Other systems, methods, features, and advantages will be or will become apparent to those skilled in the art upon studying the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included in this specification, are within the scope of this disclosure, and are protected by the appended claims. Nothing in this section should be construed as limiting these claims. Further aspects and advantages are discussed below in conjunction with embodiments of this disclosure.

[0011] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide a further explanation of the claimed disclosure. Attached Figure Description

[0012] The accompanying drawings, which are included and incorporated in and form part of this specification to provide a further understanding of this disclosure, illustrate embodiments of the disclosure and serve to explain the principles of the disclosure together with the specification. In the drawings:

[0013] Figure 1 This is a schematic view illustrating a display device according to a first embodiment of the present disclosure;

[0014] Figure 2 This is a circuit diagram schematically illustrating an example of a pixel according to a first embodiment of the present disclosure;

[0015] Figure 3 This is a view showing the configuration of the gating drive portion of the display device according to a first embodiment of the present disclosure;

[0016] Figure 4 This is a timing diagram schematically illustrating an example of a driving signal for driving a pixel according to a first embodiment of the present disclosure;

[0017] Figures 5 to 8 This shows the use of Figure 4 When the driving signal is used, the view shows the operating state of the elements within the pixel during the initialization period, sampling period, data writing period, and light emission period, respectively.

[0018] Figure 9 This is a timing diagram schematically illustrating a first modified example of a first embodiment of the present disclosure of a driving signal for driving a pixel;

[0019] Figure 10 This is a timing diagram schematically illustrating a second modified example of a first embodiment of the present disclosure, showing the driving signals for driving pixels;

[0020] Figure 11 This is a cross-sectional view schematically illustrating an example of the cross-sectional structure of a display panel according to a first embodiment of the present disclosure;

[0021] Figure 12 This is a timing diagram schematically illustrating the driving signals for driving pixels according to a first example of a second embodiment of the present disclosure;

[0022] Figure 13 This shows the use of Figure 12 A view of the operating state of elements within a pixel during the anode reset period when the drive signal is applied.

[0023] Figure 14 This is a timing diagram schematically illustrating a second example of a second embodiment of the present disclosure of a driving signal for driving a pixel;

[0024] Figure 15 This shows the use of Figure 14 A view of the operating state of elements within a pixel during the anode reset period when the drive signal is applied.

[0025] Figure 16 This is a timing diagram schematically illustrating the driving signals for driving pixels according to a third example of a second embodiment of the present disclosure;

[0026] Figure 17 This shows the use of Figure 16 A view of the operating state of elements within a pixel during the anode reset period when the drive signal is applied.

[0027] Figure 18 This is a timing diagram schematically illustrating the driving signals for driving pixels according to a first example of a third embodiment of the present disclosure;

[0028] Figure 19 This shows the use of Figure 18 A view of the operating state of elements within a pixel during the light-emitting off period when the driving signal is applied.

[0029] Figure 20 This is a timing diagram schematically illustrating a second example of a driving signal for driving a pixel according to a third embodiment of the present disclosure;

[0030] Figure 21 This shows the use of Figure 20 A view of the operating state of elements within a pixel during the light-emitting off period when the driving signal is applied.

[0031] Figure 22 This is a timing diagram schematically illustrating a third example of a third embodiment of the present disclosure of a driving signal for driving a pixel.

[0032] Figure 23 This shows the use of Figure 22A view of the operating state of elements within a pixel during the light-emitting off period when the driving signal is applied.

[0033] Figure 24 This is a view schematically illustrating an example of pixels according to a fourth embodiment of the present disclosure;

[0034] Figures 25 to 28 This is a view showing the operational states of elements within a pixel during the initialization period, sampling period, data writing period, and emission period when driven according to the fourth embodiment of this disclosure; and

[0035] Figure 29 This is a view schematically illustrating an example of pixels according to a fifth embodiment of the present disclosure.

[0036] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative sizes and descriptions of these elements may be exaggerated. Detailed Implementation

[0037] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations relevant to this document will be omitted or may be briefly discussed where it is determined that such detailed descriptions unnecessarily obscure the essential points of the inventive concept. The progression of the described processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to the order set forth herein and can be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The same reference numerals always denote the same elements. The names of the various elements used in the following explanation may have been chosen merely for convenience in writing the specification and may therefore differ from the names used in actual products.

[0038] The advantages and features of this disclosure, as well as methods of implementing them, will become apparent from the following detailed description of the embodiments, taken in conjunction with the accompanying drawings. However, this disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only these embodiments allow for the completeness of this disclosure. This disclosure is provided to fully inform those skilled in the art of this disclosure of its scope, and this disclosure may be defined by the scope of the claims.

[0039] The shapes, sizes, proportions, angles, quantities, etc., disclosed in the accompanying drawings used to explain the embodiments of this disclosure are illustrative, and this disclosure is not limited to the content described. Throughout the specification, the same reference numerals refer to the same parts.

[0040] Any implementation described in this article as an “example” is not necessarily to be interpreted as being better or more advantageous than other implementations.

[0041] Furthermore, in describing this disclosure, detailed descriptions of relevant known technologies may be omitted if it is determined that such detailed descriptions unnecessarily obscure the subject matter of this disclosure. When terms such as 'comprising,' 'including,' 'having,' 'consisting of,' etc., are used in this disclosure, additional parts may be added unless 'only' is used. When a component is represented in the singular, the plural is also included unless specifically stated otherwise.

[0042] When interpreting components, even if there is no separate explicit description, it is interpreted as including the allowance range.

[0043] Furthermore, when referring to any size, relative size, etc., the numerical values ​​or corresponding information (e.g., level, range, etc.) of a component or feature should be considered to include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. Additionally, the term "may" fully encompasses all the meanings of the term "able to".

[0044] When describing positional relationships, for example, when the positional relationship between two parts is described as 'on top of,' 'above,' 'above,' 'below,' 'next to,' 'below,' etc., one or more other parts may be located between the two parts, unless 'directly' or 'directly' is used.

[0045] When describing temporal relationships, such as when time sequence is described as 'after', 'following', 'before', etc., discontinuous cases can be included unless 'direct' or 'immediate' is used.

[0046] In describing the components of this disclosure, terms such as first, second, etc., may be used. These terms are used only to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by these terms.

[0047] Furthermore, when a component or layer is "connected," "joined," or "adhered" to another component or layer, it means that the component or layer can be directly connected or adhered to the other component or layer, or indirectly connected or adhered to the other component or layer, wherein one or more intermediate components or layers are "set" or "intercalated" between these components or layers, unless otherwise stated. This should be understood to mean that these components can be arranged to be in direct contact with each other, or can be arranged to be in non-direct contact with each other.

[0048] The expressions "first element," "second element," and " / or" "third element" should be understood as one of the first, second, and third elements, or as any one or all combinations of the first, second, and third elements. For example, A, B, and / or C can refer to: only A; only B; only C; any one or some combinations of A, B, and C; or all of A, B, and C.

[0049] The term “at least one” should be understood to include any one and all combinations of one or more of the listed related items. For example, “at least one of the first, second and third elements” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element: the first element, the second element, or the third element.

[0050] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It should also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant field, and shall not be interpreted as having an idealized or overly formal meaning unless expressly defined herein. For example, the terms “part” or “unit” may be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the described functions, as would be understood by one of ordinary skill in the art.

[0051] More precisely, these embodiments are provided to make this disclosure sufficiently comprehensive and complete to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0052] The various features of the various embodiments of this disclosure can be connected or combined with each other in part or in whole, and can be technically interlocked and driven differently, and the various embodiments can be implemented independently of each other or can be implemented together in a related relationship.

[0053] In the following description, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Furthermore, in the following embodiments, the same and similar reference numerals are assigned to the same and similar parts, and their detailed descriptions may be omitted.

[0054] <First Implementation Method>

[0055] Figure 1 This is a schematic view of a display device according to a first embodiment of the present disclosure. Figure 2 This is a circuit diagram schematically illustrating an example of a pixel according to a first embodiment of the present disclosure. Figure 3This is a view showing the configuration of the gating drive portion of a display device according to a first embodiment of the present disclosure.

[0056] Before going into detail, the display device 10 according to this disclosure may include a light-emitting display device equipped with light-emitting diodes. Furthermore, the display device 10 of this embodiment may include all types of display devices that apply the VRR (Variable Refresh Rate) method.

[0057] Meanwhile, for ease of explanation, in this disclosure, an organic light-emitting display device is used as an example to describe the display device 10.

[0058] refer to Figures 1 to 3 The display device 10 in this embodiment may include a display panel 100 and a driving circuit portion for driving the display panel 100.

[0059] Here, the driving circuit section may include, for example, a gating driving section (or gating driving circuit) 210, a data driving section (or data driving circuit) 220, and a timing control section (or timing control circuit) 240. Furthermore, the driving circuit section may include a power supply section (or power supply circuit) 280, which provides the power required to drive the display panel 100, the gating driving section 210, the data driving section 220, and the timing control section 240.

[0060] The display panel 100 may include a display area (active area) AA for displaying images and a non-display area (non-active area) NA arranged outside (or around) the display area AA.

[0061] In the display area AA, multiple pixels P can be arranged in a matrix along multiple horizontal lines (or row lines) and multiple vertical lines (or column lines).

[0062] Here, the multiple pixels P may include pixels that display different colors, such as red pixels, green pixels, and blue pixels that display red, green, and blue respectively, but are not limited to this.

[0063] In the display panel 100, various signal lines for transmitting drive signals for driving pixels P can be formed on the substrate.

[0064] In this regard, for example, multiple data lines DL that transmit data signals (or data voltages) as image signals can extend in the vertical direction and be connected to the pixels P of each vertical line.

[0065] Furthermore, the gating line GL, which transmits the gating signal (or gating voltage), can extend in the horizontal direction and connect to the pixel P corresponding to the horizontal line.

[0066] In this embodiment, multiple gating signals can be used to drive each pixel P. For example, first scan signals SC1 to fourth scan signals SC4, first light emission control signal EM1, and second light emission control signal EM2 can be used. Therefore, multiple gating lines GL can be used to transmit multiple gating signals respectively. For example, first scan lines SCL1 to fourth scan lines SCL4, first light emission control line EML1, and second light emission control line EML2 can be used.

[0067] Thus, multiple pixels P can be defined by multiple intersecting data lines DL and gating lines GL.

[0068] Each pixel P may include a light-emitting diode OD as a light-emitting element, as well as a plurality of transistors and at least one capacitor for driving the light-emitting diode OD.

[0069] Meanwhile, in this embodiment, for ease of explanation, as follows: Figure 2 The example shown is a 7T2C structure in which pixel P is equipped with 7 transistors T1 to T6 and DT, as well as two capacitors Cst and Ca. Figure 1 Each pixel P in the display device 10 can have Figure 2 Pixel configuration.

[0070] refer to Figure 2 Pixel P may include multiple switching transistors, such as first transistor T1 to sixth transistor T6, driving transistor DT, storage capacitor (or first capacitor) Cst, pumping capacitor (or auxiliary capacitor or second capacitor) Ca and light-emitting diode OD.

[0071] Each of the first transistor T1 through the sixth transistor T6 and the driving transistor DT may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0072] Each of the first transistor T1 through the sixth transistor T6 and the driving transistor DT can be an N-type or P-type transistor. Meanwhile, in this embodiment, as... Figure 2 The image shows an example in which the first transistor T1 to the sixth transistor T6 and the driving transistor DT in pixel P are all configured as N-type transistors, but it is not limited to this.

[0073] The first transistors T1 through T6 and the driving transistor DT may comprise semiconductors of the same material or semiconductors of different materials. In this regard, for example, some of the first transistors T1 through T6 and the driving transistor DT may have one of a polycrystalline silicon layer, an oxide semiconductor layer, and an amorphous silicon layer, and others of the first transistors T1 through T6 and the driving transistor DT may have another of a polycrystalline silicon layer, an oxide semiconductor layer, and an amorphous silicon layer.

[0074] Meanwhile, since oxide semiconductors have excellent cutoff current characteristics and properties suitable for switching transistors, at least one of the first transistors T1 to the sixth transistor T6 can have an oxide semiconductor layer. Furthermore, since polysilicon has excellent mobility, the driving transistor DT can have a polysilicon layer. The first transistors T1 to the sixth transistor T6 and the driving transistor DT can be configured in another way; for example, the driving transistor DT can have an oxide semiconductor layer.

[0075] Meanwhile, in this embodiment, the case where the first transistor T1 to the sixth transistor T6 both include an oxide semiconductor layer and the driving transistor DT also includes an oxide semiconductor layer is taken as an example.

[0076] Provided Figure 2 The gating signal for the nth horizontal line (more specifically, at least one of the odd-numbered and even-numbered horizontal lines constituting the nth horizontal line) can be provided from the corresponding nth stage of the gating drive section 210. For example, four scan signals, the first scan signal to the fourth scan signal (SC1 to SC4: SC1(n) to SC4(n)) and two light emission control signals, the first light emission control signal and the second light emission control signal (EM1 and EM2: EM1(n) and EM2(n)) can be provided. In this case, the first scan line SCL1 to the fourth scan line SCL4 and the first light emission control line EML1 and the second light emission control line EML2 can be arranged in the display area AA, which are connected to the nth stage and transmit the first scan signal SC1(n) to the fourth scan signal SC4(n) and the first light emission control signal EM1(n) and the second light emission control signal EM2(n) to the pixel P. Here, n can be a real number, such as a positive integer.

[0077] The first transistor T1 can be used as a sampling transistor, the second transistor T2 can be used as a data supply transistor, the third transistor T3 can be used as a reset transistor, the fourth transistor T4 can be used as a reference voltage supply transistor, and the fifth transistor T5 and the sixth transistor T6 can be used as light-emitting control transistors.

[0078] A light-emitting diode (LED) OD may include an anode electrode and a cathode electrode. The anode electrode of the LED OD may be connected to a first node N1, and a low-potential drive voltage EVSS may be applied to the cathode electrode of the LED OD.

[0079] The driving transistor DT may include, for example, a first electrode (or source electrode) connected to a first node N1, a second electrode (or drain electrode) connected to a third node N3, and a gate electrode connected to a second node N2. The driving transistor DT can provide a driving current to the light-emitting diode OD based on the voltage of the first node N1 (i.e., the data voltage Vdata stored in the storage capacitor Cst).

[0080] The first transistor T1 may include, for example, a first electrode (or source electrode) connected to the second node N2, a second electrode (or drain electrode) connected to the fourth node N4, and a gate electrode that receives the first scan signal SC1(n).

[0081] The first transistor T1 can be turned on in response to the first scan signal SC1(n), and during the data writing period, the data voltage Vdata can be transmitted through the pump capacitor Ca and applied (or written) to the gate electrode of the driving transistor DT, which is a horizontal period on which horizontal lines corresponding to the pixel P are arranged.

[0082] Furthermore, the first transistor T1 can be turned on in response to the first scan signal SC1(n), and the threshold voltage Vth of the driving transistor DT can be applied (or sampled) to the gate electrode of the driving transistor DT during a sampling period set before the data writing period on which the horizontal line corresponding to the pixel P is arranged.

[0083] The storage capacitor Cst can be connected, for example, between a first node N1 and a second node N2. In other words, the storage capacitor Cst can be connected between the first electrode and the gate electrode of the driving transistor DT. For example, the first electrode and the second electrode forming the storage capacitor Cst can be connected to the first node N1 and the second node N2, respectively.

[0084] The storage capacitor Cst can store and hold the data voltage Vdata and the threshold voltage Vth of the driving transistor DT.

[0085] The second transistor T2 may include, for example, a second electrode (or drain electrode) connected to the data line DL (or receiving the data voltage Vdata), a first electrode (or source electrode) connected to the fifth node N5, and a gate electrode for receiving the second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n) and may transmit the data voltage Vdata to the fifth node N5.

[0086] The third transistor T3 may include, for example, a second electrode (or drain electrode) connected to the reset voltage line VarL that transmits the anode reset voltage Var, a first electrode (or source electrode) connected to the first node N1, and a gate electrode that receives the third scan signal SC3(n).

[0087] The third transistor T3 can be turned on in response to the third scan signal SC3(n), and the anode reset voltage Var can be applied to the first node N1 (i.e., the anode electrode of the light-emitting diode OD) during the initialization period, which is set before the sampling period of the corresponding pixel P.

[0088] Furthermore, the third transistor T3 can be turned on in response to the third scan signal SC3(n), and the anode reset voltage Var, together with the threshold voltage Vth, can be applied (or sampled) to the gate electrode of the driving transistor DT during the sampling period of the corresponding pixel P.

[0089] The fourth transistor T4 can be connected to the second transistor T2, for example, at the fifth node N5, so that the fourth transistor T4 and the second transistor T2 can be connected in parallel.

[0090] The fourth transistor T4 may include, for example, a second electrode (or drain electrode) connected to a reference voltage line VrefL that transmits the reference voltage Vref, a first electrode (or source electrode) connected to a fifth node N5, and a gate electrode that receives the fourth scan signal SC4(n).

[0091] The fourth transistor T4 can be turned on in response to the fourth scan signal SC4(n), and the reference voltage Vref can be applied to the fifth node N5 during the initialization period and the sampling period, which are set before the data writing period of the corresponding pixel P.

[0092] The fifth transistor T5 may include, for example, a second electrode (or drain electrode) that receives a high-potential drive voltage EVDD, a first electrode (or source electrode) connected to the fourth node N4, and a gate electrode that receives a first light emission control signal EM1(n).

[0093] The sixth transistor T6 may include a second electrode (or drain electrode) connected to the fourth node N4, a first electrode (or source electrode) connected to the third node N3 (or the second electrode of the driving transistor DT), and a gate electrode that receives the second light emission control signal EM2(n).

[0094] The fifth transistor T5 and the sixth transistor T6 can be turned on in response to the corresponding first light emission control signal EM1(n) and second light emission control signal EM2(n), and can supply driving current to the light emission diode OD during the light emission period. The light emission diode OD can emit light with a brightness corresponding to the driving current. This light emission period is set after the data writing period of the corresponding pixel P.

[0095] Furthermore, the sixth transistor T6, which is directly connected to the driving transistor DT, can be turned on in response to the second light emission control signal EM2(n), and can form a current path (or charging path) together with the first transistor T1 during the sampling period of the corresponding pixel P for sampling the threshold voltage Vth at the second node N2.

[0096] In this regard, during the sampling period used to sample the threshold voltage Vth of the driving transistor DT, as previously described, the first transistor T1, the third transistor T3, and the sixth transistor T6 can be turned on.

[0097] In this configuration, a current path can be formed along the third transistor T3, the driving transistor DT, the sixth transistor T6, and the first transistor T1. Therefore, a voltage (Var+Vth) reflecting the anode reset voltage Var input through the third transistor T3 and the threshold voltage Vth of the driving transistor DT can be applied to the second node N2, whose gate electrode is connected.

[0098] The pump capacitor Ca can be connected, for example, between the fourth node N4 and the fifth node N5. In other words, the pump capacitor Ca can be connected between the first electrode and the fourth node N4, where the first electrode is the output electrode of the second transistor T2 and the fourth transistor T4 connected in parallel. For example, the third and fourth electrodes forming the pump capacitor Ca can be connected to the fourth node N4 and the fifth node N5, respectively.

[0099] By pumping capacitor Ca, the data voltage Vdata input to the fifth node N5 during the data write period can be reflected to the fourth node N4.

[0100] For example, after the reference voltage Vref is input to the fifth node N5, the data voltage Vdata can be input to the fifth node N5, and during the data write period, the difference between these voltages (ΔV = Vdata - Vref) can be reflected in the fourth node N4, which is in a floating state. Thus, the voltage difference (ΔV) including the data voltage Vdata can be reflected in the second node N2 through the turned-on first transistor T1, so that the data voltage Vdata can be reflected in the gate electrode of the driving transistor DT.

[0101] Thus, in this embodiment, pixel P can perform a sampling operation of the threshold voltage Vth of the driving transistor DT before the data writing operation.

[0102] Thus, in this embodiment, the sampling operation for threshold voltage Vth compensation can be performed separately from the data writing operation. Therefore, the sampling time of the threshold voltage Vth is not limited to the horizontal time period when data writing is performed, but can be set to be longer than the horizontal time period.

[0103] By enabling sampling for an extended period, the threshold voltage Vth can be fully sampled and reflected, thereby reducing or preventing error components in the sampled voltage.

[0104] Therefore, the threshold voltage compensation of pixel P can be improved, thus reducing compensation error and thus improving the image quality of display device 10.

[0105] The driving method for implementing the threshold voltage compensation in this embodiment will be described in more detail below.

[0106] refer to Figure 1 The timing control section 240 can process the image data Do input from the host system to suit the size and resolution of the display panel 100 and supply it to the data driving section 220. The timing control section 240 can use synchronization signals input from the host system, such as the dot clock signal CLK, the data enable signal DE, the horizontal synchronization signal HSY, and the vertical synchronization signal VSY, to generate a gating control signal GCS and a data control signal DCS. By supplying the gating control signal GCS and the data control signal DCS generated in this manner to the gating driving section 210 and the data driving section 220 respectively, the gating driving section 210 and the data driving section 220 can be controlled.

[0107] The timing control section 240 can be configured to work with various processors, such as microprocessors, mobile processors, application processors, etc., depending on the device to be installed.

[0108] Meanwhile, the host system can be, for example, a driving system for the electronic device used in the display device 10. The electronic device can be, for example, a TV, a navigation system, a monitor, a mobile device, or a wearable device.

[0109] The gating drive section 210 can receive the gating control signal GCS from the timing control section 240, generate gating signals, and apply the gating signals to the gating line GL sequentially. For example, the gating signals can be output sequentially from top to bottom in the vertical direction.

[0110] The gating drive portion 210 may be arranged, for example, on at least one side of the display area AA. In this embodiment, an example is taken where the gating drive portion 210 is configured to include a first gating drive portion 211 and a second gating drive portion 212 arranged on both sides of the display area AA (e.g., on the left and right sides of the display area AA).

[0111] The gate drive portion 210 can be formed directly in the non-display area NA on the substrate of the display panel 100, for example, in a GIP (gate in panel) structure. In this case, the gate drive portion 210 can be formed during the process of forming the elements of the display panel 100.

[0112] The gating drive section 210 configured with a GIP structure may include, for example, a first scan drive circuit that sequentially outputs a first scan signal SC1, a second scan drive circuit that sequentially outputs a second scan signal SC2, a third scan drive circuit that sequentially outputs a third scan signal SC3, a fourth scan drive circuit that sequentially outputs a fourth scan signal SC4, a first light-emitting drive circuit that sequentially outputs a first light-emitting control signal EM1, and a second light-emitting drive circuit that sequentially outputs a second light-emitting control signal EM2.

[0113] Each of the first to fourth scan driving circuits, the first light-emitting driving circuit, and the second light-emitting driving circuit may be configured with a shift register, which includes multiple stages for outputting corresponding signals.

[0114] Further reference Figure 3 Description of the strobe drive section 210. Figure 3 A portion of the gating drive section 210 is shown, and for ease of explanation, a portion of the configuration of the gating drive section 210 for the nth horizontal line configured with the nth odd-numbered horizontal line (or the 2n-1th horizontal line) and the nth even-numbered horizontal line (or the 2nth horizontal line) of the display area AA is shown.

[0115] In the first gating drive section 211 of the gating drive section 210, for example, a first scan level SSC1(n), a third scan level SSC3(n), and a fourth scan level SSC4(n) that respectively constitute a first scan drive circuit, a third scan drive circuit, and a fourth scan drive circuit can be arranged; a first light-emitting level SEM1(n) and a second light-emitting level SEM2(n) that respectively constitute a first light-emitting drive circuit and a second light-emitting drive circuit can be arranged; and an odd-numbered second scan level SSC2_O(n) and an even-numbered second scan level SSC2_E(n) that constitute a second scan drive circuit can be arranged.

[0116] Furthermore, in the second gating drive section 212 of the gating drive section 210, for example, a first scan level SSC1(n), a third scan level SSC3(n), and a fourth scan level SSC4(n) that respectively constitute the first scan drive circuit, the third scan drive circuit, and the fourth scan drive circuit can be arranged; a first light-emitting level SEM1(n) and a second light-emitting level SEM2(n) that respectively constitute the first light-emitting drive circuit and the second light-emitting drive circuit; and an odd-numbered second scan level SSC2_O(n) and an even-numbered second scan level SSC2_E(n) that constitute the second scan drive circuit.

[0117] In the gating drive section 210, the odd-numbered second scan levels SSC2_O(n) and even-numbered second scan levels SSC2_E(n) constituting the second scan drive circuit can be arranged closest to the display area AA, and the second light-emitting level SEM2(n) can be arranged at the outermost part furthest from the display area AA. Furthermore, the first light-emitting level SEM1(n) can be arranged between the first scan level SSC1(n) and the fourth scan level SSC4(n).

[0118] Figure 3 The arrangement of the first scan level SSC1(n) to the fourth scan level SSC4(n) and the first light emission level SEM1(n) and the second light emission level SEM2(n) shown is an example, and they can be arranged in various combinations in the first gating drive section 211 and the second gating drive section 212.

[0119] The first scan level SSC1(n) can generate a first scan signal SC1(n) and output it to the corresponding first scan line SCL1. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line and the pixel P_E(n) of the nth even-numbered horizontal line can be jointly subjected to the first scan signal SC1(n).

[0120] The odd-numbered second scan level SSC2_O(n) can generate an odd-numbered second scan signal SC2_O(n) and output it to the corresponding odd-numbered second scan line SCL2, and the even-numbered second scan level SSC2_E(n) can generate an even-numbered second scan signal SC2_E(n) and output it to the corresponding even-numbered second scan line SCL2. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line can be given an odd-numbered second scan signal SC2_O(n), and the pixel P_E(n) of the nth even-numbered horizontal line can be given an even-numbered second scan signal SC2_E(n). Here, the odd-numbered second scan signal SC2_O(n) and the even-numbered second scan signal SC2_E(n) can have different timing sequences. For example, the odd-numbered second scan signal SC2_O(n) and the even-numbered second scan signal SC2_E(n) can be applied to the horizontal time period (or data writing period) of the nth odd-numbered horizontal line and the immediately following horizontal time period (or data writing period) of the nth even-numbered horizontal line, respectively.

[0121] The third scan level SSC3(n) can generate a third scan signal SC3(n) and output it to the corresponding third scan line SCL3. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line and the pixel P_E(n) of the nth even-numbered horizontal line can be jointly subjected to the third scan signal SC3(n).

[0122] The fourth scan level SSC4(n) can generate the fourth scan signal SC4(n) and output it to the corresponding fourth scan line SCL4. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line and the pixel P_E(n) of the nth even-numbered horizontal line can be jointly subjected to the fourth scan signal SC4(n).

[0123] The first luminous level SEM1(n) can generate a first luminous control signal EM1(n) and output it to the corresponding first luminous control line EML1. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line and the pixel P_E(n) of the nth even-numbered horizontal line can be jointly subjected to the first luminous control signal EM1(n).

[0124] The second luminous level SEM2(n) can generate a second luminous control signal EM2(n) and output it to the corresponding second luminous control line EML2. Therefore, the pixel P_O(n) of the nth odd-numbered horizontal line and the pixel P_E(n) of the nth even-numbered horizontal line can be jointly subjected to the second luminous control signal EM2(n).

[0125] At the same time, refer to Figure 3 The reference voltage line VrefL and the reset voltage line VarL can be arranged between the gating drive section 210 and the display area AA.

[0126] The reference voltage line VrefL and the reset voltage line VarL can supply the reference voltage Vref and the anode reset voltage Var respectively from the power supply section 280 to the pixel P in the display area AA.

[0127] exist Figure 3 In the diagram, each of the reference voltage line VrefL and the reset voltage line VarL is shown as being located only on the left or right side of the display area AA, but is not limited thereto, and each of the bias voltage line VobsL, the reset voltage line VarL, and the initialization voltage line ViniL can be located on both sides, and even if it is located on one side, it is not limited to being on the left or the right side.

[0128] In addition, refer to Figure 3 One or more optical regions OA1 and OA2 can be set in the display area AA.

[0129] One or more optical regions OA1 and OA2 may be arranged to overlap with one or more optoelectronic devices (e.g., photographic devices such as cameras (or image sensors), and / or detection sensors such as proximity sensors and illuminance sensors). For the operation of the optoelectronic devices, one or more optical regions OA1 and OA2 may have light-transmitting structures formed therein, and may have a certain level or higher transmittance. In other words, the number of pixels P per unit area in one or more optical regions OA1 and OA2 may be less than the number of pixels P per unit area in the conventional area of ​​the display area AA excluding optical regions OA1 and OA2. That is, the resolution of one or more optical regions OA1 and OA2 may be lower than the resolution of the conventional area within the display area AA.

[0130] Return to reference Figure 1 The data driving section 220 can receive image data Do and data control signal DCS from the timing control section 240, and in response to the data control signal DCS, the data driving section 220 can convert the image data Do into analog image data, i.e., data voltage Vdata, and output them to the corresponding data line DL.

[0131] The power supply section 280 can use, for example, a DC-DC converter to generate the DC power required to drive the pixel array and drive circuitry of the display panel 100. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc.

[0132] The power supply section 280 can receive, for example, a power supply voltage Vcc from the host system as a driving voltage for driving the display device 10, and generate DC voltages such as low-voltage gates VGL and VEL, high-voltage gates VGH and VEH, a high-level driving voltage EVDD, and a low-level driving voltage EVSS. The low-voltage gates VGL and VEL, and the high-voltage gates VGH and VEH, can be supplied to the gate driving section 210. The high-level driving voltage EVDD and the low-level driving voltage EVSS can be jointly supplied to the pixels P in the display panel 100.

[0133] The display device 10 configured as described above can be driven at low power in the VRR method, in which the refresh cycle (or refresh rate) is adjusted to reduce power consumption.

[0134] In this regard, in the normal driving mode, which is a high-speed driving mode, the display device 10 can operate to refresh (or update) the image of the display panel 100 (or the data voltage Vdata applied to each pixel P) frame by frame. For example, in the high-speed driving mode, the display device 10 can be driven at a refresh rate of 120Hz, so that a refresh operation can be performed for each frame in 120 frames per second. In this way, in the high-speed driving mode, all frames can be designated as refresh frames for writing the data voltage Vdata.

[0135] When displaying still images, the display device 10 can be driven in a low-speed drive mode. In low-speed drive mode, the refresh rate is reduced, making the refresh cycle of the display panel 100 longer. For example, when driven at a low refresh rate of 10Hz, one refresh frame and 11 consecutive skip frames can be alternately repeated. Thus, in low-speed drive mode, the frame can be divided into a refresh frame with written data voltage Vdata and a skip frame with no written data voltage Vdata and the writing is skipped.

[0136] Thus, in low-speed drive mode, as the drive frequency decreases, the refresh frame period (or the interval between refresh frames) becomes longer, and there are one or more skipped frames between refresh frames.

[0137] During frame skipping, image refresh operations are stopped, which reduces power consumption.

[0138] During the refresh frame when writing the data voltage Vdata, the first scan signal SC1 to the fourth scan signal SC4 (more specifically, their scan pulses) can be applied to write the data voltage Vdata to the corresponding pixel P.

[0139] Furthermore, in a skip frame where no data voltage Vdata is written and the data voltage Vdata is held, an operation can be performed to apply an anode reset voltage Var to reset the anode electrode of the light-emitting diode OD. For this purpose, a third scan signal SC3 (more specifically, its scan pulse) can be applied to provide the anode reset voltage Var to pixel P.

[0140] Further references are provided below. Figures 4 to 8 Describe the drive in the refresh frame, in which the data voltage Vdata is written and the threshold voltage Vth of the drive transistor DT is sampled and compensated.

[0141] Figure 4 This is a timing diagram schematically illustrating an example of a driving signal for driving a pixel according to a first embodiment of the present disclosure. Figures 5 to 8 This shows the use of Figure 4 The view shows the operating states of the elements within a pixel during the initialization period, sampling period, data writing period, and emission period, respectively, when the driving signal is applied.

[0142] exist Figures 4 to 8 For ease of explanation, the refresh drive of pixels P_O(n) of the odd-numbered horizontal lines in the nth horizontal line is shown as an example. Simultaneously, during the corresponding horizontal time period, the corresponding second scan signal SC2_E(n) can be applied to pixels P_E(n) of the nth even-numbered horizontal line.

[0143] First, refer to Figure 4 This describes the driver in the refresh frame FRr, in which the refresh operation is performed. The refresh frame FRr can be divided into a non-emitting period Tne and an emitting period Te.

[0144] The non-light-emitting period Tne and the light-emitting period Te can be defined by the first light-emitting control signal EM1(n) and the second light-emitting control signal EM2(n) of the refresh frame FRr. In this respect, the on-level range (e.g., high-level range) of the first light-emitting control signal EM1(n) and the second light-emitting control signal EM2(n) can correspond to the light-emitting period Te, and the off-level range (e.g., low-level range) of at least one of the first light-emitting control signal EM1(n) and the second light-emitting control signal EM2(n) can correspond to the non-light-emitting period Tne. The non-light-emitting period Tne can essentially be the period during which scan signals SC1(n) to SC4(n) are applied and data refresh operations are performed, and can be said to correspond to the data refresh period or the scan drive period.

[0145] During the non-light-emitting period Tne of the refresh frame FRr, for example, the initialization period Ti, the sampling period Tsp, and the data writing period Tw can be executed sequentially.

[0146] Regarding the initialization time period Ti, refer to... Figure 4 and Figure 5 For example, the first scan signal SC1(n) can have a high level as the on level, the third scan signal SC3(n) can have a high level as the on level, the fourth scan signal SC4(n) can have a high level as the on level, and the first light emission control signal EM1(n) can have a high level as the on level.

[0147] Furthermore, during the initialization period Ti, the second scan signal SC2(n) may have a low level as a cutoff level, and the second light emission control signal EM2(n) may have a low level as a cutoff level.

[0148] In response to scan signals SC1(n) to SC4(n) and light emission control signals EM1(n) and EM2(n), the first transistor T1, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 can be turned on, and the second transistor T2 and the sixth transistor T6 can be turned off.

[0149] Therefore, the anode reset voltage Var can be provided to the first node N1 through the third transistor T3 in the on state, so that the initialization of the anode electrode of the light-emitting diode OD can be performed, that is, the anode reset.

[0150] Furthermore, the high-potential drive voltage EVDD can be provided to the second node N2 and the fourth node N4 through the first transistor T1 and the fifth transistor T5, which are in the on state, and the reference voltage Vref can be provided to the fifth node N5 through the fourth transistor T4, which is in the on state. Therefore, the voltage at the gate electrode of the drive transistor DT can be initialized, and the voltage stored in the storage capacitor Cst and the voltage stored in the pump capacitor Ca can also be initialized.

[0151] Next, regarding the sampling period Tsp executed after the initialization period Ti, refer to... Figure 4 and Figure 6 For example, the first scan signal SC1(n) can have a high level as the on level, the third scan signal SC3(n) can have a high level as the on level, the fourth scan signal SC4(n) can have a high level as the on level, and the second light emission control signal EM2(n) can have a high level as the on level (or a high pulse).

[0152] Furthermore, during the sampling period Tsp, the second scan signal SC2(n) may have a low level as a cutoff level, and the first light emission control signal EM1(n) may have a low level as a cutoff level.

[0153] In response to scan signals SC1(n) to SC4(n) and light emission control signals EM1(n) and EM2(n), the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 can be turned on, and the second transistor T2 and the fifth transistor T5 can be turned off.

[0154] Therefore, the third node N3 to which the second electrode of the driving transistor DT is connected, and the second node N2 to which the gate electrode of the driving transistor DT is connected, can be electrically short-circuited due to the first transistor T1 and the sixth transistor T6 being in the on state. Thus, the driving transistor DT can be in a diode-connected state, where the gate and drain electrodes of the driving transistor are electrically short-circuited.

[0155] At this time, the third transistor T3 can be turned on, so that a current path can be formed along the third transistor T3, the driving transistor DT, the sixth transistor T6 and the first transistor T1.

[0156] Therefore, the voltage (Var+Vth) reflecting the anode reset voltage Var input through the third transistor T3 and the threshold voltage Vth of the driving transistor DT can be applied to the second node N2, i.e., the gate electrode of the driving transistor DT.

[0157] Thus, the anode reset voltage Var and threshold voltage Vth applied to the second node N2 can be used to charge and store in the storage capacitor Cst (e.g., the storage capacitor Cst is connected to the second electrode of the second node N2).

[0158] Thus, the high pulse interval of the second light emission control signal EM2(n) (as the sampling period Tsp of the second node N2 during which the threshold voltage Vth is reflected, which essentially defines the sampling period Tsp) can be set to be longer than the data writing period Tw that is set to the horizontal period, and preferably, it can be set to be equal to or greater than twice the horizontal period.

[0159] Thus, when the sampling period Tsp can be set to be a considerably long time separate from the data writing period Tw, the threshold voltage Vth of the driving transistor DT can be fully sampled during the sampling operation.

[0160] Therefore, the error component of the threshold voltage Vth that may occur during short-term sampling (such as horizontal time intervals) can be reduced or prevented, thereby reducing the error of threshold voltage compensation, enhancing threshold voltage compensation, and thus improving the image quality of the display device 10.

[0161] Meanwhile, even during the sampling period Tsp, the anode reset voltage Var can be continuously supplied to the first node N1 through the third transistor T3, which is in the on state, so that the initialization of the anode electrode of the light-emitting diode OD can be performed, that is, the anode reset.

[0162] In addition, the reference voltage Vref can be continuously supplied to the fifth node N5 through the fourth transistor T4 which is in the on state, so that the fifth node N5 can maintain this voltage during the initialization period.

[0163] Next, regarding the data writing period Tw executed after the sampling period Tsp, please refer to [reference needed]. Figure 4 and Figure 7 For example, the first scan signal SC1(n) can have a high level as the on level, the second scan signal SC2(n) can have a high level as the on level, and the third scan signal SC3(n) can have a high level as the on level.

[0164] Furthermore, during the data writing period Tw, the fourth scan signal SC4(n) may have a low level as a cutoff level, the first light emission control signal EM1(n) may have a low level as a cutoff level, and the second light emission control signal EM2(n) may have a low level as a cutoff level.

[0165] In response to scan signals SC1(n) to SC4(n) and light emission control signals EM1(n) and EM2(n), the first transistor T1, the second transistor T2 and the third transistor T3 can be turned on, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 can be turned off.

[0166] Therefore, the data voltage Vdata can be supplied to the fifth node N5 through the second transistor T2 in the on state, and the data voltage Vdata can be reflected to the fourth node N4 through the pump capacitor Ca.

[0167] In this respect, the voltage of the fifth node N5 can be changed from the reference voltage Vref input during the sampling period Tsp to the data voltage Vdata input during the data writing period Tw.

[0168] In this scenario, the voltage difference (ΔV), (Vdata-Vref) caused by the voltage change at the fifth node N5, can be reflected in the fourth node N4, which is in a floating state during the data write period Tw, through the voltage holding action (or voltage pumping action) of the pump capacitor Ca connected between the fourth node N4 and the fifth node N5. Thus, the pump capacitor Ca performs a voltage pumping function, which reflects the voltage change at the fifth node N5 during the data write period Tw to the fourth node N4.

[0169] The voltage difference (ΔV) reflecting the data voltage Vdata can be transmitted to the second node N2 through the first transistor T1 during the data writing period Tw, so that it can be reflected in the voltage of the second node N2, that is, reflected in the voltage of the gate electrode of the driving transistor DT.

[0170] For example, during the data writing period Tw, the voltage difference (ΔV = (Vdata - Vref)) can be reflected in the second node N2, so that the voltage of the second node N2 can be changed to reflect the data voltage Vdata, and this voltage of the second node N2 can be used to charge and store in the storage capacitor Cst (e.g., the storage capacitor Cst is connected to the second electrode of the second node N2).

[0171] Meanwhile, even during the data writing period Tw, the anode reset voltage Var can be continuously supplied to the first node N1 through the third transistor T3, which is in the on state, so that the initialization of the anode electrode of the light-emitting diode OD can be performed, that is, the anode reset.

[0172] Meanwhile, regarding the data writing operations for the nth odd-numbered horizontal line and the nth even-numbered horizontal line, immediately after executing the data writing period Tw for the pixel P_O(n) of the nth odd-numbered horizontal line during the corresponding horizontal period, the data writing period Tw for the pixel P_E(n) of the nth even-numbered horizontal line can be executed during the corresponding horizontal period.

[0173] As described above, after the data writing period Tw is completed, a drive current can be supplied to the light-emitting diode OD during the light-emitting period Te to perform the light-emitting operation.

[0174] Regarding the luminescence period Te, refer to Figure 4 and Figure 8 For example, the first scan signal SC1(n) to the fourth scan signal SC4(n) can all have a low level as a cutoff level, and the first light emission control signal EM1(n) and the second light emission control signal EM2(n) can all have a high level as a conduction level.

[0175] In response to scan signals SC1(n) to SC4(n) and light emission control signals EM1(n) and EM2(n), the first transistor T1 to the fourth transistor T4 can all be turned off, and the fifth transistor T5 and the sixth transistor T6 can all be turned on.

[0176] Therefore, through the conducting fifth transistor T5 and sixth transistor T6, a current path can be formed from the terminal of the high-potential drive voltage EVDD to the terminal of the low-potential drive voltage EVSS. At this time, the drive transistor DT can be turned on according to the voltage of the second node N2 (i.e., the gate electrode of the drive transistor DT reflecting the data voltage Vdata), so that the drive current corresponding to the data voltage Vdata can be provided to the light-emitting diode OD, and the light-emitting diode OD can emit light.

[0177] Here, as described above, before the data writing period Tw, the sampling period Tsp can be set to be longer than the horizontal period, so that the threshold voltage (Vth) can be fully sampled and reflected in the voltage of the gate electrode of the driving transistor DT, thereby reducing or preventing the error component of the threshold voltage Vth.

[0178] Therefore, the influence of the error component of the threshold voltage Vth on the driving current generated in the light-emitting period Te can be reduced or eliminated, so that a driving current with improved compensation for the threshold voltage can be provided to the light-emitting diode OD.

[0179] Thus, by improving threshold voltage compensation, the light emission characteristics of the light-emitting diode OD can be improved, and the image quality characteristics of the display device 10 can be enhanced.

[0180] In the above embodiment, an example is given in which four different scan signals SC1 to SC4 and two different light emission control signals EM1 and EM2 are used to drive the pixel P of each horizontal line.

[0181] As another example, at least one of the scan signals SC1 to SC4 or at least one of the light emission control signals EM1 and EM2 can be omitted. This can be found in [reference needed]. Figure 9 and Figure 10 .

[0182] Figure 9 This is a timing diagram schematically illustrating a first modified example of a first embodiment of the present disclosure, showing the driving signals for driving pixels. Figure 10 This is a timing diagram schematically illustrating a second modified example of a first embodiment of the present disclosure, showing the driving signals for driving pixels.

[0183] Applied Figure 9 First modification example and Figure 10 The second modified example's driving signal pixel P can be with Figure 2 The pixel P shown is configured in the same way, and in this case, the fifth transistor T5 can be configured as a P-type transistor.

[0184] First, regarding the first modified example, refer to... Figure 9This can be omitted in the aforementioned implementation method (see...). Figure 4 The first light emission control signal EM1(n) is provided to the nth horizontal line, and alternatively, the first scan signal SC1 provided to subsequent horizontal lines can be used, for example, the first scan signal SC1(n+4) provided to the (n+4)th horizontal line. In other words, the first scan signal SC1(n+4) of the (n+4)th horizontal line can be applied to the P-type fifth transistor T5 instead of the first light emission control signal EM1(n).

[0185] Next, regarding the second modified example, please refer to... Figure 10 Similar to Figure 9 In a first modified example, the first scan signal SC1(n+4) of the (n+4)th horizontal line can be applied to the P-type fifth transistor T5 instead of the first light emission control signal EM1(n). Furthermore, in a second modified example, for the fourth transistor T4, the method described in the foregoing embodiment (see...) can be omitted. Figure 4 The fourth scan signal SC4(n) is provided to the nth horizontal line, and alternatively, the first scan signal SC1(n-4) of the (n-4)th horizontal line can be applied to the fourth transistor T4.

[0186] Thus, according to the first modified example, the first light emission control signal EM1 can be omitted, and according to the second modified example, the first light emission control signal EM1 and the fourth scan signal SC4 can be omitted. Therefore, in the gating drive section 210, the first light emission level SEM1 that generates the first light emission control signal EM1 can be omitted, or in addition, the fourth scan level SSC4 that generates the fourth scan signal SC4 can be omitted, thereby achieving a narrow bezel.

[0187] Further references are provided below. Figure 11 An example of the cross-sectional structure of the display panel 100 of this embodiment is described. Figure 11 This is a cross-sectional view schematically illustrating an example of the cross-sectional structure of a display panel according to a first embodiment of the present disclosure.

[0188] exist Figure 11 For ease of explanation, two thin-film transistors (TFTs) TFT1 and TFT2 are shown in pixel P within the display area AA. Here, TFT1, which is positioned relatively lower and closer to the substrate 101, is referred to as the first thin-film transistor TFT1, and this first thin-film transistor may be a polycrystalline silicon thin-film transistor. TFT2, which is positioned relatively higher and farther from the substrate 101, is referred to as the second thin-film transistor TFT2, and this second thin-film transistor may be an oxide thin-film transistor.

[0189] Meanwhile, the first thin-film transistor TFT1 can be a driving transistor ( Figure 2(DT), but not limited to this. Furthermore, the second thin-film transistor TFT2 can be the first to sixth transistors serving as switching thin-film transistors. Figure 2 One of T1 to T6, for example, connected to a storage capacitor ( Figure 2 The first transistor of Cst) Figure 2 (T1), but not limited to this.

[0190] The substrate 101 can be configured as, for example, a thin glass substrate (or glass film) or a plastic substrate (or plastic film) to achieve the flexible characteristics of the display panel 100.

[0191] Here, for example, if the substrate 101 is configured as a glass substrate, the substrate 101 may have a thickness of approximately 0.2 mm.

[0192] Meanwhile, for example, when the substrate 101 is configured as a plastic substrate, the substrate 101 may include at least one polyimide layer. In this embodiment, a substrate 101 composed of two polyimide layers is used as an example, namely a first polyimide layer 101a and a second polyimide layer 101b.

[0193] The first thin-film transistor (TFT) 1 may include a first semiconductor layer 105 disposed on a substrate 101, a first gate electrode 115 overlapping the semiconductor layer 105 and interposed therebetween with a first insulating layer 110, and a first source electrode 151 and a first drain electrode 152 located on a fourth insulating layer 145 above the first gate electrode 115. Here, the first semiconductor layer 105 may be formed of polysilicon, but is not limited thereto.

[0194] The first semiconductor layer 105 may include a central channel region and source and drain regions on both sides thereof. The first source electrode 151 and the first drain electrode 152 may be connected to the source and drain regions of the first semiconductor layer 105 through a first contact hole 156 and a second contact hole 157 formed in the insulating layers 110, 120, 125, 135 and 145 located below the first source electrode 151 and the first drain electrode 152.

[0195] The second insulating layer 120 can be formed on the first gate electrode 115 of the first thin film transistor TFT1.

[0196] The first interlayer insulating layer 125 can be formed on the second insulating layer 120. The second thin-film transistor TFT2 can be formed on the first interlayer insulating layer 125.

[0197] The second thin-film transistor TFT2 may include a second semiconductor layer 130 on a first interlayer insulating layer 125, a second gate electrode 140 overlapping the second semiconductor layer 130 and interposed therebetween with a third insulating layer 135, and a second source electrode 153 and a second drain electrode 154 located above the second gate electrode 140 on a fourth insulating layer 145. Here, the second semiconductor layer 130 may be formed of an oxide semiconductor, but is not limited thereto.

[0198] The second semiconductor layer 130 may include a central channel region and source and drain regions on both sides thereof. The second source electrode 153 and the second drain electrode 154 may be connected to the source and drain regions of the second semiconductor layer 130 through a third contact hole 158 and a fourth contact hole 159 formed in the insulating layers 135 and 145 located below the second source electrode 153 and the second drain electrode 154.

[0199] The second interlayer insulating layer (or the first planarization layer) 160 can be formed on the second thin-film transistor TFT2.

[0200] Here, the first insulating layer 110, the second insulating layer 120, the third insulating layer 135 and the fourth insulating layer 145 may be formed of inorganic insulating materials such as silicon nitride or silicon oxide, but are not limited thereto.

[0201] Furthermore, the first interlayer insulation layer 125 and the second interlayer insulation layer 160 may be formed of organic insulating materials such as photoacrylic or benzocyclobutene, but are not limited thereto.

[0202] The connection electrode 162 can be formed on the second interlayer insulating layer 160. The connection electrode 162 can be connected to the first source electrode 151 through the contact hole 161 formed in the second interlayer insulating layer 160.

[0203] A third interlayer insulating layer (or a second planarization layer) 163 may be formed on the connecting electrode 162. The third interlayer insulating layer 163 may be formed of an organic insulating material such as photoacrylic acid or benzocyclobutene, but is not limited thereto.

[0204] The light-emitting diode OD and the dam 165 can be formed on the third interlayer insulating layer 163.

[0205] A light-emitting diode (OD) may include an anode electrode (or a first electrode) 171, a light-emitting layer 172, and a cathode electrode (or a second electrode) 173.

[0206] The anode electrode 171 can be connected to the connection electrode 162 through a contact hole 164 formed in the third interlayer insulating layer 163.

[0207] The dam 165 can be set along the boundary of pixel P and can be formed to cover the edge of the anode electrode 171. The light-emitting layer 172 can be formed on the anode electrode 171 exposed through the opening of the dam 165.

[0208] The cathode electrode 173 can be formed on the light-emitting layer 172 and can be driven by a low potential voltage. Figure 2 (EVSS).

[0209] Encapsulation layer 180 may be formed on cathode electrode 173. Encapsulation layer 180 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. In this disclosure, by way of example, a structure of encapsulation layer 180 is described, wherein a first encapsulation layer 181, a second encapsulation layer 182, and a third encapsulation layer 183 are stacked in sequence.

[0210] A first encapsulation layer 181 may be formed on a substrate 101 on which a cathode electrode 173 is formed. A third encapsulation layer 183 may be formed on a substrate 101 on which a second encapsulation layer 182 is formed, and may be formed together with the first encapsulation layer 181 to surround the upper surface, lower surface, and side surface of the second encapsulation layer 182. The first encapsulation layer 181 and the third encapsulation layer 183 may minimize or prevent external moisture or oxygen from penetrating into the light-emitting diode (OD). The first encapsulation layer 181 and the third encapsulation layer 183 may be formed of an inorganic insulating material capable of low-temperature deposition, such as silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide.

[0211] The second encapsulation layer 182 can serve as a buffer layer to alleviate interlayer stress caused by bending of the display device 10 and to flatten the interlayer steps. The second encapsulation layer 182 can be formed on the substrate 101 on which the first encapsulation layer 181 is formed, using non-photosensitive organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon carbide (SiOC), or photosensitive organic insulating materials such as photoacrylic acid, but is not limited thereto. When the second encapsulation layer 182 is formed by inkjet printing, a dam DAM can be placed in the non-display area NA to reduce or prevent the liquid form of the second encapsulation layer 182 from spreading to the edge of the substrate 101. Compared to the second encapsulation layer 182, the dam DAM can be positioned closer to the edge of the substrate 101. The dam DAM reduces or prevents the second encapsulation layer 182 from spreading to the pad area with conductive pads on the outermost edge of the substrate 101.

[0212] The dam DAM can be designed to reduce or prevent the diffusion of the second encapsulation layer 182. However, if the second encapsulation layer 182 is formed during the process to exceed the height of the dam DAM, the second encapsulation layer 182, as an organic layer, will be exposed to the outside, making it easier for moisture and other substances to penetrate into the light-emitting element. To prevent this, 10 or more dam DAMs can be formed consecutively, but this is not a limitation.

[0213] The dam DAM can be formed simultaneously with the first interlayer insulation layer 125, the second interlayer insulation layer 160, and the third interlayer insulation layer 163. When the first interlayer insulation layer 125 is formed, the lower layer of the dam DAM can be formed together, and when the second interlayer insulation layer 160 and the third interlayer insulation layer 163 are formed, the upper layer of the dam DAM can be formed together, allowing the dam DAM to form a three-layer stacked structure. As another example, the dam DAM can be formed from one or both of the first interlayer insulation layer 125, the second interlayer insulation layer 160, and the third interlayer insulation layer 163.

[0214] Therefore, the dam DAM can be formed of the same material as the first interlayer insulation layer 125, the second interlayer insulation layer 160 and the third interlayer insulation layer 163, but is not limited thereto.

[0215] The dam DAM can be formed to overlap with the low-potential drive voltage line VSSL. For example, the low-potential drive voltage line VSSL can be formed in the layer below the area where the dam DAM is located in the non-display area NA.

[0216] A low-potential driving voltage line VSSL and a gated driving portion 210 configured in a GIP structure can be formed along the periphery of the display panel 100, and the low-potential driving voltage line VSSL can be located outside the gated driving portion 210. Furthermore, the low-potential driving voltage line VSSL can be connected to the cathode electrode 173 to apply a low-potential driving voltage EVSS. In the figures, the gated driving portion 210 is simply shown in planar and cross-sectional form, but it can be configured with the same structure as the first thin-film transistor TFT1 and / or the second thin-film transistor TFT2 in the display area AA.

[0217] A touch layer (or touch element layer) 190 may be disposed on the encapsulation layer 180. In the touch layer 190, a touch buffer layer 191 may be positioned between the touch sensor metal including touch electrode connection lines 192 and 194 and touch electrodes 195 and 196 and the cathode electrode 173 of the light-emitting diode OD.

[0218] The touch buffer layer 191 can prevent chemical solutions (developers, etchants, etc.) used in the manufacturing process of the touch sensor metal disposed on the touch buffer layer 191 or external moisture from penetrating into the light-emitting layer 172 containing organic materials. Therefore, the touch buffer layer 191 can reduce or prevent damage to the light-emitting layer 172, which is susceptible to chemical solutions or moisture.

[0219] According to the mutual capacitance-based touch sensor structure, touch electrodes 195 and 196 can be disposed on the touch buffer layer 191, and touch electrodes 195 and 196 can be arranged to cross each other.

[0220] Touch electrode connecting lines 192 and 194 can electrically connect touch electrodes 195 and 196. One of touch electrode connecting lines 192 and 194, and touch electrodes 195 and 196, can be located on different layers, with a touch insulating layer 193 interposed between them. Furthermore, one of touch electrode connecting lines 192 and 194, and the other of touch electrode connecting lines 192 and 194, can be located on different layers, with a touch insulating layer 193 interposed between them.

[0221] The touch electrode connecting lines 192 and 194 can be arranged to overlap with the embankment 165 to reduce or prevent a decrease in the orifice ratio, but are not limited thereto.

[0222] Meanwhile, a portion of touch electrodes 195 and 196 and a portion of touch electrode connection line 192 may extend along the top and side surfaces of the package layer 180 and the top and side surfaces of the dam DAM, and be electrically connected to the touch driving circuit via touch pads 198 and 199.

[0223] A portion of touch electrodes 195 and 196 and a portion of touch electrode connection line 192 can receive touch driving signals from the touch driving circuit and transmit them to touch electrodes 195 and 196, and can transmit touch sensing signals detected by touch electrodes 195 and 196 to the touch driving circuit.

[0224] In this regard, for example, the driver IC (e.g., data IC, etc.) of the data driver section 220, which includes touch driver circuitry, can be configured as COF type and connected to the non-display area NA of the substrate 101 of the display panel 100. In this case, one end of the touch pads 198 and 199 can be connected to the flexible circuit film on which the driver IC is mounted, so that signals can be transmitted.

[0225] Touch protection layer 197 may be disposed on touch electrodes 195 and 196. In the accompanying drawings, touch protection layer 197 is shown as being disposed only on touch electrodes 195 and 196, but is not limited thereto, and touch protection layer 197 may extend before or after the dam DAM to be disposed on touch electrode connection line 192.

[0226] In addition, the color filter can be disposed on the encapsulation layer 180. The color filter can be positioned on the touch layer 190, or positioned between the encapsulation layer 180 and the touch layer 190.

[0227] <Second Implementation Method>

[0228] Figure 12 This is a timing diagram schematically illustrating the driving signals for driving pixels according to a first example of a second embodiment of the present disclosure. Figure 13 This shows the use of Figure 12 A view of the operating state of elements within a pixel during the anode reset period when the drive signal is applied.

[0229] In the following description, detailed descriptions of components that are the same as or similar to those in the first embodiment described above may be omitted, or these descriptions may be provided briefly.

[0230] Similar to the first embodiment, in this embodiment, the sampling period Tsp of the threshold voltage (Vth) of the driving transistor DT can be set to a considerably long time separate from the data writing period Tw. Therefore, the threshold voltage Vth of the driving transistor DT can be sufficiently sampled during the sampling operation, reducing or preventing error components in the threshold voltage Vth that may occur during short-term sampling (such as horizontal periods). Thus, the threshold voltage compensation error can be reduced, and threshold voltage compensation can be enhanced.

[0231] Meanwhile, unlike the first embodiment, in this embodiment, an anode reset period Tar can be added after the data writing period Tw. This anode reset period resets the voltage at the anode electrode of the light-emitting diode OD. More specifically, the anode reset period Tar can be added between the data writing period Tw and the light-emitting period Te.

[0232] In this regard, you can refer to Figure 12 and Figure 13 The operation during the anode reset period Tar according to a first example of this embodiment is described.

[0233] The pixel P in this embodiment can have the same structure as the pixel P in the first embodiment.

[0234] In this embodiment, pixel P can be driven similarly to that in the first embodiment. In this regard, refer to... Figure 12The refresh frame FRr, which is the frame FR that performs the refresh operation, can be divided into a non-light-emitting period Tne and a light-emitting period Te.

[0235] Furthermore, during the non-light-emitting period Tne, the initialization period Ti, the sampling period Tsp, and the data writing period Tw can be executed sequentially. The operations in the initialization period Ti, the sampling period Tsp, and the data writing period Tw can be performed in the same manner as in the first embodiment, and their detailed descriptions can be omitted or provided briefly.

[0236] Furthermore, in this embodiment, after the data writing period Tw and before the light emission period Te, the anode reset period Tar can be defined as resetting the anode electrode of the light-emitting diode OD again.

[0237] Regarding the anode reset period Tar, refer to... Figure 12 and Figure 13 For example, the first scan signal SC1(n), the second scan signal SC2(n) and the fourth scan signal SC4(n) can have a low level as a cutoff level, the third scan signal SC3(n) can have a high level as a conduction level, and the first light emission control signal EM1(n) and the second light emission control signal EM2(n) can have a low level as a cutoff level.

[0238] Thus, during the anode reset period Tar, the third scan signal SC3(n) can have a high-level scan pulse P3_2. Simultaneously, the third scan signal SC3(n) can have a high-level scan pulse P3_1 before the anode reset period Tar, and this scan pulse P3_1 can be set to correspond to (or overlap with) the initialization period Ti, the sampling period Tsp, and the data writing period Tw. Here, for ease of explanation, the scan pulse P3_1 of the third scan signal SC3(n) set before the anode reset period Tar can be referred to as the first scan pulse P3_1, and the scan pulse P3_2 of the third scan signal SC3(n) set during the anode reset period Tar can be referred to as the second scan pulse P3_2.

[0239] In response to scan signals SC1(n) to SC4(n) and light emission control signals EM1(n) and EM2(n), the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 can be turned off, and the third transistor T3 can be turned on.

[0240] Therefore, the anode reset voltage Var can be provided to the first node N1 through the third transistor T3 in the on state, so that the anode electrode of the light-emitting diode OD can be reset.

[0241] As described above, during the anode reset period Tar, the anode reset voltage Var can be applied to the first node N1 connected to the first electrode of the storage capacitor Cst, and the second node N2 connected to the second electrode of the storage capacitor Cst can be in an electrically floating state.

[0242] After the anode reset period Tar is completed, the light emission period Te can continue. Similar to the first embodiment, during the light emission period Te, a drive current can be supplied to the light-emitting diode OD to perform the light emission operation.

[0243] Thus, in this embodiment, the anode reset operation that resets the voltage of the anode electrode of the light-emitting diode OD can be added after the data writing period Tw, and the light-emitting period Te can be set after the anode reset period Tar.

[0244] By performing an anode reset operation in this manner before the light-emitting operation, the voltage at the first node N1 to which the anode electrode of the LED OD is connected can be stably maintained at the anode reset voltage Var before the light-emitting operation. Therefore, the LED OD can emit light normally during the light-emitting period Te.

[0245] In this respect, the voltage of the first node N1 may not be maintained, but may fluctuate due to leakage current, etc., after data is written and before light emission. For example, the voltage of the first node N1 may increase. If the voltage of the first node N1 increases in this way, the light-emitting diode OD will light up rapidly when the light emission period Te begins, which may cause problems such as flickering.

[0246] However, in this embodiment, by setting the anode reset period Tar after data writing and before emission, the voltage of the first node N1 can be stably maintained at the anode reset voltage Var. Therefore, when the emission period Te begins, the light-emitting diode OD can emit light normally, thereby reducing or preventing image quality defects such as flicker caused by voltage fluctuations in the first node N1.

[0247] Meanwhile, in the first example of this embodiment, when the anode reset period Tar is additionally set, the third transistor T3 can be turned on, and the other transistors T1, T2, T4, T5 and T6 can be turned off.

[0248] Examples of driving methods different from the first example can be discussed below.

[0249] Figure 14 This is a timing diagram schematically illustrating a second example of a driving signal for driving a pixel according to a second embodiment of the present disclosure. Figure 15 This shows the use of Figure 14A view of the operating state of elements within a pixel during the anode reset period when the drive signal is applied.

[0250] Regarding the driving of pixel P during the anode reset period Tar in the second example of this embodiment, refer to... Figure 14 and Figure 15 The first scan signal SC1(n), the second scan signal SC2(n) and the fourth scan signal SC4(n) can have a low level as a cutoff level, the third scan signal SC3(n) can have a high level as a conduction level, the first light emission control signal EM1(n) can have a high level as a conduction level, and the second light emission control signal EM2(n) can have a low level as a cutoff level.

[0251] Thus, during the anode reset period Tar, the third scan signal SC3(n) can have a high-level scan pulse P3_2. Furthermore, during the anode reset period Tar, the first light emission control signal EM1(n) can have a high-level scan pulse.

[0252] In response to scan signals SC1(n) to SC4(n) and light emission control signals EM1(n) and EM2(n), the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 can be turned off, and the third transistor T3 and the fifth transistor T5 can be turned on.

[0253] Therefore, the anode reset voltage Var can be provided to the first node N1 through the third transistor T3 in the on state, thereby resetting the anode electrode of the light-emitting diode OD.

[0254] Furthermore, the high-potential drive voltage EVDD can be supplied to the fourth node N4 through the fifth transistor T5, which is in the on state. Therefore, the fourth node N4 can be pre-charged with the high-potential drive voltage EVDD.

[0255] As described above, during the anode reset period Tar, the anode reset voltage Var can be applied to the first node N1 connected to the first electrode of the storage capacitor Cst, and the second node N2 connected to the second electrode of the storage capacitor Cst can be in an electrically floating state.

[0256] After the anode reset period Tar is completed, the light emission period Te can continue. Similar to the first embodiment, during the light emission period Te, a drive current can be supplied to the light-emitting diode OD to perform the light emission operation.

[0257] Thus, similar to the first example, in the second example of this embodiment, the anode reset operation for resetting the voltage of the anode electrode of the light-emitting diode OD can be added after the data writing period Tw, and the light-emitting period Te can be set after the anode reset period Tar.

[0258] By performing an anode reset operation in this manner before the light-emitting operation, the voltage at the first node N1 to which the anode electrode of the LED OD is connected can be stably maintained at the anode reset voltage Var before the light-emitting operation. Therefore, the LED OD can emit light normally during the light-emitting period Te.

[0259] Furthermore, unlike the first example, in the second example of this implementation, the fifth transistor T5 can be driven into the on state during the anode reset period Tar to precharge the fourth node N4.

[0260] Figure 16 This is a timing diagram schematically illustrating the driving signals for driving pixels according to a third example of a second embodiment of the present disclosure. Figure 17 This shows the use of Figure 16 A view of the operating state of elements within a pixel during the anode reset period when the drive signal is applied.

[0261] Regarding the driving of pixel P during the anode reset period Tar in the third example of this embodiment, refer to... Figure 16 and Figure 17 The first scan signal SC1(n), the second scan signal SC2(n) and the fourth scan signal SC4(n) can have a low level as a cutoff level, the third scan signal SC3(n) has a high level as a conduction level, the first light emission control signal EM1(n) can have a low level as a cutoff level, and the second light emission control signal EM2(n) can have a high level as a conduction level.

[0262] Thus, during the anode reset period Tar, the third scan signal SC3(n) can have a high-level scan pulse P3_2. Furthermore, during the anode reset period Tar, the second light emission control signal EM2(n) can have a high-level scan pulse.

[0263] In response to scan signals SC1(n) to SC4(n) and light emission control signals EM1(n) and EM2(n), the first transistor T1, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 can be turned off, and the third transistor T3 and the sixth transistor T6 can be turned on.

[0264] Therefore, the anode reset voltage Var can be provided to the first node N1 through the third transistor T3 in the on state, thereby resetting the anode electrode of the light-emitting diode OD.

[0265] Furthermore, the sixth transistor T6, which is in the ON state, can short-circuit the fourth node N4 to the third node N3. Therefore, the fourth node N4 can be pre-charged with the voltage of the third node N3.

[0266] As described above, during the anode reset period Tar, the anode reset voltage Var can be applied to the first node N1 connected to the first electrode of the storage capacitor Cst, and the second node N2 connected to the second electrode of the storage capacitor Cst can be in an electrically floating state.

[0267] After the anode reset period Tar is completed, the light emission period Te can continue. Similar to the first embodiment, during the light emission period Te, a drive current can be supplied to the light-emitting diode OD to perform the light emission operation.

[0268] Thus, similar to the first example, in the third example of this embodiment, the anode reset operation for resetting the voltage of the anode electrode of the light-emitting diode OD can be added after the data writing period Tw, and the light-emitting period Te can be set after the anode reset period Tar.

[0269] By performing an anode reset operation in this manner before the light-emitting operation, the voltage at the first node N1 to which the anode electrode of the LED OD is connected can be stably maintained at the anode reset voltage Var before the light-emitting operation. Therefore, the LED OD can emit light normally during the light-emitting period Te.

[0270] Furthermore, unlike the first and second examples, in the third example of this implementation, the sixth transistor T6 can be driven into the on state during the anode reset period Tar to precharge the fourth node N4.

[0271] <Third Implementation Method>

[0272] Figure 18 This is a timing diagram schematically illustrating the driving signals for driving pixels according to a first example of a third embodiment of the present disclosure. Figure 19 This shows the use of Figure 18 A view of the operating state of elements within a pixel during the light-off period when the drive signal is applied.

[0273] In the following description, detailed descriptions of components that are the same as or similar to those in the first and second embodiments described above may be omitted or briefly enhanced.

[0274] Similar to the first and second embodiments, in this embodiment, the sampling period of the threshold voltage Vth of the driving transistor DT ( Figure 4 The Tsp can be set to match the data write period ( Figure 4 The threshold voltage Vth of the driving transistor DT is separated by a considerable amount of time. Therefore, the threshold voltage Vth of DT can be sufficiently sampled during the sampling operation, making it possible to reduce or prevent error components of the threshold voltage Vth that may occur during short-term sampling (such as horizontal periods). Thus, the compensation error of the threshold voltage can be reduced, and the threshold voltage compensation can be enhanced.

[0275] Meanwhile, in display devices, a light-off operation can be performed in some cases to turn off the light emission of the light-emitting diode (OD). In this regard, after data is written, a light-emitting operation can be performed, followed by a period of time during which the light emission is turned off, and then the light-emitting operation can be performed again. For example, the OD can be turned off during the blank period between adjacent frames to be in a non-light-emitting state.

[0276] In this regard, refer to Figure 18 and Figure 19 This can be used to describe the operation during the light-emitting off period Toff in the first example according to this embodiment.

[0277] exist Figure 18 For ease of explanation, the drive signals during the light-emitting period Te and the light-emitting off period Toff are shown as examples. Furthermore, as an example, the case where the first scan signal SC1(n) to the fourth scan signal SC4(n) are both at a low level (i.e., the low gate voltage VGL) during both the light-emitting period Te and the light-emitting off period Toff is shown.

[0278] In this embodiment, pixel P can be configured with the same structure as pixel P in the first or second embodiment.

[0279] In this embodiment, pixel P can be driven similarly to that in the first or second embodiment. In this regard, as described in the first or second embodiment, the refresh frame FRr, which is the frame FR performing the refresh operation, can be divided into non-light-emitting periods ( Figure 4 The Tne of the emission period and the emission period Te. Furthermore, during the non-emission period ( Figure 4 Within the Tne, initialization periods can be executed sequentially. Figure 4 Ti), sampling period ( Figure 4 Tsp) and data writing period ( Figure 4 (Tw). Furthermore, as in the second embodiment, an additional anode reset period can be provided ( Figure 12 Tar).

[0280] The operations during the initialization period, sampling period, data writing period, and anode reset period can be performed in the same manner as in the first or second embodiment, and their detailed descriptions can be omitted or provided briefly.

[0281] Furthermore, in this embodiment, for example, a light-off period Toff can be set after the light-emitting period Te or between adjacent light-emitting periods Te.

[0282] Regarding the light emission off period Toff, please refer to... Figure 18 and Figure 19 For example, the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) can all have a low level as a cutoff level, and the first light emission control signal EM1(n) and the second light emission control signal EM2(n) can all have a low level as a cutoff level.

[0283] In response to scan signals SC1(n) to SC4(n) and light emission control signals EM1(n) and EM2(n), the first transistor T1 to the sixth transistor T6 can all be turned off.

[0284] Therefore, through the fifth transistor T5 and the sixth transistor T6 which are in the off state, the terminals of the driving transistor DT and the high-potential driving voltage EVDD can be electrically disconnected from each other, so that no current path is formed, and thus the high-potential driving voltage EVDD is not supplied to the driving transistor DT.

[0285] Therefore, the driving transistor DT can be essentially turned off, so that no light-emitting current is generated. Consequently, no light-emitting current is supplied to the LED OD, and the LED OD can be turned off.

[0286] Thus, during the light-emitting off period Toff, the fifth transistor T5 and the sixth transistor T6 can be turned off, thereby disconnecting the drive current path and enabling the light-emitting diode OD to perform the light-emitting off operation. Since the light-emitting transistors T5 and T6 are driven in the off state, the drive current path is doubly blocked, thereby ensuring the reliability of the light-emitting off operation.

[0287] After the emission-off period Toff is completed, the emission-off period Te can start again.

[0288] Meanwhile, in the first example of this embodiment, when the light emission off period Toff is set, both the fifth transistor T5 and the sixth transistor T6 that control the light emission can be turned off.

[0289] Examples of driving methods different from the first example can be discussed below.

[0290] Figure 20 This is a timing diagram schematically illustrating a second example of a driving signal for driving a pixel according to a third embodiment of the present disclosure. Figure 21 This shows the use of Figure 20 A view of the operating state of elements within a pixel during the light-off period when the driving signal is applied.

[0291] Regarding the driving of pixel P during the light-off period Toff in the second example of this embodiment, refer to... Figure 20 and Figure 21 The first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n) and the fourth scan signal SC4(n) can all have a low level as the cutoff level, the first light emission control signal EM1(n) can have a high level as the conduction level (i.e., select the high voltage VEH), and the second light emission control signal EM2(n) can have a low level as the cutoff level.

[0292] In response to scan signals SC1(n) to SC4(n) and light emission control signals EM1(n) and EM2(n), the first transistor T1 to the fourth transistor T4 and the sixth transistor T6 can all be turned off, and the fifth transistor T5 can be turned on.

[0293] Therefore, through the sixth transistor T6 in the off state, the terminals of the driving transistor DT and the high-potential driving voltage EVDD can be electrically disconnected from each other, so that no current path is formed, and thus the high-potential driving voltage EVDD is not supplied to the driving transistor DT.

[0294] Therefore, the driving transistor DT can be essentially turned off, so that no light-emitting current is generated. Consequently, no light-emitting current is supplied to the LED OD, and the LED OD can be turned off.

[0295] Thus, during the light-emitting off period Toff, the sixth transistor T6 can be turned off, thereby disconnecting the drive current path and enabling the light-emitting diode OD to perform the light-emitting off operation.

[0296] After the emission-off period Toff is completed, the emission-off period Te can be executed again.

[0297] Thus, unlike the first example, in the second example of this implementation, the fifth transistor T5 can remain in the on state, and the sixth transistor T6 can switch to the off state. In this case, the first light-emitting control signal EM1(n) applied to the fifth transistor T5 does not generate a toggle that switches the voltage level during the light-emitting off period Toff, thereby reducing the increase in power consumption due to signal toggle. Therefore, compared to the first example, the power consumption during the light-emitting off operation in the second example can be reduced, resulting in low-power drive.

[0298] Figure 22 This is a timing diagram schematically illustrating a third example of a driving signal for driving a pixel according to a third embodiment of the present disclosure. Figure 23 This shows the use of Figure 22 A view of the operating state of elements within a pixel during the light-off period when the driving signal is applied.

[0299] Regarding the driving of pixel P during the light-off period Toff in the third example of this implementation, refer to... Figure 22 and Figure 23 The first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n) and the fourth scan signal SC4(n) can all have a low level as the cutoff level, the first light emission control signal EM1(n) can have a low level as the cutoff level, and the second light emission control signal EM2(n) can have a high level as the conduction level (i.e., the high voltage VEH is selected).

[0300] In response to scan signals SC1(n) to SC4(n) and light emission control signals EM1(n) and EM2(n), the first transistor T1 to the fifth transistor T5 can all be turned off, and the sixth transistor T6 can be turned on.

[0301] Therefore, through the fifth transistor T5 in the off state, the terminals of the driving transistor DT and the high-potential driving voltage EVDD can be electrically disconnected from each other, so that no current path is formed, and thus the high-potential driving voltage EVDD is not supplied to the driving transistor DT.

[0302] Therefore, the driving transistor DT can be essentially turned off, so that no light-emitting current is generated. Consequently, no light-emitting current is supplied to the LED OD, and the LED OD can be turned off.

[0303] Thus, during the light-emitting off period Toff, the fifth transistor T5 can be turned off, thereby disconnecting the drive current path and enabling the light-emitting diode OD to perform the light-emitting off operation.

[0304] After the emission-off period Toff is completed, the emission-off period Te can start again.

[0305] Thus, unlike the first and second examples, in this third example of the embodiment, the sixth transistor T6 can remain in the on state, and the fifth transistor T5 can switch to the off state. In this case, the second light-emitting control signal EM2(n) applied to the sixth transistor T6 does not generate a voltage level transition during the light-emitting off period Toff, thereby reducing the increase in power consumption due to signal transitions. Therefore, compared to the first example, the power consumption during the light-emitting off operation in the third example can be reduced, resulting in low-power operation.

[0306] <Fourth Implementation Method>

[0307] Figure 24 This is a view schematically illustrating an example of pixels according to a fourth embodiment of the present disclosure. Figures 25 to 28 This is a view showing the operational state of elements within a pixel during the initialization period, sampling period, data writing period, and emission period when driven according to the fourth embodiment of this disclosure.

[0308] In the following description, detailed descriptions of components that are the same as or similar to those in the first embodiment described above may be omitted or provided briefly.

[0309] Similar to the first embodiment, in this embodiment, the sampling period of the threshold voltage Vth of the driving transistor DT ( Figure 4 The Tsp can be set to match the data write period ( Figure 4 The threshold voltage Vth of the driving transistor DT is separated by a considerable amount of time. Therefore, the threshold voltage Vth of DT can be sufficiently sampled during the sampling operation, making it possible to reduce or prevent error components of the threshold voltage Vth that may occur during short-term sampling (such as horizontal periods). Thus, the compensation error of the threshold voltage can be reduced, and the threshold voltage compensation can be enhanced.

[0310] Meanwhile, unlike the first embodiment, in the pixel P of this embodiment, the sixth transistor T6, to which the second light emission control signal EM2(n) is applied, can be configured to be connected between the driving transistor DT and the light emission diode OD.

[0311] In this respect, the sixth transistor T6 may include a second electrode (or drain electrode) connected to the driving transistor DT at the third node N3, a first electrode (or source electrode) connected to the light-emitting diode OD at the first node N1, and a gate electrode that receives the second light-emitting control signal EM2(n).

[0312] Using the sixth transistor T6 arranged as described above, the second electrode of the driving transistor DT can be connected to the fourth node N4.

[0313] The pixel P configured as described above can be driven similarly to the first embodiment. For example, during non-light-emitting periods ( Figure 4 Within the Tne, initialization periods can be executed sequentially. Figure 4 Ti), sampling period ( Figure 4 Tsp) and data writing period ( Figure 4 (Tw), followed by the luminescent period ( Figure 4 (Te).

[0314] In this regard, refer to Figure 25 For example, during the initialization period, in response to the scan signals SC1(n) to SC4(n) and the light emission control signals EM1(n) and EM2(n), the first transistor T1, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 can be turned on, and the second transistor T2 and the sixth transistor T6 can be turned off.

[0315] Therefore, the anode electrode of the light-emitting diode OD can be initialized, i.e., the anode reset can be performed. Furthermore, the gate electrode voltage of the driving transistor DT can be initialized, and the voltage stored in the storage capacitor Cst and the voltage stored in the pump capacitor Ca can also be initialized.

[0316] Next, refer to Figure 26 During the sampling period, in response to the scan signals SC1(n) to SC4(n) and the light emission control signals EM1(n) and EM2(n), the first transistor T1, the third transistor T3, the fourth transistor T4 and the sixth transistor T6 can be turned on, and the second transistor T2 and the fifth transistor T5 can be turned off.

[0317] Therefore, through the first transistor T1 and the sixth transistor T6 in the on state, the driving transistor DT can achieve a diode connection state, wherein the gate electrode and drain electrode of the driving transistor DT are short-circuited. At this time, the third transistor T3 can be turned on, so a current path can be formed along the third transistor T3, the driving transistor DT, the sixth transistor T6, and the first transistor T1.

[0318] Therefore, the anode reset voltage Var and the threshold voltage Vth can be used to charge and store in the storage capacitor Cst at the second node N2, and the gate electrode of the driving transistor DT is connected to this second node.

[0319] The sampling period can be set to a considerably long time separate from the data writing period, so that the threshold voltage Vth of the driving transistor DT can be fully sampled during the sampling operation.

[0320] Therefore, the error component of the threshold voltage Vth that may occur during short-term sampling (such as horizontal time intervals) can be reduced or prevented, thereby reducing the error of threshold voltage compensation and enhancing threshold voltage compensation, thus improving the image quality of the display device.

[0321] Next, refer to Figure 27 During the data writing period, in response to the scan signals SC1(n) to SC4(n) and the light emission control signals EM1(n) and EM2(n), the first transistor T1, the second transistor T2 and the third transistor T3 can be turned on, and the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 can be turned off.

[0322] Therefore, the data voltage Vdata can be supplied to the fifth node N5 through the second transistor T2 in the on state, and the data voltage Vdata can be reflected to the fourth node N4 through the pump capacitor Ca. The voltage reflected at the fourth node N4 can be transmitted to the second node N2 through the first transistor T1, and can be reflected in the voltage of the second node N2, that is, reflected in the voltage of the gate electrode of the driving transistor DT.

[0323] Next, refer to Figure 28 After the data writing period Tw is completed, a drive current can be supplied to the light-emitting diode OD during the light-emitting period Te to perform the light-emitting operation.

[0324] In response to scan signals SC1(n) to SC4(n) and light emission control signals EM1(n) and EM2(n), the first transistor T1 to the fourth transistor T4 can all be turned off, and the fifth transistor T5 and the sixth transistor T6 can all be turned on.

[0325] Therefore, through the conducting fifth transistor T5 and sixth transistor T6, a current path can be formed from the terminal of the high-potential drive voltage EVDD to the terminal of the low-potential drive voltage EVSS. At this time, the drive transistor DT can be turned on according to the voltage of the second node N2 (i.e., the gate electrode of the drive transistor DT reflecting the data voltage Vdata), so that the drive current corresponding to the data voltage Vdata can be provided to the light-emitting diode OD, and the light-emitting diode OD can emit light.

[0326] <Fifth Implementation Method>

[0327] Figure 29 This is a view schematically illustrating an example of pixels according to a fifth embodiment of the present disclosure.

[0328] In the following description, detailed descriptions of components that are the same as or similar to those in the first embodiment described above may be omitted or provided briefly.

[0329] Similar to the first embodiment, in this embodiment, the sampling period of the threshold voltage Vth of the driving transistor DT ( Figure 4 The Tsp can be set to match the data write period ( Figure 4 The threshold voltage Vth of the driving transistor DT is separated by a considerable amount of time. Therefore, the threshold voltage Vth of DT can be sufficiently sampled during the sampling operation, making it possible to reduce or prevent error components of the threshold voltage Vth that may occur during short-term sampling (such as horizontal periods). Thus, the compensation error of the threshold voltage can be reduced, and the threshold voltage compensation can be enhanced.

[0330] Furthermore, unlike the first embodiment, in this embodiment, the driving transistor DT in pixel P can be configured as a P-type transistor. Therefore, the circuit structure of pixel P in this embodiment can have an inverted form compared to the circuit structure of pixel P in the first embodiment.

[0331] In this regard, for example, the P-type driving transistor DT can be connected to the light-emitting diode OD at the first node N1, and more specifically, to the cathode electrode (or first electrode) of the light-emitting diode OD. In this case, the anode electrode (or second electrode) of the light-emitting diode OD can be configured to receive a high-potential driving voltage EVDD.

[0332] Meanwhile, the first transistor T1 to the sixth transistor T6 within pixel P can be configured as N-type transistors, but are not limited to this.

[0333] In this case, the connection relationship between the driving transistor DT, the first transistor T1 to the sixth transistor T6, the storage capacitor Cst and the pump capacitor Ca can be similar to the connection relationship in the first embodiment.

[0334] For example, the first transistor T1 can be connected between the second node N2 and the fourth node N4. The second transistor T2 can be connected between the fifth node N5 and the data line DL. The fourth transistor T4 can be connected between the fifth node N5 and the reference voltage line VrefL. The third transistor T3 can be connected between the first node N1 and the reset voltage line VarL.

[0335] The fifth transistor T5 can be connected to the fourth node N4 and can receive the low-potential drive voltage EVSS. The sixth transistor T6 can be connected between the third node N3 and the fourth node N4.

[0336] The storage capacitor Cst can be connected between the first node N1 and the second node N2. The pump capacitor Ca can be connected between the fourth node N4 and the fifth node N5.

[0337] As described above, in embodiments of this disclosure, the sampling period of the threshold voltage of the driving transistor can be set to be a considerably long time separate from the data writing period.

[0338] Therefore, the threshold voltage of the driving transistor can be fully sampled during the sampling operation, which can reduce or prevent error components of the threshold voltage that may occur when sampling for short periods of time (such as horizontal periods).

[0339] Therefore, the error of threshold voltage compensation can be reduced, thus improving threshold voltage compensation, and thus enhancing the image quality of the display device.

[0340] Furthermore, an anode reset period can be added after the data writing period to reset the voltage at the anode electrode of the LED. Therefore, the anode reset voltage can be maintained stably, allowing the LED to emit light normally during the light-emitting period.

[0341] Furthermore, during the light-emitting off period, at least one of the two transistors controlling light emission can be turned off. Here, when both transistors are driven in the off state, the path of the drive current can be doubly blocked, thereby ensuring the reliability of the light-emitting off operation. Additionally, when either of the two transistors is driven in the off state, the increase in power consumption due to signal transitions applied to the on transistor can be reduced, thus achieving low-power operation.

[0342] It will be apparent to those skilled in the art that various modifications and alterations can be made to this disclosure without departing from the technical spirit or scope thereof. Therefore, this disclosure is intended to cover such modifications and alterations, provided they fall within the scope of the appended claims and their equivalents.

[0343] Cross-references to related applications

[0344] This application claims priority to Korean Patent Application No. 10-2024-0165138, filed in Korea on November 19, 2024, the entire contents of which are incorporated herein by reference as if they were set forth herein.

Claims

1. A display device, the display device comprising: A display panel, the display panel comprising pixels; as well as The pixel contains a light-emitting diode, multiple transistors, a first capacitor, and a second capacitor, wherein the multiple transistors, the first capacitor, and the second capacitor are configured to be electrically connected to the light-emitting diode. The plurality of transistors include: A driving transistor, wherein the driving transistor is connected to the anode electrode of the light-emitting diode at a first node; A first transistor is connected between a second node and a fourth node, and the gate electrode of the driving transistor is connected to the second node; The second transistor is connected between the data line and the fifth node; A third transistor is connected to the first node and is configured to receive an anode reset voltage; A fourth transistor, connected to the fifth node, and configured to receive a reference voltage; A first light-emitting control transistor, connected to the fourth node, and configured to receive a high-potential drive voltage; and A second light-emitting control transistor is connected to the fourth node, and the second light-emitting control transistor is connected to the driving transistor at the third node. The first capacitor is connected between the first node and the second node, and the second capacitor is connected between the fourth node and the fifth node.

2. The display device according to claim 1, wherein, During the sampling period for sampling the threshold voltage of the driving transistor, the first transistor, the third transistor, the fourth transistor, and the second light-emitting control transistor are configured to be turned on, and the second transistor and the first light-emitting control transistor are configured to be turned off.

3. The display device according to claim 2, wherein, During the data writing period following the sampling period, the first transistor and the second transistor are configured to be turned on, and the fourth transistor, as well as the first light-emitting control transistor and the second light-emitting control transistor, are configured to be turned off.

4. The display device according to claim 3, wherein, During the data writing period, the third transistor is configured to be turned on.

5. The display device according to claim 2, wherein, During the initialization period prior to the sampling period, the first transistor, the third transistor, the fourth transistor, and the first light-emitting control transistor are configured to be turned on, and the second transistor and the second light-emitting control transistor are configured to be turned off.

6. The display device according to claim 3, wherein, During the anode reset period following the data write period, the third transistor is configured to be turned on.

7. The display device according to claim 6, wherein, During the anode reset period, the first transistor, the second transistor, the fourth transistor, the first light-emitting control transistor, and the second light-emitting control transistor are configured to be off.

8. The display device according to claim 6, wherein, During the anode reset period, the first light-emitting control transistor is configured to be turned on, and the first transistor, the second transistor, the fourth transistor, and the second light-emitting control transistor are configured to be turned off.

9. The display device according to claim 6, wherein, During the anode reset period, the second light-emitting control transistor is configured to be turned on, and the first transistor, the second transistor, the fourth transistor, and the first light-emitting control transistor are configured to be turned off.

10. The display device according to claim 3, wherein, During the light emission period following the data writing period, the first to fourth transistors are configured to be off, and the first and second light emission control transistors are configured to be on.

11. The display device according to claim 6, wherein, During the light emission period following the anode reset period, the first to fourth transistors are configured to be off, and the first and second light emission control transistors are configured to be on.

12. The display device according to claim 10, wherein, During the light-emitting off period following the light-emitting period, at least one of the first light-emitting control transistor and the second light-emitting control transistor is configured to be off.

13. A display device, the display device comprising: A display panel, the display panel comprising pixels; The light-emitting diodes in the pixel; A driving transistor, wherein the driving transistor is connected to the anode electrode of the light-emitting diode at a first node; A first transistor is connected between a second node and a fourth node, and the gate electrode of the driving transistor is connected to the second node; The second transistor is connected between the data line and the fifth node; A third transistor is connected to the first node and is configured to receive an anode reset voltage; A fourth transistor, connected to the fifth node, and configured to receive a reference voltage; A first light-emitting control transistor is connected to the fourth node, and the first light-emitting control transistor is connected to the driving transistor at the third node; A storage capacitor is connected between the first node and the second node; as well as A pump capacitor is connected between the fourth node and the fifth node. During the sampling period, the anode reset voltage and the threshold voltage of the driving transistor are configured to be sampled and reflected in the second node, and During the data writing period following the sampling period, the data voltage is configured to be reflected in the second node.

14. The display device of claim 13, further comprising a second light-emitting control transistor connected to the fourth node, and the second light-emitting control transistor being configured to receive a high-potential drive voltage. in, During the sampling period, the first transistor, the third transistor, the fourth transistor, and the first light-emitting control transistor are configured to be turned on, and the second transistor and the second light-emitting control transistor are configured to be turned off.

15. The display device according to claim 14, wherein, During the data writing period, the first transistor, the second transistor, and the third transistor are configured to be turned on, and the fourth transistor, the first light-emitting control transistor, and the second light-emitting control transistor are configured to be turned off.

16. The display device according to claim 13, wherein, During the anode reset period following the data write period, the third transistor is configured to be turned on, and the anode reset voltage is provided to the first node.

17. The display device according to claim 14, wherein, During the light emission period following the data writing period, the first to fourth transistors are configured to be off, and the first and second light emission control transistors are configured to be on.

18. The display device according to claim 17, wherein, During the light-emitting off period following the light-emitting period, at least one of the first light-emitting control transistor and the second light-emitting control transistor is configured to be off.

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