Controller of solid state disk and peak current control method

Abstract

The invention discloses a controller of a solid state disk and a peak current control method. According to the controller provided by the embodiment of the invention, recent current peak value data, temperature and the state of the flash memory particles are fused to form multi-dimensional characteristic data, and hardware model reasoning is performed on the basis, so that the power consumption situation of the current flash memory system is accurately judged, and the situation that a current peak value exceeds the standard due to issuing of a flash memory operation command is avoided.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, specifically to a controller for a solid-state drive and a peak current control method. Background Technology

[0002] High-performance solid-state drives such as Figure 1 As shown, a parallel architecture with multiple channels and multiple flash memory dies is commonly used to overcome the performance bottleneck of single channels and single flash memory dies, and to achieve a significant increase in throughput. However, when flash memory dies perform operations such as read, write, and erase, they generate dynamic and intermittent peak currents, with the peak current intensity being higher and the duration being more concentrated during write and erase operations.

[0003] When the current peaks of multiple flash memory chips overlap over time, the total instantaneous current of the entire drive can easily exceed the maximum supply capacity of the system power supply (i.e., the peak current threshold I_max). This problem can directly trigger a chain of risks: at best, it can cause a drop in the system power supply voltage, resulting in a decrease in the stability of the SSD; at worst, it can trigger data transmission errors, or even activate the hardware thermal protection mechanism to force frequency reduction, ultimately severely restricting the SSD's sustained high-performance output capability and long-term operational reliability.

[0004] What makes things even more complicated is that the advanced operating modes introduced by modern solid-state drives to improve performance, as well as the changes in the physical characteristics of NAND itself, make the prediction and control of peak current extremely complex.

[0005] 1) Uncertainty of cache operations: Although the operation instructions for commands such as cache programming and cache read have been issued, the actual data transmission and peak current consumption depend on the readiness status of the flash memory array. The actual effective time has a significant random delay and cannot be accurately predicted by traditional static schedulers.

[0006] 2) Dynamic nature of operation interruption and resumption: The suspend and resume mechanism allows high-priority operations (such as Read) to interrupt ongoing low-priority operations (such as Program / Erase). This dynamic suspend and resume behavior completely breaks the fixed-duration current waveform model, rendering peak shifting schemes based on fixed phase offsets completely ineffective;

[0007] 3) Inherent differences in device characteristics: Physical factors such as the number of programming / erase cycles and word line distribution in different physical blocks can cause the same type of operation to produce drastically different current intensities and waveform characteristics on different flash memory chips, or even on different physical blocks of the same flash memory chip. Relying on a single, static flash memory power consumption model cannot capture these dynamic differences at this granular level.

[0008] Existing control schemes are mostly based on static models and fixed strategies, which are completely unable to cope with the above-mentioned complexity and uncertainty, and lack the ability to perceive and adapt to changes in actual working conditions. Summary of the Invention

[0009] To address the aforementioned issues, this disclosure proposes a controller for a solid-state drive and a peak current control method.

[0010] In a first aspect, embodiments of this disclosure provide a controller for a solid-state drive (SSD), the SSD further comprising a plurality of flash memory chips coupled to the controller, the controller comprising:

[0011] The main control logic and command scheduler are used to initiate an execution consultation request before issuing a flash memory operation command, and decide whether to issue the flash memory operation command immediately or delay it based on the feedback decision results. The execution consultation request includes command information of the flash memory operation command to be issued.

[0012] The current monitoring unit is used to record the instantaneous peak current actually generated by the multiple flash memory chips after the flash memory operation command is issued, and to obtain the recent peak current data.

[0013] The flash memory status tracking unit is used to acquire information on flash memory operation commands currently being prepared for issuance to the multiple flash memory chips and flash memory operation commands that have already been issued to the multiple flash memory chips, and to obtain status data of the multiple flash memory chips;

[0014] The peak current control module is used to respond to the execution consultation request by performing model reasoning based on the information of the currently prepared and issued flash operation commands on the plurality of flash memory chips, the status data of the plurality of flash memory chips, the recent current peak data, and the command information in the execution consultation request, in order to predict whether issuing the flash operation command will cause the current peak of the plurality of flash memory chips to exceed the limit, thereby generating a decision result of allowing or refusing to issue the command.

[0015] In some embodiments, the controller further includes:

[0016] The temperature sensor interface is used to periodically collect temperature data from the temperature sensor of the controller and the flash memory chip, and the peak current control module uses the temperature data to perform inference.

[0017] In some embodiments, the controller further includes:

[0018] The learning and updating logic unit is used to update the model parameters in the peak current control module online based on the deviation between the instantaneous peak current obtained after the flash memory operation command is issued and the prediction result.

[0019] In some embodiments, the peak current control module includes:

[0020] The feature extraction and construction unit is used to construct an input feature vector based on the information of the flash operation commands currently to be issued and already issued on the multiple flash memory chips, the flash command statistics, the recent current peak data, and the command information in the execution consultation request;

[0021] A hardware inference engine is used to perform forward propagation calculations based on the input feature vector and pre-stored model parameters to generate the decision result;

[0022] The main control logic unit is used to coordinate the feature extraction and construction unit and the hardware inference engine, and to return the decision result to the main control logic and command scheduler.

[0023] In some embodiments, the feature extraction and construction unit classifies and encodes the information of the currently prepared and issued flash memory operation commands on the plurality of flash memory chips, the flash memory command statistics, and the recent current peak data.

[0024] In some embodiments, the hardware inference engine includes a multiply-accumulate array and activation function units.

[0025] In some embodiments, the main control logic and command scheduler include:

[0026] The command queue management unit is used to manage the flash memory operation commands to be issued for the multiple flash memory chips through multiple queues;

[0027] The scheduling arbitration unit is used to retrieve multiple flash memory operation commands in parallel from the multiple queues, select one flash memory operation command from them according to a predetermined strategy, send the execution consultation request to the peak current control module based on the selected flash memory operation command, and decide whether to issue the flash memory operation command immediately or delay it based on the decision result.

[0028] In some embodiments, the main control logic and command scheduler further include:

[0029] The delay / retry queue management unit is used to manage flash memory operation commands that have been rejected through multiple queues, and to resubmit the commands to the queue in the command queue management unit after a delay period or after detecting a change in the flash memory status.

[0030] In some embodiments, the learning and updating logic unit is configured to be triggered periodically, triggered when an error exceeds a threshold, or triggered by changes in environmental characteristics, or one or more of these triggers.

[0031] Secondly, embodiments of this disclosure provide a method for controlling the peak current of a solid-state drive, comprising:

[0032] Receive an execution consultation request, the execution consultation request containing command information of flash memory operation commands;

[0033] Based on the information of the flash operation commands currently being prepared and already issued on the multiple flash memory chips, flash command statistics, recent current peak data, and command information in the execution consultation request, model reasoning is performed to predict whether issuing the flash operation command will cause the current peak of the multiple flash memory chips to exceed the limit, thereby generating a decision result of allowing or refusing to issue the command.

[0034] Send the decision result to drive the flash memory operation command to be issued immediately or delayed;

[0035] After the command is issued, the instantaneous peak current actually generated by the multiple flash memory chips is recorded, and the recent peak current data is obtained.

[0036] The parameters of the machine learning model are updated online based on the deviation between the actual peak current and the predicted result.

[0037] In summary, the embodiments disclosed herein achieve refined peak current control with minimal overhead through an innovative "multi-source sensing + hardware inference" architecture, effectively resolving the core contradiction between performance, power consumption, and reliability in high-performance solid-state drive design. Attached Figure Description

[0038] The above and other objects, features and advantages of the present disclosure will become clearer from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0039] Figure 1 This is a schematic block diagram of a solid-state drive controller provided in an embodiment of this disclosure;

[0040] Figure 2 This is a schematic block diagram of a solid-state drive controller provided in an embodiment of this disclosure;

[0041] Figure 3 yes Figure 2A schematic block diagram of the main control logic and command scheduler in the system;

[0042] Figure 4 yes Figure 2 A schematic block diagram of the hardware inference engine in the diagram;

[0043] Figure 5 This is a schematic flowchart of the peak current control method provided in the embodiments of this disclosure. Detailed Implementation

[0044] The following description of embodiments of the present disclosure is based on examples, but the embodiments of the present disclosure are not limited to these embodiments. In the detailed description of the embodiments of the present disclosure below, certain specific details are described in detail. Those skilled in the art can fully understand the embodiments of the present disclosure even without these detailed descriptions. To avoid obscuring the essence of the embodiments of the present disclosure, well-known methods, processes, and flows are not described in detail. Furthermore, the accompanying drawings are not necessarily drawn to scale.

[0045] The flowcharts and block diagrams in the accompanying drawings illustrate possible system frameworks, functions, and operations of the systems, methods, and apparatuses according to embodiments of this disclosure. The blocks in the flowcharts and block diagrams may represent a module, program segment, or simply a piece of code. These modules, program segments, and code are all executable instructions used to implement a specified logical function. It should also be noted that the executable instructions implementing the specified logical function can be recombined to generate new modules and program segments. Therefore, the blocks and their order in the accompanying drawings are only used to better illustrate the processes and steps of the embodiments and should not be construed as limiting the invention itself.

[0046] Flash Translation Layer: A core software / firmware component in flash storage devices such as solid-state drives (SSDs) that manages the unique attributes of NAND flash memory (such as "offsite updates", "garbage collection", "wear leveling") and simulates it as a block device that can be directly read and written by address like a traditional hard drive.

[0047] Figure 2 This is a schematic block diagram of a solid-state drive controller provided in an embodiment of this disclosure.

[0048] The Flash Translation Layer (FTL) 201 breaks down host commands received from the host interface 204 into flash operation commands and maps logical addresses to physical addresses. Each flash operation command is for reading, writing, or erasing a fixed allocation unit (e.g., 4K) on the same flash memory chip.

[0049] The main control logic and command scheduler 203 manages and schedules flash memory operation commands, and initiates an execution consultation request before issuing a flash memory operation command. The execution consultation request contains the command information of the flash memory operation command, and decides whether to issue the flash memory operation command immediately or delay it based on the feedback decision results.

[0050] The flash memory status tracking unit 207 acquires real-time information on flash memory operation commands currently being prepared for issuance to each flash memory chip and flash memory operation commands already issued to each flash memory chip, and obtains the status data of each flash memory chip. The status data of each flash memory chip includes, but is not limited to: physical location of bad blocks and word lines, the number of program / erase operations (aging level) for each physical block / physical page, and the number of read operations. In actual operation, the flash memory operation commands currently being prepared for issuance to multiple flash memory chips are cached in different buffers or queues according to the flash memory chips. Before each flash memory operation command is issued, its command information and issuance time are recorded. At the same time, after each flash memory operation command is executed, its completion time is recorded. Then, information such as the number of program / erase operations (aging level) and the number of read operations are obtained by statistics.

[0051] The current monitoring unit 208 records the instantaneous peak current actually generated by multiple flash memory chips after the flash memory operation command is issued, and obtains the recent peak current data.

[0052] In response to the execution consultation request, the peak current control module 202 performs model reasoning based on information about the currently prepared and issued flash operation commands on multiple flash memory chips, the status data of the flash memory chips, recent current peak data, and the command information in the execution consultation request, in order to predict whether issuing a flash operation command will cause the current peak of multiple flash memory chips to exceed the limit, thereby generating a decision result of allowing or refusing to issue the command.

[0053] The storage medium controller 205 receives the flash memory operation commands sent from it, generates timing signals that conform to the flash memory protocol, and drives the flash memory chips to perform specific operations.

[0054] As shown in the figure, the controller also includes a temperature sensor interface 206 for collecting the main control temperature of controller 1. Furthermore, the controller periodically sends data to... Figure 1 Read temperature commands are sent to flash memory chips 0 through N to obtain temperature data for each chip. This temperature data is also provided to the machine learning model of the peak current control module 202 for model training and inference.

[0055] The learning and updating logic unit 209 is the core of the online self-learning function. It updates the model parameters in the peak current control module online based on the deviation between the instantaneous peak current and the prediction result after the flash memory operation command is issued. The system can configure the triggering mode of the learning and updating logic unit 209, including periodic triggering, error exceeding threshold triggering, and environmental feature change triggering. Error exceeding threshold triggering starts a lightweight online learning algorithm (such as incremental learning based on stochastic gradient descent) when a large prediction deviation is detected or a specific triggering condition is met. This algorithm updates the model parameters using the latest actual data and writes the optimized parameters back to the memory storing the model parameters, completing the model's self-iteration.

[0056] In one embodiment, a recent error window is maintained. When the error is consistently high or accumulates to a certain threshold, an online learning process is automatically triggered. The learning process uses the latest N sets of data (stored in a small cache) to perform one or more gradient descent iterations to generate a set of fine-tuned model parameters (ΔW, Δb).

[0057] As shown in the figure, the peak current control module 202 also includes a main control logic unit 2021, a hardware inference engine 2022, and a feature extraction and construction unit 2023.

[0058] The feature extraction and construction unit 2023 constructs an input feature vector in real time when a flash memory operation command arrives. This input feature vector is designed to accurately describe the current "power consumption situation." In some implementation examples, the input feature vector mainly includes:

[0059] ● The encoding of the current operation type (Read, Program, Erase, Idle) performed by each flash memory chip;

[0060] ● The duration of the current operation on each flash memory chip is a core feature used to infer the current phase (rising edge, peak, falling edge, idle) of each operation.

[0061] ● The operation type of the newly arrived flash memory operation command;

[0062] ●Average number of program / erase cycles (aging degree) of the physical block corresponding to the target flash memory chip and other active flash memory chips;

[0063] ● The physical location of word lines or the physical location of key word lines (top word line, middle word line and bottom word line). In 3D flash memory chips, word lines on different physical layers may have systematic differences in operating current and delay due to differences in their parasitic capacitance and resistance.

[0064] ● The controller's main control temperature and the chip temperature readings of each flash memory chip are obtained from the temperature sensor;

[0065] ● Recent (e.g., past few microseconds) historical current peak sequence or statistics;

[0066] ●Time interval of the most recent peak current;

[0067] ● A snapshot of the recently executable command queue for each flash memory chip, including commands to be issued in the near future (e.g., within the next few microseconds), the queue depth for each flash memory chip, or the estimated time of the next command issuance based on the remaining time of the current operation. This is because subsequent commands may overlap with the current peaks of other commands. Scheduling expectations are used as a predictive feature.

[0068] The hardware inference engine 2022 uses machine learning models (such as neural networks) to perform high-speed calculations based on the input feature vector, predicting the peak current under flash memory operation commands and generating decision results. The main control logic unit 2021 coordinates the feature extraction and construction unit 2023 and the hardware inference engine 2022, and feeds back the decision results to the main control logic and command scheduler 203. That is, when the predicted peak current is less than the safety threshold, the decision result that allows the issuance of flash memory operation commands is fed back; when the predicted peak current is greater than or equal to the safety threshold, the decision result that does not allow the issuance of flash memory operation commands is fed back.

[0069] In some implementations, the feature extraction and construction unit 2023 employs different encoding methods for multi-source heterogeneous data and concatenates the encoded data into an input feature vector. This includes: for discrete features such as operation type and command type, converting them into binary vectors using independent encoding methods; for example, flash memory operation type features use 4-bit binary codes to represent the four states: Read / Program / Erase / Idle. For continuous value features such as temperature, programming / erasing (P / E) cycle count, and voltage, a linear normalization method is used to map them to the [0,1] interval, with the formula: x_norm = (x - x_min) / (x_max - x_min), where x_min and x_max are determined based on the physical range of the feature. For time-series features such as recent current peak sequences, statistical features such as recent mean, variance, and trend are extracted as input. The final feature vector X is a d-dimensional column vector, where d is the total number of features, typically ranging from 50 to 200 dimensions.

[0070] The main control logic and command scheduler 203 is the execution core of command scheduling, and its internal structure is as follows: Figure 3 As shown.

[0071] The flash memory conversion layer 201 stores the processed flash memory operation commands into multiple queues in the command queue management unit 2031. The command queue management unit 2031 acts as a buffer between the flash memory conversion layer 201 and the scheduling and arbitration unit 2032. It manages the pending flash memory operation commands for each flash memory chip through multiple queues. Typically, the command queue management unit 2031 maintains an independent queue for each flash memory chip to prevent commands from different flash memory chips from blocking each other. It also marks the priority (e.g., real-time read / write requests from the host side have higher priority than erase requests from background garbage collection (GC)) and operation type of each command, providing a basis for subsequent arbitration.

[0072] The scheduling arbitration unit 2032 continuously scans the ready commands of each queue, sends execution consultation requests to the peak current control module 202 and receives decision results, and controls the issuance of flash memory operation commands according to the decision results.

[0073] Interface unit 2033 is a "communication bridge" between the main control logic and command scheduler 203 and peak current control module 202. It is responsible for formatting the execution consultation request of the arbitration logic (including information such as command type and target flash memory chip) into a signal that can be recognized by peak current control module 202, and receiving the decision result of peak current control module 202 within a specified timing to ensure stable coordination between the two.

[0074] Command issuance interface 2034 is the "execution channel" between the main control logic, command scheduler 203 and storage media controller 205. It only forwards approved commands and ensures that the command timing complies with the requirements of flash memory protocols (such as ONFI, Toggle) to avoid hardware operation errors.

[0075] The delay / retry queue management unit 2035 provides a temporary storage and retry mechanism for rejected commands. This includes storing commands according to preset strategies (such as FIFO, retrying high-priority commands first) and resubmitting the commands to the command queue---the queue in the management unit 2031 after a delay period (or after detecting a change in system status, such as the completion of a high-power operation), to avoid command starvation.

[0076] The hardware inference engine 2022 is the computational core of the peak current control module 202. Its design goal is to complete machine learning inference with microsecond-level latency and extremely low power consumption, providing real-time decision support for command scheduling. Its internal structure is as follows: Figure 4 As shown.

[0077] When the feature extraction unit of the peak current control module 202 generates a feature vector X (describing the current system power consumption situation), the control logic 401 immediately starts the inference process: according to the preset model structure, it generates the address signal of the parameter RAM and reads the model parameters (weights W, bias b) of the current layer network.

[0078] The multiply-accumulate array 403 consists of multiple parallel multiplier-accumulator units, and specifically performs the following:

[0079] 1. Calculate the linear combination result Z = X × W + b: Perform vector-matrix multiplication on the feature vector X and the weight matrix W, and then add the bias b to obtain the linear output Z of the current layer.

[0080] 2. Parallelism and Pipeline Optimization: Multiple multiply-accumulate units work in parallel, which can calculate multiple elements of the Z vector at the same time; at the same time, a pipelined design is adopted (split into three stages: fetching → multiplication → accumulation) to achieve high throughput of outputting one calculation result per clock cycle and ensure extremely low inference latency.

[0081] 3. Data reuse and bandwidth optimization: Through intelligent data scheduling, the on-chip cache is maximized, reducing access to external storage and further reducing power consumption and latency.

[0082] Activation and output unit 404 generates the final decision through the following steps:

[0083] 1. Nonlinear activation: Execute lightweight activation functions (such as ReLU for hidden layers and Sigmoid for output layers) to introduce nonlinear mapping capabilities, enabling the model to fit complex current prediction relationships (such as the nonlinear effects of different operating phase combinations on peak current).

[0084] 2. Binary decision transformation: If it is an output layer, compare the 0~1 probability value of the Sigmoid output with a preset threshold (such as 0.5): if the probability is ≥0.5, output 1 (allow the command to be issued), and if the probability is <0.5, output 0 (reject the command to be issued); the output probability value can be selected as the confidence level, which can be used by the scheduler to optimize the retry strategy (such as extending the retry delay when the confidence level is extremely low).

[0085] For hardware inference engines, hardware-friendly activation functions are implemented by using hardware-friendly methods such as lookup tables (LUTs) or piecewise linear approximations to implement complex activation functions, balancing computational accuracy and hardware overhead.

[0086] If the model has a multi-layered structure (e.g., input layer → one hidden layer → output layer), the above steps of "reading the next layer's parameters → calculating MAC → activation" will be repeated until the final layer's calculation is completed, outputting the final binary decision. The entire process is coordinated by control logic to ensure that the data flow and control signal timing are matched. The hardware inference engine also supports dynamic adjustment of calculation precision at runtime (e.g., 8-bit / 16-bit mode) to achieve optimal energy efficiency under different workloads. A low-precision mode is used to reduce power consumption under light loads, while a high-precision mode is used under heavy loads to ensure prediction accuracy.

[0087] To implement the machine learning model, a test platform was built during the model training phase. This platform encompassed flash memory chips of different models, temperatures, and aging levels, and ran diverse workloads. During training, precision measurement equipment was used to collect sample data, and a new command was issued immediately after the sample data was collected. This sample data accurately described the power consumption scenario of the new command. The peak current was then measured over a subsequent period. If the peak current was below the safety threshold I_max, the sample was marked as "1 (allowed); if it exceeded the threshold, it was marked as "0 (rejected)". A computationally low-complexity model (such as a shallow neural network (1-2 hidden layers) or a gradient boosting decision tree (GBDT)) was then selected, and supervised learning was performed using the collected samples. The training objective was to minimize the prediction error, i.e., to learn to accurately determine under what system conditions it is safe to issue a new command.

[0088] The trained model parameters (weights, biases, split points, etc.) are quantized and stored in the on-chip read-only memory (ROM). During online inference, the hardware inference engine (composed of a multiply-accumulate array and simple activation function units) reads the parameters from the ROM and performs a series of simple multiply-accumulate (MAC) operations and logical judgments on the input features. The model outputs a binary prediction result (1 or 0), where 1 indicates that the predicted future instantaneous peak current will not exceed the limit, and 0 indicates that the predicted future instantaneous peak current is at risk of exceeding the limit after the command is issued. The initial values ​​of the trained model parameters are stored in the ROM and loaded into a writable static RAM (SRAM) during system startup.

[0089] Considering hardware implementation efficiency, the weight matrix of the machine learning model is constructed using the following optimization:

[0090] ● Hierarchical matrix structure: For a network structure containing one hidden layer, the weight matrix is ​​divided into two layers:

[0091] ■ The input-to-hidden-layer weight matrix W1 has dimensions h×d, where h is the number of hidden layer neurons (typically 8-32) and d is the total number of features, typically ranging from 50-200 dimensions.

[0092] ■ The weight matrix W2 from the hidden layer to the output layer has a dimension of 1×h.

[0093] ■ Corresponding bias vectors b1 (h-dimensional) and b2 (scalar)

[0094] ● Block-diagonal sparse optimization: To reduce the number of multipliers, the weight matrix adopts a grouped sparse structure, grouping features according to their physical meaning (such as operation state group, scheduling intention group, and environmental parameter group). The weight matrix is ​​approximately a block-diagonal matrix, which greatly reduces the hardware computational complexity.

[0095] ● Parameter quantization strategy: All parameters (weights and biases) are quantized in a fixed-point manner (e.g., 8-bit integers) before being stored in on-chip ROM / RAM, reducing storage overhead and computation bit width while ensuring accuracy.

[0096] Figure 5 This is a flowchart of a peak current control method provided in an embodiment of this disclosure. The specific process includes the following steps.

[0097] In step S501, an execution consultation request is received.

[0098] In step S502, model reasoning is performed based on the information, status data, recent current peak data, and command information in the execution consultation request of the current preparation and already issued flash operation commands on multiple flash memory chips to predict whether issuing the flash operation command will cause the current peak of multiple flash memory chips to exceed the limit, thereby generating a decision result of allowing or refusing to issue the command.

[0099] In step S503, the decision result is sent.

[0100] In step S504, the instantaneous peak current actually generated by the multiple flash memory chips after the command is issued is recorded, and recent peak current data is obtained.

[0101] In step S505, the parameters of the machine learning model are updated online based on the deviation between the actual peak current and the predicted result.

[0102] In summary, the controller and peak current control method provided in this embodiment have the following advantages:

[0103] 1) Applying machine learning models to the controller of solid-state drives (SSDs) allows the model to learn the mapping relationship between various complex states and peak current. A set of model parameters can be well adapted to different flash memory chips and different aging stages, avoiding the design reset cost for each situation. It has strong generalization and adaptability. Moreover, before issuing flash memory operation commands, the instantaneous peak current after issuing the flash memory operation commands is inferred using the applied machine learning model. This method is an active "prevention" rather than a passive "response", thereby fundamentally eliminating current overrun events. The system has extremely high reliability and avoids performance jitter and data risks caused by emergency throttling.

[0104] 2) When constructing input feature data, multi-dimensional dynamic information such as real-time current, historical waveforms, temperature, aging, and execution time of each flash memory operation command of each flash memory chip is integrated, rather than relying solely on static operation counts. The model can more accurately determine the current "power consumption situation" and know which flash memory chips are in the rising, peak, or falling current stage. This allows it to predict peak current within a smaller safety margin, which is beneficial to improving system accuracy.

[0105] 3) The hardware-implemented dedicated inference engine achieves a balance between intelligent decision-making and low overhead. Compared with pure software solutions or complex time slot simulations, it has extremely low latency (microsecond level), low resource consumption (small area overhead), and is easy to integrate into existing SSD controllers, with almost no impact on the main business pipeline.

[0106] 4) The online parameter self-learning mechanism enables the peak current control model to overcome the limitations of initial static parameters. During actual operation, the system can continuously self-calibrate and optimize the prediction model based on real current feedback and the constantly changing working environment. This ensures that the solid-state drive maintains a continuous and optimal performance-power balance throughout its entire lifespan, overcoming the drawbacks of traditional solutions that gradually fail due to model fixation, resulting in a higher level of intelligence.

[0107] 5) Through a closed-loop feedback mechanism of "prediction-execution-verification-learning," the system forms a self-improving intelligent control system. Prediction deviations are continuously corrected, making the prediction of peak current increasingly accurate over time, thereby further reducing the probability of current exceeding limits and uncovering deeper performance potential, greatly enhancing the long-term reliability of the system.

[0108] Accordingly, embodiments of this disclosure also provide, as Figure 1 The solid-state drive shown includes the modules of the above embodiments. The modules of the embodiments can be implemented as hardware, software, and firmware, and the software portion can be stored in a computer-readable storage medium.

[0109] Computer-readable storage media are, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media include: electrical connections of one or more wires; portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory); optical fibers; portable compact disk read-only memory (CD-ROM); optical storage; magnetic storage; or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with a processing unit, apparatus, or device.

[0110] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the embodiments of this disclosure. For those skilled in the art, various modifications and variations can be made to the embodiments of this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this disclosure should be included within the protection scope of the embodiments of this disclosure.

Claims

1. A controller for a solid-state drive (SSD), the SSD further comprising a plurality of flash memory chips coupled to the controller, characterized in that, The controller includes: The main control logic and command scheduler are used to initiate an execution consultation request before issuing a flash memory operation command, and decide whether to issue the flash memory operation command immediately or delay it based on the feedback decision results. The execution consultation request includes command information of the flash memory operation command to be issued. The current monitoring unit is used to record the instantaneous peak current actually generated by the multiple flash memory chips after the flash memory operation command is issued, and to obtain the recent peak current data. The flash memory status tracking unit is used to acquire information on flash memory operation commands currently being prepared for issuance to the multiple flash memory chips and flash memory operation commands that have already been issued to the multiple flash memory chips, and to obtain status data of the multiple flash memory chips; The peak current control module is used to respond to the execution consultation request by performing model reasoning based on the information of the currently prepared and issued flash operation commands on the plurality of flash memory chips, the status data of the plurality of flash memory chips, the recent current peak data, and the command information in the execution consultation request, in order to predict whether issuing the flash operation command will cause the current peak of the plurality of flash memory chips to exceed the limit, thereby generating a decision result of allowing or refusing to issue the command.

2. The controller according to claim 1, characterized in that, The controller also includes: A temperature sensor interface is used to collect temperature data from the temperature sensor of the controller and the multiple flash memory chips. The peak current control module then uses the temperature data to perform model inference.

3. The controller according to claim 1, characterized in that, The controller also includes: The learning and updating logic unit is used to update the model parameters in the peak current control module online based on the deviation between the instantaneous peak current obtained after the flash memory operation command is issued and the prediction result.

4. The controller according to claim 1, characterized in that, The peak current control module includes: The feature extraction and construction unit is used to construct an input feature vector based on the information of the currently prepared and issued flash operation commands on the multiple flash memory chips, the status data of the multiple flash memory chips, the recent current peak data, and the command information in the execution consultation request; A hardware inference engine is used to perform forward propagation calculations based on the input feature vector and pre-stored model parameters to generate the decision result; The main control logic unit is used to coordinate the feature extraction and construction unit and the hardware inference engine, and to return the decision result to the main control logic and command scheduler.

5. The controller according to claim 4, characterized in that, In the feature extraction and construction unit, information on the currently prepared and issued flash memory operation commands on the multiple flash memory chips, the status data of the multiple flash memory chips, and the recent current peak data are classified and encoded.

6. The controller according to claim 1, characterized in that, The hardware inference engine includes a multiply-accumulate array and activation function units.

7. The controller according to claim 1, characterized in that, The main control logic and command scheduler include: The command queue management unit is used to manage the flash memory operation commands to be issued for the multiple flash memory chips through multiple queues; The scheduling arbitration unit is used to retrieve multiple flash memory operation commands in parallel from the multiple queues, select one flash memory operation command from them according to a predetermined strategy, send the execution consultation request to the peak current control module based on the selected flash memory operation command, and decide whether to issue the flash memory operation command immediately or delay it based on the decision result.

8. The controller according to claim 7, characterized in that, The main control logic and command scheduler also include: The delay / retry queue management unit is used to manage flash memory operation commands that have been rejected through multiple queues, and to resubmit the commands to the queue in the command queue management unit after a delay period or after detecting a change in the flash memory status.

9. The controller according to claim 1, characterized in that, The learning and updating logic unit is configured to be triggered periodically, triggered when the error exceeds a threshold, or triggered by changes in environmental characteristics, or in one or more of these ways.

10. A method for controlling peak current in a solid-state drive (SSD), the SSD further comprising a plurality of flash memory chips coupled to the controller, characterized in that, include: Receive an execution consultation request, the execution consultation request containing command information of flash memory operation commands; Based on the information, status data, recent current peak data, and command information in the execution consultation request of the multiple flash memory chips, model reasoning is performed to predict whether issuing the flash memory operation command will cause the current peak of the multiple flash memory chips to exceed the limit, thereby generating a decision result of allowing or refusing to issue the command. Send the decision result to drive the flash memory operation command to be issued immediately or delayed; Record the instantaneous peak current actually generated by the multiple flash memory chips after the command is issued, and obtain the recent peak current data; Based on the deviation between the actual peak current and the predicted result, the parameters of the machine learning model are updated online.

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