Error correction method of NAND flash memory controller based on AHB protocol
By using a NAND flash controller based on the AHB protocol and employing ECC verification to correct data errors, the stability and reliability issues of NAND flash memory during read and write processes are resolved, enabling efficient data storage and transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HAISUXIN MICROELECTRONICS CO LTD
- Filing Date
- 2026-02-25
- Publication Date
- 2026-05-19
AI Technical Summary
NAND flash memory is prone to errors during data read and write operations, including physical wear and tear, bit flips, read/write interference, data retention issues, and errors caused by unstable power supply voltage. Furthermore, improper management of bad blocks can lead to product crashes.
A NAND flash controller based on the AHB protocol is adopted. Single-bit and double-bit errors in data transmission or storage are detected and corrected through ECC verification. The reliability and stability of data are achieved by using the ECC check bit field configuration register and ECC error correction code verification.
It improves data reliability, enhances system stability, reduces the risk of data loss, and improves storage efficiency and system performance.
Smart Images
Figure CN122067585A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of NAND flash memory controller technology, specifically to an error correction method for NAND flash memory controllers based on the AHB protocol. Background Technology
[0002] NAND flash memory is a type of FLASH memory that uses a non-linear macrocell model internally, providing a cost-effective solution for realizing large-capacity solid-state memory. NAND flash memory has advantages such as large capacity and fast write speed, making it suitable for storing large amounts of data; therefore, it has been increasingly widely used in the industry, such as in embedded products including digital cameras, MP3 player memory cards, and compact USB flash drives. However, due to its characteristics, NAND flash memory is prone to errors during data read and write processes. The specific reasons are as follows: 1. Physical wear and tear: After a certain number of erase and write cycles, NAND flash memory cells will wear down, causing some storage cells to become unusable, i.e., bad blocks.
[0003] 2. Bit flip: In NAND flash memory, without any external intervention, a single bit may change from 1 to 0 or from 0 to 1, which is called a bit flip error.
[0004] 3. Read / write interference: Certain operations on NAND flash memory, such as frequent reads, may affect the stability of adjacent cells, leading to unexpected changes in data.
[0005] 4. Data retention: Data stored in NAND flash memory may degrade over time without read / write operations, leading to data loss.
[0006] 5. Unstable power supply voltage: Unstable power supply voltage may cause NAND flash memory program errors, especially in battery-powered devices. Low battery power may cause data errors in the NAND flash memory.
[0007] 6. DRAM malfunction: If the DRAM in the system is not functioning properly, it may indicate a problem with the NAND flash memory, such as program crashes or too many bad blocks.
[0008] 7. Inadequate bad block management: NAND flash memory is susceptible to bad blocks. Poor bad block management can lead to program crashes during actual use. Therefore, this method does not meet the existing requirements, and we propose an error correction method for NAND flash memory controllers based on the AHB protocol. Summary of the Invention
[0009] The purpose of this invention is to provide an error correction method for a NAND flash memory controller based on the AHB protocol. This method uses ECC (Electronic Code Correction) to detect and correct single-bit and double-bit errors during data transmission or storage, avoiding the drawback of NAND flash memory where bit flips may occur after multiple erase / write cycles, leading to data errors. This improves data reliability and enhances system stability. Secondly, by adding extra check bits during data storage or transmission, ECC ensures that even when original data suffers a certain degree of error, it can still be correctly identified and corrected, thereby reducing the risk of data loss and improving storage efficiency. Simultaneously, ECC can maintain consistency with the read / write timing of NAND flash memory without requiring additional timing steps, resulting in a significant performance advantage for hardware ECC execution. This improves the overall system performance and solves the problems mentioned in the background section.
[0010] To achieve the above objectives, the present invention provides the following technical solution: An error correction method for NAND flash memory controllers based on the AHB protocol includes the following steps: S1. Based on the flash memory characteristics of the NAND flash memory controller, configure the bit fields of the PCR control register, PMEM register, and PATT register of the NAND flash memory controller through the AHB interface; S2. The CPU writes an enable bit to the PCR control register of the NAND flash controller through the AHB interface to enable or disable the ECC encoding function of the NAND flash controller. After the ECC encoding function is enabled, the CPU obtains the ECCEN bit of the PCR control register in the NAND flash controller through the AHB interface. The ECCEN bit is: Extended Correctable Error Count. S3. The CPU writes flash command bytes into the general storage space. Flash command bytes include read or write operations. S4. The CPU writes four bytes into the general memory space or attribute space as the starting address of the read operation; S5. Based on the configuration of S1 and S3, the CPU performs byte read or write operations in the general storage space, and then reads or writes the storage pages of the NAND flash memory controller byte by byte or double byte by double; and after the last data operation is completed, the ECC error correction code is synchronously stored in the ECCR register. S6. The CPU reads the ECC error correction code through the AHB interface, stores the read ECC error correction code in a variable, and then clears the ECC error correction code in the ECCR register. S7. Return to S2 and re-execute the write or read operation to obtain a new ECC error correction code; S8. The auxiliary software reads the ECC error correction code stored in the ECCR register through the AHB interface, and judges whether the two ECC error correction codes are correct. Then, the correction result is obtained based on the judgment result.
[0011] Furthermore, in S3 and S4, if the CPU does not write the flash command byte or address to the general storage space, the next storage page of the NAND flash controller will be read or written according to any of the following methods: The first method is to operate according to S5; The second option is to return to S3 and start writing to a new address. The third option is to return to S2 and start writing a new command.
[0012] Furthermore, in S2, the start / stop status of the ECC encoding function of the NAND flash controller is synchronized with the start / stop status of the ECCEN bit of the PCR control register; when the ECC encoding function of the NAND flash controller is enabled, the ECCEN bit of the PCR control register is enabled synchronously; when the ECC encoding function of the NAND flash controller is disabled, the ECCEN bit of the PCR control register is disabled synchronously.
[0013] Furthermore, in S3, after the CPU writes the flash command byte in the general storage space, the CLE input port of the NAND flash controller becomes valid during the valid period of the write instruction signal; when the flash command byte is recognized by the NAND flash controller and latched as a command, the CPU does not need to write the same command again.
[0014] Furthermore, in S4, after the CPU writes four bytes in the general memory space or attribute space as the start address of the read operation, the ALE input port of the NAND flash controller becomes valid during the valid period of the write instruction signal; when the NAND flash controller recognizes the byte as the start address of the read operation, the attribute storage space is used to make the NAND flash controller generate different timings to implement the pre-wait function required by the NAND flash controller.
[0015] Furthermore, in step S5, the ECC error correction code is synchronously stored in the ECCR register, specifically including the following steps: The CPU controls the NAND flash controller to write data to the storage pages of the flash memory through the AHB interface. When the storage pages of the NAND flash memory are written, the ECC calculation module synchronously calculates the value of the ECC error correction code and stores the ECC error correction code synchronously into the ECCR register.
[0016] Furthermore, in step S7, returning to step S2 to re-execute the write or read operation to obtain a new ECC error correction code specifically includes the following steps: The CPU clears the ECCEN bit in the PCR control register and writes the enable bit through the AHB interface to enable the ECC encoding function of the NAND flash controller. When a storage page of the NAND flash controller is written, the CPU reads or writes data from the storage page of the NAND flash controller through the AHB interface. When reading a storage page of the NAND flash controller, the ECC value is calculated synchronously through the ECC calculation module to obtain a new ECC error correction code.
[0017] Furthermore, in step S8, the auxiliary software reads the ECC error correction code stored in the ECCR register through the AHB interface, and determines whether the two ECC error correction codes are correct. Based on the determination result, the correction result is obtained. Specifically, this includes the following steps: The auxiliary software reads the new ECC error correction code from the ECCR register through the AHB interface. If the two ECC error correction codes are the same, no correction is required; otherwise, it indicates that there is an error in the ECC error correction code, and the auxiliary software obtains information on whether correction is possible through its correction routine.
[0018] Furthermore, after obtaining the new ECC error correction code, the original ECC error correction code and the new ECC error correction code are XORed bit by bit. If the result is 0, it means that there is no error; if there are 11 bits as 1 in the XOR result, it means that there is a bit error and it can be corrected. The method for locating the faulty bit is as follows: first determine the row address, including which byte is faulty; then determine the column address, including which bit in that byte is faulty.
[0019] Furthermore, in S8, the auxiliary software calculates two results: one is that there is no error or there is an error that the ECC error correction code cannot detect, and the other is that there is a correctable bit error.
[0020] This invention detects and corrects single-bit and double-bit errors in data transmission or storage using ECC (Electronic Code Correction), avoiding the drawbacks of NAND flash memory where bit flips may occur after multiple erase and write cycles, leading to data errors. This improves data reliability and enhances system stability. Secondly, by adding extra check bits during data storage or transmission, ECC ensures that even when original data suffers a certain degree of error, it can still be correctly identified and corrected, reducing the risk of data loss and improving storage efficiency. Furthermore, ECC can maintain consistency with the read / write timing of NAND flash memory without requiring additional timing steps, resulting in a significant performance advantage for hardware ECC execution and thus improving the overall system performance. Attached Figure Description
[0021] Figure 1 This is a functional block diagram of the NAND flash memory controller of the present invention. Detailed Implementation
[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0023] To address the technical problem in existing technologies where the characteristics of NAND flash memory controllers cause errors during data read / write operations, please refer to [link to relevant documentation]. Figure 1 This embodiment provides the following technical solution: An error correction method for NAND flash memory controllers based on the AHB protocol includes the following steps: S1. Based on the flash memory characteristics of the NAND flash controller, configure the bit fields of the PCR control register, PMEM register, and PATT register of the NAND flash controller through the AHB interface. Specifically, since the NAND flash controller is the foundation of this error correction mechanism, it also needs to be managed through a set of registers: 1. PCR control register, which includes: the ECCPS bit field used to define the extended ECC page size; the TARS bit field used to define the time from ALE low to RE low in units of AHB clock cycles. 2. SR interrupt status register, which includes the FEMPT bit field (FIFO empty flag), the IFEN bit field (interrupt falling edge detection enable), the ILEN bit field (interrupt high level detection enable), the IREN bit field (interrupt rising edge detection enable), the IFS bit field (interrupt falling edge status), the ILS bit field (interrupt high level status), and the IRS bit field (interrupt rising edge status). SR contains FIFO status and interrupt information; secondly, the NAND flash controller also has a FIFO used to store up to 16 words of data sent from the AHB interface during memory writes. 3. PMEM common memory space timer register: MEMHIZ bit field, i.e., general memory x data bus high impedance time, is used to maintain a high impedance state on the data bus for a period of time after a write operation to the NAND flash controller begins in the general memory space. This parameter defines the high impedance state time of the data bus in the number of HCLK (+1) clock cycles, and this parameter is only valid for write operations; MEMHOLD bit field, i.e., hold time in general space x, is used to hold the address signal when performing read or write operations to the NAND flash controller in the general memory space. This parameter defines the hold time of the address signal in the number of HCLK clock cycles; MEMWAIT bit field, i.e., wait time in general space. The parameter is used to define the minimum holding time for a command when performing read or write operations on the NAND flash controller in the general memory space. When the time defined by this parameter ends, if the wait signal is valid, the holding time of the command is extended. The MEMSET bit field, i.e., the setup time in the general memory space, is used to define the time before the address signal is established when performing read or write operations on the NAND flash controller in the general memory space. The parameter is defined by the number of HCLK (+1) clock cycles. The PMEM register includes operation timing parameters, which are applicable to operating or sending commands, addresses, and performing read and write operations on the NAND flash in the general memory space.4. The timing register for the PATT attribute memory space: The ATTHIZ bit field specifies the high-impedance time of the data bus in attribute space x. After a write operation to the NAND flash memory begins in attribute memory space x, the data bus must remain in a high-impedance state for a period of time. This parameter defines the high-impedance time of the data bus in HCLK(+1) clock cycles. This parameter is only valid for write operations. The ATTHOLD bit field specifies the hold time in attribute space. This is used when performing read or write operations on the NAND flash memory in attribute memory space. This parameter defines the hold time of the address signal in HCLK clock cycles. The ATTWAIT bit field specifies the wait time in attribute space. The `Time` parameter, used when performing read or write operations on NAND flash memory in the attribute storage space, defines the minimum time to hold the command in the number of HCLK(+1) clock cycles. When the time defined by this parameter ends, the command's hold time is extended if the wait signal is valid. The `ATTSET` bit field is the setup time in the attribute space. When performing read or write operations on the NAND flash memory controller in the attribute storage space, this parameter defines the time to establish the address signal beforehand in the number of HCLK(+1) clock cycles. `PATT` includes operation timing parameters applicable to operating or sending commands, addresses, and performing read / write operations on NAND flash memory in the attribute storage space. 5. ECCR, the ECC register, contains the current value of the error correction code obtained by the ECC calculation module of the NAND flash memory controller. When the CPU reads / writes data in the NAND flash memory at the correct address through the AHB interface, the ECC calculation module automatically processes the written or read data. According to the setting of the ECCPS field in the PCR control register, after reading the last byte of each memory page, the CPU must read the ECC value in the ECCR register through the AHB interface and compare it with the previously recorded ECC data to determine whether the data of the memory page is correct; and perform correction if possible. After reading the value of the FECCR register, the ECCEN bit should be set to "0" to clear the contents; when a new data page needs to be calculated, the ECCEN bit should be set to "1" again.
[0024] S2. The CPU writes an enable bit to the PCR control register of the NAND flash controller via the AHB interface to enable or disable the ECC encoding function of the NAND flash controller. After enabling the ECC encoding function, the CPU obtains the ECCEN bit of the PCR control register in the NAND flash controller via the AHB interface. The ECCEN bit is for extended correctable error count. The start / stop status of the ECC encoding function of the NAND flash controller is synchronized with the start / stop status of the ECCEN bit of the PCR control register. When the ECC encoding function of the NAND flash controller is enabled, the ECCEN bit of the PCR control register is enabled synchronously; when the ECC encoding function of the NAND flash controller is disabled, the ECCEN bit of the PCR control register is disabled synchronously. Specifically, the enable bit is written to the PCR control register via the AHB interface, and the status of the ECCEN bit is read from the AHB interface to enable or disable the ECC encoding function. This mechanism ensures the correct operation of the NAND flash controller in different states.
[0025] S3. The CPU writes a flash command byte to the general-purpose memory space. The flash command byte includes read or write operations. When the CPU writes a flash command byte to the general-purpose memory space, for example, for Samsung's NAND flash controller, this byte is 0x00. During the active period of the write instruction signal (the low pulse of NWE), the CLE input port of the NAND flash controller becomes active (high level). When the flash command byte is recognized by the NAND flash controller and latched as a command, the CPU does not need to write the same command again. S4. The CPU writes four bytes in the general memory space or attribute space, while the NAND flash controller with a smaller capacity only needs to write three bytes as the start address of the read operation. When the CPU writes four bytes in the general memory space or attribute space as the start address (STARTAD) of the read operation, taking a 64Mbx8 NAND flash controller as an example, it writes in the order of STARTAD[7:0], STARTAD[16:9], STARTAD[24:17] and STARTAD
[25] . During the effective period of the write instruction signal (the low pulse of NWE), the ALE input port of the NAND flash controller becomes active (high level). When the byte is recognized by the NAND flash controller as the start address of the read operation, the attribute storage space is used to make the NAND flash controller generate different timings to implement the pre-wait function required by the NAND flash controller. Before the NAND flash controller starts to perform a new operation on the same or another memory block, it needs to wait for the NAND flash controller to be ready (R / NB signal becomes high). During the waiting period, the NAND flash controller keeps the NCE signal active (low level).
[0026] If the CPU does not write a flash command byte or address to the general memory space, the next memory page of the NAND flash controller is read or written in any of the following ways: The first method is to operate according to S5; The second option is to return to S3 and start writing to a new address. The third option is to return to S2 and start writing a new command.
[0027] S5. Based on the configurations of S1 and S3, the CPU performs byte read or write operations in the general-purpose storage space, and then reads or writes the storage pages of the NAND flash memory controller byte by byte or double byte by double; and after the last data operation is completed, the ECC error correction code is synchronously stored in the ECCR register; specifically including the following steps: The CPU controls the NAND flash controller to write data to the flash memory pages through the AHB interface. When the flash memory pages of the NAND flash controller are written, the ECC calculation module synchronously calculates the value of the ECC error correction code and stores the ECC error correction code into the ECCR register. Specifically, the ECC calculation module is the core of this mechanism and is used to implement the function of calculating the ECC correction code.
[0028] In this embodiment: taking eight bits as an example, CP[0] is the NAND flash controller itself and the 0th, 2nd, 4th, and 6th bits of the data to be transmitted each time (processing 1 column, skipping 1 column), CP[1] is the NAND flash controller itself and the 1st, 3rd, 5th, and 7th odd-numbered bits of the data to be transmitted each time (skipping 1 column, processing 1 column), CP[2] is the NAND flash controller itself and the 0th, 1st, 4th, and 5th bits of the data to be transmitted each time (processing 2 columns, skipping 2 columns). CP[3] is the NAND flash controller itself and the 2nd, 3rd, 6th and 7th odd-numbered bits of the data to be transmitted each time (skipping 2 columns and processing 2 columns), CP[4] is the NAND flash controller itself and the 0th, 1st, 2nd and 3rd odd-numbered bits of the data to be transmitted each time (processing 4 columns and skipping 4 columns), CP[5] is the NAND flash controller itself and the 2nd, 3rd, 6th and 7th odd-numbered bits of the data to be transmitted each time (skipping 4 columns and processing 4 columns), CP[6] / CP[7] is 0. When the NAND flash controller is 16-bit, the CP value is calculated according to the similarity rule. CP[6] and CP[7] are no longer 0. RP[0] is the XOR of the bytes 0, 2, 4, 6, ..., 252, 254 (process 1 row, skip 1 row), RP[1] is the XOR of the bytes 1, 3, 5, 7, ..., 253, 255 (skip 1 row, process 1 row), and RP[2] is the XOR of the bytes 0, 1, 4, 5, 8, 9, ..., 252, 253 (process 2 rows, skip 2 rows). The RP value is calculated according to the similarity rule, and finally the ECC code is obtained.
[0029] S6. The CPU reads the ECC error correction code through the AHB interface and stores the read ECC error correction code in a variable, then clears the ECC error correction code in the ECCR register. Specifically, when the CPU needs to read or clear the ECC error correction code of the NAND flash memory controller, it reads the ECC error correction code in the ECCR register through the AHB interface. After reading, the CPU stores it in a specific variable for subsequent processing and use. Then, the CPU clears the ECC error correction code in the ECCR register, making it ready to receive new ECC error correction codes. This avoids the misuse of previously stored ECC error correction codes, ensuring data reliability and integrity.
[0030] S7. Return to S2 and re-execute the write or read operation to obtain the new ECC error correction code; specifically, this includes the following steps: The CPU clears the ECCEN bit in the PCR control register and writes an enable bit through the AHB interface to enable the ECC encoding function of the NAND flash controller. When a memory page of the NAND flash controller is written to, the CPU reads or writes data from or to that memory page through the AHB interface. When reading a memory page of the NAND flash controller, the ECC calculation module synchronously calculates the ECC value to obtain a new ECC error correction code. Specifically, when the CPU enables the ECC function of the NAND flash controller, it clears the ECCEN bit in the PCR control register and writes an enable bit through the AHB interface to start the ECC encoding process. This is to allow the CPU to send feedback to the NAND flash controller that the ECC encoding task can begin. When data is written to a memory page of the NAND flash controller, the CPU reads or writes data from that memory page through the AHB interface. When reading a memory page of the NAND flash controller, the CPU triggers the ECC calculation module, which synchronously calculates the value of the ECC error correction code and generates a new ECC error correction code based on the obtained value, thereby detecting and repairing potential errors in the flash memory.
[0031] S8. The auxiliary software reads the ECC error correction code stored in the ECCR register through the AHB interface, and determines whether the two ECC error correction codes are correct. Then, the correction result is obtained based on the determination result. Specifically, this includes the following steps: The auxiliary software reads the new ECC error correction code from the ECCR register through the AHB interface. If the two ECC error correction codes are the same, no correction is needed; otherwise, it indicates that there is an error in the ECC error correction code, and the auxiliary software obtains information on whether it can be corrected through its correction routine. The auxiliary software obtains two results: 1) No error exists or an error exists that the ECC error correction code cannot detect; 2) A correctable bit error exists. Specifically, after obtaining the new ECC error correction code, the original ECC error correction code and the new ECC error correction code are XORed bit by bit. If the result is 0, it indicates that there is no error; if 11 bits in the XOR result are 1, it indicates that there is a bit error that can be corrected. The method for locating the erroneous bit is as follows: first, determine the row address, including which byte is erroneous; then determine the column address, including which bit in that byte is erroneous. For example, the following is a verification method when the ECCPS field is set to 0 and the NAND flash controller is eight-bit: the method for determining the row address is: assuming the row address is unsignedchar... The `byteoffs` parameter is calculated by extracting bits 7, 5, 3, and 1 from bits 16 to 23 of the XOR result, which are then used as the high four bits of `byteoffs`. Bits 7, 5, 3, and 1 from bits 9 to 15 are also extracted, which are used as the low four bits of `byteoffs`. The value of `byteoffs` represents the row address of the erroneous byte, with a range of 0-255. The column address is determined by extracting bits 7, 5, and 3 from the low 8 bits, which are then used as the low three bits of `bitnum`. All other bits in `bitnum` are set to 0. `bitnum` then represents the column address of the erroneous bit, with a range of 0-7.
[0032] The beneficial effects achieved by the above are as follows: Through the above operations, data reliability is improved and system stability is enhanced; thereby reducing the risk of data loss and improving storage efficiency and overall system performance.
[0033] Working principle: ECC checks detect and correct single-bit and double-bit errors in data transmission or storage, ensuring data reliability. Secondly, ECC checks add extra check bits during data storage or transmission, allowing the original data to be correctly identified and corrected even when it suffers a certain degree of error, preventing data loss. At the same time, ECC checks can be consistent with the read and write timing of NAND FLASH without adding extra timing steps, giving hardware ECC execution a significant performance advantage.
[0034] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "possessing," or any other variations thereof are intended to cover non-exclusive possession, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.
[0035] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. An error correction method for a NAND flash memory controller based on the AHB protocol, characterized in that, Includes the following steps: S1. Based on the flash memory characteristics of the NAND flash memory controller, configure the bit fields of the PCR control register, PMEM register, and PATT register of the NAND flash memory controller through the AHB interface; S2. The CPU writes an enable bit to the PCR control register of the NAND flash controller through the AHB interface to enable or disable the ECC encoding function of the NAND flash controller. After the ECC encoding function is enabled, the CPU obtains the ECCEN bit of the PCR control register in the NAND flash controller through the AHB interface. The ECCEN bit is: Extended Correctable Error Count. S3. The CPU writes flash command bytes into the general storage space. Flash command bytes include read or write operations. S4. The CPU writes four bytes into the general memory space or attribute space as the starting address of the read operation; S5. Based on the configuration of S1 and S3, the CPU performs byte read or write operations in the general storage space, and then reads or writes the storage pages of the NAND flash memory controller byte by byte or double byte by double; and after the last data operation is completed, the ECC error correction code is synchronously stored in the ECCR register. S6. The CPU reads the ECC error correction code through the AHB interface, stores the read ECC error correction code in a variable, and then clears the ECC error correction code in the ECCR register. S7. Return to S2 and re-execute the write or read operation to obtain a new ECC error correction code; S8. The auxiliary software reads the ECC error correction code stored in the ECCR register through the AHB interface, and judges whether the two ECC error correction codes are correct. Then, the correction result is obtained based on the judgment result.
2. The error correction method for a NAND flash memory controller based on the AHB protocol according to claim 1, characterized in that: In S3 and S4, if the CPU does not write flash command bytes or addresses to the general storage space, the next storage page of the NAND flash controller will be read or written in any of the following ways: The first method is to operate according to S5; The second option is to return to S3 and start writing to a new address. The third option is to return to S2 and start writing a new command.
3. The error correction method for a NAND flash memory controller based on the AHB protocol according to claim 1, characterized in that: In S2, the start / stop status of the ECC encoding function of the NAND flash controller is synchronized with the start / stop status of the ECCEN bit of the PCR control register; when the ECC encoding function of the NAND flash controller is enabled, the ECCEN bit of the PCR control register is enabled synchronously; when the ECC encoding function of the NAND flash controller is disabled, the ECCEN bit of the PCR control register is disabled synchronously.
4. The error correction method for a NAND flash memory controller based on the AHB protocol according to claim 1, characterized in that: In S3, after the CPU writes the flash command byte into the general storage space, the CLE input port of the NAND flash controller becomes valid during the valid period of the write instruction signal; when the flash command byte is recognized by the NAND flash controller and latched as a command, the CPU does not need to write the same command again.
5. The error correction method for a NAND flash memory controller based on the AHB protocol according to claim 1, characterized in that: In step S4, after the CPU writes four bytes in the general memory space or attribute space as the start address of the read operation, the ALE input port of the NAND flash memory controller becomes valid during the valid period of the write instruction signal. When the NAND flash memory controller recognizes the byte as the start address of the read operation, the attribute memory space is used to make the NAND flash memory controller generate different timings to implement the pre-wait function required by the NAND flash memory controller.
6. The error correction method for a NAND flash memory controller based on the AHB protocol according to claim 1, characterized in that: In step S5, the ECC error correction code is synchronously stored in the ECCR register, which specifically includes the following steps: The CPU controls the NAND flash controller to write data to the storage pages of the flash memory through the AHB interface. When the storage pages of the NAND flash memory are written, the ECC calculation module calculates the value of the ECC error correction code and stores the ECC error correction code synchronously into the ECCR register.
7. The error correction method for a NAND flash memory controller based on the AHB protocol according to claim 1, characterized in that: In step S7, the write or read operation is re-executed after returning to step S2 to obtain a new ECC error correction code, specifically including the following steps: The CPU clears the ECCEN bit in the PCR control register and writes the enable bit through the AHB interface to enable the ECC encoding function of the NAND flash controller. When a storage page of the NAND flash controller is written, the CPU reads or writes data from the storage page of the NAND flash controller through the AHB interface. When reading a storage page of the NAND flash controller, the ECC value is calculated synchronously through the ECC calculation module to obtain a new ECC error correction code.
8. The error correction method for a NAND flash memory controller based on the AHB protocol according to claim 1, characterized in that: In step S8, the auxiliary software reads the ECC error correction code stored in the ECCR register through the AHB interface, determines whether the two ECC error correction codes are correct, and then obtains the correction result based on the determination result. Specifically, this includes the following steps: The auxiliary software reads the new ECC error correction code from the ECCR register through the AHB interface. If the two ECC error correction codes are the same, no correction is required; otherwise, it indicates that there is an error in the ECC error correction code, and the auxiliary software obtains information on whether correction is possible through its correction routine.
9. The error correction method for a NAND flash memory controller based on the AHB protocol according to claim 8, characterized in that: After obtaining the new ECC error correction code, the original ECC error correction code and the new ECC error correction code are XORed bit by bit. If the result is 0, it means that there is no error; if there are 11 bits in the XOR result, it means that there is a bit error and it can be corrected. The method for locating the erroneous bit is as follows: first determine the row address, then determine the column address.
10. The error correction method for a NAND flash memory controller based on the AHB protocol according to claim 1, characterized in that: In step S8, the auxiliary software calculates two results: one is that there is no error or there is an error that the ECC error correction code cannot detect, and the other is that there is a correctable bit error.