Cascade device packaging structure and cascade device
By forming a second parasitic capacitance in the package structure of the cascaded device to bypass part of the current, the problem of high-frequency oscillation in high-power applications is solved, and the reliability and durability of the device are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGDONG ZHINENG TECH CO LTD
- Filing Date
- 2026-02-24
- Publication Date
- 2026-05-19
AI Technical Summary
In high-power industrial applications, cascaded devices face an increased risk of high-frequency oscillation due to the increased operating current, a problem that current technologies have not been able to effectively address.
By electrically connecting the gate field plate and/or shielding layer of the first power device to the package frame in the cascaded device packaging structure, a second parasitic capacitance is formed, which bypasses part of the current, reduces the gate current of the first power device, and reduces parasitic inductance interference.
It effectively suppresses the risk of self-oscillation in cascaded devices, reduces gate-source voltage stress and drain-source voltage, and improves switch reliability and durability.
Smart Images
Figure CN122069772A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a packaging structure for a cascaded device and a cascaded device. Background Technology
[0002] With the development of technology, cascaded devices have been widely used in low-power consumer applications. Cascaded devices have significantly improved the efficiency and power density of switching power supplies and are cost-effective, thus receiving widespread acclaim.
[0003] In related technologies, cascaded devices typically involve connecting two switching devices in series. However, cascaded devices have not yet gained widespread acceptance in high-power industrial applications because the increased operating current leads to a higher risk of high-frequency oscillations. Summary of the Invention
[0004] The purpose of this application is to provide a packaging structure and a cascaded device to address the shortcomings of the prior art, thereby solving the aforementioned technical problems in the related art.
[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a packaging structure for a cascaded device. The packaging structure includes: a packaging frame, a first power device, and a second power device mounted on the packaging frame. The packaging frame is provided with: a device source region, a device drain region, and a device gate region. The drain of the first power device is connected to the device drain region, the source of the first power device is connected to the drain of the second power device, the gate of the first power device and the source of the second power device are both connected to the device source region, and the gate of the second power device is connected to the device gate region. The gate of the first power device is electrically connected to the gate pad of the first power device, thereby forming a first parasitic capacitance between the gate and the drain of the first power device; the gate field plate and / or shielding layer of the first power device are electrically connected to the conductive frame on the package frame, thereby forming a second parasitic capacitance between the drain of the first power device and the gate field plate and / or the shielding layer; the shielding layer is a shielding layer between the surface pad and the internal metal layer of the first power device.
[0006] Optionally, the gate, the gate field plate, and the shielding layer of the first power device are electrically connected to the conductive substrate or the conductive frame of the first power device through through-holes inside the first power device.
[0007] Optionally, the packaging frame is further provided with a bypass gate current pad for the first power device, the gate field plate and / or the shielding layer are electrically connected to the bypass gate current pad, and the bypass gate current pad is also electrically connected to the conductive frame.
[0008] Optionally, the gate field plate and / or the shielding layer are electrically connected to the bypass gate current pad via metal lines, and the bypass gate current pad is electrically connected to the conductive frame via metal lines.
[0009] Optionally, the conductive frame is the source frame of the source region of the device.
[0010] Optionally, the packaging frame is provided with a plurality of gate pads for the first power device, the gate of the first power device is electrically connected to the plurality of gate pads, the plurality of gate pads are evenly distributed, and the plurality of gate pads are electrically connected to the source of the second power device.
[0011] Optionally, the second power device is disposed on the substrate, and the plurality of gate pads are electrically connected to the source frame on the package frame through a plurality of through holes on the substrate, and the source of the second power device is electrically connected to the source frame.
[0012] Optionally, the conductive frame is the source frame of the source region of the device, and the packaging structure further includes: a first resistor and a second resistor; One end of the first resistor is electrically connected to the gate of the first power device, and the other end of the first resistor is electrically connected to the source frame; one end of the second resistor is electrically connected to the gate field plate and / or the shielding layer, and the other end of the second resistor is electrically connected to the source frame.
[0013] Optionally, the first power device is a normally-on power device, and the second power device is a normally-off power device.
[0014] Secondly, embodiments of this application also provide a cascaded device, including: the packaging structure of the cascaded device described in any of the first aspects above.
[0015] The beneficial effects of this application are as follows: This application provides a packaging structure for a cascaded device and a cascaded device. The packaging structure includes: a packaging frame, a first power device and a second power device mounted on the packaging frame; the packaging frame is provided with: a device source region, a device drain region and a device gate region; the drain of the first power device is connected to the device drain region, the source of the first power device is connected to the drain of the second power device, the gate of the first power device and the source of the second power device are both connected to the device source region, and the gate of the second power device is connected to the device gate region; the gate of the first power device is electrically connected to the gate pad of the first power device, so that a first parasitic capacitance is formed between the gate and the drain of the first power device; the gate field plate and / or shielding layer of the first power device are electrically connected to the conductive frame on the packaging frame, so that a second parasitic capacitance is formed between the drain of the first power device and the gate field plate and / or shielding layer; the shielding layer is a shielding layer between the surface pad and the internal metal layer of the first power device. The gate field plate and / or shielding layer of the first power device are electrically connected to the conductive frame on the package frame. During switching transients, part of the current is bypassed by the gate field plate and shielding layer, bypassing the gate of the first power device, reducing the gate current of the first power device. This helps to suppress the risk of self-excited oscillation of the cascaded device. In addition, it reduces the gate-source voltage stress of the first power device and the drain-source voltage of the second power device, improving the switching reliability and durability of the cascaded device. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A schematic diagram of the packaging structure of a cascaded device provided in an embodiment of this application; Figure 2 A schematic cross-sectional structure of a first power device provided in an embodiment of this application. Figure 1 ; Figure 3 A schematic cross-sectional structure of a first power device provided in an embodiment of this application. Figure 2 ; Figure 4 A schematic diagram of the circuit structure of a cascaded device provided in an embodiment of this application; Figure 5 A schematic diagram of another cascaded device packaging structure provided in an embodiment of this application; Figure 6 This is a schematic diagram of the packaging structure of another cascaded device provided in an embodiment of this application. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.
[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0020] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0021] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0022] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.
[0023] Cascaded devices have not yet gained widespread acceptance in high-power industrial applications. This is because as the operating current increases, the impact of parasitic inductance in the system and devices also increases, leading to a higher risk of high-frequency oscillations.
[0024] The packaging structure of a cascaded device provided in this application can explain the above-mentioned technical problems. The following is an explanation of the packaging structure of a cascaded device provided in this application.
[0025] Figure 1 This is a schematic diagram of the packaging structure of a cascaded device provided in an embodiment of this application, as shown below. Figure 1 As shown, the package structure includes: a package frame 10, a first power device Q1 and a second power device Q2 mounted on the package frame 10; the package frame 10 is provided with: a device source region 11, a device drain region 12 and a device gate region 13, the drain of the first power device Q1 is connected to the device drain region 12, the source of the first power device Q1 is connected to the drain of the second power device Q2, the gate of the first power device Q1 and the source of the second power device Q2 are both connected to the device source region 11, and the gate of the second power device Q2 is connected to the device gate region 13; The gate of the first power device Q1 is electrically connected to the gate pad 14 of the first power device Q1, so that a first parasitic capacitance is formed between the gate and the drain of the first power device Q1; the gate field plate and / or shielding layer of the first power device Q1 are electrically connected to the conductive frame on the package frame 10, so that a second parasitic capacitance is formed between the drain and the gate field plate and / or shielding layer of the first power device Q1; the shielding layer is the shielding layer between the surface pad and the internal metal layer of the first power device Q1.
[0026] Wherein, the gate field plate and / or shielding layer of the first power device Q1 are electrically connected to the conductive frame on the packaging frame 10, which means: only the gate field plate is electrically connected to the conductive frame, or only the shielding layer is electrically connected to the conductive frame, or both the gate field plate and the shielding layer are electrically connected to the conductive frame.
[0027] In addition, surface pads refer to the pads on the surface of the package structure of the cascaded device. The internal metal layer includes the metal layer corresponding to the source and drain of the first power device Q1, and the surface pads include the pads corresponding to the source and drain of the first power device Q1.
[0028] It should be noted that in related technologies, the gate field plate, shielding layer, and gate of the first power device Q1 are all electrically connected to the gate pad of the first power device Q1. This results in parasitic capacitances forming between the gate field plate and the drain of the first power device Q1, between the gate and the drain of the first power device Q1, and between the shielding layer and the drain of the first power device Q1. These parasitic capacitances are relatively large. However, in this embodiment, only the gate of the first power device Q1 is electrically connected to its gate pad, and a first parasitic capacitance is formed between the gate and the drain of the first power device Q1. The gate field plate and / or shielding layer of the first power device Q1 are instead electrically connected to the conductive frame on the packaging frame 10, resulting in a second parasitic capacitance forming between the drain of the first power device Q1 and the gate field plate and / or shielding layer.
[0029] In this embodiment, a second parasitic capacitance is formed, and the first parasitic capacitance is significantly reduced compared to parasitic capacitances in related technologies. Thus, during switching transients, some current flows through the second parasitic capacitance, significantly reducing the current flowing through the first parasitic capacitance. Specifically, some current is bypassed by the shielding layer, gate field plate, and conductive frame, bypassing the gate of the first power device Q1, thereby reducing the current flowing through the gate of the first power device Q1.
[0030] In addition, reducing the gate current of the first power device Q1 will reduce the interference of the parasitic inductance on the gate-source voltage Vgs of the first power device Q1. The requirements of the cascaded device on the gate parasitic inductance of the first power device Q1 will be reduced accordingly. This will help suppress the risk of self-oscillation of the cascaded device, reduce the gate-source voltage stress Vgs of the first power device Q1 and the drain-source voltage Vds of the second power device Q2, and improve the switching reliability and durability of the cascaded device.
[0031] It is worth noting that, compared to electrically connecting only the gate field plate or the shielding layer to the conductive frame on the package frame 10, the method of electrically connecting both the gate field plate and the shielding layer to the conductive frame on the package frame 10 can better reduce the current flowing through the gate of the first power device Q1.
[0032] like Figure 1 As shown, the packaging structure may further include: a substrate 15, wherein the drain D2 on the back side of the second power device Q2 is attached to the conductive metal region 16 on the front side of the substrate 15 by conductive adhesive or the like, wherein the drain of the second power device Q2 is located on the back side. Figure 1 The figures are not shown in the diagram. It should be noted that in this embodiment, the gate field plate and / or shielding layer of the first power device Q1 are replaced with conductive frames on the package frame 10. For the remaining structure and arrangement of the package structure of the cascaded device, the figures provided in this embodiment are merely examples, and it should be understood that this embodiment does not impose specific limitations on them.
[0033] In addition, the device source region 11, the device drain region 12, and the device gate region 13 can be represented as S, D, and G, respectively.
[0034] In summary, this application provides a cascaded device packaging structure, which includes a packaging frame 10, a first power device Q1 and a second power device Q2 mounted on the packaging frame 10. The packaging frame 10 is provided with a device source region 11, a device drain region 12, and a device gate region 13. The drain of the first power device Q1 is connected to the device drain region 12, the source of the first power device Q1 is connected to the drain of the second power device Q2, and the gate of the first power device Q1 and the source of the second power device Q2 are both connected to the device source region. 11. The gate of the second power device Q2 is connected to the gate region 13 of the device; the gate of the first power device Q1 is electrically connected to the gate pad of the first power device Q1, so that a first parasitic capacitance is formed between the gate and drain of the first power device Q1; the gate field plate and / or shielding layer of the first power device Q1 are electrically connected to the conductive frame on the package frame 10, so that a second parasitic capacitance is formed between the drain of the first power device Q1 and the gate field plate and / or shielding layer; the shielding layer is a shielding layer between the surface pad and the internal metal layer of the first power device Q1. The gate field plate and / or shielding layer of the first power device Q1 are electrically connected to the conductive frame on the package frame 10. During switching transients, part of the current is bypassed by the gate field plate and the shielding layer, bypassing the gate of the first power device Q1, reducing the gate current of the first power device Q1, thereby helping to suppress the risk of self-oscillation of cascaded devices. Moreover, it reduces the gate-source voltage stress of the first power device Q1 and the drain-source voltage of the second power device Q2, improving the switching reliability and durability of the cascaded devices.
[0035] Optionally, the gate, gate field plate, and shielding layer of the first power device Q1 are electrically connected to the conductive substrate or conductive frame of the first power device Q1 through through-holes.
[0036] Figure 2 A schematic cross-sectional structure of a first power device provided in an embodiment of this application. Figure 1 ,like Figure 2 As shown, the first power device Q1 includes: a substrate 111, a channel layer 112 and a barrier layer 113 epitaxially formed on the substrate 111, a gate dielectric layer 114, a drain structure 121, a gate structure 122, a source structure 123, a first passivation dielectric layer 115, a shielding layer 141 provided above the first passivation dielectric layer 115, a second passivation dielectric layer 116 covering all shielding layers 141, and a drain pad 131, a source pad 133, and a gate pad (not shown) provided on the second passivation dielectric layer 116.
[0037] Among them, such as Figure 2As shown, the gate structure 122 of the first power device Q1 is connected to the substrate 111 through a via, and the shielding layer 141 of the first power device Q1 is also connected to the substrate 111 through a via. The substrate 111 is conductive to the conductive frame disposed below the substrate. Alternatively, the gate structure 122 of the first power device Q1 can be directly connected to the conductive frame through a via, and similarly, the shielding layer 141 of the first power device Q1 can be directly connected to the conductive frame through a via.
[0038] Figure 3 A schematic cross-sectional structure of a first power device provided in an embodiment of this application. Figure 2 ,like Figure 3 As shown, in the pad structure of the first power device Q1, the source pad, drain pad 42 and gate pad are electrically connected to the source structure 123, drain structure 121 and gate structure 122 respectively through dielectric vias to form the source S, drain D and gate G of the device. The dielectric layer 20 partially covers the upper surface of the pad structure, as long as there is enough space on the upper surface of the pad structure 40 to form an electrical connection with the outside. The dielectric layer includes: passivation layer 200, third dielectric layer 203 deposited on passivation layer 200, first dielectric layer 201 deposited above the electrode structure, first gate field plate 51 deposited on the upper surface of first dielectric layer 201, fourth dielectric layer 204, second gate field plate 52 deposited on fourth dielectric layer 204, fifth dielectric layer 205, third gate field plate 53 deposited on fifth dielectric layer 205, and second dielectric layer 202 deposited on third gate field plate 53.
[0039] like Figure 3 As shown, the gate structure 122 of the first power device Q1 is connected to the substrate 111 through vias, and the first gate field plate 51, the second gate field plate 52, and the third gate field plate 53 of the first power device Q1 are also connected to the substrate 111 through vias. The substrate 111 is conductive to the conductive frame disposed below the substrate. Alternatively, the gate structure 122 of the first power device Q1 can be directly connected to the conductive frame through vias, and similarly, the first gate field plate 51, the second gate field plate 52, and the third gate field plate 53 of the first power device Q1 can be directly connected to the conductive frame through vias.
[0040] It should be noted that, Figure 2 and Figure 3 The internal structure of the first power device Q1 provided in the example is only one example, and the embodiments of this application do not impose specific limitations on the internal structure of the first power device Q1.
[0041] In summary, the embodiments of this application separate the gate field plate and / or shielding layer of the first power device Q1 from the gate of the first power device Q1 by drilling holes, thereby reducing the charging and discharging current of the gate parasitic capacitance of the first power device Q1.
[0042] Optionally, such as Figure 1 As shown, the package frame 10 is also provided with a bypass gate current pad 17 for the first power device Q1. The gate field plate and / or shielding layer are electrically connected to the bypass gate current pad 17, and the bypass gate current pad 17 is also electrically connected to the conductive frame.
[0043] Optionally, the gate pad and / or bypass gate current pad 17 of the first power device Q1 can also be directly electrically connected to the source of the second power device Q2, or the gate pad and / or bypass gate current pad 17 of the first power device Q1 can also be electrically connected to the source region 11 of the device or the source of the second power device Q2 through an external resistor of the cascaded device.
[0044] Optionally, the gate field plate and / or shielding layer are electrically connected to the bypass gate current pad 17 via metal wires, and the bypass gate current pad 17 is electrically connected to the conductive frame via metal wires.
[0045] Specifically, the gate field plate and / or shielding layer of the first power device Q1 are replaced with an electrical connection to the bypass gate current pad 17 on the package frame 10, and a second parasitic capacitance is formed between the gate field plate and / or shielding layer of the first power device Q1 and the drain. The bypass gate current pad 17 can also be referred to as the BGC pad.
[0046] In this embodiment, during the switching transient, a portion of the current is bypassed by the shielding layer, the gate field plate, and the bypass gate current pad 17, thus bypassing the gate of the first power device Q1 and reducing the gate current of the drive circuit of the first power device Q1.
[0047] It should be noted that in this embodiment, the number of bypass gate current pads 17 is one, or there may be multiple, and they may be designed at different positions of the first power device Q1. This embodiment does not impose specific limitations on this.
[0048] Figure 4 A circuit structure diagram of a cascaded device provided in an embodiment of this application is shown below. Figure 4 As shown, the drain of the first power device Q1 is connected to the drain region 12, the source of the first power device Q1 is connected to the drain of the second power device Q2, the gate of the first power device Q1 and the source of the second power device Q2 are both connected to the source region 11, and the gate of the second power device Q2 is connected to the gate region 13. A first parasitic capacitance Cgd is formed between the gate and drain of the first power device Q1, and a second parasitic capacitance Cbd is formed between the gate of the first power device Q1 and the bypass gate current pad 17. Figure 4 All the inductors in the diagram are parasitic inductors.
[0049] Optionally, the conductive frame is the source frame of the device source region 11.
[0050] It should be noted that the connection point of the bypass gate current pad 17 and the connection point of the gate of the first power device Q1 are both source frames. The parasitic capacitance of the overall cascaded device remains unchanged and does not affect its switching speed.
[0051] In summary, the cascaded device packaging structure provided in this application reduces the current passing through the gate drive circuit of the first power device Q1 during switching transients, thereby avoiding parasitic inductance and resistance interference with the gate signal of the first power device Q1, reducing the design difficulty of the cascaded device, and improving its performance, switching reliability and durability.
[0052] Optionally, the package frame 10 is provided with a plurality of gate pads for the first power device Q1, the gate of the first power device Q1 is electrically connected to the plurality of gate pads, the plurality of gate pads are evenly distributed, and the plurality of gate pads are electrically connected to the source of the second power device Q2.
[0053] Optionally, the second power device Q2 is disposed on the substrate 15, and the plurality of gate pads are electrically connected to the source frame on the package frame 10 through the plurality of through holes on the substrate 15, and the source of the second power device Q2 is electrically connected to the source frame.
[0054] Figure 5 A schematic diagram of another cascaded device packaging structure provided in this application embodiment is shown below. Figure 5 As shown, the drain of the second power device Q2 is connected to the first electrode, which is disposed on the substrate 15. Multiple second electrodes are also deployed on the substrate 15. Multiple gate pads are connected to the multiple second electrodes. The second electrodes are electrically connected to the source frame on the packaging frame 10 through through-holes on the substrate 15. The source of the second power device Q2 is electrically connected to the source frame.
[0055] In this embodiment, multiple gate pads are evenly distributed, and multiple second electrodes are also evenly distributed. This results in symmetrical distribution of gate connections between the multiple gate pads and the multiple second electrodes, which disperses the charging and discharging current of the parasitic capacitance switching transient of the first power device Q1, and at the same time reduces the gate parasitic inductance of the first power device Q1.
[0056] Optionally, the package structure further includes: a first resistor R1 and a second resistor R2; like Figure 4 As shown, one end of the first resistor is electrically connected to the gate of the first power device Q1, and the other end of the first resistor is electrically connected to the source frame; one end of the second resistor is electrically connected to the gate field plate and / or the shielding layer, and the other end of the second resistor is electrically connected to the source frame.
[0057] It should be noted that after the gate parasitic capacitance of the first power device Q1 is reduced, a first resistor with a resistance value smaller than the preset resistance value is connected in series in the drive circuit of the first power device Q1. For example, the preset resistance value can be 1000 ohms. This can avoid the first parasitic capacitance Cgd and the parasitic inductance of the first power device Q1 forming a low-damping circuit. Since the first parasitic capacitance is small, its charging current is reduced accordingly. The first resistor will not have a significant impact on the drain-source voltage stress of the second power device Q2, and the loss on the first resistor is also very small.
[0058] In addition, a second resistor is connected in series in the circuit of the second parasitic capacitor. The second parasitic capacitor and the second resistor form an RC absorption circuit to suppress oscillation. Since it is not directly connected to the gate of the first power device Q1, except for energy loss in the second resistor during switching, it has no effect on other performance of the device.
[0059] It should be noted that the first resistor R1 and the second resistor R2 are resistive devices, and of course, they can also be implemented by means of parasitic resistance. This application does not impose specific limitations on this.
[0060] Optionally, the first power device Q1 is a normally-on power device, and the second power device Q2 is a normally-off power device.
[0061] Among them, the first power device Q1 is a high-voltage normally-on power device, and the second power device Q2 is a low-voltage normally-off power device.
[0062] Figure 6 A schematic diagram of the packaging structure of another cascaded device provided in the embodiments of this application is shown below. Figure 6 As shown, the bypass gate current pad 17 is electrically connected to the conductive metal region 16 on the front side of the substrate 15. Since the drain D2 on the back side of the second power device Q2 is attached to the conductive metal region 16 on the front side of the substrate 15 by conductive adhesive or the like, the bypass gate current pad 17 can be electrically connected to the drain on the back side of the second power device Q2. The bypass gate current pad 17 is electrically connected to the conductive metal region 16 on the front side of the substrate 15 by a metal wire.
[0063] It should be noted that by electrically connecting the bypass gate current pad 17 to the drain on the back of the second power device Q2, the Coss parasitic capacitance of the cascaded device can be minimized. The parasitic capacitance of the cascaded device can be flexibly adjusted externally without modifying the internal structure of the first power device Q1, requiring minimal overall design changes and improving the ease of adjusting the parasitic capacitance of the cascaded device.
[0064] This application also provides a cascaded device, including the packaging structure of the cascaded device described above.
[0065] In summary, the cascaded device packaging structure and cascaded device provided in this application embodiment utilize the bypass gate current pad 17 to bypass part of the charging and discharging current of the parasitic capacitance during the switching transient of the first power device Q1. This prevents the current from passing through the parasitic inductance and resistance of the gate of the first power device Q1, thus avoiding interference with the gate drive signal of the relatively sensitive first power device Q1. This suppresses the self-oscillation of the cascaded device and improves its switching reliability.
[0066] Furthermore, in switching applications, the voltage difference between the first power device Q1 (Vgs) and the second power device Q2 (Vds) decreases during turn-off or freewheeling conduction transients. This reduces the voltage stress on the second power device Q2 (Vds) and the gate voltage stress on the first power device Q1, mitigating the performance degradation problem of the first power device Q1 and improving the long-term reliability of the cascaded devices. After the gate current of the first power device Q1 is bypassed, the current entering its gate interdigitates decreases; this helps to balance the gate signal on the chip, improve internal dynamic current sharing, and simplify device layout design. Additionally, modifications to the packaging allow for convenient and flexible adjustment of the internal parasitic capacitance value of the device.
[0067] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A packaging structure for a cascaded device, characterized in that, The packaging structure includes: a packaging frame, a first power device and a second power device mounted on the packaging frame; the packaging frame is provided with: a device source region, a device drain region and a device gate region, the drain of the first power device is connected to the device drain region, the source of the first power device is connected to the drain of the second power device, the gate of the first power device and the source of the second power device are both connected to the device source region, and the gate of the second power device is connected to the device gate region; The gate of the first power device is electrically connected to the gate pad of the first power device, thereby forming a first parasitic capacitance between the gate and the drain of the first power device; the gate field plate and / or shielding layer of the first power device are electrically connected to the conductive frame on the package frame, thereby forming a second parasitic capacitance between the drain of the first power device and the gate field plate and / or the shielding layer; the shielding layer is a shielding layer between the surface pad and the internal metal layer of the first power device.
2. The packaging structure according to claim 1, characterized in that, The gate, the gate field plate, and the shielding layer of the first power device are electrically connected to the conductive substrate or the conductive frame of the first power device through through-holes inside the first power device.
3. The packaging structure according to claim 1, characterized in that, The packaging frame is further provided with a bypass gate current pad for the first power device, the gate field plate and / or the shielding layer are electrically connected to the bypass gate current pad, and the bypass gate current pad is also electrically connected to the conductive frame.
4. The packaging structure according to claim 3, characterized in that, The gate field plate and / or the shielding layer are electrically connected to the bypass gate current pad via metal wires, and the bypass gate current pad is electrically connected to the conductive frame via metal wires.
5. The packaging structure according to claim 3, characterized in that, The conductive framework is the source framework of the source region of the device.
6. The packaging structure according to claim 1, characterized in that, The packaging frame is provided with a plurality of gate pads for the first power device, the gate of the first power device is electrically connected to the plurality of gate pads, the plurality of gate pads are evenly distributed, and the plurality of gate pads are electrically connected to the source of the second power device.
7. The packaging structure according to claim 6, characterized in that, The second power device is disposed on the substrate, and the plurality of gate pads are electrically connected to the source frame on the package frame through the plurality of through holes on the substrate. The source of the second power device is electrically connected to the source frame.
8. The packaging structure according to claim 1, characterized in that, The conductive frame is the source frame of the source region of the device, and the packaging structure further includes: a first resistor and a second resistor; One end of the first resistor is electrically connected to the gate of the first power device, and the other end of the first resistor is electrically connected to the source frame; one end of the second resistor is electrically connected to the gate field plate and / or the shielding layer, and the other end of the second resistor is electrically connected to the source frame.
9. The packaging structure according to any one of claims 1-8, characterized in that, The first power device is a normally-on power device, and the second power device is a normally-off power device.
10. A cascaded device, characterized in that, include: The packaging structure of the cascaded device according to any one of claims 1-9 above.