Signal generation circuit, driving method thereof and display module

Abstract

The invention discloses a signal generation circuit, a driving method thereof and a display module. A first signal control module (10) in the signal generation circuit is used for sequentially outputting n first transition control signals (V0n) to a first signal generation module (20), wherein n is an integer greater than or equal to 1; after the n first transition control signals (V0n) are output, a first target control signal (V0b) is output to the first signal generation module (20); the first signal generation module (20) is used for sequentially outputting n first transition level signals (V1n) according to the n first transition control signals (V0n) and finally outputting a first target level signal (V1b) according to the first target control signal (V0b); when ngt; when 1 is greater than 1, the voltage values of the n first transition level signals (V1n) are sequentially reduced according to the output sequence, and the voltage value of the first target level signal (V1b) is smaller than the voltage value of the first transition level signal (V1n).

Description

Signal generation circuit, driving method thereof and display module TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a signal generation circuit, a driving method thereof and a display module. BACKGROUND

[0002] Organic light-emitting diode (OLED) display products are favored by the market of high-end flagship mobile terminals due to their good flexibility, high luminous efficiency and high definition. In order to further reduce the power consumption of display products, the display products adopt a scheme of supplying power signals from an external power management chip.

[0003] SUMMARY

[0004] The present disclosure aims to provide a signal generation circuit, a driving method thereof and a display module.

[0005] In order to achieve the above-mentioned purpose, the present disclosure provides the following technical solutions:

[0006] The first aspect of the present disclosure provides a signal generation circuit, comprising: a first signal control module and a first signal generation module coupled with each other;

[0007] The first signal control module is configured to sequentially output n first transition control signals to the first signal generation module, n being an integer greater than or equal to 1; and output a first target control signal to the first signal generation module after outputting the n first transition control signals;

[0008] The first signal generation module is configured to sequentially output n first transition level signals according to the n first transition control signals, and finally output a first target level signal according to the first target control signal; when n>1, the voltage values of the n first transition level signals decrease in turn according to the output order, and the voltage value of the first target level signal is less than the voltage values of the first transition level signals.

[0009] Optionally, when n=1, the absolute value of the voltage value of one first transition level signal output by the first signal generation module is equal to 1 / 2 of the voltage value of the first target level signal.

[0010] When n>1, the mth first transition level signal and the m+1th first transition level signal among the n first transition level signals sequentially output by the first signal generation module have a fixed first voltage difference, m satisfying: 1≤m≤n-1; the nth first transition level signal and the first target level signal have the first voltage difference.

[0011] Optionally, when n = 1, the absolute value of the voltage value of a first transition level signal output by the first signal generation module is less than or greater than 1 / 2 of the voltage value of the first target level signal;

[0012] When n > 1, the first signal generation module sequentially outputs n first transition level signals, and the mth first transition level signal and the (m+1)th first transition level signal have a second voltage difference value, m satisfies: 1≤m≤n-1; the second voltage difference value sequentially increases or decreases according to the output order; the nth first transition level signal and the first target level signal have a third voltage difference value, and the third voltage difference value is greater than or less than the second voltage difference value.

[0013] Optionally, the first signal generation module outputs a time interval of each of the first transition level signals, and a time interval between the last output first transition level signal and the first target level signal is equal; or,

[0014] The first signal generation module outputs a time interval of each of the first transition level signals, and a time interval between the last output first transition level signal and the first target level signal sequentially increases; or,

[0015] The first signal generation module outputs a time interval of each of the first transition level signals, and a time interval between the last output first transition level signal and the first target level signal sequentially decreases.

[0016] Optionally, the signal generation circuit further comprises a second signal control module and a second signal generation module coupled with each other;

[0017] The second signal control module is configured to sequentially output i second transition control signals to the second signal generation module, i being an integer greater than or equal to 1; and output a second target control signal to the second signal generation module after outputting the i second transition control signals;

[0018] The second signal generation module is configured to sequentially output i second transition level signals according to the i second transition control signals, and finally output a second target level signal according to the second target control signal; when i > 1, the voltage values of the i second transition level signals sequentially decrease according to the output order, and the voltage value of the second target level signal is less than the voltage values of the second transition level signals.

[0019] Optionally, when i = 1, the absolute value of the voltage value of a second transition level signal output by the second signal generation module is equal to 1 / 2 of the voltage value of the second target level signal;

[0020] When i>1, among the i second transition level signals outputted by the second signal generating module in sequence, a jth second transition level signal and a (j+1)th second transition level signal have a fixed second voltage difference, j satisfying: 1≤j≤i-1; an ith second transition level signal and the second target level signal have the second voltage difference.

[0021] Optionally, when i=1, an absolute value of a voltage value of a second transition level signal outputted by the second signal generating module is less than or greater than 1 / 2 of a voltage value of the second target level signal;

[0022] When i>1, among the i second transition level signals outputted by the second signal generating module in sequence, a jth second transition level signal and a (j+1)th second transition level signal have a second voltage difference, j satisfying: 1≤j≤i-1; the second voltage difference increases or decreases in turn according to the output order; an ith second transition level signal and the second target level signal have a third voltage difference, the third voltage difference being greater than or less than the second voltage difference.

[0023] Optionally, the second signal generating module outputs a time interval of each second transition level signal, and a time interval between a last outputted second transition level signal and the second target level signal is equal; or,

[0024] The second signal generating module outputs a time interval of each second transition level signal, and a time interval between a last outputted second transition level signal and the second target level signal increases in turn; or,

[0025] The second signal generating module outputs a time interval of each second transition level signal, and a time interval between a last outputted second transition level signal and the second target level signal decreases in turn.

[0026] Optionally, a time when the first signal control module outputs a first first transition control signal to the first signal generating module is the same as a time when the second signal control module outputs a first second transition control signal to the second signal generating module.

[0027] Optionally, the signal generation circuit further comprises a third signal generation module coupled to the first signal generation module, the third signal generation module being configured to output two groups of transition signals according to the n first transition level signals output by the first signal generation module, each group of transition signals being output by sequentially outputting n transition power signals; the third signal generation module is further configured to finally output two target power signals according to the first target level signal output by the first signal generation module; when n > 1, the voltage values of the n transition power signals sequentially decrease in output order, and the voltage value of the target power signal is less than the voltage values of the transition power signals.

[0028] Based on the technical scheme of the above signal generation circuit, the second aspect of the present disclosure provides a display module comprising the above signal generation circuit; the display module further comprises a driving chip and a power management chip; the first signal control module, the third signal generation module, the second signal control module and the second signal generation module in the signal generation circuit are integrated in the driving chip, and the first signal generation module in the signal generation circuit is integrated in the power management chip.

[0029] Optionally, the display module further comprises a display panel and a gate drive circuit, the display panel comprises at least two display regions with different refresh rates, and the gate drive circuit comprises at least two sub-drive circuits, the sub-drive circuits being configured to drive the corresponding display regions to display.

[0030] The display module comprises at least two signal generation circuits; in different signal generation circuits, the number of first transition control signals output by the first signal control module is different, and the number of first transition level signals output by the first signal generation module is different; the signal generation circuit is configured to provide target power signals for the corresponding sub-drive circuits.

[0031] Based on the technical scheme of the above signal generation circuit, the third aspect of the present disclosure provides a driving method of a signal generation circuit, for driving the above signal generation circuit; the driving method comprises:

[0032] The first signal control module sequentially outputs n first transition control signals to the first signal generation module, n being an integer greater than or equal to 1; and after outputting the n first transition control signals, the first signal control module outputs a first target control signal to the first signal generation module;

[0033] The first signal generation module sequentially outputs n first transition level signals according to the n first transition control signals, and finally outputs a first target level signal according to the first target control signal; when n>1, voltage values of the n first transition level signals decrease in turn according to the output order, and a voltage value of the first target level signal is less than voltage values of the first transition level signals.

[0034] Optionally, the signal generation circuit further comprises a second signal control module and a second signal generation module coupled with each other; and the driving method further comprises:

[0035] The second signal control module sequentially outputs i second transition control signals to the second signal generation module, i being an integer greater than or equal to 1; and outputs a second target control signal to the second signal generation module after outputting the i second transition control signals;

[0036] The second signal generation module sequentially outputs i second transition level signals according to the i second transition control signals, and finally outputs a second target level signal according to the second target control signal; when i>1, voltage values of the i second transition level signals decrease in turn according to the output order, and a voltage value of the second target level signal is less than voltage values of the second transition level signals.

[0037] Optionally, at the same time, the first signal control module outputs a first first transition control signal to the first signal generation module, and the second signal control module outputs a first second transition control signal to the second signal generation module. BRIEF DESCRIPTION OF DRAWINGS

[0038] The accompanying drawings, which are included to provide a further understanding of the present disclosure and constitute a part of the present disclosure, illustrate the exemplary embodiments of the present disclosure and serve to explain the present disclosure, and do not limit the present disclosure in any way. In the drawings:

[0039] FIG. 1 is a first module schematic diagram of a signal generation circuit provided by an embodiment of the present disclosure;

[0040] FIG. 2 is a second module schematic diagram of a signal generation circuit provided by an embodiment of the present disclosure;

[0041] FIG. 3 is a signal timing diagram provided by an embodiment of the present disclosure;

[0042] FIG. 4 is another signal timing diagram provided by an embodiment of the present disclosure;

[0043] FIG. 5 is still another signal timing diagram provided by an embodiment of the present disclosure;

[0044] FIG. 6 is a fourth signal timing diagram provided by an embodiment of the present disclosure. Detailed Implementation

[0045] To further illustrate the signal generation circuit and its driving method, as well as the display module provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0046] With the development of OLED technology, the pursuit of ultra-thinness within limited overall device space has placed higher demands on the extended battery life of mobile phones. Research has found that reducing the power consumption of display products can extend their battery life. Therefore, a solution using an external power supply signal from the power management chip was considered to reduce power consumption. However, when using this external power supply solution, the transient current during power-on is too large, which can overload the power management chip and cause a technical problem of screen display failure.

[0047] More specifically, Figure 3 illustrates the asynchronous power-on timing of the VGL and AVEE signals. When the power signal powers on, a large current is pumped into the power management chip, with the transient pump current far exceeding the chip's maximum allowable current. For example, the transient pump current may be 100mA to 300mA, specifically current I in Figure 3. Since the power management chip's maximum allowable current is 40mA, its overload protection mechanism is triggered, causing it to stop outputting the corresponding voltage, resulting in no display on the screen.

[0048] Please refer to Figure 1. This embodiment of the present disclosure provides a signal generation circuit, including: a first signal control module 10 and a first signal generation module 20 coupled together;

[0049] The first signal control module 10 is used to sequentially output n first transition control signals V0n to the first signal generation module 20, where n is an integer greater than or equal to 1; and after outputting the n first transition control signals V0n, output a first target control signal V0b to the first signal generation module 20.

[0050] The first signal generation module 20 is used to sequentially output n first transition level signals V1n according to the n first transition control signals V0n, and finally output a first target level signal V1b according to the first target control signal V0b; when n>1, the voltage values ​​of the n first transition level signals V1n decrease sequentially according to the output order, and the voltage value of the first target level signal V1b is less than the voltage value of the first transition level signal V1n.

[0051] Exemplarily, the first signal generation module 20 generates a first transition level signal V1n for each first transition control signal V0n received. The first first transition level signal V1n is obtained by pulling down a GND voltage level (i.e., a ground voltage having a 0V potential), the second first transition level signal V1n is obtained by further pulling down the first first transition level signal V1n, the third first transition level signal V1n is obtained by further pulling down the second first transition level signal V1n, and so on, and the first target level signal V1b is obtained by further pulling down the nth first transition level signal V1n.

[0052] Exemplarily, the voltage value of the first target level signal V1b is less than or equal to -10V, but is not limited thereto.

[0053] Exemplarily, the first target level signal V1b is a low-level signal, such as a VGL signal, but is not limited thereto.

[0054] Exemplarily, the voltage value of each first transition level signal V1n is negative, the voltage values of the n first transition level signals V1n decrease in output order, and the absolute values of the voltage values of the n first transition level signals V1n increase in output order. The voltage value of the first target level signal V1b is negative, the voltage value of the first target level signal V1b is less than the voltage value of the last output first transition level signal V1n, and the absolute value of the voltage value of the first target level signal V1b is greater than the absolute value of the voltage value of the last output first transition level signal V1n.

[0055] According to the specific structure of the signal generation circuit, the signal generation circuit provided by the embodiment of the present disclosure can sequentially output n first transition control signals V0n and a first target control signal V0b to the first signal generation module 20 through the first signal control module 10, so that the first signal generation module 20 can sequentially output n first transition level signals V1n according to the sequentially received first transition control signals V0n, and finally output a first target level signal V1b according to the first target control signal V0b. The above-mentioned manner makes the entire power-on process of the first target level signal V1b experience n+1 pull-down processes, i.e., in the power-on process, the initial voltage level is sequentially pulled down to the transition level values of the first transition level signals V1n, and finally the transition level value of the nth first transition level signal V1n is pulled down to the target level value of the first target level signal V1b, and the power-on of the first target level signal V1b is completed.

[0056] It can be seen that in the signal generation circuit provided by the embodiment of the present disclosure, during the power-on process, the first signal control module 10 outputs control signals (i.e., n first transition control signals V0n and a first target control signal V0b) to the first signal generation module 20 multiple times, so that the voltage level of the first signal generation module 20 is gradually lowered, and finally the output of the first target level signal V1b is realized. Therefore, when the signal generation circuit is applied to a display product, and the first signal generation module 20 in the signal generation circuit is used as an external power supply module in a power management chip, the amplitude and occurrence time of the transient current generated during the power-on process are effectively reduced, and the technical problem of screen display failure caused by the overload of the power management chip due to the excessive transient current when the first target level signal V1b is powered on in one step can be avoided.

[0057] More specifically, as shown in FIG. 4, a timing diagram for step-by-step power-on of the VGL signal and the AVEE signal at the same time is shown. As shown in FIG. 5, a diagram of the transient current when n takes different values is shown. S1, S2, S3, and Sn in FIG. 4 represent the lowering process of each step in the step-by-step lowering. It can be seen that the larger the value of n, the more times the step-by-step lowering is performed, and the smaller the transient current drawn by the power management chip after the first target level signal V1b is powered on. In the signal generation circuit provided by the embodiment of the present disclosure, the transient current generated during the power-on process is less than 40 mA, and the action time is less than 0.6 ms.

[0058] In some embodiments, when n = 1, the absolute value of the voltage value of one first transition level signal V1n output by the first signal generation module 20 is equal to 1 / 2 of the voltage value of the first target level signal V1b.

[0059] When n > 1, among the n first transition level signals V1n output by the first signal generation module 20 in sequence, there is a fixed first voltage difference between the mth first transition level signal V1n and the (m+1)th first transition level signal V1n, and m satisfies: 1≤m≤n-1; and there is the first voltage difference between the nth first transition level signal V1n and the first target level signal V1b.

[0060] For example, among the n first transition level signals V1n output in sequence, there is a fixed first voltage difference between any two adjacent first transition level signals V1n, and there is the first voltage difference between the nth first transition level signal V1n and the first target level signal V1b; this setting mode enables the voltage level to be gradually lowered at a fixed first voltage difference during the power-on process, until the voltage value of the first target level signal V1b is reached, and the power-on process is completed.

[0061] The above settings allow the voltage level to be lowered more evenly during power-on, thereby more effectively reducing the amplitude and duration of transient current generated during power-on and avoiding abnormal problems caused by excessive transient current when the first target level signal V1b is powered on in one step.

[0062] In some embodiments, when n=1, the absolute value of the voltage of a first transition level signal V1n output by the first signal generation module 20 is less than or greater than 1 / 2 of the voltage value of the first target level signal V1b.

[0063] When n > 1, among the n first transition level signals V1n output sequentially by the first signal generation module 20, the m-th first transition level signal V1n and the (m+1)-th first transition level signal V1n have a second voltage difference, where m satisfies: 1 ≤ m ≤ n-1; the second voltage difference increases or decreases sequentially according to the output order; the n-th first transition level signal V1n and the first target level signal V1b have a third voltage difference, which is greater than or less than the second voltage difference.

[0064] For example, the second voltage difference increases sequentially according to the output order, and the third voltage difference is greater than the second voltage difference.

[0065] For example, in the output order, the second voltage difference decreases sequentially, and the third voltage difference is less than the second voltage difference.

[0066] For example, there is a second voltage difference between adjacent first transition level signals V1n, and at least two of the second voltage differences among the n first transition level signals V1n are different.

[0067] It should be noted that the second voltage difference can be the difference between the voltage value of the m-th first transition level signal V1n and the voltage value of the (m+1)-th first transition level signal V1n.

[0068] The above configuration allows for flexible configuration of the voltage values ​​of each first transition level signal V1n during power-on, thereby more effectively reducing the amplitude and duration of transient current generated during power-on and avoiding abnormal problems caused by excessive transient current when the first target level signal V1b is powered on in one step.

[0069] In some embodiments, the time interval between each of the first transition level signals V1n output by the first signal generation module 20, and the time interval between the last output first transition level signal V1n and the first target level signal V1b are equal; or,

[0070] The first signal generation module 20 outputs the time interval of each first transition level signal V1n, and the time interval between the last output first transition level signal V1n and the first target level signal V1b is sequentially increased; or,

[0071] The first signal generation module 20 outputs the time interval of each first transition level signal V1n, and the time interval between the last output first transition level signal V1n and the first target level signal V1b is sequentially decreased.

[0072] Exemplarily, in the time interval of each first transition level signal V1n output by the first signal generation module 20, and the time interval between the last output first transition level signal V1n and the first target level signal V1b, at least two time intervals are the same.

[0073] Exemplarily, in the time interval of each first transition level signal V1n output by the first signal generation module 20, and the time interval between the last output first transition level signal V1n and the first target level signal V1b, at least two time intervals are different.

[0074] It should be noted that each of the above time intervals has no specific requirements, and each time interval can be equal or unequal, which can be configured according to actual needs to achieve more flexible dynamic adjustment. For example: the power-on time of the entire first target level signal V1b is within 2ms, and if it is lowered 10 times, the lowering time of each time can be set to 0.2ms.

[0075] The above setting that the first signal generation module 20 outputs the time interval of each first transition level signal V1n, and the time interval between the last output first transition level signal V1n and the first target level signal V1b is equal, so that the occurrence time of each first transition level signal V1n can be uniformly configured during power-on, thereby more effectively reducing the transient current amplitude and occurrence time generated during power-on, and avoiding abnormal problems caused by excessive transient current when the first target level signal V1b is powered on at one step.

[0076] The above setting that the first signal generation module 20 outputs the time interval of each first transition level signal V1n, and the time interval between the last output first transition level signal V1n and the first target level signal V1b is equal, so that the occurrence time of each first transition level signal V1n can be uniformly configured during power-on, thereby more effectively reducing the transient current amplitude and occurrence time generated during power-on, and avoiding abnormal problems caused by excessive transient current when the first target level signal V1b is powered on at one step.

[0077] As shown in FIG. 2, in some embodiments, the signal generation circuit further comprises a second signal control module 30 and a second signal generation module 40 coupled with each other;

[0078] The second signal control module 30 is configured to sequentially output i second transition control signals V3i to the second signal generation module 40, where i is an integer greater than or equal to 1, and output a second target control signal V3b to the second signal generation module 40 after outputting the i second transition control signals V3i.

[0079] The second signal generation module 40 is configured to sequentially output i second transition level signals V2i according to the i second transition control signals V3i, and finally output a second target level signal V2b according to the second target control signal V3b. When i > 1, the voltage values of the i second transition level signals V2i decrease sequentially according to the output order, and the voltage value of the second target level signal V2b is less than the voltage values of the second transition level signals V2i.

[0080] For example, the second signal control module 30 and the second signal generation module 40 both belong to a driving chip. The second signal control module 30 can be output synchronously with the first signal generation module 20, or can be output asynchronously with the first signal generation module 20. The output time of the second signal control module 30 can be independently controlled according to actual driving needs, thereby controlling the output time of the second target level signal V2b.

[0081] For example, the second signal generation module 40 generates a second transition level signal V2i in response to receiving each second transition control signal V3i. The first second transition level signal V2i is obtained by pulling down a voltage reference level once, and the voltage reference level can be selected as a ground voltage, i.e., having a 0V potential. The second second transition level signal V2i is obtained by further pulling down the first second transition level signal V2i. The third second transition level signal V2i is obtained by further pulling down the second second transition level signal V2i. Similarly, the second target level signal V2b is obtained by further pulling down the nth second transition level signal V2i.

[0082] For example, the second target level signal V2b includes an AVEE signal, but is not limited thereto. The functions of the AVEE signal mainly include: (1) providing a negative power supply for an analog circuit part in the driving chip, which includes operational amplifiers, comparators, etc., for processing signals and driving pixels to emit light; (2) using the AVEE signal together with other power supply signals (such as VDD signal, VGH signal, VGL signal, etc.) to ensure the stability and performance of display driving.

[0083] In the signal generation circuit provided by the above embodiment, the second signal control module 30 sequentially outputs i second transition control signals V3i and a second target control signal V3b to the second signal generation module 40, so that the second signal generation module 40 can sequentially output i second transition level signals V2i according to the sequentially received second transition control signals V3i, and finally output a second target level signal V2b according to the second target control signal V3b. In this way, the entire power-on process of the second target level signal V2b undergoes i+1 pull-down processes, that is, during the power-on process, the initial voltage level is sequentially pulled down to the transition level values of the second transition level signals V2i, and finally the transition level value of the i-th second transition level signal V2i is pulled down to the target level value of the second target level signal V2b, completing the power-on of the second target level signal V2b.

[0084] As can be seen, in the signal generation circuit provided by the above embodiment, during the power-on process, the second signal control module 30 outputs control signals (i.e., i second transition control signals V3i and a second target control signal V3b) to the second signal generation module 40 multiple times, so that the second signal generation module 40 gradually pulls down the voltage level, and finally realizes the output of the second target level signal V2b. Therefore, when the second target level signal V2b includes an AVEE signal, the transient current amplitude and occurrence time generated during the power-on process of the AVEE signal are effectively reduced, and abnormal problems caused by excessive transient current during one-step power-on of the AVEE signal can be avoided.

[0085] In some embodiments, when i = 1, the absolute value of the voltage value of one second transition level signal V2i output by the second signal generation module 40 is equal to 1 / 2 of the voltage value of the second target level signal V2b.

[0086] When i > 1, among the i second transition level signals V2i sequentially output by the second signal generation module 40, the j-th second transition level signal V2i and the j+1-th second transition level signal V2i have a fixed second voltage difference, j satisfies: 1≤j≤i-1; and the i-th second transition level signal V2i and the second target level signal V2b have the second voltage difference.

[0087] For example, in the i second transition level signals V2i outputted in sequence, any two adjacent second transition level signals V2i have a fixed second voltage difference, and the i-th second transition level signal V2i and the second target level signal V2b have the second voltage difference. In this way, during the power-on process, the voltage level can be gradually lowered by the fixed second voltage difference until the voltage value of the second target level signal V2b is reached, completing the power-on process.

[0088] In this way, during the power-on process, the voltage level can be lowered more uniformly, thereby more effectively reducing the transient current amplitude and occurrence time generated during the power-on process, and avoiding abnormal problems caused by excessive transient current when the second target level signal V2b is powered on in one step.

[0089] In some embodiments, when i = 1, the absolute value of the voltage value of one second transition level signal V2i outputted by the second signal generation module 40 is less than or greater than 1 / 2 of the voltage value of the second target level signal V2b.

[0090] When i > 1, in the i second transition level signals V2i outputted in sequence by the second signal generation module 40, the j-th second transition level signal V2i and the j+1-th second transition level signal V2i have a second voltage difference, and j satisfies: 1≤j≤i-1. According to the output order, the second voltage difference increases or decreases in sequence. The i-th second transition level signal V2i and the second target level signal V2b have a third voltage difference, and the third voltage difference is greater than or less than the second voltage difference.

[0091] For example, according to the output order, the second voltage difference increases in sequence, and the third voltage difference is greater than the second voltage difference.

[0092] For example, according to the output order, the second voltage difference decreases in sequence, and the third voltage difference is less than the second voltage difference.

[0093] For example, adjacent second transition level signals V2i have a second voltage difference, and in the i second transition level signals V2i, at least two of the second voltage differences are different.

[0094] It should be noted that the second voltage difference can be the difference between the voltage value of the j-th second transition level signal V2i and the voltage value of the j+1-th second transition level signal V2i.

[0095] The above setting mode can flexibly configure the voltage value of each second transition level signal V2i in the power-on process, thereby more effectively reducing the transient current amplitude and occurrence time generated in the power-on process, and avoiding abnormal problems caused by excessive transient current when the second target level signal V2b is powered on at one step.

[0096] In some embodiments, the second signal generation module 40 outputs the time interval of each second transition level signal V2i, and the time interval between the last output second transition level signal V2i and the second target level signal V2b is equal; or,

[0097] The second signal generation module 40 outputs the time interval of each second transition level signal V2i, and the time interval between the last output second transition level signal V2i and the second target level signal V2b is sequentially increased; or,

[0098] The second signal generation module 40 outputs the time interval of each second transition level signal V2i, and the time interval between the last output second transition level signal V2i and the second target level signal V2b is sequentially decreased.

[0099] For example, in the time interval of each second transition level signal V2i output by the second signal generation module 40, and the time interval between the last output second transition level signal V2i and the second target level signal V2b, at least two time intervals are the same.

[0100] For example, in the time interval of each second transition level signal V2i output by the second signal generation module 40, and the time interval between the last output second transition level signal V2i and the second target level signal V2b, at least two time intervals are different.

[0101] The above setting of the second signal generation module 40 outputting the time interval of each second transition level signal V2i and the time interval between the last output second transition level signal V2i and the second target level signal V2b being equal allows the occurrence time of each second transition level signal V2i to be uniformly configured in the power-on process, thereby more effectively reducing the transient current amplitude and occurrence time generated in the power-on process, and avoiding abnormal problems caused by excessive transient current when the second target level signal V2b is powered on at one step.

[0102] The time intervals of outputting each of the second transition level signals V2i and the time interval between the last output second transition level signal V2i and the second target level signal V2b are different, so that the occurrence time of each second transition level signal V2i can be flexibly configured during power-on, thereby more effectively reducing the transient current amplitude and occurrence time generated during power-on, and avoiding abnormal problems caused by excessive transient current when the second target level signal V2b is powered on at one step.

[0103] In some embodiments, the first signal control module 10 outputs the first first transition control signal V0n at the same time as the second signal control module 30 outputs the first second transition control signal V3i to the second signal generation module 40.

[0104] As shown in FIG. 4, the above setting mode enables the first target level signal V1b and the second target level signal V2b to be powered on synchronously, thereby ensuring that the two signals reach stability at the same time, ensuring that the display product can start in a stable voltage environment, and avoiding display abnormal problems.

[0105] Moreover, when the first level signal is a VGL signal and the second level signal is an AVEE signal, both the VGL signal and the AVEE signal are negative voltage signals, and the power management of the AVEE signal and the VGL signal can be dependent on each other. Powering on the two signals synchronously can simplify the design of the power management and ensure that all related circuits obtain the required voltage at the same time.

[0106] As shown in FIGS. 1, 2 and 4, in some embodiments, the signal generation circuit further comprises a third signal generation module 50 coupled with the first signal generation module 20, the third signal generation module 50 is configured to output two groups of transition signals according to the n first transition level signals V1n output by the first signal generation module 20, and the process of outputting each group of transition signals comprises sequentially outputting n transition power signals; the third signal generation module 50 is further configured to finally output two target power signals (such as Vd1 and Vd2) according to the first target level signal V1b output by the first signal generation module 20; when n>1, the voltage values of the n transition power signals decrease in turn according to the output order, and the voltage value of the target power signal is less than the voltage value of the transition power signal.

[0107] Exemplarily, the third signal generation module 50 includes an LDO (Low Dropout Linear Regulator) circuit, but is not limited thereto. The LDO circuit is configured to generate a VGLO1 signal (i.e., Vd1) and a VGLO2 signal (i.e., Vd2) according to the VGL signal, and the VGLO1 signal and the VGLO2 signal are used to drive the shift register in the display product.

[0108] The above-mentioned signal generation circuit includes the third signal generation module 50, so that the target power signal generated by the third signal generation module 50 can be pulled down step by step in the power-on process, thereby avoiding the abnormal problem caused by one-step power-on of the target power signal.

[0109] As shown in FIG. 2, the display module further includes a driving chip and a power management chip; the first signal control module 10, the third signal generation module 50, the second signal control module 30, and the second signal generation module 40 in the signal generation circuit are integrated in the driving chip, and the first signal generation module 20 in the signal generation circuit is integrated in the power management chip.

[0110] As shown in FIG. 6, the period between addresses 0x11 and 0x29 in FIG. 6 is the power-on period, and the first signal control module 10 and the first signal generation module 20 communicate signals through the I2C communication protocol, and four control signals (i.e., four downward pulses) communicated through the I2C channel are shown in FIG. 6, each control signal corresponds to the power-on of the VGL signal, the AVDD signal, the ELVDD signal, and the ELVSS signal.

[0111] It should be noted that the display module can be applied to any product or component with display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet computer, etc.

[0112] By integrating the above-mentioned signal generation circuit in the driving chip and the power management chip, and by applying the driving chip and the power management chip to the display product, the amplitude and occurrence time of the transient current generated in the power-on process are effectively reduced, thereby avoiding the technical problem of no display on the screen caused by the overload of the power management chip due to the excessive transient current when the first target level signal V1b is powered on in one step.

[0113] In some embodiments, the display module further includes a display panel and a gate drive circuit, the display panel includes at least two display regions with different refresh rates, and the gate drive circuit includes at least two sub-drive circuits, the sub-drive circuits are configured to drive the corresponding display regions to display.

[0114] The display module includes at least two signal generation circuits; in different signal generation circuits, the number of first transition control signals V0n output by the first signal control module 10 is different, and the number of first transition level signals V1n output by the first signal generation module 20 is different; the signal generation circuit is used to provide a target power signal for the corresponding sub-drive circuit.

[0115] Exemplarily, the display panel includes a liquid crystal display panel, an organic light-emitting diode display panel, etc., but is not limited thereto.

[0116] Exemplarily, the gate drive circuit includes at least two sub-drive circuits, and each sub-drive circuit includes a plurality of cascaded shift register units. For example, the types of the shift register units include GateP GOA, GateN GOA, and EM GOA. The GateP GOA is used to provide a scanning signal with a low-level pulse to a corresponding pixel drive circuit in the display panel to control a corresponding P-type transistor in the pixel drive circuit to be turned on. The GateN GOA is used to provide a scanning signal with a high-level pulse to a corresponding pixel drive circuit in the display panel to control a corresponding N-type transistor in the pixel drive circuit to be turned on. The EM GOA is used to provide an emission control scanning signal to a corresponding pixel drive circuit in the display panel to control a corresponding emission control transistor in the pixel drive circuit to be turned on.

[0117] Exemplarily, the display module includes at least two signal generation circuits; in different signal generation circuits, the value of n is different. The power signal corresponding to the first target level signal V1b output by the signal generation circuit with a larger value of n is used to provide a sub-drive circuit for driving a display area with a higher refresh frequency, and the power signal corresponding to the first target level signal V1b output by the signal generation circuit with a smaller value of n is used to provide a sub-drive circuit for driving a display area with a lower refresh frequency.

[0118] The above setting mode makes different display areas with different refresh frequencies correspond to different sub-drive circuits, different sub-drive circuits receive different target power signals, at least part of the different target power signals are provided by different signal generation circuits, and the value of n is different in different signal generation circuits. In this way, the number of step-down times of the target power signal can be matched with the refresh frequency of the display area driven by the target power signal, so that the driving demand is met while the instantaneous current generated by the power-on of the target power signal is better reduced, and the power consumption generated during the driving of the display is better reduced.

[0119] The disclosure also provides a driving method of a signal generation circuit, which is used to drive the signal generation circuit provided in the above embodiments; the driving method includes the following steps.

[0120] The first signal control module 10 outputs n first transition control signals V0n to the first signal generation module 20 in sequence, n is an integer greater than or equal to 1; and outputs a first target control signal V0b to the first signal generation module 20 after outputting the n first transition control signals V0n.

[0121] The first signal generation module 20 outputs n first transition level signals V1n in sequence according to the n first transition control signals V0n, and finally outputs a first target level signal V1b according to the first target control signal V0b; when n>1, the voltage values of the n first transition level signals V1n decrease in sequence according to the output order, and the voltage value of the first target level signal V1b is less than the voltage values of the first transition level signals V1n.

[0122] When the signal generation circuit is driven by the driving method provided by the embodiments of the present disclosure, the first signal control module 10 outputs n first transition control signals V0n and a first target control signal V0b to the first signal generation module 20 in sequence, so that the first signal generation module 20 can output n first transition level signals V1n in sequence according to the first transition control signals V0n received in sequence, and finally output a first target level signal V1b according to the first target control signal V0b; the above driving method makes the entire power-on process of the first target level signal V1b experience n+1 pull-down processes, that is, in the power-on process, the initial voltage level is pulled down to the transition level value of each first transition level signal V1n in sequence, and finally the transition level value of the n th first transition level signal V1n is pulled down to the target level value of the first target level signal V1b, and the power-on of the first target level signal V1b is completed.

[0123] As can be seen, when the signal generation circuit is driven by the driving method provided by the embodiments of the present disclosure, the first signal control module 10 outputs control signals to the first signal generation module 20 multiple times in the power-on process, so that the first signal generation module 20 gradually pulls down the voltage level, and finally realizes the output of the first target level signal V1b. Therefore, when the signal generation circuit is applied to a display product, and the first signal generation module 20 in the signal generation circuit is applied to a power management chip as an external power supply module, the transient current amplitude and occurrence time generated in the power-on process are effectively reduced, which can avoid the technical problem of screen no display caused by the overload of the power management chip due to the excessive transient current when the first target level signal V1b is powered on in one step.

[0124] In some embodiments, the signal generation circuit further comprises a second signal control module 30 and a second signal generation module 40 coupled; and the driving method further comprises:

[0125] The second signal control module 30 sequentially outputs i second transition control signals V3i to the second signal generation module 40, i being an integer greater than or equal to 1; and outputs a second target control signal V3b to the second signal generation module 40 after outputting the i second transition control signals V3i.

[0126] The second signal generation module 40 sequentially outputs i second transition level signals V2i according to the i second transition control signals V3i, and finally outputs a second target level signal V2b according to the second target control signal V3b; when i > 1, the voltage values of the i second transition level signals V2i decrease sequentially according to the output order, and the voltage value of the second target level signal V2b is less than the voltage values of the second transition level signals V2i.

[0127] When the driving method provided by the above embodiment is used to drive the signal generation circuit, the second signal control module 30 sequentially outputs i second transition control signals V3i and a second target control signal V3b to the second signal generation module 40, so that the second signal generation module 40 can sequentially output i second transition level signals V2i according to the second transition control signals V3i received sequentially, and finally output a second target level signal V2b according to the second target control signal V3b; in this way, the entire power-on process of the second target level signal V2b experiences i+1 pull-down processes, that is, in the power-on process, the initial voltage level is sequentially pulled down to the transition level values of the second transition level signals V2i, and finally the transition level value of the i-th second transition level signal V2i is pulled down to the target level value of the second target level signal V2b, completing the power-on of the second target level signal V2b.

[0128] As can be seen, when the driving method provided by the above embodiment is used to drive the signal generation circuit, the second signal control module 30 outputs control signals to the second signal generation module 40 multiple times in the power-on process, so that the second signal generation module 40 gradually pulls down the voltage level, and finally realizes the output of the second target level signal V2b. Therefore, the amplitude and occurrence time of the transient current generated in the power-on process are effectively reduced, and the problem of excessive transient current when the second target level signal V2b is powered on in one step can be avoided.

[0129] In some embodiments, at the same time, the first signal control module 10 outputs a first first transition control signal V0n to the first signal generation module 20, and the second signal control module 30 outputs a first second transition control signal V3i to the second signal generation module 40.

[0130] When the driving method provided in the above embodiment is used to drive the signal generation circuit, the first target level signal V1b and the second target level signal V2b can be powered synchronously, so that the two signals can reach stability at the same time, and the display product can be started in a stable voltage environment, and display abnormalities can be avoided.

[0131] It should be noted that the "same layer" of the embodiments of the present disclosure can refer to a film layer on the same structure layer. Alternatively, for example, the film layers on the same layer can be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then patterning the film layer by using the same mask plate through a one-time patterning process. According to different specific patterns, the one-time patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous. These specific patterns can also be at different heights or have different thicknesses.

[0132] In the method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the sequence of the steps, and for those skilled in the art, the changes in the sequence of the steps without creative labor are within the protection scope of the present disclosure.

[0133] It should be noted that each of the embodiments in the present specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment mainly describes the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the description of the product embodiments.

[0134] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood as the usual meaning understood by those skilled in the art to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not represent any order, number or importance, but are only used to distinguish different components. "Include" or "contain" and similar words mean that the elements or objects before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connection, but can include electrical connection, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to represent relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship can also change accordingly.

[0135] It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or an intervening element can also be present.

[0136] In the description of the above embodiments, the specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0137] The above description is merely illustrative of the disclosure, and the protection scope of the disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the disclosure, and all these changes and replacements should be covered within the protection scope of the disclosure. Therefore, the protection scope of the disclosure should be subject to the protection scope of the claims.

Claims

1. A signal generation circuit, comprising: The first signal control module and the first signal generation module are coupled with each other; The first signal control module is configured to sequentially output n first transition control signals to the first signal generation module, where n is an integer greater than or equal to 1; and output a first target control signal to the first signal generation module after outputting the n first transition control signals; The first signal generation module is configured to sequentially output n first transition level signals according to the n first transition control signals, and finally output a first target level signal according to the first target control signal; When n > 1, the voltage values of the n first transition level signals decrease in turn according to the output order, and the voltage value of the first target level signal is less than the voltage values of the first transition level signals.

2. The signal generation circuit of claim 1, wherein When n = 1, the absolute value of the voltage value of the first transition level signal output by the first signal generation module is equal to 1 / 2 of the voltage value of the first target level signal; When n > 1, the first signal generation module sequentially outputs the n first transition level signals, and the mth first transition level signal and the (m+1)th first transition level signal have a fixed first voltage difference value, where m satisfies 1≤m≤n-1; and the nth first transition level signal and the first target level signal have the first voltage difference value.

3. The signal generation circuit of claim 1, wherein When n = 1, the absolute value of the voltage value of the first transition level signal output by the first signal generation module is less than or greater than 1 / 2 of the voltage value of the first target level signal; When n > 1, the first signal generation module sequentially outputs the n first transition level signals, and the mth first transition level signal and the (m+1)th first transition level signal have a second voltage difference value, where m satisfies 1≤m≤n-1; the second voltage difference value increases or decreases in turn according to the output order; the nth first transition level signal and the first target level signal have a third voltage difference value, and the third voltage difference value is greater than or less than the second voltage difference value.

4. The signal generation circuit of claim 1, wherein The time interval of each first transition level signal output by the first signal generation module and the time interval between the last output first transition level signal and the first target level signal are equal; or The time interval of each first transition level signal output by the first signal generation module and the time interval between the last output first transition level signal and the first target level signal increase in turn; or The time interval of each first transition level signal output by the first signal generation module and the time interval between the last output first transition level signal and the first target level signal decrease in turn. The signal generation circuit further comprises a second signal control module and a second signal generation module coupled with each other; 5. The signal generation circuit according to any one of claims 1 to 4, wherein ​ The second signal control module is configured to sequentially output i second transition control signals to the second signal generation module, i being an integer greater than or equal to 1; and output a second target control signal to the second signal generation module after outputting the i second transition control signals; The second signal generation module is configured to sequentially output i second transition level signals according to the i second transition control signals, and finally output a second target level signal according to the second target control signal; when i > 1, voltage values of the i second transition level signals sequentially decrease in output order, and a voltage value of the second target level signal is less than voltage values of the second transition level signals.

6. The signal generation circuit of claim 5, wherein, when i = 1, an absolute value of a voltage value of one second transition level signal output by the second signal generation module is equal to 1 / 2 of a voltage value of the second target level signal; when i > 1, between a jth second transition level signal and a (j+1)th second transition level signal among the i second transition level signals sequentially output by the second signal generation module, there is a fixed second voltage difference value, j satisfying: 1≤j≤i-1; and between the ith second transition level signal and the second target level signal, there is the second voltage difference value.

7. The signal generation circuit of claim 5, wherein, when i = 1, an absolute value of a voltage value of one second transition level signal output by the second signal generation module is less than or greater than 1 / 2 of a voltage value of the second target level signal; when i > 1, between a jth second transition level signal and a (j+1)th second transition level signal among the i second transition level signals sequentially output by the second signal generation module, there is a second voltage difference value, j satisfying: 1≤j≤i-1; and in output order, the second voltage difference value sequentially increases or decreases; between the ith second transition level signal and the second target level signal, there is a third voltage difference value, the third voltage difference value being greater than or less than the second voltage difference value.

8. The signal generation circuit of claim 5, wherein, a time interval of each of the second transition level signals output by the second signal generation module is equal to a time interval between a last output second transition level signal and the second target level signal; or, a time interval of each of the second transition level signals output by the second signal generation module sequentially increases, and a time interval between a last output second transition level signal and the second target level signal sequentially increases; or, a time interval of each of the second transition level signals output by the second signal generation module sequentially decreases, and a time interval between a last output second transition level signal and the second target level signal sequentially decreases.

9. The signal generation circuit of claim 5, wherein, a time when the first signal control module outputs a first first transition control signal to the first signal generation module is the same as a time when the second signal control module outputs a first second transition control signal to the second signal generation module. ​ 10. The signal generation circuit of claim 5, wherein, The signal generation circuit further comprises a third signal generation module coupled with the first signal generation module, the third signal generation module being configured to output two groups of transition signals according to the n first transition level signals output by the first signal generation module, and each group of transition signals being output by sequentially outputting n transition power signals; the third signal generation module is further configured to finally output two target power signals according to the first target level signal output by the first signal generation module; when n>1, the voltage values of the n transition power signals sequentially decrease in output order, and the voltage value of the target power signal is less than the voltage values of the transition power signals.

11. A display module comprising the signal generation circuit according to any one of claims 1-10; the display module further comprises a driving chip and a power management chip; the first signal control module, the third signal generation module, the second signal control module and the second signal generation module in the signal generation circuit are integrated in the driving chip, and the first signal generation module in the signal generation circuit is integrated in the power management chip.

12. The display module of claim 11, wherein, The display module further comprises a display panel and a gate driving circuit, the display panel comprises at least two display regions with different refresh rates, and the gate driving circuit comprises at least two sub-driving circuits, the sub-driving circuits being configured to drive corresponding display regions to display. The display module comprises at least two signal generation circuits; in different signal generation circuits, the number of first transition control signals output by the first signal control module is different, and the number of first transition level signals output by the first signal generation module is different; the signal generation circuit is configured to provide target power signals for corresponding sub-driving circuits.

13. A driving method of a signal generation circuit, configured to drive the signal generation circuit according to any one of claims 1-10; the driving method comprises: the first signal control module sequentially outputs n first transition control signals to the first signal generation module, n being an integer greater than or equal to 1; and outputs a first target control signal to the first signal generation module after outputting the n first transition control signals; the first signal generation module sequentially outputs n first transition level signals according to the n first transition control signals, and finally outputs a first target level signal according to the first target control signal; when n>1, the voltage values of the n first transition level signals sequentially decrease in output order, and the voltage value of the first target level signal is less than the voltage values of the first transition level signals.

14. The driving method of a signal generation circuit according to claim 13, wherein The signal generation circuit further comprises a second signal control module and a second signal generation module coupled with each other; the driving method further comprises: the second signal control module sequentially outputs i second transition control signals to the second signal generation module, i being an integer greater than or equal to 1; and outputs a second target control signal to the second signal generation module after outputting the i second transition control signals; The second signal generation module sequentially outputs i second transition level signals according to the i second transition control signals, and finally outputs a second target level signal according to the second target control signal; when i>1, voltage values of the i second transition level signals decrease in turn according to the output order, and a voltage value of the second target level signal is smaller than the voltage values of the second transition level signals.

15. The driving method of the signal generation circuit according to claim 13, wherein, At the same time, the first signal control module outputs the first transition control signal to the first signal generation module, and the second signal control module outputs the first second transition control signal to the second signal generation module.

Images