Display device

Abstract

Embodiments of the present disclosure may provide a display device including: a display panel in which a plurality of sub-pixels are arranged and which displays an image; a data driving circuit configured to supply a data voltage corresponding to image data to the plurality of sub-pixels through the data lines; a first switch supplying a precharge voltage to each of the data lines; and a second switch connecting two data lines among the data lines, in which the data driving circuit supplies a data voltage corresponding to the image data to each of the plurality of sub-pixels, outputs a switching signal to each of the first switches based on an amount of change in the sequentially output image data, and outputs a switching signal to each of the second switches based on an amount of change in the sequentially output image data. And outputting a control signal to each of the second switches based on the amount of change in the image data, thereby providing a display device capable of reducing power consumption.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0168124, filed on November 22, 2024, which is incorporated herein by reference for all purposes, as if fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to data driving circuits and display devices. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is increasing in various forms, and recently, various types of display devices such as liquid crystal displays and organic light-emitting displays are being used.

[0005] These display devices require data drive circuits that can reduce power consumption and display images stably.

[0006] Conventional display devices may have the problem of not being able to share voltage between the lines of the output data voltage. Therefore, embodiments of this disclosure propose a data drive circuit and display device capable of sharing voltage by arranging transistors between the lines of the output data voltage. Summary of the Invention

[0007] Embodiments of this disclosure may provide a data driving circuit and a display device that determine voltage sharing among multiple lines based on changes in image data sequentially output from the data driving circuit.

[0008] Embodiments of this disclosure may provide a display device comprising: a display panel having a plurality of sub-pixels arranged therein, and the display panel being configured to display an image; a data driving circuit configured to supply data voltages to the plurality of sub-pixels via data lines; a first switch configured to supply a pre-charge voltage to the data lines; and a second switch connecting two of the data lines, wherein the data driving circuit is configured to: supply data voltages corresponding to image data to the plurality of sub-pixels, output a switch signal to each of the first switches based on changes in sequentially output image data, and output a control signal to each of the second switches based on changes in image data.

[0009] According to embodiments of this disclosure, a data drive circuit and a display device may be provided, comprising a plurality of transistors electrically connected to each of a plurality of data lines.

[0010] According to embodiments of this disclosure, a data drive circuit and a display device capable of charging multiple data lines by controlling multiple transistors can be provided.

[0011] According to embodiments of this disclosure, a display device can be driven with low power by providing a data drive circuit that shares voltage, current, and charge among multiple output circuits. Attached Figure Description

[0012] Figure 1 This is a system configuration diagram of a display device according to an embodiment of the present disclosure.

[0013] Figure 2 A display device including a switch control unit is shown according to an embodiment of the present disclosure.

[0014] Figure 3 It is an equivalent circuit diagram of a sub-pixel included in a display device according to an embodiment of the present disclosure.

[0015] Figure 4 The connection relationships between a plurality of switching transistors, a switching control unit, and a plurality of output circuits according to embodiments of the present disclosure are shown.

[0016] Figure 5 A switch control unit that outputs a control signal based on a signal output from a shift register, according to an embodiment of the present disclosure, is shown.

[0017] Figure 6 The diagram illustrates the connection relationships between a plurality of switching transistors, a switching control unit, a plurality of output circuits, and a plurality of logic units according to embodiments of the present disclosure.

[0018] Figure 7 A switch control unit that outputs control signals based on signals output from a logic unit is shown according to an embodiment of the present disclosure.

[0019] Figure 8 It is a timing diagram of multiple signals based on the change of MSB value according to an embodiment of the present disclosure.

[0020] Figure 9 This is a table showing the power consumption reduction status of various embodiments according to this disclosure. Detailed Implementation

[0021] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and in which the same reference numerals and symbols may be used to denote the same or similar parts, even when these parts are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and parts incorporated herein may be omitted where such detailed descriptions would obscure the subject matter of some embodiments of the invention. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed by” as used herein are generally intended to allow for the addition of additional parts, unless said terms are used in conjunction with the term “only.” As used herein, unless the context clearly indicates otherwise, the singular forms are intended to include the plural forms.

[0022] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but is only used to distinguish the corresponding element from other elements.

[0023] When referring to a first element being "connected or coupled to" a second element, or "in contact with or overlapping" a second element, it should be interpreted that not only can the first element be "directly connected or coupled to" the second element or "directly in contact with or overlapping" a second element, but a third element can also be "placed" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact with," or "overlapped" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact with," or "overlapped" with each other.

[0024] When time-related terms such as “after,” “follow,” “next,” “before,” etc., are used to describe the handling or operation of an element or configuration, or a process or step in an operation, handling, or manufacturing method, these terms may be used to describe non-continuous or non-sequential handling or operation, unless the terms “directly” or “immediately after” are used together.

[0025] Furthermore, when referring to any size, relative dimensions, etc., the numerical values ​​or corresponding information of the component or feature (e.g., level, range, etc.) should be considered, including tolerances or error ranges that may be caused by various factors (e.g., processing factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0026] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0027] Figure 1 This is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0028] Figure 1 A schematic configuration of a display device according to an embodiment of the present disclosure is shown.

[0029] Reference Figure 1 The display device 100 according to embodiments of the present disclosure may include: a display panel 110, in which a plurality of gate lines GL and a plurality of data lines DL are connected, and a plurality of sub-pixels SP are arranged in a matrix; a gate driving circuit 130 for driving the plurality of gate lines GL; a data driving circuit 120 for supplying data voltage through the plurality of data lines DL; a controller 140 for controlling the gate driving circuit 130 and the data driving circuit 120; and a power management circuit 150.

[0030] The display panel 110 can display images based on scan signals transmitted from the gate drive circuit 130 via multiple gate lines GL and data voltages transmitted from the data drive circuit 120 via multiple data lines DL.

[0031] The display panel 110 may include a plurality of pixels arranged in a matrix, and each pixel may include sub-pixels SP of different colors, such as white sub-pixels, red sub-pixels, green sub-pixels, and blue sub-pixels. In addition, each sub-pixel SP may be defined by a plurality of data lines DL and a plurality of gate lines GL.

[0032] A sub-pixel SP may include: a thin-film transistor (TFT) formed in a region where a data line DL intersects a gate line GL; a light-emitting device such as an organic light-emitting diode charged with a data voltage; and a storage capacitor electrically connected to the light-emitting device to maintain the voltage.

[0033] For example, if a display device 100 with a resolution of 2,160 × 3,840 includes three sub-pixels SP of red (R), green (G) and blue (B), a total of 11,520 (i.e., 3,840 × 3) data lines DL can be provided by 2,160 gate lines GL and 3,840 data lines DL respectively connected to the three sub-pixels (RGB), and the sub-pixels SP can be arranged at each point where the gate lines GL and data lines DL intersect.

[0034] The gate drive circuit 130 can be controlled by the controller 140, and can control the driving timing of multiple sub-pixels SP by sequentially outputting scan signals to multiple gate lines GL arranged on the display panel 110.

[0035] In this configuration, the gate drive circuit 130 may include one or more gate drive integrated circuits (GDICs), and depending on the driving method, may be located on only one side of the display panel 110 or on both sides of the display panel 110. Alternatively, the gate drive circuit 130 may be integrated into the bezel area of ​​the display panel 110 and implemented as a gate in-panel (GIP).

[0036] The data driving circuit 120 can receive image data DATA from the controller 140 and convert the received image data DATA into an analog data voltage. The data driving circuit 120 can output the data voltage to each data line DL according to the timing of the scan signal applied through the gate line GL, so that each sub-pixel SP connected to the data line DL emits light with a brightness corresponding to the data voltage.

[0037] Similarly, the data driving circuit 120 may include one or more source driver integrated circuits (SDICs), and the source driver integrated circuits (SDICs) may be connected to the bonding pads of the display panel 110 via tape auto-bonding (TAB) or chip-on-glass (COG) methods, or may be placed directly on the display panel 110.

[0038] In some cases, each source driver integrated circuit (SDIC) can be integrated and disposed on the display panel 110. Alternatively, each source driver integrated circuit (SDIC) can be implemented as a chip-on-film (COF) circuit, in which case each source driver integrated circuit (SDIC) can be mounted on a circuit film and electrically connected to the data line DL of the display panel 110 through the circuit film.

[0039] The controller 140 can supply various control signals to the gate drive circuit 130 and the data drive circuit 120, and control the operation of the gate drive circuit 130 and the data drive circuit 120. That is, the controller 140 can control the gate drive circuit 130 to output a scan signal according to the timing implemented in each frame, and can transmit image data DATA received from the outside to the data drive circuit 120.

[0040] In this configuration, the controller 140 can receive various timing signals, including the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, and the master clock MCLK, as well as image data DATA, from the external host system 160.

[0041] The host system 160 can be any of a TV system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, and wearable device.

[0042] Therefore, the controller 140 can use various timing signals received from the host system 160 to generate control signals and transmit the control signals to the gate drive circuit 130 and the data drive circuit 120.

[0043] For example, controller 140 can output various gate control signals, including a gate start pulse GSP, a gate clock GCLK, and a gate output enable signal GOE, to control gate drive circuit 130. Here, the gate start pulse GSP is a signal used to control the start time of operation of one or more gate driver integrated circuits GDIC constituting gate drive circuit 130. Additionally, the gate clock GCLK can be a clock signal commonly input to one or more gate driver integrated circuits GDIC to control the shift timing of scan signals. Furthermore, the gate output enable signal GOE can be a signal used to specify timing information for one or more gate driver integrated circuits GDIC.

[0044] Additionally, the controller 140 can output various data control signals, including a source start pulse SSP, a source clock SCLK, and a source output enable signal SOE, to control the data drive circuit 120. Here, the source start pulse SSP can be a signal used to control the timing of data sampling for one or more source driver integrated circuits (SDICs) constituting the data drive circuit 120. The source clock SCLK can be a clock signal used to control the timing of data sampling in the source driver integrated circuits (SDICs). The source output enable signal SOE can be a signal used to control the output timing of the data drive circuit 120.

[0045] The display device 100 may include a power management circuit 150, which supplies various voltages or currents to the display panel 110, the gate driving circuit 130, and the data driving circuit 120, or controls the various voltages or currents to be supplied.

[0046] The power management circuit 150 can adjust the DC input voltage Vin supplied from the host system 160 to generate the power required to drive the display panel 110, the gate drive circuit 130, and the data drive circuit 120.

[0047] Simultaneously, the sub-pixel SP can be located at the intersection of the gate line GL and the data line DL, and a light-emitting device can be arranged in each sub-pixel SP. For example, an organic light-emitting display device can include a light-emitting device such as an organic light-emitting diode in each sub-pixel SP, and can display an image by controlling the current flowing to the light-emitting device according to the data voltage.

[0048] The display device 100 can be of various types, such as a liquid crystal display, an organic light-emitting display, and a plasma display panel.

[0049] Figure 2 A display device 100 including a switch control unit 200 according to an embodiment of the present disclosure is shown.

[0050] Reference Figure 2 The display device 100 may include a data driving circuit 120 and a display panel 110.

[0051] The data driving circuit 120 may include multiple output circuits OC that sequentially output data voltages corresponding to the image data DATA. For example, the data driving circuit 120 may include a first output circuit OC1, a second output circuit OC2, a third output circuit OC3, and a fourth output circuit OC4. The data driving circuit 120 may include a switch control unit 200.

[0052] Display panel 110 may include multiple subpixels SP. For example, display panel 110 may include a first subpixel SP1, a second subpixel SP2, a third subpixel SP3, and a fourth subpixel SP4. For example, the first subpixel SP1 may be a red subpixel. The second subpixel SP2 may be a white subpixel. The third subpixel SP3 may be a green subpixel. The fourth subpixel SP4 may be a blue subpixel.

[0053] The output circuits OC1 to OC4 can be electrically connected to the sub-pixels SP1 to SP4 and the data lines DL1 to DL4, respectively.

[0054] The first output circuit OC1, in response to the first source output enable signal SOE1, outputs first image data to the first sub-pixel SP1 via the first data line DL1. The second output circuit OC2, in response to the second source output enable signal SOE2, outputs second image data to the second sub-pixel SP2 via the second data line DL2. The third output circuit OC3, in response to the third source output enable signal SOE3, outputs third image data to the third sub-pixel SP3 via the third data line DL3. The fourth output circuit OC4, in response to the fourth source output enable signal SOE4, outputs fourth image data to the fourth sub-pixel SP4 via the fourth data line DL4.

[0055] The operation of a display device 100, based on an example of outputting a data voltage during a period when the source output enable signal SOE is at a high level, will be described below.

[0056] Sharing at least one of charge, voltage, and current between data lines can be called charge-sharing. Sharing at least one of charge, voltage, and current by connecting data lines to a predetermined voltage line can be called pre-charging.

[0057] Before outputting the data voltage corresponding to the image data DATA, at least one data line DL can be pre-charged, or multiple data lines DL can share the charge to prevent insufficient charging of multiple data lines DL or to save power consumption.

[0058] The switch control unit 200 can control the pre-charging and charge sharing of multiple data lines DL. For example, when the first source enable signal SOE1 is low, the first data line DL1 can be pre-charged or charge-shared. For example, when the second source enable signal SOE2 is low, the second data line DL2 can be pre-charged or charge-shared. For example, when the third source enable signal SOE3 is low, the third data line DL3 can be pre-charged or charge-shared. For example, when the fourth source enable signal SOE4 is low, the fourth data line DL4 can be pre-charged or charge-shared.

[0059] Multiple output circuits can each output a channel signal CHS to the switch control unit 200. For example, the first output circuit OC1 can output the first channel signal CHS1 to the switch control unit 200. The second output circuit OC2 can output the second channel signal CHS2 to the switch control unit 200. The third output circuit OC3 can output the third channel signal CHS3 to the switch control unit 200. The fourth output circuit OC4 can output the fourth channel signal CHS4 to the switch control unit 200. Figure 5 The description illustrates detailed descriptions of the first channel signal CHS1, the second channel signal CHS2, the third channel signal CHS3, and the fourth channel signal CHS4.

[0060] The switch control unit 200 can output first control signals CS1, second control signals CS2, third control signals CS3, fourth control signals CS4, fifth control signals CS5, and sixth control signals CS6 respectively to multiple transistors electrically connected to multiple output circuits, based on the first channel signal CHS1, the second channel signal CHS2, the third channel signal CHS3, and the fourth channel signal CHS4. The switch control unit 200 can also output first switch signals SW1, second switch signals SW2, third switch signals SW3, and fourth switch signals SW4 to multiple transistors controlling the connection between the control voltage line that controls the pre-charging of multiple data lines DL and the multiple data lines DL. Figure 4 The description will include detailed examples of several transistors.

[0061] The pre-charging and charge sharing of multiple data lines DL can be controlled according to the first switch signal SW1, the second switch signal SW2, the third switch signal SW3, the fourth switch signal SW4, the first control signal CS1, the second control signal CS2, the third control signal CS3, the fourth control signal CS4, the fifth control signal CS5, and the sixth control signal CS6. Figure 4 The description will exemplify the descriptions of the first switch signal SW1, the second switch signal SW2, the third switch signal SW3, the fourth switch signal SW4, the first control signal CS1, the second control signal CS2, the third control signal CS3, the fourth control signal CS4, the fifth control signal CS5, and the sixth control signal CS6.

[0062] The sub-pixel SP driven by the data voltage output from the output circuit will be described below.

[0063] Figure 3 It is an equivalent circuit diagram of the sub-pixel SP included in the display device 100 according to the embodiments of the present disclosure.

[0064] Reference Figure 3 In the display device 100 according to the embodiments of the present disclosure, the sub-pixel SP may include one or more transistors and capacitors, and the organic light-emitting diode may be configured as a light-emitting device ED.

[0065] For example, a subpixel SP may include a driving transistor DT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor CST, and a light-emitting device ED.

[0066] The driving transistor DT may have a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DT may be a gate node, to which a data voltage VDATA is applied from the data driving circuit 120 via the data line DL when the switching transistor SWT is turned on. The second node N2 of the driving transistor DT may be electrically connected to the anode electrode of the light-emitting device ED, and may be either a source node or a drain node. The third node N3 of the driving transistor DT may be electrically connected to the driving voltage line VDDL to which the driving voltage VDD is applied, and may be either a drain node or a source node.

[0067] In this case, during the display driving period, the driving voltage VDD required to display the image can be supplied to the driving voltage line VDDL.

[0068] The switching transistor SWT can be electrically connected between the first node N1 of the driving transistor DT and the data line DL, and the gate line GL can be connected to the gate node, operating according to the scan signal SCAN supplied through the gate line GL. Furthermore, if the switching transistor SWT is turned on, the data voltage VDATA supplied through the data line DL can be transmitted to the gate node of the driving transistor DT, thereby controlling the operation of the driving transistor DT.

[0069] The sensing transistor SENT can be electrically connected between the second node N2 of the driving transistor DT and the reference voltage line VREFL, and the gate line can be connected to the gate node to operate according to the sensing signal SENSE supplied through the gate line. If the sensing transistor SENT is turned on, the sensing reference voltage VREF supplied through the reference voltage line VREFL is transmitted to the second node N2 of the driving transistor DT.

[0070] In other words, the voltage of the first node N1 and the second node N2 of the driving transistor DT can be controlled by controlling the switching transistor SWT and the sensing transistor SENT, so that current can be supplied to drive the light-emitting device ED.

[0071] The gate nodes of the switching transistor SWT and the sensing transistor SENT can be connected together to a single gate line GL, or they can be connected to different gate lines GL. Here, an example is shown where the switching transistor SWT and the sensing transistor SENT are connected to different gates, and in this case, the switching transistor SWT and the sensing transistor SENT can be independently controlled by a scan signal SCAN and a sensing signal SENSE transmitted through different gate lines.

[0072] Meanwhile, when the switching transistor SWT and the sensing transistor SENT are connected to a gate line GL, the switching transistor SWT and the sensing transistor SENT can be simultaneously controlled by the scan signal SCAN and the sensing signal SENSE transmitted through a gate line, thereby increasing the aperture ratio of the sub-pixel SP.

[0073] Meanwhile, the transistors disposed in the sub-pixel SP can include not only n-type transistors but also p-type transistors. In the following text, the case where the transistors include n-type transistors will be illustrated.

[0074] The storage capacitor CST can be electrically connected between the first node N1 and the second node N2 of the driving transistor DT, and maintains the data voltage VDATA within one frame.

[0075] Depending on the type of driving transistor DT, the storage capacitor CST can be connected between the first node N1 and the third node N3 of the driving transistor DT. The anode of the light-emitting device ED can be electrically connected to the second node N2 of the driving transistor DT, and the reference voltage VSS can be applied to the cathode of the light-emitting device ED.

[0076] Here, the reference voltage VSS can be ground voltage or a voltage higher or lower than ground voltage. Furthermore, the reference voltage VSS can vary depending on the driving state. For example, the reference voltage VSS during display driving time and the reference voltage VSS during sensing driving time can be set to be different from each other.

[0077] The subpixel SP structure described above as an example is a 3T (transistor) 1C (capacitor) structure, and is merely an example for illustration. A subpixel may include one or more transistors, or in some cases, one or more capacitors. Alternatively, each of the multiple subpixel SPs may have the same structure, or some of the multiple subpixel SPs may have different structures.

[0078] Figure 4 The connection relationship between a plurality of switching transistors SWT1 to SWT10, a switching control unit 200, and a plurality of output circuits OC1 to OC4 according to an embodiment of the present disclosure is shown.

[0079] The data drive circuit 120 may include a first output circuit OC1, a second output circuit OC2, a third output circuit OC3, and a fourth output circuit OC4. Multiple data lines DL1 to DL4 can be connected to the control voltage line VCIL for the output pre-charge voltage VCI. The data drive circuit 120 may include a switch control unit 200. (The remaining text is omitted.) Figure 2 Description of the overlapping switch control unit 200.

[0080] The first switching transistor SWT1 controls the electrical connection between the first data line DL1 and the second data line DL2. The second switching transistor SWT2 controls the electrical connection between the first data line DL1 and the third data line DL3. The third switching transistor SWT3 controls the electrical connection between the first data line DL1 and the fourth data line DL4. The fourth switching transistor SWT4 controls the electrical connection between the second data line DL2 and the third data line DL3. The fifth switching transistor SWT5 controls the electrical connection between the second data line DL2 and the fourth data line DL4. The sixth switching transistor SWT6 controls the electrical connection between the third data line DL3 and the fourth data line DL4.

[0081] Multiple output circuits may include a shift register SR, a sample latch circuit SAR, a hold latch circuit HOR, a digital-to-analog converter DAC, and an amplifier AMP.

[0082] For example, the first output circuit OC1 may include a first shift register SR1, a first sampling latch circuit SAR1, a first holding latch circuit HOR1, a first digital-to-analog converter DAC1, and a first amplifier AMP1. The first output circuit OC1 may be connected to a first data line DL1, a seventh switching transistor SWT7 that controls the pre-charging of the first data line DL1, and a first transistor T1 that controls the output of a first data voltage corresponding to the first image data according to a first source enable signal SOE1.

[0083] For example, the second output circuit OC2 may include a second shift register SR2, a second sampling latch circuit SAR2, a second holding latch circuit HOR2, a second digital-to-analog converter DAC2, and a second amplifier AMP2. The second output circuit OC2 may be connected to a second data line DL2, an eighth switching transistor SWT8 that controls the pre-charging of the second data line DL2, and a second transistor T2 that controls the output of a second data voltage corresponding to the second image data according to a second source enable signal SOE2.

[0084] For example, the third output circuit OC3 may include a third shift register SR3, a third sampling latch circuit SAR3, a third holding latch circuit HOR3, a third digital-to-analog converter DAC3, and a third amplifier AMP3. The third output circuit OC3 may be connected to the third data line DL3, a ninth switching transistor SWT9 that controls the pre-charging of the third data line DL3, and a third transistor T3 that controls the output of the third data voltage corresponding to the third image data according to the third source enable signal SOE3.

[0085] For example, the fourth output circuit OC4 may include a fourth shift register SR4, a fourth sample latch circuit SAR4, a fourth hold latch circuit HOR4, a fourth digital-to-analog converter DAC4, and a fourth amplifier AMP4. The fourth output circuit OC4 may be connected to a fourth data line DL4, a tenth switching transistor SWT10 that controls the pre-charging of the fourth data line DL4, and a fourth transistor T4 that controls the output of the fourth data voltage corresponding to the fourth image data according to the fourth source enable signal SOE4.

[0086] The seventh switching transistor SWT7, the eighth switching transistor SWT8, the ninth switching transistor SWT9, and the tenth switching transistor SWT10 can be referred to as the first precharge transistor, the second precharge transistor, the third precharge transistor, and the fourth precharge transistor, respectively.

[0087] The switch control unit 200 can receive the first channel signal CHS1, the second channel signal CHS2, the third channel signal CHS3, and the fourth channel signal CHS4 from the first shift register SR1, the second shift register SR2, the third shift register SR3, and the fourth shift register SR4, respectively.

[0088] The switch control unit 200 can control the on and off states of each of the multiple switching transistors SWT1 to SWT10. The on and off states of the multiple switching transistors can be controlled based on the voltage levels of multiple control signals and multiple switching signals output from the switch control unit 200 to the multiple switching transistors.

[0089] For example, the switch control unit 200 can provide a first control signal CS1 to the gate node of the first switch transistor SWT1 and output a second control signal CS2 to the gate node of the second switch transistor SWT2. The switch control unit 200 can output a third control signal CS3 to the gate node of the third switch transistor SWT3 and a fourth control signal CS4 to the gate node of the fourth switch transistor SWT4. The switch control unit 200 can output a fifth control signal CS5 to the gate node of the fifth switch transistor SWT5. The switch control unit 200 can output a sixth control signal CS6 to the gate node of the sixth switch transistor SWT6.

[0090] For example, the switch control unit 200 can output a first switch signal SW1 to the gate node of the seventh switch transistor SWT7. For example, the switch control unit 200 can output a second switch signal SW2 to the gate node of the eighth switch transistor SWT8. For example, the switch control unit 200 can output a third switch signal SW3 to the gate node of the ninth switch transistor SWT9. For example, the switch control unit 200 can output a fourth switch signal SW4 to the gate node of the tenth switch transistor SWT10.

[0091] The following phenomenon can be called charge sharing: before the output circuit outputs a data voltage in response to the source enable signal SOE, the voltage level of the connected data lines DL changes as they are connected to each other. For example, the voltage of two connected data lines DL can be the sum of the voltage of the high-voltage data line DL and the voltage of the low-voltage data line DL, and then divided by 2.

[0092] For example, if the first switching transistor SWT1 is turned on in response to the first control signal CS1, then the first data line DL1 and the second data line DL2 can be electrically connected.

[0093] Therefore, the charge of the data line with the higher voltage and the charge of the data line with the lower voltage can be shared among the voltages of the first data line DL1 and the second data line DL2. If the voltage levels of the first data line DL1 and the second data line DL2 become the same due to charge sharing, the data line with the lower voltage can be charged and the data line with the higher voltage can be discharged.

[0094] For example, if a second control signal CS2 with an on level is input to the gate node of the second switching transistor SWT2, the first data line DL1 and the third data line DL3 can be electrically connected.

[0095] Therefore, the charge of the data line with the higher voltage and the charge of the data line with the lower voltage can be shared among the first data line DL1 and the third data line DL3. If the voltage levels of the first data line DL1 and the third data line DL3 become the same due to charge sharing, the data line with the lower voltage can be charged, and the data line with the higher voltage can be discharged.

[0096] For example, if a third control signal CS3 with an on level is input to the gate node of the third switching transistor SWT3, then the first data line DL1 and the fourth data line DL4 can be electrically connected.

[0097] Therefore, the charge of the data line with the higher voltage and the charge of the data line with the lower voltage can be shared among the first data line DL1 and the fourth data line DL4. As the voltage levels of the first data line DL1 and the fourth data line DL4 become the same due to charge sharing, the data line with the lower voltage can be charged, and the data line with the higher voltage can be discharged.

[0098] For example, if a fourth control signal CS4 with an on level is input to the gate node of the fourth switching transistor SWT4, then the second data line DL2 and the third data line DL3 can be electrically connected.

[0099] Therefore, the charge of the data line with the higher voltage and the charge of the data line with the lower voltage can be shared among the second data line DL2 and the third data line DL3. As the voltage levels of the second data line DL2 and the third data line DL3 become the same due to charge sharing, the data line with the lower voltage can be charged, and the data line with the higher voltage can be discharged.

[0100] For example, if a fifth control signal CS5 with an on level is input to the gate node of the fifth switching transistor SWT5, then the second data line DL2 and the fourth data line DL4 can be electrically connected.

[0101] Therefore, the charge of the data line with the higher voltage (DL2) and the charge of the data line with the lower voltage (DL4) can be shared. As the voltage levels of the second data line DL2 and the fourth data line DL4 become the same due to charge sharing, the data line with the lower voltage (DL2) can be charged, and the data line with the higher voltage (DL4) can be discharged.

[0102] For example, if a sixth control signal CS6 with an on level is input to the gate node of the sixth switching transistor SWT6, then the third data line DL3 and the fourth data line DL4 can be electrically connected.

[0103] Therefore, the charge of the data line with the higher voltage and the charge of the data line with the lower voltage can be shared among the third data line DL3 and the fourth data line DL4. If the voltage levels of the third data line DL3 and the fourth data line DL4 become the same due to charge sharing, the data line with the lower voltage can be charged, and the data line with the higher voltage can be discharged.

[0104] Before the output circuit outputs the data voltage VDATA in response to the source enable signal SOE, the control voltage line VCIL is electrically connected to the output circuit, allowing the data line DL included in the output circuit to be charged. This phenomenon can be called pre-charging: by electrically connecting the control voltage line VCIL to the output circuit, the data line DL of the output circuit is charged.

[0105] For example, if the switch control unit 200 inputs a first switch signal SW1 with an on level to the gate node of the seventh switch transistor SWT7, then the control voltage line VCIL and the first data line DL1 can be electrically connected. If the control voltage line VCIL and the first data line DL1 are electrically connected, then the first data line DL1 can be charged.

[0106] For example, if the switch control unit 200 inputs a second switch signal SW2 with an on level to the gate node of the eighth switch transistor SWT8, the control voltage line VCIL and the second data line DL2 can be electrically connected, and the second data line DL2 can be charged.

[0107] For example, if the switch control unit 200 inputs a third switch signal SW3 with a conduction level to the gate node of the ninth switch transistor SWT9, the control voltage line VCIL and the third data line DL3 can be electrically connected, and the third data line DL3 can be charged.

[0108] For example, if the switch control unit 200 inputs a fourth switch signal SW4 with a conduction level to the gate node of the tenth switch transistor SWT10, the control voltage line VCIL and the fourth data line DL4 can be electrically connected, and the fourth data line DL4 can be charged.

[0109] The first sampling latch circuit SAR1 can sequentially sample the first image data supplied from the controller 140 according to the sampling signal, and supply the sampled data to the first holding latch circuit HOR1. The second sampling latch circuit SAR2 can sequentially sample the second image data supplied from the controller 140 according to the sampling signal, and supply the sampled data to the second holding latch circuit HOR2. The third sampling latch circuit SAR3 can sequentially sample the third image data supplied from the controller 140 according to the sampling signal, and supply the sampled data to the third holding latch circuit HOR3. The fourth sampling latch circuit SAR4 can sequentially sample the fourth image data supplied from the controller 140 according to the sampling signal, and supply the sampled data to the fourth holding latch circuit HOR4.

[0110] The first hold latch circuit HOR1 stores first image data sampled from the first sampling latch circuit SAR1 and supplies the stored first image data to the first digital-to-analog converter DAC1 synchronously with the source output enable signal SOE. The second hold latch circuit HOR2 stores second image data sampled from the second sampling latch circuit SAR2 and supplies the stored second image data to the second digital-to-analog converter DAC2 synchronously with the source output enable signal SOE. The third hold latch circuit HOR3 stores third image data sampled from the third sampling latch circuit SAR3 and supplies the stored third image data to the third digital-to-analog converter DAC3 synchronously with the source output enable signal SOE. The fourth hold latch circuit HOR4 stores fourth image data sampled from the fourth sampling latch circuit SAR4 and supplies the stored fourth image data to the fourth digital-to-analog converter DAC4 synchronously with the source output enable signal SOE.

[0111] The first digital-to-analog converter (DAC1) converts image data supplied from the first latch circuit (HOR1) into analog voltage. The second DAC2 converts image data supplied from the second latch circuit (HOR2) into analog voltage. The third DAC3 converts image data supplied from the third latch circuit (HOR3) into analog voltage. The fourth DAC4 converts image data supplied from the fourth latch circuit (HOR4) into analog voltage.

[0112] A first amplifier AMP1 amplifies or compensates the analog voltage transmitted from a first digital-to-analog converter DAC1 and supplies data voltage to a first data line DL1. A second amplifier AMP2 amplifies or compensates the analog voltage transmitted from a second digital-to-analog converter DAC2 and supplies data voltage to a second data line DL2. A third amplifier AMP3 amplifies or compensates the analog voltage transmitted from a third digital-to-analog converter DAC3 and supplies data voltage to a third data line DL3. A fourth amplifier AMP4 amplifies or compensates the analog voltage transmitted from a fourth digital-to-analog converter DAC4 and supplies data voltage to a fourth data line DL4. In one embodiment, the first amplifier AMP1 to the fourth amplifier AMP4 can be implemented as buffer amplifiers.

[0113] The first transistor T1 can control the electrical connection between the first amplifier AMP1 and the first data line DL1 in response to the first source enable signal SOE1. The second transistor T2 can control the electrical connection between the second amplifier AMP2 and the second data line DL2 in response to the second source enable signal SOE2. The third transistor T3 can control the electrical connection between the third amplifier AMP3 and the third data line DL3 in response to the third source enable signal SOE3. The fourth transistor T4 can control the electrical connection between the fourth amplifier AMP4 and the fourth data line DL4 in response to the fourth source enable signal SOE4.

[0114] The following describes the operation of the switch control unit 200 in outputting multiple signals based on the first channel signal CHS1, the second channel signal CHS2, the third channel signal CHS3, and the fourth channel signal CHS4.

[0115] Figure 5 A switch control unit 200 that outputs a control signal based on a signal output from a shift register, according to an embodiment of the present disclosure, is shown.

[0116] Reference Figure 5The controller 140 can control the output of channel signals CHS1 to CHS4 based on the amount of change in the image data sequentially supplied to each output circuit. For example, the controller 140 can determine the output of multiple channel signals CHS1 to CHS4 based on the change in the most significant bit (also known as “MSB”) of the image data input to each of the multiple output circuits OC1 to OC4.

[0117] For example, if the MSB value of the image data changes from '0' to '1', the controller 140 can determine the channel signal of the corresponding channel as a first signal. For example, if the MSB value of the image data changes from '1' to '0', the controller 140 can determine the channel signal of the corresponding channel as a second signal. For example, if the MSB value of the image data remains '0', the controller 140 can determine the channel signal of the corresponding channel as a third signal. For example, if the MSB value of the image data remains '1', the controller 140 can determine the channel signal of the corresponding channel as a third signal. In the following explanation, the operation of the data drive circuit 120 will be illustrated using an example where the MSB value of the image data is '1' and the MSB value is '0 ...

[0118] The first signal can be a signal with the digital value '01'. The second signal can be a signal with the digital value '10'. The third signal can be a signal with the digital value '00'. The fourth signal can be a signal with the digital value '11'.

[0119] For example, controller 140 can determine the channel signal based on the change in the value of the most significant 2 bits of image data DATA input to multiple output circuits. For example, if the value of the most significant 2 bits of image data DATA changes from '00' to '11', controller 140 can determine the channel signal of the corresponding channel as a first signal. For example, if the value of the most significant 2 bits of image data DATA changes from '11' to '00', controller 140 can determine the channel signal of the corresponding channel as a second signal. For example, if the value of the most significant 2 bits of image data DATA changes from '00' to '10', controller 140 can determine the channel signal of the corresponding channel as a first signal. For example, if the value of the most significant 2 bits of image data DATA changes from '11' to '01', controller 140 can determine the channel signal of the corresponding channel as a second signal. For example, if the value of the most significant 2 bits of image data DATA remains '00', controller 140 can determine the channel signal of the corresponding channel as a third signal. For example, if the most significant two bits of the image data DATA are kept to be '11', the controller 140 can determine the channel signal of the corresponding channel as the third signal.

[0120] Controller 140 can provide source start pulse SSP, source clock SCLK and channel signal to multiple shift registers SR1 to SR4.

[0121] Multiple shift registers SR1 to SR4 can generate sampling signals in response to the source start pulse SSP and source clock SCLK input from controller 140. Controller 140 can control the signal values ​​of the channel signals CHS1 to CHS4 output from the multiple shift registers SR1 to SR4.

[0122] For example, refer to Figure 5 If the MSB value of the image data supplied to the first shift register SR1 changes from '0' to '1', the first shift register SR1 can output the first channel signal CHS1 corresponding to the first signal to the switch control unit 200.

[0123] If the MSB value of the image data supplied to the second shift register SR2 changes from '1' to '0', then the second shift register SR2 can output the second channel signal CHS2 corresponding to the second signal to the switch control unit 200. If the MSB value of the image data supplied to the third shift register SR3 remains '0', then the third shift register SR3 can output the third channel signal CHS3 corresponding to the third signal to the switch control unit 200. If the MSB value of the image data supplied to the fourth shift register SR4 remains '1', then the fourth shift register SR4 can output the fourth channel signal CHS4 corresponding to the third signal to the switch control unit 200.

[0124] Because the data line DL connected to the output circuit that outputs the first signal has a large amount of image data variation, the increase in data voltage VDATA can be greater than the increase in data voltage VDATA of the data line DL connected to the output circuit that outputs another signal. Therefore, the data line DL connected to the output circuit that outputs the first signal needs to be pre-charged or share charge. Because the data line DL connected to the output circuit that outputs the second signal has a large amount of image data variation, the decrease in data voltage VDATA can be greater than the decrease in data voltage VDATA of the data line DL connected to the output circuit that outputs another signal. Therefore, the data line DL connected to the output circuit that outputs the second signal can share charge with the data line DL connected to the other output circuit. The switch control unit 200 can control the data lines DL connected to multiple output circuits so that the data line DL connected to the output circuit that outputs the first signal can be pre-charged or share charge. The switch control unit 200 can control the data lines DL connected to multiple output circuits so that when there is a data line DL connected to the output circuit that outputs the second signal, the data line DL connected to the output circuit that outputs the second signal can share charge with the data line DL connected to the output circuit that outputs the first signal.

[0125] For example, refer to Figure 5 The switch control unit 200 can output a first control signal CS1 with a conduction level to the gate node of the first switching transistor SWT1 based on a first signal corresponding to the first output circuit OC1 and a second signal corresponding to the second output circuit OC2. In this case, the switch control unit 200 can output a first switch signal SW1, a second switch signal SW2, a third switch signal SW3, a fourth switch signal SW4, a second control signal CS2, a third control signal CS3, a fourth control signal CS4, a fifth control signal CS5, and a sixth control signal CS6 with a turn-off level.

[0126] With the first switching transistor SWT1 turned on, the first output circuit OC1 and the second output circuit OC2 can be connected. With the first output circuit OC1 and the second output circuit OC2 connected, the first data line DL1 and the second data line DL2 can share charge. Various cases of electrical connections between multiple output circuits are described below. Figure 8 Examples are given in the description.

[0127] Figure 6 The diagram illustrates the connection relationships between a plurality of switching transistors SWT1 to SWT10, a switching control unit 200, a plurality of output circuits OC1 to OC4, and a plurality of logic units 610, 620, 630, and 640 according to an embodiment of the present disclosure.

[0128] exist Figure 6 In the description, omission and Figure 4 Overlapping descriptions.

[0129] Each of the multiple output circuits may include a logic unit.

[0130] Reference Figure 6 The first output circuit OC1 may include a first logic unit 610 connected to the first sampling latch circuit SAR1 and the first holding latch circuit HOR1. The second output circuit OC2 may include a second logic unit 620 connected to the second sampling latch circuit SAR2 and the second holding latch circuit HOR2. The third output circuit OC3 may include a third logic unit 630 connected to the third sampling latch circuit SAR3 and the third holding latch circuit HOR3. The fourth output circuit OC4 may include a fourth logic unit 640 connected to the fourth sampling latch circuit SAR4 and the fourth holding latch circuit HOR4.

[0131] The first logic unit 610 can determine the first channel signal CHS1 by comparing the MSB value or the most significant 2 bits of the first image data sampled by the first sampling latch circuit SAR1 with the MSB value or the most significant 2 bits of the first image data supplied to the first holding latch circuit HOR1. The first logic unit 610 can output the determined first channel signal CHS1 to the switch control unit 200.

[0132] The second logic unit 620 can determine the second channel signal CHS2 by comparing the MSB value or the most significant 2 bits of the second image data sampled by the second sampling latch circuit SAR2 with the MSB value or the most significant 2 bits of the second image data supplied to the second holding latch circuit HOR2. The second logic unit 620 can output the determined second channel signal CHS2 to the switch control unit 200.

[0133] The third logic unit 630 determines the third channel signal CHS3 by comparing the MSB value or the most significant two bits of the third image data sampled by the third sampling latch circuit SAR3 with the MSB value or the most significant two bits of the third image data supplied to the third holding latch circuit HOR3. The third logic unit 630 can output the determined third channel signal CHS3 to the switch control unit 200.

[0134] The fourth logic unit 640 can determine the fourth channel signal CHS4 by comparing the MSB value or the most significant two bits of the fourth image data sampled by the fourth sampling latch circuit SAR4 with the MSB value or the most significant two bits of the fourth image data supplied to the fourth holding latch circuit HOR4. The fourth logic unit 640 can output the determined fourth channel signal CHS4 to the switch control unit 200.

[0135] Reference Figure 7 This example demonstrates the operation of each of the multiple logic units that determine the channel signal.

[0136] The switch control unit 200 can output each of a plurality of control signals and each of a plurality of switch signals to each of a plurality of switch transistors based on channel signals received from a plurality of logic units. The plurality of switch transistors can control the electrical connections between output circuits based on the plurality of control signals. The plurality of switch transistors can control the electrical connection between the control voltage line VCIL and the output circuit based on the plurality of switch signals.

[0137] The following examples will demonstrate the operation of each of the multiple logic units of the channel signal.

[0138] Figure 7 A switch control unit 200 that outputs control signals based on signals output from a logic unit is shown according to an embodiment of the present disclosure.

[0139] omission and Figure 6 The description of multiple overlapping logical units.

[0140] Reference Figure 7The first logic unit 610 can receive from the first sampling latch circuit SAR1 a value corresponding to the most significant two bits of the first image data sampled by the first sampling latch circuit SAR1. The first logic unit 610 can also receive from the first holding latch circuit HOR1 a value corresponding to the most significant two bits of the first image data supplied to the first holding latch circuit HOR1. The first logic unit 610 can generate a first channel signal CHS1 based on the difference between the most significant two bits provided from the first sampling latch circuit SAR1 and the most significant two bits provided from the first holding latch circuit HOR1. The first channel signal CHS1 can be provided to the switch control unit 200.

[0141] For example, the first logic unit 610 can receive the most significant two bits with the value '00' from the first sampling latch circuit SAR1 and the most significant two bits with the value '11' from the first holding latch circuit HOR1. Therefore, the first logic unit 610 can generate a two-bit first signal with the value '01'.

[0142] Reference Figure 7 The second sampling latch circuit SAR2 can provide the second logic unit 620 with a value corresponding to the most significant two bits of the second image data. The second holding latch circuit HOR2 can also provide the second logic unit 620 with a value corresponding to the most significant two bits of the second image data. The second logic unit 620 can generate the second channel signal CHS2 based on the difference between the most significant two bits provided by the second sampling latch circuit SAR2 and the second holding latch circuit HOR2.

[0143] For example, the second logic unit 620 can receive the most significant two bits with a value of '11' from the second sampling latch circuit SAR2 and the most significant two bits with a value of '00' from the second holding latch circuit HOR2. Therefore, the second logic unit 620 can generate a two-bit second signal with a value of '10'. The second logic unit 620 can output a second channel signal CHS2 corresponding to the generated second signal to the switch control unit 200.

[0144] Reference Figure 7The third logic unit 630 can receive from the third sampling latch circuit SAR3 a value corresponding to the most significant two bits of the third image data sampled by SAR3. The third logic unit 630 can also receive from the third holding latch circuit HOR3 a value corresponding to the most significant two bits of the third image data supplied to HOR3. The third logic unit 630 can generate a third channel signal CHS3 based on the difference between the most significant two bits provided by SAR3 and HOR3. The third channel signal CHS3 can be provided to the switch control unit 200.

[0145] For example, the third logic unit 630 can receive the most significant two bits with the value '11' from the third sampling latch circuit SAR3 and the third holding latch circuit HOR3. Therefore, the third logic unit 630 can generate a two-bit third signal with the value '11' or '00'.

[0146] Reference Figure 7 The fourth logic unit 640 can receive from the fourth sampling latch circuit SAR4 a value corresponding to the most significant two bits of the fourth image data sampled by SAR4. The fourth logic unit 640 can also receive from the fourth holding latch circuit HOR4 a value corresponding to the most significant two bits of the fourth image data supplied to HOR4. The fourth logic unit 640 can generate a fourth channel signal CHS4 based on the difference between the most significant two bits provided by SAR4 and HOR4. The fourth channel signal CHS4 can be provided to the switch control unit 200.

[0147] For example, the fourth logic unit 640 can receive the most significant two bits with the value '00' from the fourth sampling latch circuit SAR4 and the most significant two bits with the value '00' from the fourth holding latch circuit HOR4. Therefore, the fourth logic unit 640 can generate a two-bit third signal with the value '00' or '11'.

[0148] The switch control unit 200 can output multiple switch control signals and multiple control signals by receiving first channel signal CHS1, second channel signal CHS2, third channel signal CHS3 and fourth channel signal CHS4 from the first output circuit OC1, the second output circuit OC2, the third output circuit OC3 and the fourth output circuit OC4 respectively.

[0149] For example, the switch control unit 200 can receive a first signal from the first output circuit OC1. The switch control unit 200 can receive a second signal from the second output circuit OC2. The switch control unit 200 can receive a third signal from the third output circuit OC3. The switch control unit 200 can receive a third signal from the fourth output circuit OC4. The switch control unit 200 can output a first control signal CS1 with a conduction level to the gate node of the first switching transistor SWT1, allowing the first output circuit OC1 and the second output circuit OC2 to share charge. The switch control unit 200 can output a first switch signal SW1, a second switch signal SW2, a third switch signal SW3, a fourth switch signal SW4, a second control signal CS2, a third control signal CS3, a fourth control signal CS4, a fifth control signal CS5, and a sixth control signal CS6 with a turn-off level.

[0150] Various situations regarding electrical connections between multiple output circuits will be discussed below. Figure 8 Examples are given in the description.

[0151] Figure 8 It is a timing diagram of multiple signals based on the change of MSB value according to an embodiment of the present disclosure.

[0152] Reference Figure 8 The timing diagram can represent the states of the first MSB value CHS1_MSB of the first output circuit OC1, the second MSB value CHS2_MSB of the second output circuit OC2, the third MSB value CHS3_MSB of the third output circuit OC3, and the fourth MSB value CHS4_MSB of the fourth output circuit OC4. The on / off levels of the first to fourth switch control signals SW1 to SW4 and the first to sixth control signals CS1 to CS6 can be controlled based on the changes in each of the first to fourth MSB values ​​CHS1_MSB, CHS2_MSB, CHS3_MSB, and CHS4_MSB.

[0153] The timing diagram can represent the on and off states of the first switch signal SW1, the second switch signal SW2, the third switch signal SW3, the fourth switch signal SW4, the first control signal CS1, the second control signal CS2, the third control signal CS3, the fourth control signal CS4, the fifth control signal CS5, and the sixth control signal CS6.

[0154] The switch control unit 200 can control multiple switching transistors, enabling data lines DL connected to the output circuit where the MSB value changes from '0' to 1 and data lines DL connected to the output circuit where the MSB value changes from '1' to '0' to share charge.

[0155] The switch control unit 200 can control multiple switching transistors so that, among the data lines DL connected to the output circuit whose MSB value changes from '0' to '1', the data line closest to the data line corresponding to the output circuit whose MSB value changes from '1' to '0' can share charge.

[0156] If both an output circuit with an increased MSB value and an output circuit with a decreased MSB value exist simultaneously, a control signal can be output at an ON level to control the switching transistor connected to the data line DL of the corresponding output circuit.

[0157] If only an output circuit with an increased MSB value exists, a switching signal can be output at an on level to turn on the switching transistor that precharges the data line DL connected to the corresponding output circuit.

[0158] The timing diagram may include multiple time periods during which multiple switching transistors are controlled when the source enable signal SOE is low. The timing diagram may include a first time period P1 to a 24th time period P24.

[0159] During the first time period P1, the first MSB value CHS1_MSB can change from '0' to '1'. The second MSB value CHS2_MSB, the third MSB value CHS3_MSB, and the fourth MSB value CHS4_MSB can remain unchanged.

[0160] The switch control unit 200 can output a first switch signal SW1 with an on level to the gate node of the seventh switch transistor SWT7 to precharge the first data line DL1. The second switch signal SW2, the third switch signal SW3, the fourth switch signal SW4, the first control signal CS1, the second control signal CS2, the third control signal CS3, the fourth control signal CS4, the fifth control signal CS5, and the sixth control signal CS6 can have an off level. The voltage of the precharged first data line DL1 can increase exponentially.

[0161] During the third time period P3, the fifth time period P5, the seventh time period P7, the ninth time period P9, the eleventh time period P11, the thirteenth time period P13, and the fifteenth time period P15, multiple transistors SWT1 to SWT10 can operate as they did in the first time period P1. That is, if at least one of the first to fourth MSB values ​​CHS1_MSB, CHS2_MSB, CHS3_MSB, and CHS4_MSB increases and the remaining first to fourth MSB values ​​CHS1_MSB, CHS2_MSB, CHS3_MSB, and CHS4_MSB remain unchanged, the data line corresponding to the output circuit with the increased MSB value can be pre-charged.

[0162] During the second time period P2, the first MSB value CHS1_MSB of the first output circuit OC1 can change from '1' to '0'. The second MSB value CHS2_MSB2 can change from '0' to '1'. The third MSB value CHS3_MSB and the fourth MSB value CHS4_MSB can remain unchanged.

[0163] The switch control unit 200 can output a first control signal CS1 with an on level to the gate node of the first switch transistor SWT1. The first switch signal SW1, the second switch signal SW2, the third switch signal SW3, the fourth switch signal SW4, the second control signal CS2, the third control signal CS3, the fourth control signal CS4, the fifth control signal CS5, and the sixth control signal CS6 can have an off level.

[0164] In response to the first control signal CS1, the first switching transistor SWT1 can be turned on, and the first data line DL1 and the second data line DL2 can be connected. Therefore, the first data line DL1 and the second data line DL2 can share charge. The voltage of the charge-sharing data line DL can increase exponentially.

[0165] During the sixth period P6, the tenth period P10, and the fourteenth period P14, multiple transistors SWT1 to SWT10 can operate as they did in the second period P2.

[0166] During the fourth period P4, the first MSB value CHS1_MSB can change from '1' to '0'. The second MSB value CHS2_MSB can change from '1' to '0'. The third MSB value CHS3_MSB can change from '0' to '1'. The fourth MSB value CHS4_MSB can remain unchanged.

[0167] The switch control unit 200 can output a fourth control signal CS4 with an on level to the gate node of the fourth switch transistor SWT4. The first switch signal SW1, the second switch signal SW2, the third switch signal SW3, the fourth switch signal SW4, the first control signal CS1, the second control signal CS2, the third control signal CS3, the fifth control signal CS5, and the sixth control signal CS6 can have an off level.

[0168] In response to the fourth control signal CS4, which has an on-level, the fourth switching transistor SWT4 can be turned on, and the second data line DL2 and the third data line DL3 can be connected. Therefore, the second data line DL2 and the third data line DL3 can share charge.

[0169] During the 12th period P12, multiple transistors SWT1 to SWT10 can operate in the same manner as in the fourth period P4.

[0170] During the eighth time period P8, the first MSB value CHS1_MSB can change from '1' to '0'. The second MSB value CHS2_MSB can change from '1' to '0'. The third MSB value CHS3_MSB can change from '1' to '0'. The fourth MSB value CHS4_MSB can change from '0' to '1'.

[0171] The switch control unit 200 can output a sixth control signal CS6 with an on level to the gate node of the sixth switch transistor SWT6. That is, among the data lines DL1, DL2, and DL3 connected to the output circuit where the MSB value changes from '1' to '0', the sixth switch transistor SWT6, connected to the third data line DL3 and the fourth data line DL4 closest to the fourth data line DL4 connected to the output circuit where the MSB value changes from '0' to '1', can be turned on. The first switch signal SW1, the second switch signal SW2, the third switch signal SW3, the fourth switch signal SW4, the first control signal CS1, the second control signal CS2, the third control signal CS3, the fourth control signal CS4, and the fifth control signal CS5 can have an off level.

[0172] If the sixth switching transistor SWT6 is turned on, the third data line DL3 and the fourth data line DL4 can be connected. Therefore, the third data line DL3 and the fourth data line DL4 can share charge.

[0173] During time period P16, the first MSB value CHS1_MSB, the second MSB value CHS2_MSB, the third MSB value CHS3_MSB, and the fourth MSB value CHS4_MSB can change from '1' to '0'.

[0174] Therefore, the first switch signal SW1, the second switch signal SW2, the third switch signal SW3, the fourth switch signal SW4, the first control signal CS1, the second control signal CS2, the third control signal CS3, the fourth control signal CS4, the fifth control signal CS5, and the sixth control signal CS6 can have a turn-off level voltage. For example, if the first signal is not provided (i.e., when only at least some of the second and third signals are output), the switch control unit 200 can turn off all the switching transistors and charge-sharing transistors.

[0175] During period 18 (P18), multiple transistors SWT1 to SWT10 can operate as they did during period 16 (P16).

[0176] During the 17th time period P17, the first MSB value CHS1_MSB, the second MSB value CHS2_MSB, the third MSB value CHS3_MSB, and the fourth MSB value CHS4_MSB can change from '0' to '1'.

[0177] Therefore, the switch control unit 200 can output a first switch signal SW1, a second switch signal SW2, a third switch signal SW3, and a fourth switch signal SW4, each with a conduction level, to the gate nodes of the seventh switch transistor SWT7, the eighth switch transistor SWT8, the ninth switch transistor SWT9, and the tenth switch transistor SWT10, respectively. The first control signal CS1, the second control signal CS2, the third control signal CS3, the fourth control signal CS4, the fifth control signal CS5, and the sixth control signal CS6 can have a turn-off level voltage.

[0178] Therefore, the seventh switching transistor SWT7, the eighth switching transistor SWT8, the ninth switching transistor SWT9, and the tenth switching transistor SWT10 can be turned on. Therefore, the first data line to the fourth data line DL1 to DL4 can be pre-charged.

[0179] In this way, when only the first signal is output from the output circuit (i.e., when the MSB of the image data changes from 0 to 1), the data line corresponding to the first signal output can be precharged.

[0180] During time period P19 (19th period), the first MSB value CHS1_MSB and the fourth MSB value CHS4_MSB can change from '0' to '1'. The second MSB value CHS2_MSB and the third MSB value CHS3_MSB can remain unchanged.

[0181] Therefore, the switch control unit 200 can output a first switch signal SW1 with an on level to the gate node of the seventh switch transistor SWT7 to precharge the first data line DL1. The switch control unit 200 can output a fourth switch signal SW4 with an on level to the gate node of the tenth switch transistor SWT10 to precharge the fourth data line DL4.

[0182] During time period P20 (20th period), the second MSB value CHS2_MSB and the third MSB value CHS3_MSB can change from '0' to '1'. The first MSB value CHS1_MSB and the fourth MSB value CHS4_MSB can change from '1' to '0'.

[0183] Therefore, the switch control unit 200 can output a first control signal CS1 with a conduction level to the gate node of the first switching transistor SWT1. The second control signal CS2, the third control signal CS3, the fourth control signal CS4, the fifth control signal CS5, and the sixth control signal CS6 can have a turn-off level voltage.

[0184] The switch control unit 200 can output a third switch signal SW3 with an on level to the gate node of the ninth switch transistor SWT9 in order to precharge the third data line DL3.

[0185] During time period P21 (21st period), the MSB values ​​of the first MSB value CHS1_MSB and the fourth MSB value CHS4_MSB can change from '0' to '1'. The second MSB value CHS2_MSB and the third MSB value CHS3_MSB can change from '1' to '0'.

[0186] Therefore, the switch control unit 200 can output a first control signal CS1 and a sixth control signal CS6 with a conduction level to the gate node of the first switching transistor SWT1 and the gate node of the sixth switching transistor SWT6, respectively. Here, the data line connected to the output circuit where the MSB value changes from '0' to '1' can be connected to the closest data line where the MSB value changes from '1' to '0'. For example, the first data line DL1 can be connected to the second data line DL2, and the third data line DL3 can be connected to the fourth data line DL4.

[0187] During time period P22, the first MSB value (CHS1_MSB) can change from '1' to '0'. The second MSB value (CHS2_MSB) can remain unchanged. The third MSB value (CHS3_MSB) can change from '0' to '1'. The fourth MSB value (CHS4_MSB) can change from '1' to '0'.

[0188] Therefore, the switch control unit 200 can output a sixth control signal CS6 with an on level to the gate node of the sixth switch transistor SWT6. The first switch signal SW1, the second switch signal SW2, the third switch signal SW3, the fourth switch signal SW4, the first control signal CS1, the second control signal CS2, the third control signal CS3, the fourth control signal CS4, and the fifth control signal CS5 can have an off level.

[0189] With the sixth switching transistor SWT6 turned on, the third data line DL3 and the fourth data line DL4 can be connected. Therefore, the third data line DL3 and the fourth data line DL4 can share charge.

[0190] During period 24 (P24), multiple transistors SWT1 to SWT10 can operate in the same manner as during period 22 (P22).

[0191] During time period P23 (23rd period), the first MSB value CHS1_MSB can change from '0' to '1'. The second MSB value CHS2_MSB can remain unchanged. The third MSB value CHS3_MSB can change from '1' to '0'. The fourth MSB value CHS2_MSB4 can change from '0' to '1'.

[0192] Therefore, the switch control unit 200 can output a sixth control signal CS6 with a conduction level and a first switch signal SW1. Thus, the third data line DL3 and the fourth data line DL4 can share charge, and data line DL1 can be pre-charged. That is, the third data line DL3 can share charge with the fourth data line DL4, which is the closest data line among the data lines DL1 and DL4 connected to the output circuit where the MSB value changes from '0' to '1', and the remaining first data line DL1 can be pre-charged.

[0193] The second switch signal SW2, the third switch signal SW3, the fourth switch signal SW4, the first control signal CS1, the second control signal CS2, the third control signal CS3, the fourth control signal CS4, and the fifth control signal CS5 can have a turn-off level voltage.

[0194] The power improvements will be described below in terms of pre-charging and charge sharing.

[0195] Figure 9 This is a table showing the power consumption reduction status according to embodiments of this disclosure.

[0196] In the case of pre-charging or charge sharing, the steps required to increase the voltage of the data line DL are divided. Therefore, the amount of voltage change is reduced, and thus the required power can also be reduced.

[0197] Reference Figure 9 Based on several examples of pre-charging and charge sharing, multiple output circuits can be pre-charged and charge-shared. For example, the examples may include: a first example C1 where only pre-charging occurs; a second example C2 where only charge sharing occurs; a third example C3 where both pre-charging and charge sharing occur; and a fourth example C4 where neither pre-charging nor charge sharing occurs. In the following description, power consumption is defined as follows: a drive voltage of 6V, a voltage output from the control voltage line VCIL of 3V, and a data voltage VDATA at full swing. The full swing of the drive voltage, the voltage output from the control voltage line VCIL, and the data voltage VDATA can be modified.

[0198] In the first example C1, where the number of output circuits whose MSB value changes from '0' to '1' is 1 and the number of output circuits whose MSB value changes from '1' to '0' is zero, the corresponding output circuit can be pre-charged. In this case, the power consumption of the output circuit can be reduced by 25%.

[0199] For example, to output the data voltage VDATA, the output circuit may require 6mW of power based on a voltage of 6V and a current of 1mA. The output circuit pre-charged according to the first example C1 requires 1.5mW of power during pre-charging, based on a voltage of 3V and a current of 0.5mA. When outputting the data voltage VDATA, the output circuit pre-charged according to the first example C1 requires 3mW of power based on a voltage of 6V and a current of 0.5mA. Therefore, the output circuit pre-charged according to the first example C1 may require 4.5mW of power to output the data voltage VDATA. Thus, the output circuit pre-charged according to the first example C1 can output the data voltage VDATA at 75% of the power used in conventional output circuits.

[0200] In the second example C2, where the number of output circuits whose MSB value changes from '0' to '1' is 1 and the number of output circuits whose MSB value changes from '1' to '0' is 1, the corresponding output circuits can perform charge sharing. The power consumption of the charge-sharing output circuits can be reduced by 50%.

[0201] For example, based on a voltage of 6V and a current of 1mA, the power required for the two output circuits to output the data voltage VDATA could be 12mW. When outputting the data voltage VDATA, the two output circuits sharing the charge could require 6mW of power. Therefore, according to the second example C2, the charge-sharing output circuit can output the data voltage VDATA at 50% of the power used by the existing output circuit.

[0202] According to the third example C3, the number of output circuits whose MSB value changes from '0' to '1' is 2 and the number of output circuits whose MSB value changes from '1' to '0' is 1, the output circuits can perform pre-charging and charge sharing.

[0203] Referring to the description in the first example C1, the pre-charged output circuit may require 4.5mW of power. Referring to the description in the second example C2, the charge-sharing output circuit may require 3mW of power. Therefore, the charge-sharing output circuit and the pre-charged output circuit may require 7.5mW of power. The two existing output circuits may require 12mW of power. Therefore, the charge-sharing output circuit and the pre-charged output circuit may output the data voltage VDATA at 62.5% of the power used by the two existing output circuits.

[0204] According to the fourth example C4, where the number of output circuits whose MSB value changes from '0' to '1' is 4 and the number of output circuits whose MSB value changes from '1' to '0' is zero, the output circuits may not require precharging and charge sharing.

[0205] When there are 4 output circuits whose MSB value changes from '1' to '0' and no output circuit whose MSB value changes from '0' to '1', the output circuits can operate as in the fourth example C4.

[0206] The implementation methods of the above-described disclosure are briefly described below.

[0207] A display device according to an embodiment of the present disclosure may include: a display panel in which a plurality of sub-pixels are arranged and the display panel is configured to display an image; a data driving circuit configured to supply data voltage to the plurality of sub-pixels via data lines; a first switch configured to supply pre-charge voltage to the data lines; and a second switch connected to two of the data lines.

[0208] The data driving circuit is configured to sequentially supply data voltages corresponding to image data to a plurality of sub-pixels, output switch signals to each of the first switches based on the changes in the sequentially output image data, and output control signals to each of the second switches based on the changes in the image data.

[0209] The data driving circuit is configured to include: a first output circuit configured to sequentially output data voltages corresponding to first image data to a first sub-pixel among a plurality of sub-pixels via a first data line; a second output circuit configured to sequentially output data voltages corresponding to second image data to a second sub-pixel among a plurality of sub-pixels via a second data line; a third output circuit configured to sequentially output data voltages corresponding to third image data to a third sub-pixel among a plurality of sub-pixels via a third data line; and a fourth output circuit configured to sequentially output data voltages corresponding to fourth image data to a fourth sub-pixel among a plurality of sub-pixels via a fourth data line.

[0210] The second switch may include: a first switching transistor configured to connect a first data line and a second data line according to a first control signal; a second switching transistor configured to connect a first data line and a third data line according to a second control signal; a third switching transistor configured to connect a first data line and a fourth data line according to a third control signal; a fourth switching transistor configured to connect a second data line and a third data line according to a fourth control signal; a fifth switching transistor configured to connect a second data line and a fourth data line according to a fifth control signal; and a sixth switching transistor configured to connect a third data line and a fourth data line according to a sixth control signal.

[0211] The first switch may include: a first precharge transistor configured to connect a first data line to a control voltage line for applying a precharge voltage according to a first switch signal; a second precharge transistor configured to connect the control voltage line to the second data line according to a second switch signal; a third precharge transistor configured to connect the control voltage line to the third data line according to a third switch signal; and a fourth precharge transistor configured to connect the control voltage line to the fourth data line according to a fourth switch signal.

[0212] Each of the first, second, third, and fourth output circuits is configured to supply an output signal having one of the first, second, and third signals to the switch control unit of the data drive circuit based on the change in the most significant bit (MSB) value of its respective image data.

[0213] If the MSB value of at least one output circuit changes from 0 to 1, the output circuit whose MSB value changes from 0 to 1 can supply a first signal to the switch control unit.

[0214] If the MSB value of at least one output circuit changes from 1 to 0, the output circuit whose MSB value changes from 1 to 0 can supply a second signal to the switch control unit.

[0215] If the MSB value of at least one output circuit does not change, the output circuit with the unchanged MSB value can supply a third signal to the switch control unit.

[0216] Each of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit is configured to supply an output signal having one of the first signal, the second signal, and the third signal to the switch control unit of the data drive circuit based on the change in the value of the most significant two bits of the image data.

[0217] If the value of the most significant 2 bits of at least one output circuit changes from 00 to 11, the output circuit whose most significant 2 bits change from 00 to 11 is configured to supply the first signal to the switch control unit.

[0218] If the value of the most significant 2 bits of at least one output circuit changes from 11 to 00, the output circuit whose value changes from 11 to 00 is configured to supply the second signal to the switch control unit.

[0219] If the most significant two bits of at least one output circuit change from 00 to 10, the output circuit whose most significant two bits change from 00 to 10 is configured to supply the first signal to the switch control unit.

[0220] If the value of the most significant 2 bits of at least one output circuit changes from 11 to 01, the output circuit whose most significant 2 bits change from 11 to 01 is configured to supply the second signal to the switch control unit.

[0221] If the first signal and the second signal are output from the output signals of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit, then the switching transistor that connects the data line of the output circuit that outputs the first signal to the data line of the output circuit that outputs the second signal can be turned on.

[0222] Among the data lines of the output circuit that outputs the first signal, the data line closest to the data line of the output circuit that outputs the second signal can be connected to the data line of the output circuit that outputs the second signal.

[0223] If at least one of the output signals of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit is a first signal and the remaining output signal is a third signal, then the precharge transistor corresponding to the data line of the output circuit supplying the first signal can be turned on.

[0224] If there are more output circuits that output the first signal than output circuits that output the second signal, then the switching transistor that connects the data line of the output circuit that outputs the first signal to the data line of the output circuit that outputs the second signal, and the data line of the output circuit that outputs the second signal, can be turned on.

[0225] In this case, the data line connected to the output circuit corresponding to the first output signal, but not the precharge transistor connected to the switched transistor, can be turned on.

[0226] If there are more output circuits that output the second signal than output circuits that output the first signal, then the switching transistor that connects the data line of the output circuit that outputs the second signal to the data line of the output circuit that outputs the first signal and the data line of the output circuit that outputs the first signal can be turned on.

[0227] In this case, the data line connected to the output circuit corresponding to the output of the second signal, but not the precharge transistor connected to the turned-on switching transistor, can be turned off.

[0228] Each of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit may include a logic unit configured to output one of the first signal, the second signal, and the third signal to the switch control unit based on changes in the MSB value of the image data.

[0229] If the MSB value of the output circuit including the logic unit changes from 0 to 1, the logic unit can output the first signal.

[0230] If the MSB value of the output circuit including the logic unit changes from 1 to 0, the logic unit can output a second signal.

[0231] If the MSB value of the output circuit including the logic unit does not change, the logic unit can output a third signal.

[0232] The display device may also include a controller configured to supply image data to the data driving circuitry.

[0233] The controller is configured to provide at least one of a first signal, a second signal, and a third signal to at least one of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit based on the MSB value of the corresponding image data output from each of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit.

[0234] If the MSB value of the corresponding image data changes from 0 to 1, the controller can provide a first signal to the output circuit where the MSB value of the corresponding image data changes from 0 to 1.

[0235] If the MSB value of the corresponding image data changes from 1 to 0, the controller can provide a second signal to the output circuit where the MSB value of the corresponding image data changes from 1 to 0.

[0236] If the MSB value of the corresponding image data does not change, the controller can provide a third signal to the output circuit where the MSB value of the corresponding image data does not change.

[0237] An output circuit providing a first signal is configured to supply the first signal to a switch control unit, an output circuit providing a second signal is configured to supply the second signal to a switch control unit, and an output circuit providing a third signal is configured to supply the third signal to a switch control unit.

[0238] The above description is presented to enable any person skilled in the art to make and use the technical concepts of the present invention, and is provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The above description and drawings provide examples of the technical concepts of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention.

Claims

1. A display device, comprising: A display panel, wherein a plurality of sub-pixels are arranged in the display panel, and the display panel is configured to display an image; A data driving circuit is configured to supply data voltage to the plurality of sub-pixels via data lines; A first switch is configured to supply a pre-charge voltage to the data line; as well as The second switch connects two of the data lines. The data driving circuit is configured to: sequentially supply data voltages corresponding to image data to the plurality of sub-pixels; output a switching signal to each of the first switches based on the change in the sequentially output image data; and output a control signal to each of the second switches based on the change in the image data.

2. The display device according to claim 1, wherein, The data driving circuit includes: A first output circuit is configured to sequentially output data voltages corresponding to the first image data to a first sub-pixel among the plurality of sub-pixels via a first data line; The second output circuit is configured to sequentially output data voltages corresponding to the second image data to the second sub-pixels among the plurality of sub-pixels via the second data line; A third output circuit is configured to sequentially output data voltages corresponding to the third image data to the third sub-pixel among the plurality of sub-pixels via a third data line; and A fourth output circuit is configured to sequentially output data voltages corresponding to the fourth image data to the fourth sub-pixel among the plurality of sub-pixels via a fourth data line; and The second switch includes: A first switching transistor is configured to connect the first data line and the second data line according to a first control signal; A second switching transistor is configured to connect the first data line and the third data line according to a second control signal; A third switching transistor is configured to connect the first data line and the fourth data line according to a third control signal; A fourth switching transistor is configured to connect the second data line and the third data line according to a fourth control signal; A fifth switching transistor, configured to connect the second data line and the fourth data line according to a fifth control signal; and A sixth switching transistor is configured to connect the third data line and the fourth data line according to a sixth control signal.

3. The display device according to claim 2, wherein, The first switch includes: A first precharge transistor is configured to connect the first data line to a control voltage line for applying a precharge voltage according to a first switch signal. A second precharge transistor is configured to connect the control voltage line and the second data line according to a second switch signal; A third precharge transistor is configured to connect the control voltage line and the third data line according to a third switch signal; and A fourth precharge transistor is configured to connect the control voltage line and the fourth data line according to a fourth switch signal.

4. The display device according to claim 3, wherein, Each of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit is configured to supply an output signal having one of the first signal, the second signal, and the third signal to the switch control unit of the data drive circuit based on the change in the most significant bit (MSB) value of its respective image data.

5. The display device according to claim 4, wherein, If the MSB value of at least one output circuit changes from 0 to 1, the output circuit whose MSB value changes from 0 to 1 supplies the first signal to the switch control unit. Wherein, if the MSB value of at least one output circuit changes from 1 to 0, the output circuit whose MSB value changes from 1 to 0 supplies the second signal to the switch control unit, and If the MSB value of at least one output circuit does not change, the output circuit with the unchanged MSB value supplies the third signal to the switch control unit.

6. The display device according to claim 3, wherein, Each of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit is configured to supply an output signal having one of the first signal, the second signal, and the third signal to the switch control unit of the data drive circuit based on the change in the value of the most significant two bits of the image data.

7. The display device according to claim 6, wherein, If the most significant two bits of at least one output circuit change from 00 to 11, the output circuit whose most significant two bits change from 00 to 11 is configured to supply the first signal to the switch control unit. Specifically, if the most significant two bits of at least one output circuit change from 11 to 00, the output circuit whose most significant two bits change from 11 to 00 is configured to supply the second signal to the switch control unit. Wherein, if the most significant two bits of at least one output circuit change from 00 to 10, the output circuit whose most significant two bits change from 00 to 10 is configured to supply the first signal to the switch control unit. Specifically, if the most significant two bits of at least one output circuit change from 11 to 01, the output circuit whose most significant two bits change from 11 to 01 is configured to supply the second signal to the switch control unit. If the value of the most significant two bits of at least one output circuit remains unchanged, the output circuit whose value of the most significant two bits remains unchanged supplies the third signal to the switch control unit.

8. The display device according to claim 5, wherein, If the first signal and the second signal are output among the output signals of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit, then the switching transistor connected to the data line of the output circuit that outputs the first signal and the data line of the output circuit that outputs the second signal will be turned on.

9. The display device according to claim 8, wherein, Among the data lines of the output circuit that outputs the first signal, the data line closest to the data line of the output circuit that outputs the second signal is connected to the data line of the output circuit that outputs the second signal.

10. The display device according to claim 5, wherein, If at least one of the output signals of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit is the first signal and the remaining output signal is the third signal, then the precharge transistor corresponding to the data line of the output circuit supplying the first signal is turned on.

11. The display device according to claim 5, wherein, If there are more output circuits that output the first signal than output circuits that output the second signal, then the switching transistor that connects the data line of the output circuit that outputs the first signal to the data line of the output circuit that outputs the second signal and the data line of the output circuit that outputs the second signal is closest to each other is turned on, and the precharge transistor that is connected to the data line of the output circuit that outputs the first signal but not connected to the turned-on switching transistor is turned on.

12. The display device according to claim 5, wherein, If there are more output circuits that output the second signal than output circuits that output the first signal, then the switching transistor that connects the data line of the output circuit that outputs the second signal to the data line of the output circuit that outputs the first signal and the data line of the output circuit that outputs the first signal is connected is turned on, and the precharge transistor that is connected to the data line of the output circuit that outputs the second signal but not connected to the turned-on switching transistor is turned off.

13. The display device according to claim 3, wherein, Each of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit includes a logic unit configured to output one of a first signal, a second signal, and a third signal to the switch control unit of the data drive circuit based on changes in the MSB value of the image data.

14. The display device according to claim 13, wherein, If the MSB value of the output circuit including the logic unit changes from 0 to 1, the logic unit outputs the first signal. Wherein, if the MSB value of the output circuit including the logic unit changes from 1 to 0, the logic unit outputs the second signal, and If the MSB value of the output circuit including the logic unit does not change, the logic unit outputs the third signal.

15. The display device of claim 3, further comprising a controller configured to supply image data to the data driving circuit. in, The controller is configured to provide at least one of a first signal, a second signal, and a third signal to at least one of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit based on the MSB value of the corresponding image data output from each of the first output circuit, the second output circuit, the third output circuit, and the fourth output circuit.

16. The display device according to claim 15, wherein, If the MSB value of the corresponding image data changes from 0 to 1, the controller provides the first signal to the output circuit where the MSB value of the corresponding image data changes from 0 to 1. Specifically, if the MSB value of the corresponding image data changes from 1 to 0, the controller provides the second signal to the output circuit where the MSB value of the corresponding image data changes from 1 to 0. If the MSB value of the corresponding image data does not change, the controller provides the third signal to the output circuit where the MSB value of the corresponding image data does not change.

17. The display device according to claim 16, wherein, An output circuit provided with the first signal is configured to supply the first signal to a switch control unit of the data drive circuit, an output circuit provided with the second signal is configured to supply the second signal to the switch control unit, and an output circuit provided with the third signal is configured to supply the third signal to the switch control unit.

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