Display screen refreshing method, display device and electronic equipment

Abstract

The embodiment of the invention provides a display screen refreshing method, a display device and electronic equipment, relates to the technical field of communication, and is used for improving the display effect. According to the method, a first clock signal and a first frame signal output by a time schedule controller are pulse signals with a fixed period, and a display screen can be refreshed only when a second clock signal and a second frame signal are pulse signals with a fixed period. The source driver outputs a first locking signal which jumps at a first moment; outputting a second clock signal and a second frame signal after the first clock signal and the first frame signal are locked at a first moment; the period of the second clock signal and the period of the second frame signal are changed, so that when the second clock signal and the second frame signal are pulse signals with non-fixed periods, at the moment, when the display screen is refreshed based on the second clock signal and the second frame signal, the display screen keeps the current frame image not to be refreshed, and abnormal data cannot be displayed by the display screen; the display screen does not have abnormal display, and the display effect is improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a display screen refresh method, display device, and electronic device. Background Technology

[0002] Electrostatic discharge (ESD) is a major factor affecting the reliability of display modules in electronic devices. This is especially true for electronic devices with high protection requirements, where the display module's ability to withstand ESD is crucial. For example, a commonly used display module must maintain normal display performance within ±8 kV of air discharge voltage or ±6 kV of contact discharge voltage. Electronic devices undergo ESD testing before leaving the factory. ESD can cause abnormal display on the screen, such as flickering (including flickering patterns, flashing bands, flickering lines, and flickering black screens) and black screens.

[0003] Currently, abnormal display issues are handled through software; however, abnormal displays still occur during the processing, resulting in poor display quality. Summary of the Invention

[0004] This application provides a display screen refresh method, display device, and electronic device to improve display performance.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] A first aspect provides a display screen refresh method applied to a display device, the display device including a timing controller, a source driver, and a display screen. The method includes: outputting a first clock signal and a first frame signal through the timing controller; outputting a first lock signal through the source driver, the first lock signal changing at a first moment; and outputting a second clock signal and a second frame signal after the first clock signal and the first frame signal are locked at the first moment. The display screen is then refreshed.

[0007] In this system, both the first clock signal and the first frame signal are fixed-period pulse signals. The transition of the first lock signal at the first moment indicates that the display device is in an abnormal state, including electrostatic discharge. Locking the first clock signal at the first moment means that the state of the first clock signal after the first moment remains fixed and unchanged, thus the state of the second clock signal after the first moment is the locked level. Similarly, locking the first frame signal at the first moment means that the state of the first frame signal after the first moment remains fixed and unchanged, thus the state of the second frame signal after the first moment is the locked level.

[0008] In the above technical solution, since both the first clock signal and the first frame signal are fixed-period pulse signals, the display screen will only be refreshed when both the second clock signal and the second frame signal are fixed-period pulse signals. The first lock signal changes at the first moment (i.e., the display device is in an abnormal state), and after the first clock signal and the first frame signal are locked at the first moment, the second clock signal and the second frame signal are output. Thus, after the first moment, both the second clock signal and the second frame signal are locked at a level (i.e., both are fixed levels), changing the period of the second clock signal and the period of the second frame signal, making both the second clock signal and the second frame signal non-fixed-period pulse signals. When refreshing the display screen based on the second clock signal and the second frame signal, since both the second clock signal and the second frame signal are non-fixed-period pulse signals, the display screen maintains the current frame and is not refreshed, abnormal data is not displayed, and there is no abnormal display, thus improving the display effect.

[0009] In any possible implementation of the first aspect, the second clock signal is low after the first moment, and the second frame signal is high after the first moment. In the above possible implementations, after the first moment, both the second clock signal and the second frame signal are pulse signals with non-fixed periods. When the display screen is refreshed using the second clock signal and the second frame signal, the display screen maintains the current frame image without being refreshed, abnormal data is not displayed on the display screen, and there is no abnormal display on the display screen, thus improving the display effect.

[0010] In any possible implementation of the first aspect, the first lock signal transitions at a second time point, which is after the first time point; the duration of the level of the second clock signal after the first time point is greater than the first duration, which is the duration between the second time point and the first time point; and / or, the duration of the level of the second frame signal after the first time point is greater than the first duration.

[0011] The transition at the second moment is used to indicate that the display device has ended an abnormal state. For example, the transition at the second moment can be used to indicate that the display device has ended an electrostatic discharge state. The duration of the low level of the second clock signal after the first moment is longer than the first duration, and / or, the duration of the high level of the second frame signal after the first moment is longer than the first duration.

[0012] In the above possible implementations, after the first locking signal changes at the second moment to end the abnormal state, the second clock signal is continuously low and the second frame signal is continuously high. Both the second clock signal and the second frame signal are specific timing sequences for continuous output. The display screen maintains the display of the current frame image. The display screen does not refresh during the display time of the current frame image to prevent abnormal data from being displayed on the display screen and improve the display effect.

[0013] In any possible implementation of the first aspect, the second clock signal has the same timing as the first clock signal after the third time point, and the third time point is not earlier than the second time point; the second frame signal has the same timing as the first frame signal after the fourth time point, and the fourth time point is not earlier than the second time point.

[0014] The third and fourth moments can be the same moment or different moments.

[0015] In the above possible implementations, the timing of the second clock signal and the first clock signal are the same, and the timing of the second frame signal and the first frame signal are the same. The display screen displays normally, ensuring the normal display of the data to be displayed and improving the display effect.

[0016] In any possible implementation of the first aspect, the method further includes setting the first locking signal to the target level before the first moment.

[0017] The target level can be a high level.

[0018] In the above possible implementations, since the first moment is the moment when the level of the first locking signal changes, the state of the display device before the first moment includes the power-on state. This ensures that the first locking signal is at the target level when the display device is in the power-on state, preventing the controller from locking the first clock signal and the second frame signal when the device is in the power-on state, thereby reducing the error rate.

[0019] In any possible implementation of the first aspect, before the first moment, the timing of the second clock signal is the same as that of the first clock signal, and the timing of the second frame signal is the same as that of the first frame signal. In the above possible implementations, the normal display of the data to be displayed is guaranteed.

[0020] Secondly, a display device is provided, comprising: a timing controller, a controller, a source driver, and a display screen, wherein the controller is connected to the timing controller and the source driver. The timing controller is used to output a first clock signal and a first frame signal; the source driver is used to output a first lock signal, the first lock signal changing at a first moment; the controller is used to lock the first clock signal and the first frame signal at the first moment and output a second clock signal and a second frame signal; the source driver is used to refresh the display screen based on the second clock signal and the second frame signal.

[0021] In the above technical solution, since both the first clock signal and the first frame signal are fixed-period pulse signals, the display screen will only be refreshed when both the second clock signal and the second frame signal are fixed-period pulse signals. When the first lock signal changes at the first moment (i.e., the display device is in an abnormal state), the first clock signal and the first frame signal are locked at the first moment, and then the second clock signal and the second frame signal are output. In this way, the second clock signal and the second frame signal are both locked at a level (i.e., both are fixed levels) after the first moment, which changes the period of the second clock signal and the period of the second frame signal, making both the second clock signal and the second frame signal non-fixed-period pulse signals. When the display screen is refreshed based on the second clock signal and the second frame signal, since both the period of the second clock signal and the second frame signal are non-fixed period pulse signals, the display screen maintains the current frame image and will not be refreshed. Abnormal data will not be displayed on the display screen, and there will be no abnormal display on the display screen, thus improving the display effect. On the other hand, compared with software processing of abnormal display, using the controller to process abnormal display is less time-consuming. For example, the response time of the controller to process abnormal display can be within 200ns, which is much less than the time required to refresh a row of pixels on the display screen at the highest refresh rate (1.9μs). This shortens the time and ensures that the display screen displays normally during the electrostatic discharge test of the electronic device.

[0022] In any possible implementation of the second aspect, the second clock signal is low after the first moment, and the second frame signal is high after the first moment.

[0023] In any possible implementation of the second aspect, the first locking signal transitions at a second time (ends electrostatic discharge state), the second time being after the first time; the duration of the second clock signal's level (which is low) after the first time is greater than the first duration, the first duration being the duration between the second time and the first time; and / or, the duration of the second frame signal's level (which is high) after the first time is greater than the first duration.

[0024] In any possible implementation of the second aspect, the second clock signal has the same timing as the first clock signal after the third time point, and the third time point is not earlier than the second time point; the second frame signal has the same timing as the first frame signal after the fourth time point, and the fourth time point is not earlier than the second time point, wherein the third time point and the fourth time point may be the same or different.

[0025] In any possible implementation of the second aspect, the controller is also configured to set the first locking signal to a target level before the first moment, for example, the target level is a high level.

[0026] In any possible implementation of the second aspect, before the first moment, the timing of the second clock signal is the same as that of the first clock signal, and the timing of the second frame signal is the same as that of the first frame signal.

[0027] In any possible implementation of the second aspect, the controller includes: an AND gate, a NOT gate, and an OR gate; the AND gate is used to receive a first clock signal and a first lock signal, and output a second clock signal; the NOT gate is used to receive the first lock signal and output a second lock signal; and the OR gate is used to receive the second lock signal and a first frame signal, and output a second frame signal. In the above possible implementations, using the controller to handle abnormal display on the screen shortens the processing time and improves the display effect.

[0028] Thirdly, an electronic device is provided, comprising a processor and a display device, wherein the processor is configured to send display data to the display device, and the display device is configured to display the display data, and the display device is a display device provided as in the second aspect or any possible implementation thereof.

[0029] It is understood that the beneficial effects achieved by any of the display devices and electronic devices provided above can be referred to in the beneficial effects of the display screen refresh method provided above, and will not be repeated here. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of a display module provided in an embodiment of this application;

[0031] Figure 2 A schematic diagram of the structure of a display screen provided in an embodiment of this application;

[0032] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0033] Figure 4 This is a schematic diagram of the structure of a display device provided in an embodiment of this application;

[0034] Figure 5 A schematic diagram of a first clock signal and a first frame signal provided for an embodiment of this application;

[0035] Figure 6 A timing diagram of a signal provided in an embodiment of this application;

[0036] Figure 7 A timing diagram of another signal provided in an embodiment of this application;

[0037] Figure 8 This is a schematic diagram of another display device provided in an embodiment of this application;

[0038] Figure 9 A timing diagram of a signal under different states is provided for an embodiment of this application;

[0039] Figure 10 A timing diagram of a first locking signal and a second clock signal provided for an embodiment of this application;

[0040] Figure 11 A timing diagram of another first locking signal and a second clock signal provided for an embodiment of this application;

[0041] Figure 12 This is a flowchart of a display screen refresh method provided in an embodiment of this application. Detailed Implementation

[0042] The following sections will discuss the fabrication and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this application and technology, and do not limit the scope of this application.

[0043] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to one of ordinary skill in the art.

[0044] Each circuit or other component may be described or referred to as "for" performing one or more tasks. In this context, "for" is used to imply a structure by indicating that the circuit / component includes a structure (e.g., a circuit system) that performs one or more tasks during operation. Therefore, even when the specified circuit / component is currently inoperable (e.g., not turned on), it can still be referred to as "for performing that task." Circuits / components used with the term "for" include hardware, such as circuits that perform operations.

[0045] The technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, a, b, and c; where a, b, and c can be single or multiple.

[0046] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or order of execution. The term "coupling" is used to indicate an electrical connection, including direct connection via wires or terminals or indirect connection via other devices. Therefore, "coupling" should be considered as a broad type of electronic communication connection.

[0047] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0048] Before introducing the embodiments of this application, firstly, in conjunction with Figure 1 and Figure 2 The structure of the display module and the display principle of the screen are explained.

[0049] For example, Figure 1 This is a schematic diagram of the structure of a display module provided in an embodiment of this application. The display module includes a timing controller (TCON), multiple source drivers (SD), and a display screen.

[0050] The TCON (Transformer Control Unit) is the core component controlling the display screen. It converts the video signal to be displayed into the data signal required by the source driver and outputs it. The TCON also outputs the GOA (Gate On Array) signal. For example, the TCON may include a gate driver on array (GOA) circuit. The GOA circuit is a gate circuit integrated on the array substrate and can be used to replace traditional gate driver chips to control the opening or closing of the gates of pixels in the display screen. The GOA circuit can output the GOA signal. The GOA signal is used to control the refresh of the display screen. The GOA signal includes a frame signal STV and a clock signal CKV. The frame signal STV indicates the start or end of a frame. Each frame corresponds to one frame signal STV, or each frame has one frame signal at the beginning and one at the end.

[0051] The SD is used to receive GOA signals and data signals from the TCON, and uses the GOA signals and data signals to control the display screen to refresh the display. For example, the display screen may include a liquid crystal display screen or an organic light-emitting diode (OLED) display screen.

[0052] Specifically, the display screen includes a multi-row, multi-column pixel array. Each of the multiple SDs corresponds to one or more columns of pixels in the display screen. The TCON can be used to send a GOA signal and a data signal for the corresponding column or more columns of pixels to each SD. Each SD can be used to control the refresh display of the corresponding column or more columns of pixels based on the GOA signal and the data signal. Multiple SDs control the refresh display of the display screen. In practical applications, the display module can control the entire display screen through one SD, or it can control the display screen together through multiple SDs. This application does not impose specific limitations on this comparison. Figure 1 Take multiple SD-controlled displays as an example.

[0053] For example, Figure 2 This is a schematic diagram of the structure of a display screen provided in an embodiment of this application. The display screen includes a multi-row, multi-column pixel array. Figure 2 The example described uses a pixel array comprising 7 rows of pixels, with multiple columns of pixels controlled by a single SD (Screen Display). When data needs to be displayed on the screen, the SD controls the pixel array to refresh the display row by row based on the GOA (Glass Outer Array) signal and the data signal. Specifically, the SD opens the gate of each row of pixels in the display row by row based on the GOA signal, and controls the charging voltage of each row of pixels row by row based on the data signal, so that each pixel in each row is charged to its required voltage to display different gray levels. Figure 2 The dashed arrows in the image indicate the order in which pixels are refreshed and displayed.

[0054] The following section introduces and explains the relevant knowledge about electrostatic discharge (ESD).

[0055] ESD is a major factor affecting the reliability of display modules in electronic devices, especially for electronic devices with high protection requirements, where the display module's ability to withstand ESD is crucial. For example, a commonly used display module needs to meet the following criteria: normal display performance within ±8 kV of air discharge voltage or ±6 kV of contact discharge voltage. For ease of understanding, let's assume the following: Criterion A: normal display performance within the specified limits (including air discharge and contact discharge voltages); Criterion B: temporary loss or reduction of display performance within the specified limits after interference, but automatic recovery after the interference stops; Criterion C: temporary loss or reduction of display performance within the specified limits after interference, but requiring operator intervention to recover; Criterion D: loss or reduction of display performance due to hardware or software damage or data loss, with no possibility of recovery. In practical applications, different electronic devices need to meet different criteria. For example, in-vehicle devices need to meet criterion B, while portable electronic devices such as mobile phones, tablets, and laptops need to meet criterion A. However, most electronic devices need to meet criterion A.

[0056] Electronic devices must undergo ESD certification testing before being put on the market. Only electronic devices that pass ESD certification testing can be released to the market. ESD can cause abnormal display on the display module. For example, abnormal display can include screen flickering (including flickering patterns, shiny bands, flickering lines, and flickering black screen) and black screen. In some embodiments, abnormal display can be handled through the following two methods.

[0057] Option 1: Software-based polling-based exception handling. Specifically, through software polling detection running on TCON, when a low-level lock signal is detected, TCON performs a reset operation on SD during idle periods of computing power. The display will resume normal operation once the lock signal changes from low to high.

[0058] Option 2: Interrupt-based exception handling. Specifically, when the TCON internal functional module detects that the lock signal is low, the TCON executes an interrupt response. The TCON controls the GOA signal to maintain its current level for a certain period of time (e.g., one frame). At the same time, the SD is reset within one frame, causing the lock signal to change from low to high. When displaying the next frame, the display screen displays normally.

[0059] However, both of the above solutions are time-consuming, and abnormal displays still occur during the processing, resulting in poor display quality. Specifically, Solution 1 is limited by the computing power of TCON. Taking the most powerful TCON as an example, the entire processing time is at least 1ms, and the display still contains 1ms of abnormal data. For instance, taking a 90Hz refresh rate display module as an example, the time to display one frame is 1000ms divided by 90Hz, approximately 11ms. If there is 1ms of abnormal data in one frame, this 1ms of abnormal data will manifest as... The abnormal display in the horizontal image manifests as flickering and shimmering bands. Solution two: Due to limitations in the TCON interrupt response time, for example, in some embodiments, the fastest TCON interrupt response time is 33μs, and the display still exhibits 33μs of abnormal data. For instance, taking a 90Hz refresh rate 1080p display module as an example, the display time for one frame is 1000ms divided by 90Hz, approximately 11ms. The refresh time for one line is 11000μs divided by 1080, approximately 10.18us. The 33us of abnormal data manifests as three rows of pixels in a single frame (11ms), specifically as shimmering bands and thin, flashing lines.

[0060] Since both of the above methods are time-consuming and have poor display effects, ESD certification tests on electronic devices using either method still show abnormal displays and fail to meet the A criterion, i.e., they cannot meet the A criterion requirements for certification.

[0061] Based on this, this application provides a display screen refresh method, which is applied in a display device including a TCON, an SD, and a display screen. A first clock signal and a first frame signal are output through a timing controller. A first lock signal is output through a source driver. The first lock signal changes at a first moment, and after the first clock signal and the first frame signal are locked at the first moment, a second clock signal and a second frame signal are output. Since the first clock signal and the first frame signal are both fixed-period pulse signals, the display screen is refreshed only when the second clock signal and the second frame signal are both fixed-period pulse signals. When the first lock signal changes at the first moment (i.e., the display device is in an abnormal state), the first clock signal and the first frame signal are locked at the first moment, and then the second clock signal and the second frame signal are output. Thus, the second clock signal and the second frame signal are both locked at a level (i.e., both are fixed levels) after the first moment, changing the period of the second clock signal and the period of the second frame signal, making both the second clock signal and the second frame signal non-fixed-period pulse signals. When the display screen is refreshed based on the second clock signal and the second frame signal, since the period of the second clock signal and the second frame signal are both non-fixed period pulse signals, the display screen maintains the current frame image and will not be refreshed. Abnormal data will not be displayed on the display screen, and there will be no abnormal display on the display screen, thus improving the display effect.

[0062] The technical solution of this application can be applied to various electronic devices with display devices. Optionally, the electronic device may include, but is not limited to: mobile phone, tablet computer, laptop computer, handheld computer, mobile internet device (MID), camera, wearable device, audio equipment, audio and video player, set-top box, game console, printer, mouse, keyboard, in-vehicle equipment, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, smart home device, smart robot, workshop equipment, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, or wireless terminal in smart home, flight equipment, etc. For example, wearable devices include smartwatches, smart bracelets, pedometers, etc.; vehicle-mounted devices include devices on vehicles such as cars, airplanes, ships, trains, and high-speed trains; smart home devices include refrigerators, televisions, air conditioners, electricity meters, etc.; and flying devices include smart robots, hot air balloons, drones, airplanes, etc.

[0063] In one possible embodiment, the electronic device may be a medium-to-large screen electronic device that includes a display device.

[0064] The following example uses a mobile phone as an example to illustrate the structure of this electronic device. Figure 3 As shown, the electronic device may include components such as a radio frequency (RF) circuit 110, a memory 120, an input unit 130, a display device 140, a sensor 150, an audio circuit 160, a processor 170, and a power supply 180. Optionally, the display device 140 may be one of the display devices described above.

[0065] RF circuit 110 can be used to send and receive information, or to receive or send signals during a call. Specifically, it receives downlink information from the base station and processes it in processor 170; additionally, it sends uplink data to the base station. Typically, RF circuit 110 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier (LNA), a duplexer, etc. Furthermore, RF circuit 110 can also communicate wirelessly with networks and other devices.

[0066] The memory 120 can be used to store data, software programs, and modules; it includes a program storage area and a data storage area. The program storage area can store the operating system and applications required for at least one function, such as sound playback and image playback functions. The data storage area can store data created based on the use of the electronic device, such as audio data, image data, and a phone book. Furthermore, the electronic device may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. In embodiments of this application, the memory may include multiple memories, including a first memory and a second memory.

[0067] Input unit 130 can be used to receive input numerical or character information, and to generate key signal inputs related to user settings and function control of the electronic device. Input unit 130 may include touch screen 131 and other input devices 132. Touch screen 131 can collect touch operations on or near the user and drive corresponding connected devices according to a pre-set program. For example, touch operations may include operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touch screen. Optionally, other input devices 132 may include, but are not limited to, one or more of a physical keyboard, function keys, mouse, joystick, etc., such as volume control buttons, power switch buttons, etc.

[0068] Display device 140 can be used to display information input by the user or information provided to the user, as well as various menus of the electronic device. In one example, display device 140 may include a display screen 141. The display screen 141 may be configured as an LCD, an organic light-emitting diode (OLED), or an AMOLED. Furthermore, touch screen 131 may cover the display screen 141. When touch screen 131 detects a touch operation on or near it, it transmits the information to processor 170 to determine the type of touch event. Subsequently, processor 170 provides corresponding visual output on display screen 141 according to the type of touch event. Although in the figures, touch screen 131 and display screen 141 are shown as two separate components to implement the input and output functions of the electronic device, in some embodiments, touch screen 131 and display screen 141 may be integrated to implement the input and output functions of the electronic device.

[0069] Sensor 150 may include one or more sensors for providing status assessments of various aspects of the electronic device. Sensor 150 may include a light sensor, which can be used in imaging applications, i.e., as a component of a camera or video camera. Furthermore, sensor 150 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor. Sensor 150 can detect acceleration / deceleration, orientation, on / off state, relative positioning of components, or temperature changes of the electronic device.

[0070] Audio circuitry 160, a speaker, and a microphone provide an audio interface between the user and the electronic device. Audio circuitry 160 converts received audio data into electrical signals and transmits them to the speaker, where the speaker converts them into sound signals for output. On the other hand, the microphone converts collected sound signals into electrical signals, which are then received by audio circuitry 160, converted into audio data, and output to RF circuitry 110 for transmission to, for example, another mobile phone, or to memory 120 for further processing.

[0071] The processor 170 is the control center of the electronic device, connecting various parts of the device through various interfaces and lines. It performs various functions and processes data by running or executing software programs and / or modules stored in the memory 120, and by calling data stored in the memory 120, thereby providing overall control of the electronic device. Optionally, the processor 170 may include one or more processing units, which may include, but are not limited to: a central processing unit (CPU), a network processing unit (NPU), a graphics processing unit (GPU), an image signal processor (ISP), a tensor processing unit (TPU), a data processing unit (DPU), a digital signal processor (DSP), a microcontroller, or a microprocessor. Furthermore, the processor 170 may also include other hardware circuits or accelerators, such as application-specific integrated circuits (ASICs), complex programmable logic devices (CPLDs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. Optionally, the processor 170 may also be a combination of functions that implement computing, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, etc.

[0072] The electronic device may also include a power supply 180 (e.g., a battery) to power various components. The power supply 180 can be logically connected to the processor 170 via a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system. Optionally, the power management system can simultaneously support fast charging and non-fast charging technologies. In practical applications, the power management system can charge the battery in the power supply 180 using either fast charging or non-fast charging technologies.

[0073] The electronic device may also include a wireless fidelity (WiFi) module, a Bluetooth module, etc., which will not be described in detail in the embodiments of this application. Those skilled in the art will understand that... Figure 3The illustrated electronic device structure does not constitute a limitation on the electronic device and may include more or fewer components than illustrated, or combine certain components, or have different component arrangements.

[0074] The display refresh method provided in this application can be implemented in hardware or software. The specific implementation methods of hardware and software are described below.

[0075] The display refresh method provided in this application can be implemented in hardware or software. The specific implementation methods of hardware and software are described below. Figure 4 First, the process of refreshing the display screen through hardware will be explained in detail.

[0076] Figure 4 This is a schematic diagram of a display device provided in an embodiment of this application. The display device can be as described above. Figure 3 The display device 140 shown is included. This display device includes a TCON 210, a controller 220, an SD 230, and a display screen 240. The controller 220 is connected to the TCON 210 and the SD 230, and the display screen 240 is connected to the SD 230. The TCON 210 can be used to output a first clock signal CKV1 and a first frame signal STV1; the SD 230 can be used to output a first lock signal LO1, which transitions at a first time T1. The transition of the first lock signal LO1 indicates that the display device is in an abnormal state, including an electrostatic discharge state; the controller 220 can be used to lock the first clock signal CKV1 and the first frame signal STV1 at the first time T1, and output a second clock signal CKV2 and a second frame signal STV2; the SD 230 can be used to refresh the display screen 240 based on the second clock signal CKV2 and the second frame signal STV2.

[0077] The abnormal state of the display device may include electrostatic discharge state and interference state, etc. In the following embodiments, the abnormal state of the display device is electrostatic discharge state as an example for illustration.

[0078] In one possible embodiment, TCON 210 can be used to receive a video signal to be displayed from a processor and convert the video signal into a data signal. For example, the processor can be as described above. Figure 3The processor 170 shown can transmit video signals including, but not limited to, Mobile Industry Processor Interface (MIPI) signals and Video Buffer Object (VBO) signals, and data signals including, but not limited to, Port-to-Port (PTP) signals and Mini-Low-Voltage Differential Signaling (mini-LVDS) signals. PTP signals can also be referred to as P2P signals; in this application, P2P signals indicate that the data signals use the PTP protocol. Furthermore, TCON 210 is also used to output data signals to SD 230 and to output a first clock signal CKV1 and a first frame signal STV1 to controller 220. SD 230 can be used to send a first lock signal LO1 to controller 220. When the first lock signal LO1 transitions at a first time T1, controller 220, based on the transition of the first lock signal at the first time T1, locks the first clock signal CKV1 and the first frame signal STV1 at the first time T1, and outputs a second clock signal CKV2 and a second frame signal STV2. SD 230 can be used to control the refresh display of display screen 240 based on the second clock signal CKV2, the second frame signal STV2, and the data signal. For example, SD 230 can be used to refresh display screen 240 line by line based on the second clock signal CKV2 and the second frame signal STV2, and control display screen 240 to display line by line based on the data signal. The second clock signal CKV2 can be used to control the refresh time of the row pixels, and the second frame signal STV2 is a frame start signal or a frame end signal, which can be used to indicate the start or end of a frame. That is, the second frame signal STV2 can be used to control the start refresh time of the first row of pixels in display screen 240, and SD 230 starts refreshing display screen 240 line by line based on the second frame signal STV2.

[0079] The first lock signal LO1 is a lock signal used for communication between TCON 210 and SD 230. SD 230 can send the first lock signal LO1 to TCON 210 to establish a communication link between SD 230 and TCON 210. For example, in a non-electrostatic discharge state, the first lock signal LO1 is at a first level (e.g., high level). In an electrostatic discharge state, SD 230 causes the first lock signal LO1 to transition from the first level to a second level (e.g., low level). The first lock signal LO1 being low can also be referred to as an abnormal timing signal. Therefore, the transition of the first lock signal is used to indicate the electrostatic discharge state. For example, when the first lock signal LO1 transitions from high to low, it indicates that the display device is in an electrostatic discharge state; when the first lock signal LO1 transitions from low to high, it indicates that the display device has ended the abnormal state. The first lock signal can be represented as SD lock1.

[0080] Secondly, the first moment T1 is the moment when the level of the first locking signal LO1 changes; for example, the first locking signal LO1 changes from a high level to a low level at the first moment T1. For example, the state of the display device includes a power-on state (i.e., the electronic device containing the display device is in a power-on state, and this electronic device may include the aforementioned...). Figure 3 The electronic device shown in the figure is in a normal display state and an abnormal display state. In the power-on state and the normal display state, the first locking signal LO1 is at a high level. When the first locking signal LO1 changes at the first moment T1, for example, the first locking signal LO1 changes from a high level to a low level at the first moment T1, the display device is in an abnormal display state, or in an electrostatic discharge state.

[0081] In addition, such as Figure 5 As shown, both the first clock signal CKV1 and the first frame signal STV1 are pulse signals with fixed periods. For example, the first clock signal CKV1 is a pulse signal with a period of Ta, and the first frame signal STV1 is a pulse signal with a period of Tb. Ta and Tb can be the same or different, and this application does not impose specific limitations on them. The first clock signal CKV1 includes multiple first pulses P1, and the first frame signal STV1 includes multiple second pulses P2. The timing relationship between the first clock signal CKV1 and the first frame signal STV1 is such that there is a second pulse P2 between any two adjacent first pulses P1.

[0082] In practical applications, TCON 210 can also output multiple first clock signals CKV1 and multiple first frame signals STV1. When TCON 210 outputs multiple first clock signals CKV1 and multiple first frame signals STV1, for each of the multiple first clock signals CKV1, controller 220 locks the first clock signal CKV1 at time T1 based on the transition of the first locking signal LO1 at time T1 and outputs the corresponding second clock signal CKV2. Multiple first clock signals CKV1 correspond to multiple second clock signals CKV2. Similarly, for each of the multiple first frame signals STV1, controller 220 locks the first frame signal STV1 at time T1 based on the transition of the first locking signal LO1 at time T1 and outputs the corresponding second frame signal STV2. Multiple first frame signals STV1 correspond to multiple second frame signals STV2. SD 230 can be used to progressively refresh display screen 240 based on multiple second clock signals CKV2 and multiple second frame signals STV2. The refresh time of each row of pixels is controlled by one second clock signal CKV2 or by a combination of multiple second clock signals CKV2. The multiple second frame signals STV2 can be used to jointly control the start refresh time of the first row of pixels in display screen 240. That is, SD 230 starts progressively refreshing display screen 240 based on multiple second frame signals STV2. Figure 4 The example uses a first clock signal CKV1 and a first frame signal STV1.

[0083] Furthermore, locking the first clock signal CKV1 and outputting the second clock signal CKV2 at the first time T1 means that the state of the first clock signal CKV1 after the first time T1 is fixed at a level (i.e., low level) and remains unchanged. Thus, the state of the second clock signal CKV2 before the first time T1 is consistent with the state of the first clock signal CKV1 before the first time T1. The state of the second clock signal CKV2 after the first time T1 (low level) is the locked level state, meaning the second clock signal CKV2 is low after the first time T1. Similarly, locking the first frame signal STV1 and outputting the second frame signal STV2 at the first time T1 means that the state of the first frame signal STV1 after the first time T1 is fixed at a level (i.e., high level) and remains unchanged. Thus, the state of the second frame signal STV2 before the first time T1 is consistent with the state of the first frame signal STV1 before the first time T1. The state of the second frame signal STV2 after the first time T1 (high level) is the locked level state, meaning the second frame signal STV2 is high after the first time T1.

[0084] Since the first moment T1 can be the transition moment of the first clock signal CKV1 or the first frame signal STV1 (e.g., the moment when a high level transitions to a low level or a low level transitions to a high level), the moment of high level, or the moment of low level, the following combines... Figure 6 Each will be explained separately.

[0085] First, we will explain the four possible scenarios for the first time point T1 based on the first clock signal CKV1.

[0086] In the first possible example, such as Figure 6 As shown in (a), the first time T1 is the moment when the first clock signal CKV1 changes from high level to low level. The first clock signal CKV1 is locked to be low level after the first time T1 and remains unchanged. In this way, the state of the second clock signal CKV2 before the first time T1 is the same as the state of the first clock signal CKV1 before the first time T1. The low level state of the second clock signal CKV2 after the first time T1 is the locked level state.

[0087] In the second possible example, such as Figure 6 As shown in (b), the first time T1 is the moment when the first clock signal CKV1 changes from low level to high level. The first clock signal CKV1 is locked to be low level after the first time T1 and remains unchanged. In this way, the state of the second clock signal CKV2 before the first time T1 is the same as the state of the first clock signal CKV1 before the first time T1. The low level state of the second clock signal CKV2 after the first time T1 is the locked level state.

[0088] In the third possible example, such as Figure 6 As shown in (c), the first time T1 is when the first clock signal CKV1 is at a high level. The first clock signal CKV1 is locked to a low level after the first time T1 and remains unchanged. Thus, the state of the second clock signal CKV2 before the first time T1 is the same as the state of the first clock signal CKV1 before the first time T1. The low level state of the second clock signal CKV2 after the first time T1 is the locked level state.

[0089] In the fourth possible example, such as Figure 6 As shown in (d), the first time T1 is when the first clock signal CKV1 is at a low level. The first clock signal CKV1 is locked to be at a low level after the first time T1 and remains unchanged. In this way, the state of the second clock signal CKV2 before the first time T1 is the same as the state of the first clock signal CKV1 before the first time T1. The low level state of the second clock signal CKV2 after the first time T1 is the locked level state.

[0090] In the four possible embodiments described above, the first clock signal CKV1 is a pulse signal with a fixed period. Before the first time T1, the timing of the second clock signal CKV2 is the same as that of the first clock signal CKV1. That is, before the first time T1, the second clock signal CKV2 is also a pulse signal with a fixed period. After the first time T1, the second clock signal CKV2 is a continuous low level and is a pulse signal with a non-fixed period.

[0091] The following describes the four possible scenarios for the first time step T1 in the first frame signal STV1.

[0092] In a first possible embodiment, exemplarily, such as Figure 6 As shown in (c), the first time T1 is the moment when the first frame signal STV1 changes from high level to low level. The first frame signal STV1 is locked to be high level after the first time T1 and remains unchanged. In this way, the state of the second frame signal STV2 before the first time T1 is the same as the state of the first frame signal STV1 before the first time T1. The high level state of the second frame signal STV2 after the first time T1 is the locked level state.

[0093] In a second possible embodiment, the first time T1 is the moment when the first frame signal STV1 changes from low level to high level. The first frame signal STV1 is locked to be high level after the first time T1 and remains unchanged. In this way, the state of the second frame signal STV2 before the first time T1 is the same as the state of the first frame signal STV1 before the first time T1. The high level state of the second frame signal STV2 after the first time T1 is the locked level state.

[0094] In a third possible embodiment, an example, such as Figure 6 (a) Figure 6 (b) and Figure 6 As shown in (d), the first time T1 is when the first frame signal STV1 is at a high level. The first frame signal STV1 is locked to be at a high level after the first time T1 and remains unchanged. In this way, the state of the second frame signal STV2 before the first time T1 is the same as the state of the first frame signal STV1 before the first time T1. The high level state of the second frame signal STV2 after the first time T1 is the locked level state.

[0095] In the fourth possible embodiment, the first time T1 is the time when the first frame signal STV1 is at a low level. The first frame signal STV1 is locked to a high level after the first time T1 and remains unchanged. In this way, the state of the second frame signal STV2 before the first time T1 is the same as the state of the first frame signal STV1 before the first time T1. The high level state of the second frame signal STV2 after the first time T1 is the locked level state.

[0096] In the above four possible embodiments, the first frame signal STV1 is a pulse signal with a fixed period. Before the first time T1, the timing of the first frame signal STV1 is the same as that of the second frame signal, that is, the second frame signal STV2 is a pulse signal with a fixed period. After the first time T1, the second frame signal STV2 is a continuous high level, and the second frame signal STV2 is a pulse signal with a non-fixed period.

[0097] In one possible embodiment, exemplarily, such as Figure 7 As shown, the first locking signal LO1 changes at the second time T2, that is, at the second time T2, the first locking signal LO1 changes from low level to high level, and the display device ends the electrostatic discharge state. The second time T2 is after the first time T1.

[0098] The following is combined Figure 7 The timing relationship between the second clock signal CKV2 and the first clock signal CKV1 after the second time point T2, and the timing relationship between the second frame signal STV2 and the first frame signal STV1 will be explained.

[0099] like Figure 7 As shown, the duration of the second clock signal CKV2's level after the first time T1 is greater than the first duration Tc, and / or, the duration of the second frame signal STV2's level after the first time T1 is greater than the first duration Tc, where the first duration Tc is the duration between the second time T2 and the first time T1. For example, the duration of the second clock signal CKV2's level after the first time T1 is the second duration Td, and the end time of the second duration Td is the third time T3; the duration of the second frame signal STV2's level after the first time T1 is the third duration Tf, and the end time of the third duration Tf is the fourth time T4. The second duration Td is greater than the first duration Tc, and the third duration Tf is greater than the first duration Tc. Optionally, the third duration Tf and the second duration Td can be the same or different; this application's embodiments do not impose limitations. Figure 7 The example given is that the third duration Tf is greater than the second duration Td.

[0100] In one possible embodiment, please continue reading Figure 7After the third time point T3, the timing of the second clock signal CKV2 is the same as that of the first clock signal CKV1, and the third time point T3 is not earlier than the second time point T2. After the fourth time point T4, the timing of the second frame signal STV2 is the same as that of the first frame signal STV1, and the fourth time point T4 is not earlier than the second time point T2. After the fourth time point T4, both the second clock signal CKV2 and the second frame signal STV are restored to pulse signals with a fixed period. After the fourth time point T4, SD 230 can be used to refresh the display screen 240 based on the second clock signal CKV2 and the second frame signal STV, and the display screen 240 continues to display the next frame of data. Figure 7 The example given is that the third time T3 is after the second time T2, and the fourth time T4 is after the second time T2.

[0101] The specific structure of controller 220 is described below.

[0102] Since TCON 210 can output one first clock signal CKV1 and one first frame signal STV1, or multiple first clock signals CKV1 and multiple first frame signals STV1, multiple first clock signals CKV1 and one first frame signal STV1, or one first clock signal and multiple first frame signals STV1, the number of AND gates and OR gates included in controller 220 will also differ depending on the number of signals output by TCON 210 (including the first clock signal CKV1 and the first frame signal STV1). The four possible cases mentioned above will be explained below.

[0103] In a first possible embodiment, TCON 210 outputs a first clock signal CKV1 and a first frame signal STV1. Controller 220 includes an AND gate, a NOT gate, and an OR gate. The first input of the AND gate is connected to TCON 210, the second input of the AND gate can be used to receive a first lock signal LO1, and the output of the AND gate is connected to SD 230. The input of the NOT gate can be used to receive the first lock signal LO1, the output of the NOT gate is connected to the first input of the OR gate, the second input of the OR gate is connected to TCON 210, and the output of the OR gate is connected to SD 230.

[0104] The AND gate can be used to receive the first clock signal CKV1 and the first lock signal LO1, and perform logical operations on the first clock signal CKV1 and the first lock signal LO1 to output the second clock signal CKV2. The NOT gate can be used to receive the first lock signal LO1 and perform logical operations on the first lock signal LO1 to output the first lock signal LO2. The OR gate can be used to receive the second lock signal LO2 and the first frame signal STV1, and perform logical operations on the second lock signal LO2 and the first frame signal STV1 to output the second frame signal STV2.

[0105] In a second possible embodiment, TCON 210 outputs multiple first clock signals CKV1 and multiple first frame signals STV1. Controller 220 includes multiple AND gates, NOT gates, and multiple OR gates. The first input of each AND gate is connected to TCON 210, the second input of each AND gate can be used to receive a first lock signal LO1, and the output of each AND gate is connected to SD 230. The input of the NOT gate can be used to receive the first lock signal LO1, the output of the NOT gate can be connected to the first input of each OR gate, the second input of each OR gate is connected to TCON 210, and the output of each OR gate is connected to SD 230.

[0106] In this configuration, each of the multiple first clock signals CKV1 corresponds to an AND gate, each of the multiple first frame signals STV1 corresponds to an OR gate, and the multiple first frame signals STV1 share a NOT gate. Each AND gate can be used to receive the corresponding first clock signal CKV1 and the first lock signal LO1, and perform logical operations on the corresponding first clock signal CKV1 and the first lock signal LO1 to output a second clock signal CKV2. Multiple AND gates output multiple second clock signals CKV2. A NOT gate can be used to receive the first lock signal LO1 and perform logical operations on the first lock signal LO1 to output a first lock signal LO2. Each OR gate can be used to receive the corresponding second lock signal LO2 and the first frame signal STV1, and perform logical operations on the second lock signal LO2 and the first frame signal STV1 to output a second frame signal STV2.

[0107] In a third possible embodiment, TCON 210 outputs multiple first clock signals CKV1 and a first frame signal STV1, and controller 220 includes multiple AND gates, NOT gates, and OR gates. The connection relationships and functions of the multiple AND gates are similar to those in the second possible embodiment described above, the connection relationships and functions of the OR gates are similar to those in the first possible embodiment described above, and the connection relationships and functions of the NOT gates are similar to those in either the first or second possible embodiment described above, and will not be repeated here.

[0108] In a fourth possible embodiment, TCON 210 outputs a first clock signal CKV1 and multiple first frame signals STV1, and controller 220 includes AND gates, NOT gates, and multiple OR gates. The connection relationships and functions of the AND gates are similar to those in the first possible embodiment, the connection relationships and functions of the multiple OR gates are similar to those in the second possible embodiment, and the connection relationships and functions of the NOT gates are similar to those in either the first or second possible embodiment, and will not be repeated here.

[0109] The following describes the specific structure of controller 220 by taking the TCON 210 as an example, which outputs multiple first clock signals CKV1 and multiple first frame signals STV1. For example, TCON 210 can output four first clock signals, which can be represented as CKV1-1 to CKV1-4 respectively, and three first frame signals, which can be represented as STV1-1 to STV1-4 respectively.

[0110] Combination Figure 4 like Figure 8As shown, the controller 220 includes: four AND gates, a NOT gate 301, and three OR gates. The four AND gates can be represented as 302 to 305, and the three OR gates can be represented as 306 to 308. Specifically, AND gate 302 can be used to receive the first clock signal CKV1-1 and the first lock signal LO1, and perform logical operations on the first clock signal CKV1-1 and the first lock signal LO1 to output the second clock signal CKV2-1; AND gate 303 can be used to receive the first clock signal CKV1-2 and the first lock signal LO1, and perform logical operations on the first clock signal CKV1-2 and the first lock signal LO1 to output the second clock signal CKV2-2; AND gate 304 can be used to receive the first clock signal CKV1-3 and the first lock signal LO1, and perform logical operations on the first clock signal CKV1-3 and the first lock signal LO1 to output the second clock signal CKV2-3; AND gate 305 can be used to receive the first clock signal CKV1-4 and the first lock signal LO1, and perform logical operations on the first clock signal CKV1-4 and the first lock signal LO1 to output the second clock signal CKV2-4. OR gate 306 can be used to receive the second lock signal LO2 and the first frame signal STV1-1, and perform logical operations on the second lock signal LO2 and the first frame signal STV1-1 to output the second frame signal STV2-1. OR gate 307 can be used to receive the second lock signal LO2 and the first frame signal STV1-2, and perform logical operations on the second lock signal LO2 and the first frame signal STV1-2 to output the second frame signal STV2-2. OR gate 308 can be used to receive the second lock signal LO2 and the first frame signal STV1-3, and perform logical operations on the second lock signal LO2 and the first frame signal STV1-3 to output the second frame signal STV2-3.

[0111] Since the state of the first lock signal LO1 is unknown when the display device is powered on (i.e., the electronic device containing the display device is powered on), and abnormal timing of the first lock signal LO1 is not enabled during power-on, that is, if the first lock signal LO1 is an abnormal signal (low level) during power-on, the controller 220 does not lock the first clock signal CKV1 and the first frame signal STV1, so that the timing of the first clock signal CKV1 is the same as the timing of the second clock signal, and the timing of the first frame signal STV1 is the same as the timing of the second frame signal STV2 during power-on. Therefore, the controller 220 is also used to set the first lock signal LO1 to a target level before the first time T1, for example, the target level can be a high level. In one example, when the device is powered on, the controller 220 can perform an OR operation on the first latch signal LO1 and the general purpose input output (GPIO) signal output by TCON 210, so that the first latch signal LO1 is high when the device is powered on, wherein the GPIO signal is high when the device is powered on, and when the device is powered off, the GPIO signal changes from high to low and remains there.

[0112] Optional, such as Figure 8 As shown, the controller 220 further includes an OR gate 309. The first input of the OR gate 309 is connected to the SD 230, the second input of the OR gate 309 can be used to receive GPIO signals, and the output of the OR gate 309 is connected to the second input of each of a plurality of AND gates. The OR gate 309 can be used to receive a first lock signal LO1 and a GPIO signal, and perform an OR operation on the first lock signal LO1 and the GPIO signal to output the first lock signal LO1.

[0113] The following is combined Figure 8 ,like Figure 9 As shown, the signal timing relationship when the display device is in different states will be explained.

[0114] First state: Power-on state.

[0115] Since the GPIO signal is high when the power is on, the state of the first lock signal is unknown. OR gate 309 performs an OR operation on the first lock signal LO1 and the GPIO signal to set the first lock signal LO1 high and output it. Each AND gate performs an AND logic operation on the first lock signal LO1 and the corresponding first clock signal CKV1. Since the first lock signal LO1 is high, the AND logic operation does not change the timing of the first clock signal CKV1. Therefore, the timing of the first clock signal CKV1 is the same as the timing of the second clock signal CKV2. The NOT gate receives the first lock signal LO1 and inverts it to output the second lock signal LO2. The second lock signal LO2 is low. Each OR gate performs an OR operation on the second lock signal LO2 and the first frame signal STV1. Since the second lock signal LO2 is low, the OR operation does not change the timing of the first frame signal STV1. Therefore, the timing of the first frame signal STV1 is the same as the timing of the second frame signal STV2.

[0116] Second state: Normal display state after power-on ends.

[0117] When the power-on state ends, the GPIO signal changes from high level to low level, and the state of the first lock signal LO1 is high level. The OR gate 309 performs an OR operation on the first lock signal LO1 and the GPIO signal, which does not change the timing of the first lock signal LO1, so the first lock signal LO1 is high level. The timing of the first clock signal CKV1 is the same as the timing of the second clock signal CKV2, and the timing of the first frame signal STV1 is the same as the timing of the second frame signal STV2.

[0118] Third state: electrostatic discharge state.

[0119] The first lock signal LO1 transitions from high to low at time T1, the GPIO signal is low, and OR gate 309 performs an OR operation on the first lock signal LO1 and the GPIO signal to set the first lock signal LO1 low and output it. At time T1, each AND gate performs an AND operation on the first lock signal LO1 and the corresponding first clock signal CKV1 to set the second clock signal CKV2 low and output it. The NOT gate inverts the first lock signal LO1 to output the second lock signal LO2. At time T1, each OR gate performs an OR operation on the second lock signal LO2 and the first frame signal STV1 to set the second frame signal STV2 high and output it. Since the second clock signal CKV2 is in a fixed low state and the second frame signal STV2 is in a fixed high state after time T1, the second clock signal CKV2 and the second frame signal STV2 are non-fixed period pulse signals, the display screen 240 does not refresh and maintains the current frame.

[0120] When the electrostatic discharge state ends, the first lock signal LO1 changes from low to high at the second time T2. OR gate 309 performs an OR operation on the first lock signal LO1 and the GPIO signal to set the first lock signal LO1 high and output it. The timing of the first clock signal CKV1 is the same as that of the second clock signal CKV2, and the timing of the first frame signal STV1 is the same as that of the second frame signal STV2. The display device then returns to the third state.

[0121] In practical applications, when the display device ends the electrostatic discharge state, the display screen 240 maintains the display of the current frame and displays normally in the next frame. For example, after about 200ns of electrostatic discharge, the first lock signal LO1 changes from low level to high level, that is, after about 200ns of electrostatic discharge, the first lock signal LO1 returns to normal. The response time of the controller 220 is 200ns, which is much less than the time required to refresh one row of pixels in the display screen 240 at the highest refresh rate (i.e., the horizontal frequency time). For example, the horizontal frequency time can be 1.9μs. After the second clock signal CKV2 outputs a low level for about 11ms to 16ms (the time required to display one frame), the timing of the second clock signal CKV2 is the same as the timing of the first clock signal CKV1. Similarly, after the second frame signal STV2 outputs a high level for about 11ms to 16ms, the timing of the second frame signal STV2 is the same as the timing of the first frame signal STV1.

[0122] The electrostatic discharge certification test cycle is usually 1 second. Within the 1-second cycle, the display screen 240 can maintain the current frame when the first lock signal LO1 is abnormal, and the next frame is normal, which solves the problem of abnormal display of the display screen 240 during the electrostatic discharge certification process.

[0123] For example, Figure 10 This is a timing diagram illustrating a first locking signal LO1 and second clock signals CKV2-1 to CKV2-3, provided in an embodiment of this application. The horizontal axis represents time (μs), and the vertical axis represents voltage (V). Curve S1 represents the first locking signal LO1, and curves S2 to S4 represent the second clock signals CKV2-1 to CKV2-3. At the first time point T1, the first locking signal LO1 transitions from a high level to a low level. The second clock signals CKV2-1 to CKV2-3 remain low after time point T1, and are fixed-period pulse signals before time point T1. Figure 11 for Figure 10 The diagram shows the measured timing of the first lock signal LO1 and the second clock signals CKV2-1 to CKV2-3. The horizontal axis represents time (ns). Figure 11Taking the second clock signals CKV2-1 to CKV2-3 as an example, all of them are at a high level before the transition time T1, with T1 being 0ns.

[0124] In one possible embodiment, the TCON and SD can be integrated on different chips. For example, the chip including the TCON can be a timing controller integrated circuit (TCON IC), and the chip including the SD can be a source driver integrated circuit (SD IC). The controller can be integrated on the chip or located at the board level. For example, it can be integrated into the on-chip logic of the chip, which can be a TCON IC or an SD IC, or it can be a chip other than a TCON IC or an SD IC. This application does not make any specific limitations in comparison.

[0125] This application provides a display device including a TCON 210, a controller 220, and an SD 230, with the controller 220 connected to the TCON and SD 230. The SD 230 can output a first lock signal, which transitions at a first moment and indicates an electrostatic discharge state. The TCON 210 can output a first clock signal and a first frame signal. The controller 220 can lock the first clock signal, the first frame signal, and the first lock signal at the first moment to output a second clock signal and a second frame signal. The SD 230 refreshes the display screen 240 based on the second clock signal and the second frame signal. Since both the first clock signal and the first frame signal are fixed-period pulse signals, the display screen 240 will only be refreshed when both the second clock signal and the second frame signal are fixed-period pulse signals. In the electrostatic discharge state, the controller 220 locks the first clock signal and the first frame signal at the first moment and outputs the second clock signal and the second frame signal. That is, the controller 220 changes the period of the second clock signal and the period of the second frame signal, so that both the period of the second clock signal and the period of the second frame signal are non-fixed-period signals. At this time, when the SD 230 refreshes the display screen based on the second clock signal and the second frame signal, the display screen maintains the current frame image and will not be refreshed. Abnormal data will not be displayed on the display screen, and there is no abnormal display on the display screen, thus improving the display effect. Compared with software processing of abnormal display, using the controller 220 to process abnormal display is less time-consuming. For example, the response time of the controller 220 in processing abnormal display can be within 200ns, which is much less than the time required to refresh one row of pixels on the display screen at the highest refresh rate (1.9μs). This shortens the time and ensures that the display screen displays normally during the electrostatic discharge test of the electronic device.

[0126] The following is combined Figure 12The process of refreshing the display screen via software will be described in detail. This software includes programs or instructions running in the controller of the display device.

[0127] This application also provides a display screen refresh method, such as... Figure 12 As shown, this method is used in a display device, which can be the aforementioned... Figure 4 or Figure 8 The method, as shown in the illustration, includes the following steps.

[0128] S121, output the first clock signal CKV1 and the first frame signal STV1 through TCON 210.

[0129] In one possible embodiment, TCON 210 receives the video signal to be displayed from the processor and converts the video signal into a data signal. Further, TCON 210 outputs a first clock signal CKV1 and a first frame signal STV1 to controller 220, and outputs a data signal to SD 230. In practical applications, TCON 210 may also output multiple first clock signals CKV1 and multiple first frame signals STV1; this application does not specifically limit this.

[0130] In this application, both the first clock signal CKV1 and the first frame signal STV1 are pulse signals with fixed periods. For example, the first clock signal CKV1 is a pulse signal with a period of Ta, and the first frame signal STV1 is a pulse signal with a period of Tb. Ta and Tb can be the same or different, and this application does not make any specific restrictions on this.

[0131] S122. Output the first lock signal LO1 through SD 230. The first lock signal LO1 changes at the first moment T1.

[0132] The first locking signal LO1 changes at the first moment T1 to indicate that the display device is in an abnormal state. The abnormal state of the display device includes electrostatic discharge state and interference state, etc. The electrostatic discharge state will be used as an example for explanation below.

[0133] The first lock signal LO1 is the lock signal for communication between TCON 210 and SD 230. SD 230 can send the first lock signal LO1 to TCON 210 to establish a communication link between SD 230 and TCON 210. For example, in a non-electrostatic discharge state, the first lock signal LO1 is at a first level (e.g., high level). In an electrostatic discharge state, SD 230 causes the first lock signal LO1 to transition from the first level to a second level (e.g., low level). The first lock signal LO1 being low can also be referred to as an abnormal timing of the first lock signal LO1. Therefore, the transition of the first lock signal is used to indicate the electrostatic discharge state. For example, when the first lock signal LO1 transitions from high to low, it indicates that the display device is in an electrostatic discharge state; when the first lock signal LO1 transitions from low to high, it indicates that the display device has ended the electrostatic discharge state. The first lock signal can be represented as SD lock1.

[0134] Additionally, the first moment T1 is the moment when the level of the first lock signal LO1 changes; for example, the first lock signal LO1 changes from a high level to a low level at the first moment T1. For instance, the state of the display device includes a power-on state (i.e., the electronic device containing the display device is in a power-on state, and this electronic device may include the aforementioned...). Figure 3 The electronic device shown in the figure is in a normal display state and an abnormal display state. In the power-on state and the normal display state, the first locking signal LO1 is at a high level. When the first locking signal LO1 changes at the first moment T1, for example, the first locking signal LO1 changes from a high level to a low level at the first moment T1, the display device is in an abnormal display state, or in an electrostatic discharge state.

[0135] S123, the first clock signal CKV1 and the first frame signal STV1 are locked at the first time T1, and then the second clock signal CKV2 and the second frame signal STV2 are output.

[0136] Specifically, locking the first clock signal CKV1 and outputting the second clock signal CKV2 at the first time T1 means that the state of the first clock signal CKV1 after the first time T1 is locked to a fixed level (i.e., low level) and remains unchanged. In this way, the state of the second clock signal CKV2 before the first time T1 is consistent with the state of the first clock signal CKV1 before the first time T1. The state of the second clock signal CKV2 after the first time T1 (low level) is the locked level state. That is, the second clock signal CKV2 is low level after the first time T1.

[0137] In addition, locking the first frame signal STV1 and outputting the second frame signal STV2 at the first time T1 means that locking the state of the first frame signal STV1 after the first time T1 is a fixed level (i.e., high level) and keeping it unchanged. In this way, the state of the second frame signal STV2 before the first time T1 is the same as the state of the first frame signal STV1 before the first time T1. The state of the second frame signal STV2 after the first time T1 (high level) is the locked level state, that is, the second frame signal STV2 is high level after the first time T1.

[0138] Wherein, the first moment T1 can be the transition moment of the first clock signal CKV1 or the first frame signal STV1 (such as the moment when the high level transitions to the low level or the moment when the low level transitions to the high level), the moment when the level is high or the moment when the level is low.

[0139] In one possible embodiment, before the first time T1, the timing of the second clock signal CKV2 is the same as that of the first clock signal CKV1, and the timing of the second frame signal STV2 is the same as that of the first frame signal STV1.

[0140] In one possible embodiment, when TCON 210 outputs multiple first clock signals CKV1 and multiple first frame signals STV1, for each of the multiple first clock signals CKV1, controller 220 locks the first clock signal CKV1 at time T1 based on the transition of the first locking signal LO1 at time T1 and outputs the corresponding second clock signal CKV2, with the multiple first clock signals CKV1 corresponding to the multiple second clock signals CKV2. Similarly, for each of the multiple first frame signals STV1, controller 220 locks the first frame signal STV1 at time T1 based on the transition of the first locking signal LO1 at time T1 and outputs the corresponding second frame signal STV2, with the multiple first frame signals STV1 corresponding to the multiple second frame signals STV2.

[0141] S124, Refresh the display screen.

[0142] In one possible embodiment, when TCON 210 outputs the first clock signal CKV1 and the first frame signal STV1, SD 230 can be used to control the refresh display of the screen based on the second clock signal CKV2, the second frame signal STV2, and the data signal. For example, SD 230 can be used to refresh the screen line by line based on the second clock signal CKV2 and the second frame signal STV2, and control the screen to display line by line based on the data signal. The second clock signal CKV2 can be used to control the refresh time of the row pixels, and the second frame signal STV2 is a frame start signal or a frame end signal, which can be used to indicate the start or end of a frame. That is, the second frame signal STV2 can be used to control the start refresh time of the first row of pixels on the screen, and SD 230 starts refreshing the screen line by line based on the second frame signal STV2.

[0143] In one possible embodiment, when TCON 210 outputs multiple first clock signals CKV1 and multiple first frame signals STV1, SD 230 can be used to refresh the display screen line by line based on multiple second clock signals CKV2 and multiple second frame signals STV2. The refresh time of each row of pixels is controlled by one second clock signal CKV2 or by a combination of multiple second clock signals CKV2. The multiple second frame signals STV2 can be used to jointly control the start refresh time of the first row of pixels in the display screen, that is, SD 230 starts to refresh the display screen line by line based on multiple second frame signals STV2.

[0144] Furthermore, the method provided in this application embodiment further includes: the first lock signal LO1 changes at a second time T2, the second time T2 being after the first time T1; the duration of the level of the second clock signal CKV2 after the first time T1 is greater than a first duration, the first duration being the duration between the second time T2 and the first time T1; and / or, the duration of the level of the second frame signal STV2 after the first time T1 is greater than the first duration.

[0145] In one possible embodiment, the second clock signal CKV2 has the same timing as the first clock signal CKV1 after the third time T3, and the third time T3 is not earlier than the second time T2; the second frame signal STV2 has the same timing as the first frame signal STV1 after the fourth time T4, and the fourth time T4 is not earlier than the second time T2. The fourth time T4 and the third time T3 can be the same time or different times; this application does not impose any limitation on this comparison.

[0146] In one possible embodiment, the method provided in this application further includes: setting the first locking signal LO1 to a target level before a first moment, for example, the target level can be a high level.

[0147] In one possible embodiment, the method provided in this application further includes: before the first moment, the timing of the second clock signal CKV2 is the same as the timing of the first clock signal CKV1, and the timing of the second frame signal STV2 is the same as the timing of the first frame signal STV1.

[0148] All relevant content involved in the above-described embodiments of the display device can be referenced in the embodiments of the display refresh method, and will not be repeated here.

[0149] The display refresh method provided in this application embodiment is such that, since the first clock signal and the first frame signal are both pulse signals with fixed periods, the display screen will only be refreshed when the second clock signal and the second frame signal are both pulse signals with fixed periods. That is, when the first locking signal changes at the first moment T1 (i.e., in the electrostatic discharge state), the controller locks the first clock signal and the first frame signal at the first moment and outputs the second clock signal and the second frame signal. In other words, the controller changes the period of the second clock signal and the period of the second frame signal, so that the period of the second clock signal and the second frame signal are both signals with non-fixed periods. At this time, when the SD refreshes the display screen based on the second clock signal and the second frame signal, the display screen maintains the current frame image and will not be refreshed. Abnormal data will not be displayed on the display screen, and there is no abnormal display on the display screen, thus improving the display effect.

[0150] Based on this, this application also provides an electronic device, which includes a processor and a display device. The processor can be used to send display data to the display device, and the display device can be used to display the display data; wherein, the display device can be any of the display devices provided above. It is understood that all related content involved in the above embodiments can be referenced in the embodiments of this electronic device, and this application will not repeat it here.

[0151] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can also be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed.

[0152] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0153] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. This readable storage medium may include various media capable of storing program code, such as a USB flash drive, external hard drive, read-only memory, random access memory, magnetic disk, or optical disk. Based on this understanding, the technical solution of the embodiments of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0154] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display screen refresh method, characterized in that, Applied in a display device, the display device including a timing controller, a source driver, and a display screen, the method includes: The timing controller outputs a first clock signal and a first frame signal; The source driver outputs a first lock signal, which changes at a first moment. After the first clock signal and the first frame signal are locked at the first moment, the second clock signal and the second frame signal are output. Refresh the display screen.

2. The method according to claim 1, characterized in that, The second clock signal is low after the first moment, and the second frame signal is high after the first moment.

3. The method according to claim 1 or 2, characterized in that, The first locking signal changes at a second time point, which is after the first time point. The duration of the second clock signal level after the first time point is greater than the first duration, where the first duration is the duration between the second time point and the first time point; And / or, the duration of the second frame signal's level after the first moment is greater than the first duration.

4. The method according to claim 3, characterized in that, The second clock signal has the same timing sequence as the first clock signal after the third time point, and the third time point is not earlier than the second time point; The second frame signal has the same timing as the first frame signal after the fourth time point, and the fourth time point is not earlier than the second time point.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: The first locking signal is set to the target level before the first moment.

6. The method according to any one of claims 1-5, characterized in that, Before the first moment, the timing of the second clock signal is the same as that of the second clock signal, and the timing of the second frame signal is the same as that of the first frame signal.

7. A display device, characterized in that, The display device includes a timing controller, a source driver, a controller, and a display screen, wherein the controller is connected to the timing controller and the source driver; The timing controller is used to output a first clock signal and a first frame signal; The source driver is used to output a first lock signal, which changes at a first moment; The controller is configured to lock the first clock signal and the first frame signal at the first moment, and output the second clock signal and the second frame signal. The source driver is also used to refresh the display screen according to the second clock signal and the second frame signal.

8. The apparatus according to claim 7, characterized in that, The second clock signal is low after the first moment, and the second frame signal is high after the first moment.

9. The apparatus according to claim 7 or 8, characterized in that, The first locking signal changes at a second time point, which is after the first time point. The duration of the second clock signal level after the first time point is greater than the first duration, where the first duration is the duration between the second time point and the first time point; And / or, the duration of the second frame signal's level after the first moment is greater than the first duration.

10. The apparatus according to claim 9, characterized in that, The second clock signal has the same timing sequence as the first clock signal after the third time point, and the third time point is not earlier than the second time point; The second frame signal has the same timing as the first frame signal after the fourth time point, and the fourth time point is not earlier than the second time point.

11. The apparatus according to any one of claims 7-10, characterized in that, The controller is further configured to set the first locking signal to a target level before the first moment.

12. The apparatus according to any one of claims 7-11, characterized in that, Before the first moment, the timing of the second clock signal is the same as that of the first clock signal, and the timing of the second frame signal is the same as that of the first frame signal.

13. An electronic device, characterized in that, The electronic device includes a processor and a display device, the processor being configured to provide display data to the display device, the display device being the display device as described in any one of claims 7-12.

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