Network packet processing device and network packet forwarding method

Abstract

The invention discloses a network data packet processing device and a network data packet forwarding method. The device comprises a parallel processing circuit, a data packet distribution circuit and a data packet order-preserving processing circuit. The parallel processing circuit comprises a plurality of data packet processing circuits which are used for carrying out parallel processing on different data packets. Each packet processing circuit includes a network processor core. The data packet distribution circuit respectively distributes a plurality of data packets to the plurality of data packet processing circuits. The data packet order-preserving processing circuit performs order-preserving transmission on a plurality of processed data packets generated by the parallel processing circuit, and the plurality of processed data packets comprise a first processed data packet and a second processed data packet which respectively correspond to the first data packet and the second data packet in the plurality of data packets. And the sequence of the first processed data packet and the second processed data packet in the output data stream is the same as the sequence of the first processed data packet and the second processed data packet in the input data stream.

Description

Technical Field

[0001] This invention relates to network packet forwarding, and more particularly to a network packet processing apparatus and a related network packet forwarding method that improves packet forwarding efficiency through multi-core parallel processing. Background Technology

[0002] A gateway is a common network device used to connect different networks and forward data packets from one network to another, such as packet forwarding between wired and wireless networks. A network processing unit (NPU) is a high-speed programmable processor specifically designed for network packet processing (e.g., network packet forwarding). It possesses specific features and architectures to accelerate network packet processing efficiency. Generally, to enable interoperability between various wireless chip models, packet forwarding on the wireless end is handled by the network processor. However, under high-speed forwarding requirements, the network processor can become a bottleneck. For example, a network processor using a single core to process data streams will have low packet forwarding efficiency, and even increasing the network processor's operating frequency cannot achieve the goal of high-speed forwarding. Summary of the Invention

[0003] One of the objectives of this invention is to provide a network packet processing device and a related network packet forwarding method that improve packet forwarding efficiency through multi-core parallel processing.

[0004] In one embodiment of the present invention, a network packet processing apparatus is disclosed. The network packet processing apparatus includes a parallel processing circuit, a packet distribution circuit, and a packet ordering processing circuit. The parallel processing circuit includes multiple packet processing circuits for parallel processing of different packets, wherein each packet processing circuit includes a network processor core. The packet distribution circuit distributes multiple packets to the multiple packet processing circuits respectively. The packet ordering processing circuit sends the multiple processed packets generated by the parallel processing circuit in an ordered manner, wherein the multiple processed packets include a first processed packet and a second processed packet, corresponding to a first packet and a second packet respectively, and the order of the first and second processed packets in an output data stream sent by the packet ordering processing circuit is the same as the order of the first and second packets in an input data stream received by the packet distribution circuit.

[0005] In another embodiment of the present invention, a network packet forwarding method is disclosed. The network packet forwarding method includes: processing different data packets in parallel using multiple packet processing circuits in a parallel processing circuit, wherein each packet processing circuit includes a network processor core; distributing multiple data packets to the multiple packet processing circuits respectively; and sending the multiple processed data packets generated by the parallel processing circuits in an ordered manner, wherein the multiple processed data packets include a first processed data packet and a second processed data packet, respectively corresponding to a first data packet and a second data packet among the multiple data packets, and the order of the first and second processed data packets in an output data stream is the same as the order of the first and second data packets in an input data stream.

[0006] In another embodiment of the present invention, a network packet processing apparatus is disclosed. The network packet processing apparatus includes a parallel processing circuit, a packet distribution circuit, and a packet sending circuit. The parallel processing circuit includes multiple network processing cores. The multiple network processing cores include a first network processing core, which is used to independently process a first packet without relying on other network processor cores among the multiple network processing cores, and generate a first processed packet. The packet distribution circuit is used to distribute the first packet to the first network processing core. The packet sending circuit is used to send the first processed packet.

[0007] According to the multi-core parallel processing architecture proposed in this invention, multiple data packets are distributed to multiple data packet processing circuits for parallel processing (especially network processor cores within these circuits). Each network processor core processes the data packets independently without relying on other network processor cores. In other words, the processing of data packets by each network processor core does not affect the processing of data packets by other network processor cores. Thus, the multi-core parallel processing architecture proposed in this invention can effectively improve data packet forwarding efficiency. Furthermore, the multi-core parallel processing architecture proposed in this invention also supports a pre-order processing mechanism, ensuring that the processed data packets generated by different network processor cores through parallel processing maintain the original data stream sequence during actual forwarding. Moreover, the multi-core parallel processing architecture proposed in this invention also supports a data packet out-of-order exception handling mechanism, allowing the data packet distribution circuit to be reset when a hardware malfunction occurs, thus ensuring normal system operation. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a network data packet processing device according to an embodiment of the present invention.

[0009] Figure 2 This is a flowchart of a data packet distribution operation and a data packet sequence number distribution operation according to an embodiment of the present invention.

[0010] Figure 3 This is a flowchart of a data packet processing operation according to an embodiment of the present invention.

[0011] Figure 4 This is a flowchart of a data packet out-of-order exception handling mechanism according to an embodiment of the present invention.

[0012] Figure 5 This is a flowchart of a data packet distribution operation and a data packet sequence number distribution operation that supports a data packet out-of-order exception handling mechanism according to an embodiment of the present invention.

[0013] [Symbol Explanation]

[0014] 100: Network packet processing device

[0015] 102: Packet Distribution Circuit

[0016] 104: Parallel Processing Circuit

[0017] 106: Data packet order preservation processing circuit

[0018] 108: Dynamic Random Access Memory

[0019] 110: Packet Buffer

[0020] 112_1, 112_N: Data packet processing circuit

[0021] 114_1, 114_N: Ring buffer

[0022] 116_1, 116_N: Network processor cores

[0023] 118_1, 118_N: Output buffers

[0024] 120_1, 120_K: Serial number pool

[0025] S_IN: Input data stream

[0026] S_OUT: Output data stream

[0027] PKT: Data Packet

[0028] PKT_DESCR: Packet descriptor

[0029] PKT_INF: Data packet information

[0030] S202~S214, S302~S310, S402~S424, S501, S502, S504: Steps Detailed Implementation

[0031] Certain terms are used in the specification and claims to refer to specific elements. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same element. This specification and claims do not distinguish elements based on differences in name, but rather on differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." Furthermore, the terms "coupled" or "coupled" herein include any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0032] Figure 1 This is a schematic diagram of a network packet processing apparatus according to an embodiment of the present invention. For example, the network packet processing apparatus 100 can be applied to a network device, such as a gateway. As shown, the network packet processing apparatus 100 may include a packet distribution circuit 102, a parallel processing circuit 104, a packet ordering processing circuit 106, and a dynamic random access memory (DRAM) 108. Please note that... Figure 1 Only the elements related to the present invention are shown. In reality, the network packet processing device 100 may include other elements to achieve the specified function. For example, the network packet processing device 100 may also include a central processing unit (CPU), a hardware acceleration forwarding circuit (or frame engine), a network interface card (NIC), etc.

[0033] When the network packet processing device 100 receives a network packet (hereinafter referred to as a packet) PKT from the network connection port, the packet PKT is written to the packet buffer 110 configured in the dynamic random access memory 108. For example, when the packet buffer 110 is initialized, it is divided into multiple storage blocks according to a fixed block size to store multiple packet PKTs respectively. The parallel processing circuit 104 disclosed in this invention can then access the packet PKTs in the packet buffer 110 through direct memory access (DMA).

[0034] Parallel processing circuit 104 includes multiple data packet processing circuits 112_1 to 112_N ( This is used to perform parallel processing on different data packet PKTs. Furthermore, the data packet processing circuits 112_1 to 112_N can have the same circuit architecture, such as... Figure 1 As shown, packet processing circuit 112_1 includes a ring buffer 114_1, a network processor core (NPU core) 116_1, and an output buffer (e.g., a first-in-first-out (FIFO) buffer) 118_1, and packet processing circuit 112_N includes a ring buffer 114_N, a network processor core 116_N, and an output buffer (e.g., a first-in-first-out buffer) 118_N. The network processor cores 116_1 to 116_N in the parallel processing circuit 104 can be implemented using a multi-core RISC-V processor, but the present invention is not limited thereto.

[0035] The packet distribution circuit 102 distributes multiple packets to the packet processing circuits 112_1 to 112_N respectively, so that they can be processed in parallel by the packet processing circuits 112_1 to 112_N (especially the network processor cores 116_1 to 116_N in the packet processing circuits 112_1 to 112_N). Note that each network processor core 116_1 to 116_N will complete the packet processing independently without the help of other network processor cores. In other words, the parallel processing performed by the parallel processing circuit 104 is not pipeline processing. Therefore, when each network processor core 116_1 to 116_N performs packet processing, it will not affect the packet processing being performed by other network processor cores. In this way, the multi-core parallel processing architecture proposed in this invention can effectively improve the packet forwarding efficiency.

[0036] The packet ordering processing circuit 106 has a packet sending function, and therefore can be used as a packet sending circuit to send the processed packets generated individually by each network processor core 116_1 to 116_N in the parallel processing circuit 104. In this embodiment, in addition to the data packet sending function, the data packet ordering processing circuit 106 may also have a data packet ordering function. That is, the data packet ordering processing circuit 106 is used to send multiple processed data packets generated by the parallel processing circuit 104 (for example, data packets that need to be forwarded generated by different network processor cores 116_1 to 116_N through parallel processing) in order. In other words, the processed data packets generated by different network processor cores 116_1 to 116_N through parallel processing must maintain the sequence in the original data stream and cannot be out of order during actual forwarding. For example, the multiple processed data packets generated by different network processor cores 116_1 to 116_N through parallel processing include a first processed data packet and a second processed data packet, which correspond to a first data packet and a second data packet in the multiple data packets distributed by the data packet distribution circuit 102, respectively. The order of the first and second processed data packets in the output data stream S_OUT sent by the data packet ordering processing circuit 106 is the same as the order of the first and second data packets in the input data stream S_IN received by the data packet distribution circuit 102.

[0037] The operational details of the data packet distribution circuit 102, the parallel processing circuit 104, and the data packet order preservation processing circuit 106 will be explained below with reference to the accompanying drawings.

[0038] As mentioned earlier, the processed data packets generated by different network processor cores 116_1 to 116_N through parallel processing must maintain the sequence of the original data stream and not be out of order during actual forwarding. To ensure that the processed data packets maintain the sequence of the original data stream during forwarding, the multi-core parallel processing architecture proposed in this invention is coupled with data packet sequence numbers. The out-of-order status is detected by checking the data packet sequence numbers. In this embodiment, when the input data stream S_IN passes through the data packet distribution circuit 102, each data packet is assigned a data packet sequence number SEQ. Then, the data packet distribution circuit 102 distributes multiple data packets to the data packet processing circuits 112_1 to 112_N for parallel processing according to a predetermined distribution strategy (e.g., a predetermined order of the data packet processing circuits 112_1 to 112_N). In addition, each packet processing circuit 112_1 / 112_N includes a ring buffer 114_1 / 114_N for storing the packet descriptor PKT_DESCR. Each packet descriptor PKT_DESCR records some metadata of the corresponding packet. For example, the packet descriptor PKT_DESCR contains multiple fields to record the buffer address pkt_address of the packet in the packet buffer 110 and the packet length pkt_len. In this embodiment, in addition to these conventional information, the packet descriptor PKT_DESCR may also record the packet sequence number SEQ distributed by the packet distribution circuit 102.

[0039] In this embodiment, the data packet distribution circuit 102 may have multiple sequence number pools 120_1 to 120_K. The different sequence number pools 120_1 to 120_K have different numerical ranges that do not overlap with each other, and each sequence number pool can use a counter to count from the initial value to the maximum value, and then reset to the initial value to continue counting. For example, assuming that the packet distribution circuit 102 has two sequence number pools 120_1 and 120_K (K=2), the sequence number SEQ provided by sequence number pool 120_1 can fall in the numerical range {0, 1, 2, 3, …, 32767}, and the sequence number SEQ provided by another sequence number pool 120_K (K=2) can fall in the numerical range {32768, 32769, 32770, …, 65535}. Please note that this is only an example, and the present invention is not limited thereto. In fact, the number of sequence number pools and the numerical range of each sequence number pool can be determined according to design considerations.

[0040] Figure 2 This is a flowchart of a data packet distribution operation and a data packet sequence number distribution operation according to an embodiment of the present invention. Figure 2 The operation shown can be performed by Figure 1 The packet distribution circuit 102 shown is used to perform this operation. Furthermore, if substantially the same result can be obtained, the steps do not necessarily need to be followed exactly. Figure 2 The process is executed in the order shown. In step S202, the packet distribution circuit 102 initializes the parameter i and the packet sequence number SEQ, where parameter i is used to control packet distribution and packet sequence number SEQ is used to control packet sequence number distribution. For ease of explanation, it is assumed that the packet sequence number SEQ is provided by the sequence number pool 120_1 and the value range of the packet sequence number SEQ is {0, 1, 2, …, M-1}. In addition, the value range of parameter i is {0, 1, 2, …, N-1}, and the N network processor cores 116_1 to 116_N are represented as NPU[0] to NPU[N-1], respectively. Therefore, the initial value of parameter i is 0 (i.e., i=0), and the initial value of packet sequence number SEQ is 0 (i.e., SEQ=0).

[0041] In step S204, the packet distribution circuit 102 distributes the packet sequence number SEQ (SEQ=0 at this time) to a packet in the input data stream S_IN and decides to distribute the packet to the ring buffer of the network processor core NPU[i]. In step S206, the packet distribution circuit 102 determines whether the ring buffer of the network processor core NPU[i] is currently full. If the ring buffer of the network processor core NPU[i] is currently full, it means that the network processor core NPU[i] is currently under full load. Therefore, the packet distribution circuit 102 will continue to wait until the ring buffer of the network processor core NPU[i] has available storage space. If the packet distribution circuit 102 finds that the ring buffer of the network processor core NPU[i] has available storage space, the process will proceed to step S208.

[0042] In step S208, the packet distribution circuit 102 determines whether load balancing adjustment is needed. If the processing capabilities of network processor cores 116_1 to 116_N are unbalanced, and the packet distribution circuit 102 needs to wait continuously in step S206 until the ring buffer of the current network processor core NPU[i] has available storage space, then the packet distribution circuit 102 can perform load balancing adjustment to alleviate the processing burden of the current network processor core NPU[i]. In step S212, the packet distribution circuit 102 distributes an empty packet (i.e., a packet that does not need to be processed) to the current network processor core NPU[i]. That is, the packet distribution circuit 102 distributes the current packet sequence number SEQ to the empty packet and writes the current packet sequence number SEQ to the ring buffer of the network processor core NPU[i]. In other words, the packet descriptor PKT_DESCR of the empty packet records the current packet sequence number SEQ. In addition, because load balancing will distribute empty packets to the current network processor core NPU[i], the packet distribution circuit 102 can forward the packets in the input data stream S_IN that were originally to be distributed to the current network processor core NPU[i] to other network processor cores (e.g., the next network processor core NPU[i+1]).

[0043] If the packet distribution circuit 102 does not need to wait for the ring buffer to have available storage space in step S206, that is, the current network processor core NPU[i] is not yet fully loaded, then the packet distribution circuit 102 does not need to perform load balancing adjustment. In step S210, the packet distribution circuit 102 will distribute the packets in the input data stream S_IN to the current network processor core NPU[i]. That is, the packet distribution circuit 102 will distribute the current packet sequence number SEQ to the packets in the input data stream S_IN and write the current packet sequence number SEQ (at this time, SEQ=0) to the ring buffer of the network processor core NPU[i]. In other words, the packet descriptor PKT_DESCR of the packets in the input data stream S_IN will record the current packet sequence number SEQ.

[0044] In step S214, the packet distribution circuit 102 updates the parameter i and the packet sequence number SEQ, for example, i=(i+1)%N and SEQ=(SEQ+1)%M. Then, the process returns to step S204, where the packet distribution circuit 102 distributes the updated packet sequence number SEQ to the packets in the input data stream S_IN, and decides whether to distribute the packet to the network processor core NPU[i] according to the updated parameter i. Please note that if load balancing adjustment has been performed previously (step S212), since the data packet originally to be distributed to the previous network processor core NPU[i-1] is replaced by an empty packet, the data packet distribution circuit 102 decides that the data packet to be distributed to the current network processor core NPU[i] will be the data packet originally to be distributed to the previous network processor core NPU[i-1] (i.e., the data packet in the input data stream); if load balancing adjustment has not been performed previously (step S212), the data packet distribution circuit 102 decides that the data packet to be distributed to the current network processor core NPU[i] will be the next data packet of the data packet processed by the previous network processor core NPU[i-1] (the next data packet in the input data stream).

[0045] according to Figure 2 As shown in the process, the packet distribution circuit 102 adopts an average distribution method. Therefore, according to the predetermined order of the packet processing circuits 112_1 to 112_N (e.g., i=(i+1)%N), multiple packets (including packets actually received by the network packet processing device 100 from the network and / or empty packets that are load balanced by the packet distribution circuit 102) are distributed to the packet processing circuits 112_1 to 112_N for multi-core parallel processing. For example, the packet distribution circuit 102 distributes the packet PKT0 (a packet that needs to be forwarded or an empty packet that does not need to be forwarded) with packet sequence number SEQ=0 to the network processor core NPU[0] for processing, distributes the packet PKT1 (a packet that needs to be forwarded or an empty packet that does not need to be forwarded) with packet sequence number SEQ=1 to the network processor core NPU[1] for processing, distributes the packet PKT2 (a packet that needs to be forwarded or an empty packet that does not need to be forwarded) with packet sequence number SEQ=2 to the network processor core NPU[2] for processing, and so on; in addition, when the packet PKT0 with packet sequence number SEQ=N-1... N-1 After the data packet (which needs to be forwarded or is an empty packet that does not need to be forwarded) is distributed to the network processor core NPU [N-1], the data packet distribution circuit 102 will distribute the data packet with data packet sequence number SEQ=N to the network processor core NPU [N-1]. N (Packets that need to be forwarded or empty packets that do not need to be forwarded) are distributed to the network processor core NPU[0] for processing, and the packet with packet sequence number SEQ=N+1 is PKTN+1 (Packets that need to be forwarded or empty packets that do not need to be forwarded) are distributed to the network processor core NPU[1] for processing, and the packet with packet sequence number SEQ=N+2 is PKT N+2 (Packets that need to be forwarded or empty packets that do not need to be forwarded) are distributed to the network processor core NPU[2] for processing, and so on; in addition, step S214 will be repeatedly executed to update the packet sequence number SEQ (that is, SEQ=SEQ+1). Since the numerical range of the packet sequence number SEQ is {0, 1, 2, …, M-1}, when the packet sequence number SEQ increases and reaches the maximum value M-1, the next packet sequence number SEQ will return to the minimum value 0 (that is, SEQ=(SEQ+1)%M=0). In other words, under a total of M packet sequence numbers {0, 1, 2, …, M-1}, the order of the packet sequence numbers is as follows: When a data packet with sequence number SEQ=M-1 is PKT M-1 After the data packet (which needs to be forwarded or is an empty packet that does not need to be forwarded) is distributed to the network processor core NPU [(M-1)%N], the data packet distribution circuit 102 will distribute the data packet with data packet sequence number SEQ=0 to the network processor core NPU [(M-1)%N]. M (Packets that need to be forwarded or empty packets that do not need to be forwarded) are distributed to the network processor core NPU[M%N] for processing, and the packet with packet sequence number SEQ=1 is PKT. M+1 (Packets that need to be forwarded or empty packets that do not need to be forwarded) are distributed to the network processor core NPU [(M+1)%N] for processing, and the packet with packet sequence number SEQ=2 is PKT. M+2 (Packets that need to be forwarded or empty packets that do not need to be forwarded) are distributed to the network processor core NPU[(M+2)%N] for processing, and so on.

[0046] Step S214 will be repeatedly executed to update parameter i (i.e., i = i + 1). Since parameter i is the index value of the network processor core and the number of network processor cores 116_1 to 116_N (i.e., NPU[0] to NPU[N-1]) is N, the value range of parameter i is {0, 1, 2, …, N-1}. Therefore, when the value of parameter i increases and reaches the maximum value N-1, the next value of parameter i will return to the minimum value 0 (i.e., i = (i + 1)%N = 0). After N data packets have been sequentially distributed to network processor cores 116_1 to 116_N (i.e., NPU[0] to NPU[N-1]), the next data packet will be distributed to network processor core 116_1 (i.e., NPU[0]). That is to say, the allocation of data packets to network processor cores is based on modulo-digital operations. For example, when the currently waiting data packet is the (K+1)th data packet PKT in the input data stream S_IN K Because the preceding data packets PKT0 to Kth data packets PKT K-1 The data packets will be distributed sequentially to the network processor cores NPU[0] to NPU[N-1]. Whenever N data packets have been sequentially distributed to the network processor cores NPU[0] to NPU[N-1], the next data packet will be distributed to the network processor core NPU[0]. Therefore, according to the modulo operation, the (K+1)th data packet PKT... KThe data packet will be distributed to the network processor NPU[K%N]. Assuming the data packet currently awaiting distribution is the 9th data packet with sequence number SEQ=8 (K=8) and the number of network processor cores N=4, according to the modulo operation, the 9th data packet with sequence number SEQ=8 (K=8) will be distributed to the network processor NPU[0] (the remainder of 8 / 4 is 0); assuming the data packet currently awaiting distribution is the 14th data packet with sequence number SEQ=13 (K=13) and the number of network processor cores N=4, according to the modulo operation, the 14th data packet with sequence number SEQ=13 (K=13) will be distributed to the network processor NPU[1] (the remainder of 13 / 4 is 1), and so on. Furthermore, as mentioned earlier, the numerical range of the data packet sequence number SEQ is {0, 1, 2, …,} Therefore, when the packet sequence number SEQ increases and reaches the maximum value M-1, the next packet sequence number SEQ will return to the minimum value 0. Assuming the packet currently awaiting distribution is the (M+1)th packet with packet sequence number SEQ=0 (K=M) and the number of network processor cores N=4, according to modulo operations, the (M+1)th packet with packet sequence number SEQ=0 (K=M) will be distributed to the network processor NPU[M%N]. Assuming the packet currently awaiting distribution is the (M+9)th packet with packet sequence number SEQ=8 (K=M+N)... 8) Given that the number of network processor cores N=4, according to the modulo operation, the (M+9)th data packet (K=M+8) with data packet sequence number SEQ=8 will be distributed to the network processor NPU[(M+8)%N]; assuming that the data packet currently waiting to be distributed is the (M+14)th data packet (K=M+13) with data packet sequence number SEQ=13 and the number of network processor cores N=4, according to the modulo operation, the (M+14)th data packet (K=M+13) with data packet sequence number SEQ=13 will be distributed to the network processor NPU[(M+13)%N], and so on.

[0047] like Figure 1As shown, each packet processing circuit 112_1 / 112_N includes a ring buffer 114_1 / 114_N, a network processor core 116_1 / 116_N, and an output buffer 118_1 / 118_N. The ring buffer 114_1 / 114_N stores the packet descriptor PKT_DESCR of the corresponding packet to be processed by the network processor core 116_1 / 116_N. Therefore, the network processor core 116_1 / 116_N reads the packet descriptor PKT_DESCR of the packet to be processed from the ring buffer 114_1 / 114_N (including information such as buffer address pkt_address and packet length pkt_len), and reads the packet from the packet buffer 110 and performs the relevant packet processing according to the information provided by the packet descriptor PKT_DESCR. In addition, after the packet processing is completed, the network processor core 116_1 / 116_N writes the packet information PKT_INF to the output buffer 118_1 / 118_N. In addition to the usual buffer address pkt_address, packet length pkt_len, etc., the packet information PKT_INF may also include the packet sequence number SEQ distributed by the packet distribution circuit 102 and / or the flag discard_flag set by the network processor core 116_1 / 116_N.

[0048] Figure 3 This is a flowchart of a data packet processing operation according to an embodiment of the present invention. Figure 3 The operation shown can be performed by Figure 1 Each data packet processing circuit 112_1 / 112_N shown is used to perform this operation. Furthermore, if substantially the same result can be obtained, the steps do not necessarily need to be followed exactly. Figure 3The process is executed in the order shown. In step S302, the network processor core 116_1 / 116_N reads the packet descriptor from the corresponding ring buffer 114_1 / 114_N and processes the packet PKT with the packet sequence number SEQ (distributed by the packet distribution circuit 102) according to the packet descriptor. During packet processing, in step S304, the network processor core 116_1 / 116_N determines whether the packet PKT needs to be forwarded. For example, the network processor core 116_1 / 116_N determines whether the packet needs to be dropped or whether the packet is empty. If the packet PKT needs to be forwarded (i.e., the packet does not need to be dropped and the packet is not empty), the network processor core 116_1 / 116_N performs normal processing and sending operations. In step S306, the network processor core 116_1 / 116_N sets the discard_flag=0 to mark that this packet PKT needs to be sent out by the network packet processing device 100. If the data packet PKT does not need to be forwarded (i.e., the data packet needs to be dropped or the data packet is empty), the network processor core 116_1 / 116_N will perform out-of-order processing auxiliary operation. In step S308, the network processor core 116_1 / 116_N will set the flag discard_flag=1 to mark that this data packet PKT does not need to be sent out by the network data packet processing device 100. In step S310, the network processor core 116_1 / 116_N will write the data packet information PKT_INF of the processed data packet PKT to the output buffer 118_1 / 118_N. The data packet information PKT_INF includes regular information (e.g., pkt_address, pkt_len, etc.) and also includes additional information added by the present invention (e.g., data packet sequence number SEQ and flag discard_flag) for use in subsequent order-keeping transmission operations.

[0049] As described above, the packet distribution circuit 102 uses an average distribution method. Therefore, according to the predetermined order of the packet processing circuits 112_1 to 112_N (e.g., i=(i+1)%N), it distributes multiple packets (including packets actually received by the network packet processing device 100 from the network and / or empty packets for load balancing adjustment by the packet distribution circuit 102) to the packet processing circuits 112_1 to 112_N for multi-core parallel processing. However, the processed packets generated by the parallel processing of different network processor cores 116_1 to 116_N must maintain the sequence in the original data stream and cannot be out of order during actual forwarding. Therefore, the packet ordering processing circuit 106 reads the packet processing circuits 112_1 to 112_N (especially the output buffers 118_1 to 118_N of the packet processing circuits 112_1 to 112_N) according to the predetermined order used by the packet distribution circuit 102 (e.g., i=(i+1)%N). For example, the packet ordering processing circuit 106 will sequentially read the output buffers of the network processor core NPU[0], the network processor core NPU[1], the network processor core NPU[2], and so on. Furthermore, after the packet ordering processing circuit 106 reads the output buffer of the network processor core NPU[N-1], it will subsequently sequentially read the output buffers of the network processor core NPU[0], the network processor core NPU[1], the network processor core NPU[2], and so on. Additionally, the packet sequence number SEQ in the packet information PKT_INF can be used to detect whether packet out-of-order delivery has occurred, and the discard_flag in the packet information PKT_INF can be used to indicate whether packet transmission requires processing.

[0050] Please refer to the following: Figure 4 and Figure 5 . Figure 4 This is a flowchart of a data packet out-of-order exception handling mechanism according to an embodiment of the present invention. Figure 5 This is a flowchart of a data packet distribution operation and a data packet sequence number distribution operation that supports a data packet out-of-order exception handling mechanism according to an embodiment of the present invention. Figure 4 The operation shown can be performed by Figure 1 The packet ordering processing circuit 106 shown is used to perform this operation. Furthermore, if roughly the same result can be obtained, the steps do not necessarily need to be followed exactly. Figure 4 Execute in the order shown. Figure 5 The operation shown can be performed by Figure 1 The data packet distribution circuit 102 shown is used to perform this, compared to the original Figure 2 The operation shown Figure 5The illustrated steps include those for handling out-of-order packet exceptions. However, if a largely similar result can be obtained, the steps do not necessarily need to be followed exactly. Figure 5 Execute in the order shown.

[0051] exist Figure 5 In step S501, the packet distribution circuit 102 initializes the parameter i and the packet sequence number SEQ. The parameter i controls the packet distribution, and the packet sequence number SEQ controls the packet sequence number distribution. For ease of explanation, it is assumed that the packet distribution circuit 102 has two sequence number pools 120_1 and 120_K (K=2). The numerical range of sequence number pool 120_1 is {0, 1, 2, …, M-1}, and the numerical range of sequence number pool 120_2 is {M, M+1, M+2, …, 2M-1}. Initially, the packet distribution circuit 102 selects sequence number pool 120_1 to provide the packet sequence number SEQ. In addition, the numerical range of parameter i is {0, 1, 2, …, N-1}, and the N network processor cores 116_1 to 116_N are represented as NPU[0] to NPU[N-1]. In step S501, the initial value of parameter i is 0 (i.e., i=0), and the initial value of data packet sequence number SEQ is 0 (i.e., SEQ=0). Since the data packet order preservation processing circuit 106 has not yet started the data packet out-of-order exception handling procedure, the data packet distribution circuit 102 will not execute steps S502 and S504. For subsequent steps regarding data packet distribution and data packet sequence number distribution, please refer to... Figure 2 The explanation is unnecessary to elaborate on here.

[0052] In step S402, the packet ordering processing circuit 106 decides to start reading packet information PKT_INF (containing packet sequence number SEQ and discard_flag) from the output buffer (i.e., ring buffer 118_1) of the network processor core NPU[i] (i.e., NPU[i] = NPU[0]). In step S404, the packet ordering processing circuit 106 determines whether packet out-of-order exception handling is currently underway. Since the packet ordering processing circuit 106 has not yet started the packet out-of-order exception handling program, the process proceeds to step S406. In step S406, the packet ordering processing circuit 106 determines whether the packet sequence number SEQ conforms to the predetermined packet sequence number order (e.g., ...). That is, the data packet ordering processing circuit 106 will determine whether the data packet sequence number SEQ is consistent with the expected data packet sequence number. If the data packet is the data packet that the data packet distribution circuit 102 distributes the sequence number for the first time according to the current sequence number pool, then the expected data packet sequence number will be the initial data packet sequence number provided by the current sequence number pool (SEQ=0). On the other hand, if the data packet is not the data packet that the data packet distribution circuit 102 distributes the sequence number for the first time according to the current sequence number pool, then the expected data packet sequence number will depend on the data packet sequence number of the previously processed data packet plus 1 (SEQ=(SEQ+1)%M).

[0053] If the packet ordering processing circuit 106 determines in step S406 that the packet sequence number SEQ matches the expected packet sequence number (e.g., the sequence numbers of the preceding and following packets are consecutive), then in step S408, the packet ordering processing circuit 106 will determine whether the discard_flag flag is 1. If the discard_flag flag is 1, it indicates that the packet should be discarded or is an empty packet. Therefore, the packet ordering processing circuit 106 will update the parameter i in step S412 (e.g., i = (i + 1) % N), and then the process will return to step S402. On the other hand, if the discard_flag flag is 0, it indicates that the packet needs to be forwarded. Therefore, the packet ordering processing circuit 106 will first send the packet in step S410, and then update the parameter i in step S412 (e.g., i = (i + 1) % N). Then, the process will return to step S402.

[0054] If the data packet order preservation processing circuit 106 determines in step S406 that the data packet sequence number SEQ is inconsistent with the expected data packet sequence number (for example, the sequence numbers of the preceding and following data packets are not consecutive), it indicates that the hardware of the data packet distribution circuit 102 may have an unexpected abnormality. Therefore, the data packet distribution circuit 102 needs to be reset to reset the data packet sequence number. At this time, the data packet order preservation processing circuit 106 will start the data packet out-of-order exception handling program in step S414.

[0055] In response to the activation of the out-of-order packet handling procedure, both the packet order preservation circuit 106 and the packet distribution circuit 102 will perform relevant operations. In step S502, the packet distribution circuit 102 stops using a current sequence number pool (e.g., sequence number pool 120_1) to distribute packet sequence numbers and reports the last distributed packet sequence number SEQ_F of the current sequence number pool to the packet order preservation circuit 106. Therefore, the packet order preservation circuit 106 can obtain the last distributed packet sequence number SEQ_F of the current sequence number pool (e.g., sequence number pool 120_1) from the packet distribution circuit 102 in step S416. In step S504, the data packet distribution circuit 102 will reset (i=0) and switch to another sequence number pool different from the current sequence number pool to continue distributing data packet sequence numbers. For example, if the current sequence number pool is sequence number pool 120_1, the data packet distribution circuit 102 will switch to sequence number pool 120_K (K=2) and reset the data packet sequence number to the initial value of sequence number pool 120_K (K=2) (i.e., SEQ=M). However, if the current sequence number pool is sequence number pool 120_K (K=2), the data packet distribution circuit 102 will switch to sequence number pool 120_1 and reset the data packet sequence number to the initial value of sequence number pool 120_1 (i.e., SEQ=0).

[0056] After the packet ordering processing circuit 106 obtains the last distributed packet sequence number SEQ_F, it no longer checks whether the packet sequence numbers are consecutive. Instead, it sends out all packets that need to be forwarded between the current packet sequence number SEQ and the last distributed packet sequence number SEQ_F. After processing (discarding or forwarding) the packet with the last distributed packet sequence number SEQ_F, it manages the ordering transmission operation according to another sequence number pool different from the current sequence number pool (for example, step S406 will refer to another sequence number pool to check the packet sequence number). For example, if the current sequence number pool is sequence number pool 120_1, the packet ordering processing circuit 106 will use sequence number pool 120_K (K=2). However, if the current sequence number pool is sequence number pool 120_K (K=2), the packet ordering processing circuit 106 will use sequence number pool 120_1.

[0057] After the packet ordering processing circuit 106 starts the packet out-of-order exception handling program, in step S402, the packet ordering processing circuit 106 continues to read packet information PKT_INF (including packet sequence number SEQ and discard_flag) from the output buffer of the network processor core NPU[i] according to the current value of parameter i. In step S404, the packet ordering processing circuit 106 determines whether packet out-of-order exception handling is currently in progress. Since the packet ordering processing circuit 106 has already started the packet out-of-order exception handling program, the process proceeds to step S418. In step S418, the packet ordering processing circuit 106 determines whether the packet sequence number SEQ obtained in step S402 is equal to the last distributed packet sequence number SEQ_F obtained in step S416.

[0058] If the data packet sequence number SEQ is not equal to the last distributed data packet sequence number SEQ_F (step S418), the data packet ordering processing circuit 106 will determine whether the discard_flag is 1 in step S408. If the discard_flag is 1, it means that the data packet should be discarded or is an empty packet. Therefore, the data packet ordering processing circuit 106 will update the parameter i in step S412 (e.g., i = (i+1)%N). Then, the process will return to step S402 to continue executing the data packet out-of-order exception handling procedure. On the other hand, if the discard_flag is 0, it means that the data packet needs to be forwarded. Therefore, the data packet ordering processing circuit 106 will first send the data packet in step S410, and then update the parameter i in step S412 (e.g., i = (i+1)%N). Then, the process will return to step S402 to continue executing the data packet out-of-order exception handling procedure.

[0059] If the data packet sequence number SEQ is equal to the last distributed data packet sequence number SEQ_F (step S418) (meaning that all data packets between the current data packet sequence number SEQ and the last distributed data packet sequence number SEQ_F that need to be forwarded have been sent out, and the last distributed data packet sequence number SEQ_F remains to be processed), then the data packet ordering processing circuit 106 will determine whether the discard_flag is 1 in step S420. If the discard_flag is 1, it means that the data packet should be discarded or is an empty packet. Therefore, the data packet ordering processing circuit 106 does not need to send out the data packet with the last distributed data packet sequence number SEQ_F, but will directly execute step S424 to resume the normal processing flow. On the other hand, if the discard_flag is 0, it means that the data packet needs to be forwarded. Therefore, the data packet ordering processing circuit 106 will first send the data packet in step S422, and then execute step S424 to resume the normal processing flow. That is, after step S420 or S422, the processing (discarding or forwarding) of the data packet with the last distributed data packet sequence number SEQ_F has been completed.

[0060] In step S424, the packet ordering processing circuit 106 resets parameter i (i.e., i=0) and manages the ordering transmission operation based on a different sequence number pool than the current one. For example, if the current sequence number pool is sequence number pool 120_1, the packet ordering processing circuit 106 will start from the initial value (SEQ=M) of sequence number pool 120_K (K=2) to determine whether the packet sequence number matches the expected packet sequence number (i.e., whether the packet sequence numbers are consecutive). However, if the current sequence number pool is sequence number pool 120_K (K=2), the packet distribution circuit 102 will start from the initial value (SEQ=0) of sequence number pool 120_1 to determine whether the packet sequence number matches the expected packet sequence number (i.e., whether the packet sequence numbers are consecutive). After completing the operation in step S424, the packet ordering processing circuit 106 resumes the normal processing flow, and therefore, the process returns to step S402.

[0061] In summary, according to the multi-core parallel processing architecture proposed by this invention, multiple data packets are distributed to multiple data packet processing circuits for parallel processing (especially the network processor cores within these circuits). Each network processor core processes the data packets independently without relying on other network processor cores. In other words, when one network processor core performs data packet processing, it does not affect the data packet processing being performed by other network processor cores. Thus, the multi-core parallel processing architecture proposed by this invention can effectively improve data packet forwarding efficiency. Furthermore, the multi-core parallel processing architecture proposed by this invention also supports a pre-order processing mechanism, ensuring that the processed data packets generated by different network processor cores through parallel processing maintain the sequence of the original data stream during actual forwarding. Moreover, the multi-core parallel processing architecture proposed by this invention also supports a data packet out-of-order exception handling mechanism, allowing the data packet distribution circuit to be reset when a hardware malfunction occurs, thus ensuring normal system operation.

[0062] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be within the scope of the present invention.

Claims

1. A network data packet processing apparatus, comprising: Parallel processing circuit, comprising: Multiple packet processing circuits are used to process different packets in parallel, wherein each packet processing circuit includes: Network processor core; A packet distribution circuit, used to distribute multiple packets to the multiple packet processing circuits respectively; and A data packet ordering processing circuit is used to send multiple processed data packets generated by the parallel processing circuit in an ordered manner. The multiple processed data packets include a first processed data packet and a second processed data packet, which correspond to the first data packet and the second data packet in the multiple data packets, respectively. The order of the first and second processed data packets in the output data stream sent by the data packet ordering processing circuit is the same as the order of the first and second data packets in the input data stream received by the data packet distribution circuit.

2. The network packet processing apparatus of claim 1, wherein the packet distribution circuit distributes the plurality of packets to the plurality of packet processing circuits respectively according to a predetermined order of one of the plurality of packet processing circuits; and the packet order preservation processing circuit reads the plurality of packet processing circuits according to the predetermined order.

3. The network packet processing apparatus as described in claim 1, wherein each packet processing circuit further comprises: A ring buffer is used to store packet descriptors, which contain packet sequence numbers; The network processor core reads the packet descriptor from the ring buffer and performs packet processing based on the packet descriptor.

4. The network data packet processing apparatus as claimed in claim 3, wherein the data packet distribution circuit further distributes multiple data packet sequence numbers to the multiple data packets according to a predetermined data packet sequence number order.

5. The network packet processing apparatus of claim 4, wherein the plurality of data packets includes an empty packet for load balancing adjustment, and the plurality of data packet sequence numbers includes the data packet sequence number distributed to the empty packet.

6. The network packet processing apparatus of claim 4, wherein each packet processing circuit further comprises: Output buffer; The network processor core further writes the data packet information to the output buffer after completing the data packet processing, and the data packet information includes the data packet sequence number.

7. The network packet processing apparatus of claim 6, wherein the packet ordering processing circuit is further configured to read the packet information stored in the output buffer, and manage the ordering transmission operation according to the packet sequence number in the packet information and the predetermined packet sequence number order.

8. The network packet processing apparatus of claim 7, wherein when the packet sequence number does not conform to the predetermined packet sequence number order, the packet distribution circuit stops using the current sequence number pool to distribute packet sequence numbers and switches to another sequence number pool to distribute packet sequence numbers, and the packet order preservation processing circuit obtains the last distributed packet sequence number from the current sequence number pool from the packet distribution circuit, and after completing the processing of the packet with the last distributed packet sequence number, manages the order preservation transmission operation according to the other sequence number pool.

9. The network packet processing apparatus of claim 6, wherein the network processor core further writes a flag to the output buffer after completing the packet processing, the flag indicating whether the packet does not need to be forwarded, and the packet ordering processing circuit further reads the flag stored in the output buffer and manages the ordering transmission operation according to the flag.

10. A method for forwarding network data packets, comprising: Different data packets are processed in parallel by multiple data packet processing circuits in the parallel processing circuit, where each data packet processing circuit contains a network processor core. Distribute multiple data packets to the multiple data packet processing circuits respectively; and The multiple processed data packets generated by the parallel processing circuit are sent in order, wherein the multiple processed data packets include a first processed data packet and a second processed data packet, which correspond to the first data packet and the second data packet in the multiple data packets, respectively, and the order of the first and second processed data packets in the output data stream is the same as the order of the first and second data packets in the input data stream.

11. The network packet forwarding method as described in claim 10, wherein the step of distributing the plurality of packets to the plurality of packet processing circuits includes: According to a predetermined sequence of one of the plurality of data packet processing circuits, the plurality of data packets are respectively distributed to the plurality of data packet processing circuits; and The steps for sending the multiple processed data packets generated by the parallel processing circuit in an ordered manner include: The multiple data packet processing circuits are read according to the predetermined order.

12. The network packet forwarding method as described in claim 10, wherein each packet processing circuit further comprises: A ring buffer is used to store packet descriptors, which contain packet sequence numbers; The network processor core reads the packet descriptor from the ring buffer and performs packet processing based on the packet descriptor.

13. The network packet forwarding method as described in claim 12, wherein the step of distributing the plurality of packets to the plurality of packet processing circuits includes: Multiple data packet sequence numbers are distributed to the multiple data packets according to a predetermined data packet sequence number order.

14. The network packet forwarding method as described in claim 13, wherein the plurality of packets includes an empty packet for load balancing adjustment, and the plurality of packet sequence numbers includes the packet sequence number distributed to the empty packet.

15. The network packet forwarding method as described in claim 13, wherein each packet processing circuit further comprises: Output buffer; The network processor core further writes the packet information to the output buffer after completing the packet processing, and the packet information includes the packet sequence number.

16. The network packet forwarding method as described in claim 15, wherein the step of sending the plurality of processed data packets generated by the parallel processing circuit in an ordered manner includes: Read the data packet information stored in the output buffer; and The operation of maintaining the order of transmission is managed based on the sequence number of the data packet in the data packet information and the predetermined sequence number order of the data packet.

17. The network packet forwarding method as described in claim 16, further comprising: When the data packet sequence number does not conform to the predetermined data packet sequence number order, the current sequence number pool is stopped from distributing data packet sequence numbers, and the distribution is switched to another sequence number pool; and The steps for managing the ordered transmission operation based on the data packet sequence number and the predetermined data packet sequence number order in the data packet information include: When the sequence number of the data packet does not conform to the predetermined sequence number order, the last distributed data packet sequence number of the current sequence number pool is obtained, and after the processing of the data packet with the last distributed data packet sequence number is completed, the order-keeping transmission operation is managed according to the other sequence number pool.

18. The network packet forwarding method as described in claim 15, wherein the network processor core further writes a flag to the output buffer after completing the packet processing, the flag indicating whether the packet does not need to be forwarded, and the step of sending the plurality of processed packets generated by the parallel processing circuit in order includes: Read the flag stored in the output buffer and manage the order-keeping transmission operation based on the flag.

19. A network data packet processing apparatus, comprising: Parallel processing circuitry, comprising multiple network processing cores, including: The first network processing core is used to process the first data packet independently without relying on other network processor cores among the multiple network processing cores, and to generate the first processed data packet. as well as A data packet distribution circuit is used to distribute the first data packet to the first network processing core; A data packet sending circuit is used to send the first processed data packet.

20. The network data packet processing apparatus as described in claim 19, wherein the first network processing core is the network processing core currently processing data packets, and when the load of the first network processing core meets the load conditions, the data packet distribution circuit distributes empty packets to the first network processing core.

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