Single-frame exposure high-dynamic image sensor system, pixel reading method, pixel reading device and pixel reading equipment
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 创睛半导体(成都)有限公司
- Filing Date
- 2024-11-20
- Publication Date
- 2026-05-22
AI Technical Summary
Existing multi-frame image synthesis methods are prone to image ghosting, have long readout times, low output frame rates, and large intermediate data buffering requirements, which increases design costs.
The high dynamic range image sensor system employing single-frame exposure utilizes a readout circuit composed of a pixel array, row selection control module, column selection control module, comparator, counter, and digital module, combined with a pre-comparator and multi-level comparison unit, to automatically control whether to merge or not merge the readout signals, thereby achieving high dynamic range under a single exposure.
It reduces readout time, increases output frame rate, reduces intermediate data buffering, avoids image ghosting, and lowers design costs.
Smart Images
Figure CN122073645A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of image sensor technology, and more particularly to an image sensor system that achieves high dynamic range with single-frame exposure, as well as a method, apparatus, and device for reading out pixel signals from the image sensor. Background Technology
[0002] CMOS image sensors (CIS) are widely used in digital still cameras, cellular phones, security cameras, medical devices, and automobiles. High dynamic range image sensors mean that captured images have more complete detail information, displaying both bright and dark details in a single frame, meeting the high-quality imaging needs of various application scenarios.
[0003] A common method to improve image dynamic range is to obtain images with different brightness levels through long and short exposures, and then combine the two frames. A drawback of this approach is that severe image ghosting can easily occur during multi-frame image synthesis. Another published method uses a large-pixel structure to obtain multiple frames with different brightness levels through a single exposure, and then combines these frames into a high dynamic range image. This approach places higher demands on the pixel structure and, due to the need for multi-frame image synthesis, increases the amount of intermediate data buffering and correspondingly prolongs the signal readout time, resulting in a lower output frame rate for the image sensor. A low frame rate can cause stuttering during image sensor shooting, while a high frame rate will produce a smoother and clearer image when shooting fast-paced action scenes.
[0004] Therefore, there is a need for a method that can achieve high dynamic range in a single exposure and readout state, which reduces the amount of intermediate data buffering, increases the frame rate, and avoids image ghosting. Summary of the Invention
[0005] The following description illustrates the contribution of this invention to the prior art.
[0006] The problem solved by this invention is that existing multi-frame image synthesis is prone to producing image ghosting, and because it requires data from multiple frames, the readout time is long and the output frame rate is low. At the same time, intermediate data caching increases the size of the storage circuit and increases the design cost.
[0007] One object of the present invention is to provide a high dynamic range image sensor system with single-frame exposure, comprising:
[0008] The pixel array converts light signals into voltage signals using photodiodes;
[0009] The row selection control module provides lateral control signals for pixels;
[0010] The column selection control module provides vertical control signals for pixels;
[0011] The comparator pre-compares the pixel output signal with the reference ramp signal, transmits the comparison result to the column selection control module, and selects the readout mode based on the comparison result;
[0012] The counter counts the signal quantized by the comparator;
[0013] The digital module processes the output value of the counter and then outputs the image.
[0014] The reference voltage generation module is used to generate a reference ramp signal;
[0015] The load MOS provides tail current to the pixel array.
[0016] Furthermore, the readout circuit of the pixel unit includes: a first photodiode PD1, a first transfer transistor MN1, a second photodiode PD2, a second transfer transistor MN2, a third photodiode PD3, a third transfer transistor MN3, a fourth photodiode PD4, a fourth transfer transistor MN4, a first reset control switch MN5, a second reset control switch MN6, a source follower transistor MN7, and a row selection transistor MN8.
[0017] The cathode of the first photodiode PD1 is connected to the source of the first transfer transistor MN1, and the connection relationship between the remaining photodiodes PD2 to PD4 and the transfer transistors MN2 to MN4 is similar; the drains of the first to fourth transfer transistors are connected, the common terminal of the drains of the four transfer transistors is connected to the source of the first reset transistor MN5, the drain of the first reset transistor MN5 is connected to the source of the second reset transistor MN6, and the drain of the second reset transistor MN6 is connected to the power supply.
[0018] The common terminal of the drain of the first to fourth transfer transistors is simultaneously connected to the gate of the source follower transistor MN7. The drain of the source follower transistor is connected to the power supply, and its source is connected to the drain of the horizontal select transistor MN8. The source of the horizontal select transistor MN8 is connected to the output signal line VOUT.
[0019] The gates of the first to fourth transfer transistors are connected to control signal lines TX1 to TX4, respectively; the first and second reset transistors are connected to control signal lines CX and RX, respectively; and the row select transistor is connected to control signal line SX.
[0020] Furthermore, the column selection control module includes an XOR gate (NOR), a DFF flip-flop (DFF), an OR gate (OR), a level converter, and an inverter. The output of the XOR gate (NOR) is connected to the CK terminal of the DFF flip-flop (DFF), the Q terminal of the DFF flip-flop (DFF) is connected to the A terminal of the OR gate (OR), the output of the OR gate (OR) is connected to the input of the level converter (OR), and the output of the level converter (OR) is connected to the inverter (OR).
[0021] The input terminals A and B of the XOR gate are connected to the output signal VTCX and the enable signal HS_EN during the pre-compare period of the comparator, respectively.
[0022] Furthermore, the comparator employs a structure consisting of two-stage comparison units and two identical cascaded NAND gates.
[0023] Further, the two-stage comparison unit includes a first-stage comparison unit and a second-stage comparison unit. The first-stage comparison unit includes P-channel MOSFETs MP0, MP1, MP2, MP3, and N-channel MOSFETs MN10, MN11, and MN12. The source of NMOS transistor MN10 is grounded, and its drain is connected to the common terminal of the sources of NMOS transistors MN11 and MN12. The drain of NMOS transistor MN11 is connected to the drain of PMOS transistor MP0, and the source of MP0 is connected to the power supply VDDH. The drain of NMOS transistor MN12 is connected to the drain of PMOS transistor MP1, and the source of MP1 is connected to... The power supply is VDDH. The drain of PMOS transistor MP0 is connected to the common terminal of the gates of MP0 and MP1. The gate of NMOS transistor is connected to one plate of capacitor C0, and the other plate of capacitor C0 is connected to the reference ramp signal Vramp. The drain of PMOS transistor MP2 is connected to the gate of NMOS transistor MN11, and the source of MP2 is connected to the drain of MN11. The gate of NMOS transistor MN12 is connected to one plate of capacitor C1, and the other plate of capacitor C1 is connected to the pixel signal Vpix. The source of PMOS transistor MP3 is connected to the drain of MN12, and the drain of MP3 is connected to the gate of MN12.
[0024] The secondary comparator unit includes a P-channel MOSFET MP4 and an N-channel MOSFET MN13. The source of MN13 is grounded, and its drain is connected to the drain of MP4. The source of MP4 is connected to the power supply VDDH, and the gate of MP4 is connected to the drain of MP1. The gate of MP4 is connected to the output signal Vout1 of the primary comparator unit, and the gate of MN13 is connected to the bias voltage signal Vbias.
[0025] Furthermore, the NAND gate includes a first NAND gate and a second NAND gate, wherein P-channel MOSFETs MP5 and MP6, and N-channel MOSFETs MN14 and MN15 constitute the first NAND gate; and P-channel MOSFETs MP7 and MP8, and N-channel MOSFETs MN16 and MN17 constitute the second NAND gate.
[0026] The source of MP15 is connected to the power supply VDDL, the drain is connected to the drain of MN14, the source of MN14 is connected to the drain of MN15, the source of MN15 is grounded, the gate of MN14 is connected to the gate of MP5, the common terminal of the drain of MP5 and the drain of MN14 is connected to the drain of MP6, and the source of MP6 is connected to the power supply VDDL.
[0027] The source of MP17 is connected to the power supply VDDL, and its drain is connected to the drain of MN16. The source of MN16 is connected to the drain of MN17. The source of MN17 is grounded. The gate of MN16 is connected to the gate of MP7. The common terminal of the drain of MP7 and the drain of MN16 is connected to the drain of MP8. The source of MP8 is connected to the power supply VDDL.
[0028] Another object of the present invention is to provide a pixel readout method for the above-mentioned image sensor, the method comprising the following steps:
[0029] S1. Set control signals RX and CX to high level, turn on transistors MN6 and MN5, clear the floating diffusion region FD to zero, and after clearing, set control signals RX and CX to low level. Compare the reference voltage signal with the pixel voltage signal to obtain the pixel's low noise.
[0030] S2. Enter the pixel signal readout interval, set the control signal TX1 to high level, and transfer the electrons of the photodiode PD1 to the floating diffusion region FD. At this time, the reference ramp signal and the pixel voltage signal are pre-compared, and the readout mode is selected based on the pre-comparison result.
[0031] S3. Perform a difference operation between the pixel signal obtained in step 2 and the pixel noise floor in step 1 to finally obtain the effective signal quantization value of the pixel.
[0032] Furthermore, the readout mode of step S2 includes:
[0033] When the pixel voltage signal is less than the reference ramp signal during the pre-comparison period, the comparator output signal VTCX is high, and pixel merging is not required. Only the signal of one pixel is read at a time, and it must be cleared after reading. The comparator outputs the signal of each pixel.
[0034] When the pixel voltage signal is greater than the reference ramp signal during the pre-comparison period, the comparator output signal VTCX is low, pixel merging is required, the control signal RX is high, and the control signal CX remains low. After the signal of each pixel is read out, the floating diffusion region FD will not be cleared to zero. The readout signal is the sum of the signal values of multiple pixels.
[0035] Another object of the present invention is to provide a pixel readout device for an image sensor system, the device comprising:
[0036] The control unit is used to set the control signals RX and CX to high level, turn on the MN6 and MN5 transistors, clear the floating diffusion region FD to zero, and after clearing, set the control signals RX and CX to low level, compare the reference voltage signal with the pixel voltage signal, and obtain the pixel's low noise.
[0037] The selection unit is used to enter the pixel signal readout interval, set the control signal TX1 to a high level, transfer the electrons of the photodiode PD1 to the floating diffusion region FD, pre-compare the reference ramp signal with the pixel voltage signal at this time, and select the readout mode based on the pre-compare result to obtain the pixel signal quantity.
[0038] The arithmetic unit is used to perform a difference operation between the pixel signal quantity and the pixel's noise floor to obtain the quantized value of the effective pixel signal.
[0039] Another object of the present invention is to provide an electronic device including a memory, a central processing unit, and a computer program stored in the memory and executable on the central processing unit, the electronic device further including at least two functional modules independent of the central processing unit, wherein the computer program, when executed, implements the methods described in the foregoing embodiments.
[0040] The improved image sensor system of this invention introduces a pre-comparison period during the pixel readout stage. Based on the comparison result, it automatically controls whether to merge or not merge the readout signals. This control method enables each pixel to automatically adjust its readout mode (single-PD readout mode or multi-PD cumulative readout mode) according to the scene brightness under single-exposure conditions, ultimately achieving high dynamic range in a single frame image. Compared with methods that achieve high dynamic range through multiple exposures, this method reduces readout time and significantly improves the output frame rate; furthermore, it reduces the amount of intermediate data, thus reducing the need for data buffering hardware.
[0041] The design concept, principle, and implementation means of the present invention will be described below with reference to the accompanying drawings and embodiments, so as to more clearly describe the technical features and beneficial effects of the present invention. Attached Figure Description
[0042] The accompanying drawings provided herein are used to further illustrate embodiments of the present invention and constitute a part of this application, but do not constitute a limitation on the embodiments of the present invention.
[0043] Figure 1 This is a schematic diagram of the image sensor system according to Embodiment 1 of the present invention;
[0044] Figure 2 This is a schematic diagram of a possible readout circuit structure for the smallest pixel unit according to Embodiment 1 of the present invention;
[0045] Figure 3 This is a schematic diagram of the structure of a possible column selection control module according to Embodiment 1 of the present invention;
[0046] Figure 4 This is a schematic diagram of a possible comparator structure according to Embodiment 1 of the present invention;
[0047] Figure 5This is a timing diagram of the control when the pixel output signal Vpix is less than the reference ramp signal Vramp in Embodiment 2 of the present invention;
[0048] Figure 6 This is a timing diagram for the control of the pixel output signal Vpix when it is greater than the reference ramp signal Vramp in Embodiment 2 of the present invention. Detailed Implementation
[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific examples and accompanying drawings. The illustrative embodiments and descriptions of this invention are for illustrative purposes only. However, those skilled in the art should understand that well-known structures, materials, or operating methods have not been shown or described in detail to avoid obscuring specific content.
[0050] Example 1
[0051] Figure 1 The improved image sensor system structure of the present invention is shown in the figure. The system includes a pixel array, a row selection control module, a column selection control module, a comparator, a counter, a digital module, a reference voltage generation module, and a load MOS. Specifically, the pixel array converts light signals into voltage signals via photodiodes; the row selection control module provides lateral control signals for the pixels; the column selection control module provides vertical control signals for the pixels; the comparator pre-compares the pixel output signal with a reference ramp signal and transmits the comparison result to the column selection control module, which selects the readout mode based on the comparison result; the counter counts the signal quantized by the comparator; the digital module processes the output value of the counter and outputs the image; the reference voltage generation module generates the reference ramp signal; and the load MOS provides tail current to the pixel array.
[0052] The pixel array consists of M×N pixels, with the smallest unit being a 2×2 structure. It contains four colors: R, Gr, Gb, and B, with each color composed of four pixels of the same color. Since each pixel corresponds to a photodiode (PD), the readout circuit structure of the smallest pixel unit is as follows: Figure 2 As shown. The readout circuit of this pixel unit includes: a first photodiode PD1, a first transfer transistor MN1, a second photodiode PD2, a second transfer transistor MN2, a third photodiode PD3, a third transfer transistor MN3, a fourth photodiode PD4, a fourth transfer transistor MN4, a first reset control switch MN5, a second reset control switch MN6, a source follower transistor MN7, and a row selection transistor MN8.
[0053] The cathode of the first photodiode PD1 is connected to the source of the first transfer transistor MN1, and the connection relationship between the remaining photodiodes PD2-PD4 and the transfer transistors MN2-MN4 is similar. The drains of the first to fourth transfer transistors are connected, the common terminal of the drains of the four transfer transistors is connected to the source of the first reset transistor MN5, the drain of the first reset transistor MN5 is connected to the source of the second reset transistor MN6, and the drain of the second reset transistor MN6 is connected to the power supply.
[0054] The common terminal of the drain of the first to fourth transfer transistors is simultaneously connected to the gate of the source follower transistor MN7. The drain of the source follower transistor is connected to the power supply, and its source is connected to the drain of the horizontal select transistor MN8. The source of the horizontal select transistor MN8 is connected to the output signal line VOUT.
[0055] The gates of the first to fourth transfer transistors are connected to control signal lines TX1 to TX4, respectively; the first and second reset transistors are connected to control signal lines CX and RX, respectively; and the row select transistor is connected to control signal line SX.
[0056] The working principle of this pixel readout circuit is as follows: During the pre-comparison period, when the pixel voltage signal is less than the reference ramp signal of that period, pixel merging is not required, and only the signal of one pixel is read out at a time (during the signal readout period, the transmission transistor corresponding to the photodiode is turned on, the first reset transistor is closed, and the second reset transistor is closed). After each readout, both the first and second reset transistors are turned on to clear the floating diffusion region FD to zero. When the pixel voltage signal is greater than the reference ramp signal of that period, pixel merging is required, and the signals of several pixels are read out (during the signal readout period, the transmission transistor corresponding to the photodiode is turned on in sequence, the first transmission transistor is kept closed, the floating diffusion region FD is not cleared to zero, and the readout signal is the sum of the readout signals of multiple pixels).
[0057] It should be noted that the pixel readout circuit of the present invention is not limited to the case of 4 photodiodes. It can be adjusted according to the actual situation and can be any even number of photodiodes. Therefore, the merged pixels can be any pixels of the same color.
[0058] Figure 3 The image sensor system of Embodiment 1 illustrates a possible structure of the column selection control module, which includes an XOR gate (NOR), a flip-flop (DFF), an OR gate (OR), a level converter, and an inverter. The output of the XOR gate (NOR) is connected to the CK terminal of the flip-flop (DFF), the Q terminal of the flip-flop (DFF) is connected to the A terminal of the OR gate (OR), the output of the OR gate is connected to the input of the level converter, and the output of the level converter is connected to the inverter.
[0059] The input terminals A and B of the XOR gate are connected to the output signal VTCX and the enable signal HS_EN during the pre-compare period of the comparator, respectively.
[0060] Figure 4 The image sensor system of Embodiment 1 illustrates a possible structure of a comparator, which includes a first-level comparison unit, a second-level comparison unit, and two NAND gates.
[0061] The first-level comparator unit includes P-channel MOSFETs MP0, MP1, MP2, and MP3, and N-channel MOSFETs MN10, MN11, and MN12. The source of NMOS MN10 is grounded, and its drain is connected to the common terminal of the sources of NMOS MN11 and MN12. The drain of NMOS MN11 is connected to the drain of PMOS MOSFET MP0, and the source of MP0 is connected to the power supply VDDH. The drain of NMOS MN12 is connected to the drain of PMOS MOSFET MP1, and the source of MP1 is connected to the power supply VDDH. The drain of MP0 is connected to the common terminal of the gates of MP0 and MP1; the gate of the NMOS transistor is connected to one plate of capacitor C0, and the other plate of capacitor C0 is connected to the reference ramp signal Vramp; the drain of PMOS transistor MP2 is connected to the gate of NMOS transistor MN11, and the source of MP2 is connected to the drain of MN11; the gate of NMOS transistor MN12 is connected to one plate of capacitor C1, and the other plate of capacitor C1 is connected to the pixel signal Vpix; the source of PMOS transistor MP3 is connected to the drain of MN12, and the drain of MP3 is connected to the gate of MN12.
[0062] The secondary comparator unit includes a P-channel MOSFET MP4 and an N-channel MOSFET MN13. The source of MN13 is grounded, and its drain is connected to the drain of MP4. The source of MP4 is connected to the power supply VDDH, and the gate of MP4 is connected to the drain of MP1. The gate of MP4 is connected to the output signal Vout1 of the primary comparator unit, and the gate of MN13 is connected to the bias voltage signal Vbias.
[0063] The two NAND gates have the same structure. The first NAND gate consists of P-channel MOSFETs MP5 and MP6, and N-channel MOSFETs MN14 and MN15. The source of MP15 is connected to the power supply VDDL, and its drain is connected to the drain of MN14. The source of MN14 is connected to the drain of MN15, and the source of MN15 is grounded. The gate of MN14 is connected to the gate of MP5. The common terminal of the drains of MP5 and MN14 is connected to the drain of MP6, and the source of MP6 is connected to the power supply VDDL. The second NAND gate uses the same structure, including P-channel MOSFETs MP7 and MP8, and N-channel MOSFETs MN16 and MN17. The source of MP17 is connected to the power supply VDDL, and its drain is connected to the drain of MN16. The source of MN16 is connected to the drain of MN17. The source of MN17 is grounded. The gate of MN16 is connected to the gate of MP7. The common terminal of the drain of MP7 and the drain of MN16 is connected to the drain of MP8. The source of MP8 is connected to the power supply VDDL.
[0064] The output signal Vout2 of the secondary comparator unit is connected to the common terminal of the gate of MP5 and the gate of MN14, and also to the common terminal of the gate of MP7 and the gate of MN16; the common terminal of the drain of MP5 and the drain of MN14 is connected to the output signal VTCX of the first NAND gate; the common terminal of the drain of MP7 and the drain of MN16 outputs the output signal VTCN of the second NAND gate.
[0065] Example 2
[0066] The difference between this embodiment and Embodiment 1 is that this embodiment provides a pixel readout method for a high dynamic range image sensor with single-frame exposure, including the following steps:
[0067] S1. Set control signals RX and CX to high level, turn on transistors MN6 and MN5, clear the floating diffusion region FD to zero, and after clearing, set control signals RX and CX to low level. Compare the reference voltage signal with the pixel voltage signal to obtain the pixel's noise floor.
[0068] S2. Enter the pixel signal readout interval, set the control signal TX1 to high level, and transfer the electrons of the photodiode PD1 to the floating diffusion region FD. At this time, the reference ramp signal and the pixel voltage signal are pre-compared.
[0069] When the pixel voltage signal is lower than the reference ramp signal (during the pre-comparison period), the comparator output signal VTCX is high. Pixel merging is not required; only one pixel's signal is read at a time (by setting the control signal of the photodiode corresponding to the pixel to a high level). After each read, the signal must be cleared (both control signals RX and CX are set to a high level). Figure 5 As shown.
[0070] When the pixel voltage signal is greater than the reference ramp signal (during the pre-comparison period), the comparator output signal VTCX is low, requiring pixel merging. The control signal RX is high, while the control signal CX remains low. After each pixel's signal is read out, the floating diffusion region FD will not be cleared to zero. Figure 6 As shown.
[0071] S3. Perform a difference operation between the pixel signal quantity obtained in step 2 and the background noise of the pixel in step 1 to obtain the effective signal quantization value of the pixel. It should be noted that, for the case where pixels are not merged, the signal quantity of multiple pixels is subtracted from the background noise of the pixel to obtain the effective signal quantization value corresponding to each pixel; while for the case where pixels are merged, the signal quantity of the merged pixel is subtracted from the background noise of the pixel to obtain the effective signal quantization value corresponding to the merged pixel.
[0072] Figure 5 The timing diagram shows the operation when pixels are not merged. As shown in the figure, when the pixel voltage signal Vpix is less than the reference ramp signal Vramp, it means that the pixel signal is greater than the preset signal ΔV (the reference ramp signal during the pre-comparison period). In a bright scene, the comparator output signal VTCX is high. This signal is fed back to the column selection control module to control that only one pixel signal is read at a time, and the signal must be cleared after each reading.
[0073] Figure 6 The timing sequence of pixel merging is shown in the figure. When the pixel voltage signal Vpix > the reference ramp signal Vramp, it means that the pixel signal is less than the preset signal ΔV (the reference ramp signal during the pre-comparison period). In a dark scene, the comparator output signal VTCX is low. This signal is fed back to the column selection control module to control the reading of the accumulated signal of multiple pixels.
[0074] Another embodiment of the present invention provides a pixel readout device for an image sensor system, the device comprising:
[0075] The control unit is used to set the control signals RX and CX to high level, turn on the MN6 and MN5 transistors, clear the floating diffusion region FD to zero, and after clearing, set the control signals RX and CX to low level, compare the reference voltage signal with the pixel voltage signal, and obtain the pixel's low noise.
[0076] The selection unit is used to enter the pixel signal readout interval, set the control signal TX1 to a high level, transfer the electrons of the photodiode PD1 to the floating diffusion region FD, pre-compare the reference ramp signal with the pixel voltage signal at this time, and select the readout mode based on the pre-compare result to obtain the pixel signal quantity.
[0077] The arithmetic unit is used to perform a difference operation between the pixel signal quantity and the pixel's noise floor to obtain the quantized value of the effective pixel signal.
[0078] Another embodiment of the present invention provides an electronic device including a memory, a central processing unit (CPU), and a computer program stored in the memory and executable on the CPU. The electronic device further includes at least two functional modules independent of the CPU, and the computer program, when executed, implements the methods described in the foregoing embodiments.
[0079] This invention introduces a pre-comparison period during the pixel readout stage. Based on the comparison result, it automatically controls whether or not to merge the readout signals. This control method enables each pixel to automatically adjust its readout mode (single-PD readout mode or multi-PD cumulative readout mode) according to the scene brightness under single-exposure conditions, ultimately achieving high dynamic range in a single frame image. Compared with methods that achieve high dynamic range through multiple exposures, this method reduces readout time and significantly improves the output frame rate; furthermore, it reduces the amount of intermediate data, thus reducing the need for data buffering hardware.
[0080] The various technical features of the embodiments described above can be combined arbitrarily. For the sake of brevity, not all possible combinations of the various technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered to be within the scope of this specification. Moreover, the terms "having," "comprising," "including," and similar terms should be understood as "comprising," unless otherwise specifically stated. In addition, the accompanying drawings are provided for the purpose of explaining to those skilled in the art, and the drawings are not necessarily drawn to scale.
Claims
1. A high dynamic range image sensor system with single-frame exposure, characterized in that, The system includes a pixel array, a row selection control module, a comparator, a counter, a digital module, a reference voltage generation module, and a load MOS. It also includes: A pixel array, consisting of M×N pixel units, is used to convert light signals into voltage signals via photodiodes. The column selection control module is used to provide vertical control signals for pixels; The comparator pre-compares the pixel output signal with the reference ramp signal, transmits the comparison result to the column selection control module, and selects the readout mode based on the comparison result.
2. The image sensor system according to claim 1, characterized in that, The readout circuit of the pixel unit includes: a first photodiode PD1, a first transfer transistor MN1, a second photodiode PD2, a second transfer transistor MN2, a third photodiode PD3, a third transfer transistor MN3, a fourth photodiode PD4, a fourth transfer transistor MN4, a first reset control switch MN5, a second reset control switch MN6, a source follower transistor MN7, and a row selection transistor MN8. The cathode of the first photodiode PD1 is connected to the source of the first transfer transistor MN1, and the connection relationship between the remaining photodiodes PD2 to PD4 and the transfer transistors MN2 to MN4 is similar; the drains of the first to fourth transfer transistors are connected, the common terminal of the drains of the four transfer transistors is connected to the source of the first reset transistor MN5, the drain of the first reset transistor MN5 is connected to the source of the second reset transistor MN6, and the drain of the second reset transistor MN6 is connected to the power supply. The common terminal of the drain of the first to fourth transfer transistors is simultaneously connected to the gate of the source follower transistor MN7. The drain of the source follower transistor is connected to the power supply, and its source is connected to the drain of the horizontal select transistor MN8. The source of the horizontal select transistor MN8 is connected to the output signal line VOUT. The gates of the first to fourth transfer transistors are connected to control signal lines TX1 to TX4, respectively; the first and second reset transistors are connected to control signal lines CX and RX, respectively; and the row select transistor is connected to control signal line SX.
3. The image sensor system according to claim 1, characterized in that, The column selection control module includes an XOR gate (NOR), a DFF flip-flop (DFF), an OR gate (OR), a level converter, and an inverter. The output of the XOR gate (NOR) is connected to the CK terminal of the DFF flip-flop (DFF), the Q terminal of the DFF flip-flop (DFF) is connected to the A terminal of the OR gate (OR), the output of the OR gate (OR) is connected to the input of the level converter (OR), and the output of the level converter (OR) is connected to the inverter (OR). The input terminals A and B of the XOR gate are connected to the output signal VTCX and the enable signal HS_EN during the pre-compare period of the comparator, respectively.
4. The image sensor system according to claim 1, characterized in that, The comparator employs a two-stage comparison unit and a structure of two identical NAND gates cascaded together.
5. The image sensor system according to claim 4, characterized in that, The two-stage comparison unit includes a first-stage comparison unit and a second-stage comparison unit. The first-stage comparison unit includes P-channel MOSFETs MP0, MP1, MP2, and MP3, and N-channel MOSFETs MN10, MN11, and MN12. The source of NMOS MN10 is grounded, and its drain is connected to the common terminal of the sources of NMOS MN11 and MN12. The drain of NMOS MN11 is connected to the drain of PMOS MOSFET MP0, and the source of MP0 is connected to the power supply VDDH. The drain of NMOS MN12 is connected to the drain of PMOS MOSFET MP1, and the source of MP1 is connected to the power supply VDDH. VDDH, the drain of PMOS transistor MP0 is connected to the common terminal of the gates of MP0 and MP1; the gate of NMOS transistor is connected to one plate of capacitor C0, and the other plate of capacitor C0 is connected to the reference ramp signal Vramp; the drain of PMOS transistor MP2 is connected to the gate of NMOS transistor MN11, and the source of MP2 is connected to the drain of MN11; the gate of NMOS transistor MN12 is connected to one plate of capacitor C1, and the other plate of capacitor C1 is connected to the pixel signal Vpix; the source of PMOS transistor MP3 is connected to the drain of MN12, and the drain of MP3 is connected to the gate of MN12. The secondary comparator unit includes a P-channel MOSFET MP4 and an N-channel MOSFET MN13. The source of MN13 is grounded, and its drain is connected to the drain of MP4. The source of MP4 is connected to the power supply VDDH, and the gate of MP4 is connected to the drain of MP1. The gate of MP4 is connected to the output signal Vout1 of the primary comparator unit, and the gate of MN13 is connected to the bias voltage signal Vbias.
6. The image sensor system according to claim 4, characterized in that, The NAND gate includes a first NAND gate and a second NAND gate, wherein P-channel MOSFETs MP5 and MP6, and N-channel MOSFETs MN14 and MN15 constitute the first NAND gate; P-channel MOSFETs MP7 and MP8, and N-channel MOSFETs MN16 and MN17 constitute the second NAND gate. The source of MP15 is connected to the power supply VDDL, the drain is connected to the drain of MN14, the source of MN14 is connected to the drain of MN15, the source of MN15 is grounded, the gate of MN14 is connected to the gate of MP5, the common terminal of the drain of MP5 and the drain of MN14 is connected to the drain of MP6, and the source of MP6 is connected to the power supply VDDL. The source of MP17 is connected to the power supply VDDL, and its drain is connected to the drain of MN16. The source of MN16 is connected to the drain of MN17. The source of MN17 is grounded. The gate of MN16 is connected to the gate of MP7. The common terminal of the drain of MP7 and the drain of MN16 is connected to the drain of MP8. The source of MP8 is connected to the power supply VDDL.
7. A pixel readout method for an image sensor system as described in claim 1, characterized in that, The method includes the following steps: S1. Set control signals RX and CX to high level, turn on transistors MN6 and MN5, clear the floating diffusion region FD to zero, and after clearing, set control signals RX and CX to low level. Compare the reference voltage signal with the pixel voltage signal to obtain the pixel's low noise. S2. Enter the pixel signal readout interval, set the control signal TX1 to high level, and transfer the electrons of the photodiode PD1 to the floating diffusion region FD. Pre-compare the reference ramp signal with the pixel voltage signal at this time, and select the readout mode based on the pre-compare result to obtain the pixel signal quantity. S3. Perform a difference operation between the pixel signal obtained in step 2 and the pixel noise floor in step 1 to finally obtain the effective signal quantization value of the pixel.
8. The pixel readout method of the image sensor system according to claim 7, characterized in that, The readout mode in step S2 includes: When the pixel voltage signal is less than the reference ramp signal during the pre-comparison period, the comparator output signal VTCX is high, and pixel merging is not required. Only the signal of one pixel is read at a time, and it must be cleared after reading. The comparator outputs the signal of each pixel. When the pixel voltage signal is greater than the reference ramp signal during the pre-comparison period, the comparator output signal VTCX is low, pixel merging is required, the control signal RX is high, and the control signal CX remains low. After the signal of each pixel is read out, the floating diffusion region FD will not be cleared to zero. The readout signal is the sum of the signal values of multiple pixels.
9. A pixel readout device for an image sensor system, characterized in that, The device includes: The control unit is used to set the control signals RX and CX to high level, turn on the MN6 and MN5 transistors, clear the floating diffusion region FD to zero, and after clearing, set the control signals RX and CX to low level, compare the reference voltage signal with the pixel voltage signal, and obtain the pixel's low noise. The selection unit is used to enter the pixel signal readout interval, set the control signal TX1 to a high level, transfer the electrons of the photodiode PD1 to the floating diffusion region FD, pre-compare the reference ramp signal with the pixel voltage signal at this time, and select the readout mode based on the pre-compare result to obtain the pixel signal quantity. The arithmetic unit is used to perform a difference operation between the pixel signal quantity and the pixel's noise floor to obtain the quantized value of the effective pixel signal.
10. An electronic device comprising a memory, a central processing unit (CPU), and a computer program stored in the memory and executable on the CPU, characterized in that, The electronic device further includes at least two functional modules independent of the central processing unit, wherein the computer program, when executed, implements the method as described in any one of claims 7 to 8.