Annular buffer data transmission method, chip and system in QSPIVideo mode

Abstract

The invention discloses an annular buffer data transmission method, chip and system in a QSPIVideo mode. A host sends a frame synchronization instruction packet to a display driving chip through a QSPI interface; after the frame synchronization instruction packet, the host sends a line synchronization instruction packet to the display driving chip through the QSPI interface; a host continuously writes continuous data blocks comprising multiple rows of pixel data into an annular buffer of a display driving chip through an interface in a direct memory access (DMA) mode, and the continuous data blocks do not comprise row synchronization instruction packets; the display driving chip stores the received continuous data blocks in an annular buffer, reads pixel data line by line from the annular buffer, and generates corresponding line synchronizing signals to drive the display panel to display multiple lines of pixel data; according to the method, the annular buffer is introduced and the communication protocol is optimized, so that the data transmission efficiency is greatly improved and the host load is reduced on the premise that the chip cost is not obviously increased.

Description

Technical Field

[0002] This invention relates to the field of integrated circuits and display driver technology, specifically to a ring buffer data transmission method, chip, and system in QSPIVideo mode. Background Technology

[0004] In embedded microcontroller systems, such as IoT terminals, wearable devices, and industrial human-machine interfaces, the performance, power consumption, and cost of the display subsystem are key considerations in system design. The interface technology between the microcontroller and the display driver chip plays a crucial role in this process. Common display interfaces include SPI, MCU interfaces, RGB interfaces, and MIPIDSI, but each has its limitations.

[0005] Traditional SPI interface (its communication structure is as follows) Figure 1 As shown, the basic communication timing is as follows: Figure 2 Although it is simple and easy to use, its single data line structure severely limits its theoretical bandwidth, which is usually no more than 50-80MHz, making it difficult to meet the growing graphical interface refresh requirements of modern embedded applications.

[0006] The MCU interface (also known as the I80 interface) has the following communication structure: Figure 3 As shown, the host needs to handle complex timings, and the numerous parallel lines result in complex PCB routing. Furthermore, the built-in GRAM capacity is limited, making it difficult to support high resolution and high refresh rates.

[0007] RGB interface (its system framework is as follows) Figure 4 As shown, the timing diagram for SYNC mode is as follows: Figure 5 Although it can achieve high-speed refresh, it requires a dedicated LCD controller and a large number of signal lines (such as at least 28 lines for 24-bit RGB), resulting in high hardware costs and complex wiring, making it unsuitable for microsystems that are sensitive to size and cost.

[0008] MIPI DSI interface (its physical connection is as follows) Figure 6 As shown, the protocol layered structure is as follows: Figure 7 (As shown) It has high bandwidth and few lines, but its protocol stack is complex and the physical layer (D-PHY) is difficult to implement. It requires high-performance processors or dedicated IP support, resulting in high overall system cost.

[0009] Therefore, a compromise solution—QSPI Video mode—emerged. It is based on the widely used QSPI (four-wire SPI, interface structure as follows) Figure 8The interface (shown) effectively increases bandwidth by increasing the number of data lines (to four) while maintaining the relative simplicity of the protocol. In Video mode, the display driver chip does not need to integrate a large-capacity GRAM; the host computer refreshes the screen by continuously sending pixel data streams through the QSPI interface, just like driving an RGB screen.

[0010] However, existing standard QSPI Video mode implementations have significant drawbacks that severely limit their application in high-performance or high-refresh-rate scenarios (see [link]). Figure 9 (Schematic diagram of traditional QSPI Video mode operation).

[0011] The protocol is inefficient, and DMA utilization is low: the standard protocol requires the host to send a field synchronization (VSYNC) instruction packet at the beginning of each frame and a line synchronization (HSYNC) instruction packet before each line of pixel data. This means that when transmitting a frame of image, the effective pixel data is interspersed by a large number of HSYNC instruction packets. For example, for a 320x480 resolution screen, each frame requires sending 481 instructions / data packets (1 VSYNC + 480 [HSYNC + one line of data]). The host usually uses DMA to improve transmission efficiency, but DMA can often only process one such "data packet" (such as one line of data plus the preceding HSYNC packet) at a time. Since mainstream MCUs can transfer tens of KB of data at a time via DMA, while one line of RGB565 data is only 640 bytes, the potential of the DMA channel (such as the ability to transfer 65535 bytes at a time) is seriously wasted, resulting in extremely low bandwidth utilization (see...). Figure 10 (A schematic diagram of the working timing of a single frame of RGB565 in traditional QSPI Video mode).

[0012] Excessive CPU interrupt load: Due to the need to initiate transmission line by line, if DMA is used, a DMA transmission completion interrupt will be generated after each line is transmitted (taking only tens of microseconds). At a 60fps refresh rate, the interrupt frequency reaches as high as 28.8kHz. Such a high frequency of interrupts severely consumes CPU resources, making it difficult for the system to handle other tasks during screen scrolling, resulting in overall performance degradation.

[0013] Unreasonable requirements are placed on the cache capacity of the driver chip: In order to alleviate the above problems, some improvement solutions attempt to integrate a larger capacity RAM into the display driver chip to cache multiple lines or frames of data. However, this directly leads to an increase in chip area and cost, which violates the original intention of QSPI Video mode to reduce the complexity and cost of the driver.

[0014] Therefore, the inefficient communication mechanism of the existing QSPI Video mode has become a bottleneck for its widespread application in embedded systems that pursue high performance and low power consumption. Summary of the Invention

[0016] The technical problem to be solved by this invention is to propose a ring buffer data transmission method, driver chip and system for QSPI Video mode. The method and system improve data transmission efficiency and reduce host load by introducing a ring buffer and optimizing the communication protocol without significantly increasing chip cost.

[0017] To address the aforementioned technical problems, this invention provides a ring buffer data transmission method in QSPIVideo mode, applicable to a system including a host and a display driver chip, wherein the display driver chip internally contains a ring buffer; the method includes:

[0018] The host sends frame synchronization command packets to the display driver chip via the QSPI interface;

[0019] Following the frame synchronization instruction packet, the host sends a line synchronization instruction packet to the display driver chip via the QSPI interface;

[0020] Following the line synchronization instruction packet, the host continuously writes a continuous data block containing multiple rows of pixel data to the ring buffer of the display driver chip through the QSPI interface and using the direct memory access (DMA) method. The continuous data block does not include the line synchronization instruction packet.

[0021] The display driver chip stores the received continuous data blocks in the ring buffer, and reads pixel data line by line from the ring buffer according to internal timing control, while generating corresponding line synchronization signals to drive the display panel to complete the display of the multiple lines of pixel data.

[0022] Preferably, the ring buffer is composed of multiple independent row buffer units connected end to end, used to buffer data when the write and read rates are mismatched.

[0023] Preferably, the number of rows contained in the consecutive data block written by the host in a single DMA transfer is less than or equal to the depth of the ring buffer; the depth is determined based on the ratio between the QSPI interface data transfer rate and the display scan rate, and its minimum depth D min The following relationship must be satisfied:

[0024] Among them, T disp_batch To display the total time required to display all rows of data within the continuous data block, T write_batch The time required to transmit this continuous data block via the QSPI interface, T line N is the time it takes to display one line of data on the screen. margin The number of rows reserved.

[0025] Preferably, the T write_batch Related to the QSPI clock frequency, data bus width, and the total number of bytes in the consecutive data blocks; the T disp_batch It is determined by the display frame rate, the total number of lines, and the number of lines contained in the consecutive data blocks.

[0026] Preferably, after completing the DMA transfer of the consecutive data blocks, the host generates an interrupt or event notification; for the display of a frame of image, the number of interrupts generated by the host is equal to the number of consecutive data blocks into which the frame of image data is divided.

[0027] Preferably, during the transmission of visible line data of a frame of image, the host repeatedly executes the process of sending a line synchronization instruction packet and then continuously writing a multi-line data block until all visible line data of the frame has been transmitted.

[0028] To address the aforementioned technical problems, this invention also discloses a ring buffer data transmission method in QSPIVideo mode, applied to a host computer, wherein the host computer communicates with a display driver chip via a QSPI interface; the method includes:

[0029] The host sends frame synchronization command packets to the display driver chip via the QSPI interface;

[0030] Following the frame synchronization instruction packet, the host sends a line synchronization instruction packet to the display driver chip via the QSPI interface;

[0031] Following the line synchronization instruction packet, the host continuously writes a continuous data block containing multiple rows of pixel data to the ring buffer of the display driver chip through the QSPI interface and using the direct memory access (DMA) method. The continuous data block does not include the line synchronization instruction packet.

[0032] To address the aforementioned technical problems, this invention also discloses a display driver chip for implementing the method described above, comprising:

[0033] The QSPI slave interface module is used to communicate with the host and receive commands and data packets.

[0034] A ring-shaped buffer memory is used to cache consecutive data blocks containing multiple rows of pixel data received from the QSPI slave interface module;

[0035] The display timing controller is used to generate the field synchronization, line synchronization, and pixel clock signals required to drive the display panel.

[0036] The buffer management and control logic module is connected to the QSPI slave interface module, the ring buffer memory, and the display timing controller. The buffer management and control logic module is configured to: control the writing of received continuous data blocks into the ring buffer memory, and control the reading of pixel data line by line from the ring buffer memory and output it to the display panel interface according to the line synchronization timing generated by the display timing controller.

[0037] Preferably, the circular buffer memory is composed of multiple physically independent row buffer units forming a logical circular queue. The buffer management and control logic module maintains a write pointer and a read pointer, which respectively point to the next writable and readable row buffer unit in the circular queue. The buffer management and control logic module also includes a data packet parsing unit, which is used to identify the frame synchronization instruction packet and the row synchronization instruction packet sent by the host, and trigger the corresponding internal state switch.

[0038] To address the aforementioned technical problems, the present invention also discloses a display system, comprising a host, a display panel, and a display driver chip as described above. The host is connected to the display driver chip via a QSPI bus, and the display driver chip drives the display panel.

[0039] After adopting the above method and system, the QSPIVideo mode ring buffer data transmission method is applied to a system including a host and a display driver chip, wherein the display driver chip contains a ring buffer. The method includes: the host sending a frame synchronization command packet to the display driver chip through the QSPI interface; after the frame synchronization command packet, the host sending a line synchronization command packet to the display driver chip through the QSPI interface; immediately following the line synchronization command packet, the host continuously writes a continuous data block including multiple rows of pixel data to the ring buffer of the display driver chip through the QSPI interface and using direct memory access (DMA) mode, wherein the continuous data block does not include the line synchronization command packet.

[0040] The display driver chip stores the received continuous data blocks in the ring buffer, and reads pixel data line by line from the ring buffer according to internal timing control, while generating corresponding line synchronization signals to drive the display panel to complete the display of the multiple lines of pixel data.

[0041] The beneficial effects of this invention are:

[0042] Significantly improves DMA utilization and transmission bandwidth: The host DMA can transfer a large amount of continuous pixel data (such as hundreds of rows) at once, so that the QSPI bus is in an effective data transmission state almost all the time during the transmission, eliminating bus idle caused by frequent insertion of HSYNC command packets, and DMA bandwidth utilization can be improved by tens of times;

[0043] Significantly reduces host CPU load: The host only generates a DMA completion interrupt once for each batch of multi-line data (e.g., 100 lines), reducing the interrupt frequency from hundreds per frame to just a few. This frees the CPU from frequent interrupt handling, allowing it to efficiently execute other applications during screen pushes and ensuring overall system performance.

[0044] Optimizing chip cost and area: The ring buffer depth required by this invention only needs to smooth the rate difference between burst writes and constant-speed scan reads from the host, typically only needing to cache a few to dozens of lines of data, far smaller than a full frame or multiple frames. This significantly reduces the demand on the SRAM capacity inside the display driver chip, effectively controlling chip area and manufacturing costs.

[0045] Excellent compatibility and ease of use: This invention is an enhancement rather than a replacement for the standard QSPI Video protocol. The chip can select its operating mode via configuration registers, maintaining backward compatibility. Driver modifications on the host side are also relatively simple, mainly involving changing the data packaging method from "line-by-line" to "batch-by-batch". Attached Figure Description

[0047] Figure 1 This is a schematic diagram of a traditional SPI bus communication structure.

[0048] Figure 2 This is a schematic diagram of the basic communication timing of traditional SPI.

[0049] Figure 3 This is a schematic diagram of the traditional MCU (I80) interface communication structure.

[0050] Figure 4 This is a schematic diagram of a traditional RGB interface system framework.

[0051] Figure 5 This is the timing diagram for the traditional RGB interface in SYNC mode.

[0052] Figure 6 This is a schematic diagram of the physical connection of a traditional MIPI DSI interface.

[0053] Figure 7 This is a schematic diagram of the layered structure of the traditional MIPI DSI protocol.

[0054] Figure 8 This is a schematic diagram of the traditional QSPI interface structure.

[0055] Figure 9 This is a schematic diagram of the traditional QSPI Video mode operation.

[0056] Figure 10This is a schematic diagram of the working timing of a single-line RGB565 in traditional QSPI Video mode.

[0057] Figure 11 This is a schematic diagram of the system architecture and internal modules of the display driver chip provided in an embodiment of the present invention.

[0058] Figure 12 This is a schematic diagram of the structure and pointer management of the ring buffer in an embodiment of the present invention.

[0059] Figure 13 This is a software flowchart of the host-side display driver thread in an embodiment of the present invention.

[0060] Figure 14 This diagram illustrates a comparison of data transmission between the traditional QSPI Video mode and the mode of this invention. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0063] Example 1

[0064] Please see Figure 11 and Figure 13 ;

[0065] This embodiment discloses a ring buffer data transmission method in QSPIVideo mode, applied to a system including a host and a display driver chip, wherein the display driver chip contains a ring buffer; the method includes:

[0066] The host sends frame synchronization command packets to the display driver chip via the QSPI interface;

[0067] Following the frame synchronization instruction packet, the host sends a line synchronization instruction packet to the display driver chip via the QSPI interface;

[0068] Following the line synchronization instruction packet, the host continuously writes a continuous data block containing multiple rows of pixel data to the ring buffer of the display driver chip through the QSPI interface and using the direct memory access (DMA) method. The continuous data block does not include the line synchronization instruction packet.

[0069] The display driver chip stores the received continuous data blocks in the ring buffer, and reads pixel data line by line from the ring buffer according to internal timing control, while generating corresponding line synchronization signals to drive the display panel to complete the display of the multiple lines of pixel data.

[0070] Example 2

[0071] This embodiment is based on Embodiment 1. In this embodiment, the ring buffer is composed of multiple independent row buffer units connected end to end, which is used to buffer data when the write and read rates are mismatched.

[0072] The number of rows contained in the consecutive data block written by the host in a single DMA transfer is less than or equal to the depth of the ring buffer; the depth is determined based on the ratio between the QSPI interface data transfer rate and the display scan rate, and its minimum depth D min The following relationship must be satisfied: ;

[0073] Among them, T_ disp_batch To display the total time required to display all rows of data within the contiguous data block, T_ write_batch The time required to transmit this continuous data block via the QSPI interface, T_ line N_ is the time it takes to display one line of data on the screen. margin The number of rows reserved.

[0074] The T_ write_batch Related to the QSPI clock frequency, data bus width, and the total number of bytes in the consecutive data blocks; the T_ disp_batch It is determined by the display frame rate, the total number of lines, and the number of lines contained in the consecutive data blocks.

[0075] Example 3

[0076] This embodiment is based on Embodiment 1. In this embodiment, after the host completes the DMA transfer of the continuous data block, it generates an interrupt or event notification. For the display of a frame of image, the number of interrupts generated by the host is equal to the number of continuous data blocks into which the frame of image data is divided.

[0077] During the transmission of visible line data for a frame of image, the host repeatedly executes the process of sending a line synchronization instruction packet and then continuously writing a multi-line data block until all visible line data for that frame has been transmitted.

[0078] Example 4

[0079] This embodiment is based on Embodiment 1. In this embodiment, the workflow of the ring buffer data transmission method in QSPIVideo mode is as follows, combined with... Figure 11, Figure 13 illustrate:

[0080] Initialization: The host configures the display driver chip's operating mode, resolution, pixel format, and other parameters.

[0081] Start of Frame: At the start of each frame, the host sends a VSYNC instruction packet. The display controller inside the chip resets the field scan counter accordingly.

[0082] Sending Vertical Back Edge (VBP): The host sends several HSYNC packets (corresponding to VBP rows), with a brief delay after each packet. Each time the chip receives an HSYNC packet, its internal row counter in the display controller increments, simulating the blanking period.

[0083] Send visible row data:

[0084] a. The host enters a loop (see...) Figure 13 (Left half). At the start of the loop, the host first sends an HSYNC instruction packet.

[0085] b. Next, the host calculates the number of lines that can be sent continuously this time, send_lines. It takes the minimum value between the preset maximum number of lines to send (MAX_LINES, for example, 100) and the number of remaining unsent lines.

[0086] c. The host temporarily disables interrupts (to prevent DMA setup from being interrupted), then initiates QSPI DMA transfer, sending consecutive lines of pixel data (e.g., 100 lines * 640 bytes / line = 64KB) from the frame buffer to the display driver chip in one continuous sequence, without inserting any HSYNC packets during this process. Afterwards, interrupts are enabled.

[0087] d. The host thread waits for a semaphore (line_sem). When the DMA transfer completes and triggers an interrupt, the semaphore is released in the interrupt service routine (ISR) (see...). Figure 13 (Right half)

[0088] e. After receiving the semaphore, the host thread updates the count of lines sent and jumps back to step a to send the next HSYNC packet. Then it continuously sends the next batch of multiple lines of data until all visible lines in the current frame have been sent.

[0089] Chip-side parallel processing:

[0090] a. When the host sends an HSYNC packet, the chip's packet processor recognizes it and may use it for internal state synchronization or as a start marker for multiple data blocks. b. When the host continuously sends pixel data streams, the chip writes them sequentially to a ring buffer. Assuming 100 lines are written at a time, these 100 lines will sequentially fill multiple Linebuffer units in the ring buffer, and head_ptr will move accordingly. c. Simultaneously, the chip's display controller generates an HSYNC signal at fixed intervals (e.g., one line time T_line). Each time an HSYNC is generated, the scheduling logic retrieves one line of data from the Linebuffer pointed to by tail_ptr, outputs it, and moves tail_ptr. d. As long as the ring buffer depth is designed reasonably (ensuring that unread data is not overwritten during peak write speed periods), the entire data transmission and display process can proceed smoothly, decoupling the host's "burst writes" from the screen's "uniform speed scan display."

[0091] Vertical Lead-Out (VFP) Transmission and Frame End: After the visible line is transmitted, the host sends several HSYNC packets (corresponding to the VFP line) to complete the frame. Then, the transmission of VSYNC packets for the next frame begins, and the cycle repeats.

[0092] Example 5

[0093] This embodiment is based on Embodiment 1. In this embodiment...

[0094] Example of ring buffer depth design:

[0095] Assuming a QSPI clock SCK = 100MHz, operating in Quad mode (4 data lines), transmitting 1 byte requires 2 clock cycles (1 byte = 8 bits, 4 bits are transmitted per cycle, therefore 8 bits / 4 = 2 cycles). If the host's maximum single DMA transfer is 65536 bytes (corresponding to approximately 102 lines of RGB565 data), then the time T required for QSPI transmission is... write_batch for:

[0096]

[0097] Assuming a screen resolution of 480 lines and a refresh rate of 60Hz, the display time for one line, T_line, is:

[0098]

[0099] The total time T required to display 102 rows of data disp_batch for:

[0100]

[0101] Because the display read speed (3.54ms) is slower than the QSPI write speed (1.31ms), a ring buffer is needed to temporarily store data that has not yet been displayed. To ensure no overflow, the minimum depth D_min required for the ring buffer can be estimated as follows:

[0102]

[0103] Considering the design margin (N_margin), a practical depth of 72 or 80 lines can be selected. However, this is a theoretical calculation based on an extreme continuous write of 102 lines. In practical applications, the physical depth of the ring buffer (the number of line buffers) can be much smaller than this calculated value. If the host only sends 32768 bytes of data at a time, the required ring buffer depth can be reduced proportionally (only 32 lines are needed). If the host's QSPI clock SCK does not reach 100MHz, the required ring buffer depth will be even smaller. Therefore, the ring buffer depth can be flexibly selected. A ring buffer with an actual depth of around 16 lines is sufficient to meet the requirements, achieving a good benefit ratio, which is much smaller than the frame buffer, greatly saving chip area.

[0104] Example 6

[0105] Please see Figure 13 ,

[0106] This embodiment discloses a ring buffer data transmission method in QSPIVideo mode, applied to a host computer, which communicates with a display driver chip via a QSPI interface; the method includes:

[0107] The host sends frame synchronization command packets to the display driver chip via the QSPI interface;

[0108] Following the frame synchronization instruction packet, the host sends a line synchronization instruction packet to the display driver chip via the QSPI interface;

[0109] Following the line synchronization instruction packet, the host continuously writes a continuous data block containing multiple rows of pixel data to the ring buffer of the display driver chip through the QSPI interface and using the direct memory access (DMA) method. The continuous data block does not include the line synchronization instruction packet.

[0110] Example 7

[0111] This embodiment discloses a display driver chip that implements the method described in any one of embodiments one to six, including:

[0112] The QSPI slave interface module is used to communicate with the host and receive commands and data packets.

[0113] A ring-shaped buffer memory is used to cache consecutive data blocks containing multiple rows of pixel data received from the QSPI slave interface module;

[0114] The display timing controller is used to generate the field synchronization, line synchronization, and pixel clock signals required to drive the display panel.

[0115] The buffer management and control logic module is connected to the QSPI slave interface module, the ring buffer memory, and the display timing controller. The buffer management and control logic module is configured to: control the writing of received continuous data blocks into the ring buffer memory, and control the reading of pixel data line by line from the ring buffer memory and output it to the display panel interface according to the line synchronization timing generated by the display timing controller.

[0116] Example 8

[0117] This embodiment is based on Embodiment 7. In this embodiment, the circular buffer memory is composed of multiple physically independent row buffer units forming a logical circular queue. The buffer management and control logic module maintains a write pointer and a read pointer, which respectively point to the next writable and readable row buffer unit in the circular queue.

[0118] The buffer management and control logic module also includes a data packet parsing unit, which is used to identify frame synchronization instruction packets and line synchronization instruction packets sent by the host, and trigger corresponding internal state switching.

[0119] Example 9

[0120] This embodiment discloses a display system, including a host, a display panel, and a display driver chip as described in any one of embodiments seven or eight. The host is connected to the display driver chip via a QSPI bus, and the display driver chip drives the display panel.

[0121] Example 10

[0122] This embodiment is based on Embodiment Eight. In this embodiment...

[0123] like Figure 11 The diagram illustrates the display system architecture applying this invention. The host MCU is connected to the display driver chip designed in this invention via a QSPI bus. The core improvement of this display driver chip lies in its internal integration of a high-efficiency data processing pipeline based on a ring buffer, mainly including:

[0124] QSPI Slave Interface and Packet Processor: Responsible for communicating with the host, receiving and parsing command packets such as VSYNC and HSYNC. Upon recognizing an HSYNC packet, it anticipates a continuous stream of pixel data and initiates the process of writing this data stream into a ring buffer.

[0125] A ring buffer composed of multiple line buffers: This is the core storage structure of this invention. For example... Figure 12 As shown, it consists of N (e.g., 4, 8, or 16) independent line buffer units forming a logical circular queue. The buffer management logic maintains a write pointer (head_ptr) and a read pointer (tail_ptr). head_ptr points to the next Line buffer that can be written to, and tail_ptr points to the next Line buffer that will be read by the display scanning engine. When the pointer reaches the end of the queue, it automatically wraps back to the beginning of the queue, achieving circular reuse.

[0126] Display Controller (Disp Ctrl) and Timing Generator: This module independently generates the precise timing signals required to drive the LCD panel, including VSYNC and HSYNC. The generation of HSYNC no longer depends on external input; instead, it is periodically generated by an internal counter based on configured display parameters (such as line timing).

[0127] Buffering and display scheduling logic (in) Figure 11 This is manifested as the control flow between modules: this logic coordinates the entire data path. When the host sends a batch of continuous multi-line pixel data via QSPI, the scheduling logic controls the sequential cyclic writing of this data into each Linebuffer pointed to by the head pointer head_ptr, and updates head_ptr accordingly. Simultaneously, each time the display controller generates an HSYNC signal, the scheduling logic controls the reading of a line of pixel data from the Linebuffer pointed to by the tail pointer tail_ptr and sends it to the LCD panel, then updates tail_ptr.

[0128] The advantages of this invention compared to the traditional approach are as follows (see attached image). Figure 14 :

[0129] Traditional mode: Transmitting 25 lines of data requires sending 25 "HSYNC+data" packets, resulting in 25 interrupts.

[0130] The present invention's mode requires only one "HSYNC" packet to transmit 25 lines of data, followed by a continuous transmission of the 25 lines of data at once, generating only one interruption. The improvement in transmission efficiency and interrupt load is immediately apparent.

[0131] This invention is not limited to the specific embodiments described above. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this invention should be included within the protection scope of this invention. For example, the specific implementation of the ring buffer, the format of host data packaging, and the specific design of the chip's internal state machine can all be adjusted according to actual circumstances. It should be understood that the above are merely preferred embodiments of this invention and should not be construed as limiting the patent scope of this invention. Any equivalent structural or procedural transformations made using the content of this specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this invention.

Claims

1. A ring-buffered data transmission method in QSPIVideo mode, characterized in that, An application is made in a system comprising a host and a display driver chip, wherein the display driver chip contains a ring buffer. The method includes: the host sending a frame synchronization command packet to the display driver chip via a QSPI interface; following the frame synchronization command packet, the host sending a line synchronization command packet to the display driver chip via the QSPI interface; immediately following the line synchronization command packet, the host continuously writing a continuous data block comprising multiple lines of pixel data to the ring buffer of the display driver chip via the QSPI interface and using direct memory access (DMA), wherein the continuous data block does not contain the line synchronization command packet; the display driver chip storing the received continuous data block in the ring buffer and reading pixel data line by line from the ring buffer according to internal timing control, while generating a corresponding line synchronization signal to drive the display panel to complete the display of the multiple lines of pixel data.

2. The ring buffer data transmission method for QSPIVideo mode according to claim 1, characterized in that, The ring buffer consists of multiple independent row buffer units connected end to end, used to buffer data when the write and read rates are mismatched.

3. The ring buffer data transmission method for QSPIVideo mode according to claim 2, characterized in that, The number of rows contained in the consecutive data block written by the host in a single DMA transfer is less than or equal to the depth of the ring buffer; the depth is determined based on the ratio between the QSPI interface data transfer rate and the display scan rate, and its minimum depth D min The following relationship must be satisfied: Among them, T disp_batch To display the total time required to display all rows of data within the continuous data block, T write_batch The time required to transmit this continuous data block via the QSPI interface, T line N is the time it takes to display one line of data on the screen. margin The number of rows reserved.

4. The ring buffer data transmission method for QSPIVideo mode according to claim 3, characterized in that, The T write_batch Related to the QSPI clock frequency, data bus width, and the total number of bytes in the consecutive data blocks; the T disp_batch It is determined by the display frame rate, the total number of lines, and the number of lines contained in the consecutive data blocks.

5. The ring buffer data transmission method for QSPIVideo mode according to claim 1, characterized in that, After completing the DMA transfer of the consecutive data blocks, the host generates an interrupt or event notification; for the display of a frame of image, the number of interrupts generated by the host is equal to the number of consecutive data blocks into which the frame of image data is divided.

6. The ring buffer data transmission method for QSPIVideo mode according to claim 1, characterized in that, During the transmission of visible line data for a frame of image, the host repeatedly executes the process of sending a line synchronization instruction packet and then continuously writing a multi-line data block until all visible line data for that frame has been transmitted.

7. A ring-buffered data transmission method for QSPIVideo mode, characterized in that, The method is applied to a host computer that communicates with a display driver chip via a QSPI interface; the method includes: the host computer sending a frame synchronization instruction packet to the display driver chip via the QSPI interface; Following the frame synchronization instruction packet, the host sends a line synchronization instruction packet to the display driver chip via the QSPI interface; Following the line synchronization instruction packet, the host continuously writes a continuous data block containing multiple rows of pixel data to the ring buffer of the display driver chip through the QSPI interface and using the direct memory access (DMA) method. The continuous data block does not include the line synchronization instruction packet.

8. A display driver chip implementing the method as described in any one of claims 1 to 7, characterized in that, include: The QSPI slave interface module is used to communicate with the host and receive commands and data packets. A ring-shaped buffer memory is used to cache consecutive data blocks containing multiple rows of pixel data received from the QSPI slave interface module; The display timing controller is used to generate the field synchronization, line synchronization, and pixel clock signals required to drive the display panel. The buffer management and control logic module is connected to the QSPI slave interface module, the ring buffer memory, and the display timing controller. The buffer management and control logic module is configured to: control the writing of received continuous data blocks into the ring buffer memory, and control the reading of pixel data line by line from the ring buffer memory and output it to the display panel interface according to the line synchronization timing generated by the display timing controller.

9. The display driver chip according to claim 7, characterized in that, The circular buffer memory consists of a logical circular queue composed of multiple physically independent row buffer units. The buffer management and control logic module maintains a write pointer and a read pointer, which point to the next writable and readable row buffer unit in the circular queue, respectively. The buffer management and control logic module also includes a data packet parsing unit, which is used to identify frame synchronization instruction packets and row synchronization instruction packets sent by the host and trigger corresponding internal state switching.

10. A display system, characterized in that, The device includes a host computer, a display panel, and a display driver chip as described in any one of claims 7 to 9, wherein the host computer is connected to the display driver chip via a QSPI bus, and the display driver chip drives the display panel.

Images