Dual-view display device

Abstract

A dual-view display device includes: a display panel comprising a display area having a left sub-pixel and a right sub-pixel, and a non-display area; a first transistor, which switches according to the voltage of a first node and is connected to a high-level signal and a second node; a second transistor, which switches according to a light-emitting signal and is connected to the second node and a fourth node; a third transistor, which switches according to a second scan signal and is connected to the first node and the second node; a fourth transistor, which switches according to the second scan signal and is connected to the fourth node; a fifth transistor, which switches according to the light-emitting signal and is connected to a third node and a reference signal; a sixth transistor, which switches according to the first scan signal and is connected to the third node; and a seventh transistor, connected to the fourth node, wherein the seventh transistor of the left sub-pixel and the seventh transistor of the right sub-pixel switch according to a left light-emitting control signal and a right light-emitting control signal, respectively.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0170825, filed on November 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a display device, and more specifically, to a dual-view display device, wherein the brightness of a left image and a right image displayed in a left view area and a right view area, respectively, is independently adjusted. Background Technology

[0004] Recently, with the emergence of an information-oriented society, interest in information displays for processing and displaying massive amounts of information, as well as the demand for portable information media, has increased. Furthermore, with the increasing demand for portable information media, various lightweight and thin flat panel display devices have been developed and have become a focus.

[0005] Among various flat panel display devices, organic light-emitting diode (OLED) display devices are light-emitting devices that do not include backlight units used in non-light-emitting devices such as liquid crystal displays (LCDs). As a result, OLED display devices have advantages in terms of viewing angle, contrast ratio, and power consumption, making them suitable for a wide range of applications.

[0006] Specifically, OLED displays are already being used in vehicle dashboards. In the automotive field, dual-view OLED displays that allow drivers and passengers to view different images have been researched and developed.

[0007] In dual-view OLED displays, a film or lens is used to display the left and right images in the left and right view areas, respectively. However, since a single light-emitting signal is used to display the left and right images, their brightness is not adjusted independently. Summary of the Invention

[0008] Therefore, the present invention aims to provide a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0009] More specifically, the present invention aims to provide a dual-view display device, wherein by providing light-emitting control transistors that switch according to a left light-emitting control signal and a right light-emitting control signal respectively in the left and right sub-pixels displaying the left and right images, the brightness of the left and right images can be adjusted independently and low power consumption can be obtained.

[0010] Furthermore, the present invention aims to provide a dual-view display device in which the brightness of the left and right images is independently adjusted and low power consumption is achieved by switching the light-emitting transistors that display the left sub-pixel of the left image and the right sub-pixel of the right image according to the left light-emitting signal and the right light-emitting signal, respectively.

[0011] Additional features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the invention. These and other advantages of the invention will be realized and obtained by means of the structures specifically pointed out in the written description, the claims, and the drawings.

[0012] To achieve these and other advantages and in accordance with the intent of the invention, as embodied and broadly described herein, a dual-view display device includes: a display panel comprising a display area having a left sub-pixel and a right sub-pixel, and a non-display area surrounding the display area; a first transistor in each of the left and right sub-pixels, the first transistor being switched according to a voltage of a first node and connected to a high-level signal and a second node; a second transistor in each of the left and right sub-pixels, the second transistor being switched according to a light-emitting signal and connected to a second node and a fourth node; and a third transistor in each of the left and right sub-pixels, the third transistor being switched according to a second scan signal and connected to the first node and the second node. A fourth transistor, in each of the left and right sub-pixels, is switched and connected to the fourth node according to the second scan signal; a fifth transistor, in each of the left and right sub-pixels, is switched and connected to the third node and a reference signal according to the emission signal; a sixth transistor, in each of the left and right sub-pixels, is switched and connected to the third node according to the first scan signal; and a seventh transistor, in each of the left and right sub-pixels, is connected to the fourth node, wherein the seventh transistor of the left sub-pixel and the seventh transistor of the right sub-pixel are switched according to the left emission control signal and the right emission control signal, respectively.

[0013] On the other hand, a dual-view display device includes: a display panel comprising a display area having a left sub-pixel and a right sub-pixel, and a non-display area surrounding the display area; a first transistor, in each of the left sub-pixel and the right sub-pixel, the first transistor switching according to a voltage of a first node and connected to a high-level signal and a second node; a second transistor, in each of the left sub-pixel and the right sub-pixel, the second transistor connected to a second node and a fourth node; and a third transistor, in each of the left sub-pixel and the right sub-pixel, the third transistor switching according to a second scan signal and connected to... The first node and the second node; a fourth transistor, in each of the left sub-pixel and the right sub-pixel, the fourth transistor being switched and connected to the fourth node according to the second scan signal; a fifth transistor, in each of the left sub-pixel and the right sub-pixel, the fifth transistor being connected to the third node and the reference signal; and a sixth transistor, in each of the left sub-pixel and the right sub-pixel, the sixth transistor being switched and connected to the third node according to the first scan signal, wherein the second transistor of the left sub-pixel and the second transistor of the right sub-pixel are switched according to the left emission signal and the right emission signal, respectively.

[0014] It should be understood that the foregoing general description and the following detailed description are illustrative and intended to provide further explanation of the claimed invention. Attached Figure Description

[0015] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0016] In the attached diagram:

[0017] Figure 1 This is a view showing a dual-view display device according to a first embodiment of the present invention;

[0018] Figure 2 This is a circuit diagram showing the left and right sub-pixels of a dual-view display device according to a first embodiment of the present invention;

[0019] Figure 3 This is a view showing multiple signals of the left and right sub-pixels of the dual-view display device according to a first embodiment of the present invention;

[0020] Figure 4 This is a plan view showing the left and right sub-pixels of a dual-view display device according to a first embodiment of the present invention;

[0021] Figure 5 This is a cross-sectional view showing the left and right sub-pixels of a dual-view display device according to a first embodiment of the present invention;

[0022] Figure 6 This is a circuit diagram showing the left and right sub-pixels of a dual-view display device according to a second embodiment of the present invention;

[0023] Figure 7 This is a view showing multiple signals of the left and right sub-pixels of a dual-view display device according to a second embodiment of the present invention. Detailed Implementation

[0024] The advantages and features of the invention, as well as its implementation methods, will become apparent from the exemplary aspects described below with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the exemplary aspects set forth herein. Rather, these exemplary aspects are provided so that the disclosure of the invention will be thorough and complete, assisting those skilled in the art in fully understanding the scope of the invention. Furthermore, the invention is defined only by the scope of the claims.

[0025] The shapes, dimensions, scales, angles, quantities, etc., illustrated in the accompanying drawings for the purpose of describing various exemplary aspects of the invention are given by way of example only. Therefore, the invention is not limited to the illustrations in the drawings. Unless otherwise stated, similar reference numerals refer to similar elements throughout the specification.

[0026] In the following description, where a detailed description of a known function or configuration may unnecessarily obscure a feature or aspect of the invention, a detailed description of such a known function or configuration may be omitted, or a brief description may be provided.

[0027] When using terms such as “including,” “having,” or “comprising,” one or more additional elements may be added unless a term such as “only” is used. Elements described in the singular are intended to include multiple elements, and vice versa, unless the context clearly indicates otherwise.

[0028] When interpreting an element, it should be interpreted as including a range of errors or tolerances, even if no explicit description of such a range of errors or tolerances is provided.

[0029] In describing positional relationships, such as when using terms like "on," "above," "below," "above," "below," "next to," or "next to" to describe the positional relationship between two components, one or more other components may be located between the two components unless more restrictive terms such as "immediately," "directly," or "immediately following" are used. For example, when one element or layer is situated on top of another element or layer, a third layer or element may be located between them.

[0030] Although the terms “first,” “second,” “A,” “B,” (a), (b), etc., may be used herein to refer to various elements, these elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. These terms are used only to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0031] The term "at least one" should be understood to include all combinations of one or more related elements. For example, the term "at least one of the first, second and third elements" may include all combinations of two or more of the first, second and third elements, as well as the first, second or third element.

[0032] The term "display device" can include display devices in the narrow sense, such as liquid crystal modules (LCMs), organic light-emitting diode (OLED) modules, and quantum dot (QD) modules that include a display panel and driving units for driving the display panel. Additionally, the term "display device" can include finished products (or final products) that include LCMs, OLED modules, and QD modules, such as laptops, televisions, computer monitors, display devices including automotive display equipment or other forms of equipment besides vehicles, and sets of electronic devices or assemblies (or assemblies of equipment) such as smartphones or tablets.

[0033] Therefore, the display device of the present invention may include: an application product or complete set of equipment including an LCM, OLED module and QD module for an end user device; and a display device in the narrow sense, such as an LCM, OLED module and QD module.

[0034] Depending on the context, an LCM, OLED module, and QD module having a display panel and a driving unit can be described as a "display device," and an electronic device including an LCM, OLED module, and QD module as finished products can be described as an "assembly." For example, a display device in a narrow sense may include: a liquid crystal, organic light-emitting diode, and quantum dot display panel; and a source printed circuit board (PCB) for a control unit for driving the display panel; and the assembly may further include an assembly PCB electrically connected to the source PCB for controlling the entire assembly.

[0035] The display panel of the present invention may include all types of display panels, such as liquid crystal display panels, organic light-emitting diode display panels, quantum dot display panels, and electroluminescent display panels. The display panel of the present invention is not limited to a specific display panel having a curved frame with a flexible substrate and a lower backplate support for an organic light-emitting diode display panel. The shape or size of the display panel used in the display device of the present invention is not limited thereto.

[0036] For example, when the display panel is an organic light-emitting diode (OLED) display panel, the display panel may include multiple gate lines, multiple data lines, and sub-pixels in the intersection areas of the multiple gate lines and multiple data lines. The display panel may include: an array of thin-film transistors having elements for selectively applying voltage to each sub-pixel; a light-emitting element layer on the array; and a packaging substrate or package covering the light-emitting element layer. The package protects the thin-film transistors and the light-emitting element layer from external impacts and prevents or at least reduces the penetration of moisture or oxygen into the light-emitting element layer. Additionally, the light-emitting element layer on the array may include an inorganic light-emitting layer, such as a nanoscale material layer or quantum dots.

[0037] The thin-film transistor of the present invention may include one of oxide thin-film transistors, amorphous silicon thin-film transistors, and low-temperature polycrystalline silicon thin-film transistors.

[0038] Features of various embodiments of the present invention may be combined or integrated with each other, either partially or completely. These features may be technically connected and operated in various ways, as will be fully understood by those skilled in the art. These aspects may be implemented independently or in conjunction with each other in various combinations.

[0039] In the following, a display device according to various exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein the influence on the oxide semiconductor layer of the thin-film transistor of the driving element portion is reduced by shielding light emitted and transmitted from the sub-pixels and / or light input from the outside.

[0040] Figure 1This is a view illustrating a dual-view display device according to a first embodiment of the present invention. While the display device may be an organic light-emitting diode (OLED) display device, it is not limited thereto. For example, the display device may be a quantum dot display device, a micro-light-emitting diode (LED) display device, or a miniature light-emitting diode (LED) display device.

[0041] exist Figure 1 According to a first embodiment of the present invention, a dual-view display device 110 includes a timing control unit 120 (e.g., a circuit), a data driving unit 122 (e.g., a circuit), a first gate driving unit 124 (e.g., a circuit), a second gate driving unit 126 (e.g., a circuit), and a display panel 128.

[0042] The timing control unit 120 uses an image signal IS transmitted from an external system such as a graphics card or a television system and multiple timing signals to generate left image data RGB1, right image data RGBr, data control signal DCS, and gate control signal GCS, wherein the multiple timing signals include a data enable signal DE, a horizontal synchronization signal HSY, a vertical synchronization signal VSY, and a clock signal CLK.

[0043] The timing control unit 120 transmits the left image data RGB1, the right image data RGBr, and the data control signal DCS to the data driving unit 122, and transmits the gate control signal GCS to the first gate driving unit 124 and the second gate driving unit 126.

[0044] Data drive unit 122 uses the left image data RGB1, right image data RGBr, and data control signal DCS transmitted from timing control unit 120 to generate a left data signal (left data voltage) Vdal (see...). Figure 2 ) and right data signal (right data voltage) Vdar ​​(see Figure 2 The left data signal Vdal and the right data signal Vdar ​​are applied to the data line DL of the display panel 128.

[0045] The first gate driving unit 124 and the second gate driving unit 126 use the gate control signal GCS transmitted from the timing control unit 120 to generate gate signals (gate voltages) Sc1, Sc2, Em, Ecl, and Ecr (see... Figure 2 The gate signals Sc1, Sc2, Em, Ecl and Ecr are applied to the gate line GL of the display panel 128.

[0046] The first gate driving unit 124 and the second gate driving unit 126 may have an in-panel gate (GIP) type, which is formed in the non-display area NDA of the substrate of the display panel 128 having gate lines GL, data lines DL and pixels P.

[0047] Despite Figure 1 In one embodiment, the first gate driving unit 124 and the second gate driving unit 126 are disposed in two sides of the display panel 128, but in another embodiment, one gate driving unit may be disposed in one side of the display panel 128.

[0048] Display panel 128 includes a display area DA in its central portion and a non-display area NDA surrounding the display area DA. Display panel 128 uses gate signals Sc1, Sc2, Em, Ecl, and Ecr, a left data signal Vdal, and a right data signal Vdar ​​to display images. For displaying images, display panel 128 includes multiple sub-pixels SP, multiple gate lines GL, and multiple data lines DL in the display area DA.

[0049] Multiple sub-pixels SP include a left sub-pixel SP1 for displaying the left image and a right sub-pixel SPr for displaying the right image. Gate line GL and data line DL intersect each other to define the left sub-pixel SP1 and the right sub-pixel SPr. Each of the left sub-pixel SP1 and the right sub-pixel SPr is connected to the gate line GL and the data line DL.

[0050] For example, the left lens 178, which is hemispherical or semi-cylindrical in shape and focuses light towards the front along the left direction (see...). Figure 5 The right lens 180, which is in a hemispherical or semi-cylindrical shape and is positioned on the display panel 128 corresponding to the left sub-pixel SP1, and focuses the light towards the front in a right direction (see...). Figure 5 It is set on the display panel 128 corresponding to the right sub-pixel SPr.

[0051] Among multiple sub-pixels SP, some sub-pixels that make up white constitute a pixel.

[0052] For example, the first, second, and third sub-pixels corresponding to red, green, and blue in a plurality of sub-pixels SP can constitute a pixel, or the first, second, third, and fourth sub-pixels corresponding to red, green, blue, and white in a plurality of sub-pixels can constitute a pixel.

[0053] Each of the left sub-pixel SP1 and the right sub-pixel SPr may include multiple transistors (such as switching transistors, driving transistors, and sensing transistors), storage capacitors, and light-emitting diodes.

[0054] In the dual-view display device 110, the left data signal Vdal (see...) corresponds to the left image data RGB1. Figure 2 The signal is applied to the left sub-pixel SP1 of the display area DA of the display panel 128, and corresponds to the right data signal Vdar ​​of the right image data RGBr (see...). Figure 2The right sub-pixel SPr of the display area DA of the display panel 128 is applied.

[0055] As a result, the display panel 128 of the dual-view display device 110 can display the left image corresponding to the left image data RGB1 through the left sub-pixel SP1 of the display area DA along the left direction, and the dual-view display device 110 can display the right image corresponding to the right image data RGBr through the right sub-pixel SPr of the display area DA along the right direction.

[0056] Despite Figure 1 In one embodiment, the first gate driving unit 124 and the second gate driving unit 126 generate a left light emission control signal Ec1 and a right light emission control signal Ecr and supply the left light emission control signal Ec1 and the right light emission control signal Ecr to the left sub-pixel SP1 and the right sub-pixel SPr of the display panel 128. However, in another embodiment, the timing control unit 120 can generate the left light emission control signal Ec1 and the right light emission control signal Ecr and supply the left light emission control signal Ec1 and the right light emission control signal Ecr to the left sub-pixel SP1 and the right sub-pixel SPr of the display panel 128.

[0057] The structure and operation of the left and right sub-pixels of the dual-view display device 110 will be illustrated with reference to the accompanying drawings.

[0058] Figure 2 This is a circuit diagram showing the left and right sub-pixels of a dual-view display device according to a first embodiment of the present invention. Figure 3 This is a view showing multiple signals of the left and right sub-pixels of a dual-view display device according to a first embodiment of the present invention.

[0059] exist Figure 2 In the dual-view display device 110 according to the first embodiment of the present invention, each of the left sub-pixel SP1 and the right sub-pixel SPr of the display panel 128 includes a first transistor T1 to a seventh transistor T7, a storage capacitor Cs, and one of a left light-emitting diode Del and a right light-emitting diode Del.

[0060] Despite Figure 2 In one embodiment, the first transistor T1 to the seventh transistor T7 are positive, but in another embodiment, at least one of the first transistor T1 to the seventh transistor T7 may be negative.

[0061] The first transistor T1, acting as the driving transistor, switches according to the voltage of the first node N1. The gate of the first transistor T1 is connected to the first node N1, the source of the first transistor T1 is connected to the high-level signal (high-level voltage) Vdd, and the drain of the first transistor T1 is connected to the second node N2.

[0062] The second transistor T2, which acts as a light-emitting transistor, switches according to the light-emitting signal Em. The gate of the second transistor T2 is connected to the light-emitting signal Em, the source of the second transistor T2 is connected to the second node N2, and the drain of the second transistor T2 is connected to the fourth node N4.

[0063] The third transistor T3, which acts as a sensing transistor, is switched according to the second scan signal Sc2. The gate of the third transistor T3 is connected to the second scan signal Sc2, the source of the third transistor T3 is connected to the second node N2, and the drain of the third transistor T3 is connected to the first node N1.

[0064] The fourth transistor T4 is switched according to the second scan signal Sc2. The gate of the fourth transistor T4 is connected to the second scan signal Sc2, the source of the fourth transistor T4 is connected to the fourth node N4, and the drain of the fourth transistor T4 is connected to the reference signal (reference voltage) Vrf.

[0065] The fifth transistor T5 switches according to the light emission signal Em. The gate of the fifth transistor T5 is connected to the light emission signal Em, the source of the fifth transistor T5 is connected to the third node N3, and the drain of the fifth transistor T5 is connected to the reference signal Vrf.

[0066] The sixth transistor T6, acting as a switching transistor, is switched according to the first scan signal Sc1. The gate of the sixth transistor T6 is connected to the first scan signal Sc1, the source of the sixth transistor T6 is connected to the third node N3, and the drain of the sixth transistor T6 is connected to either the left data signal Vdal or the right data signal Vdar.

[0067] The seventh transistor T7, acting as a light-emitting transistor, is switched according to the left light-emitting control signal Ec1 or the right light-emitting control signal Ecr. The gate of the seventh transistor T7 is connected to the left light-emitting control signal Ec1 or the right light-emitting control signal Ecr, the source of the seventh transistor T7 is connected to the fourth node N4, and the drain of the seventh transistor T7 is connected to the anode of the left light-emitting diode Del or the anode of the right light-emitting diode Der.

[0068] The storage capacitor Cs stores either the left data signal Vdal or the right data signal Vdar ​​and the threshold voltage (Vth) of the first transistor T1. The first capacitor electrode of the storage capacitor Cs is connected to the first node N1, and the second capacitor electrode of the storage capacitor Cs is connected to the third node N3.

[0069] Each of the left LED Del and the right LED Der is connected between the seventh transistor T7 and the low-level signal (low-level voltage) Vss, and emits light with a brightness proportional to the current of the first transistor T1. The anode of each of the left LED Del and the right LED Der is connected to the drain of the seventh transistor T7, and the cathode of each of the left LED Del and the right LED Der is connected to the low-level signal Vss.

[0070] The left lens 178, which is hemispherical or semi-cylindrical in shape and focuses light towards the front along the left direction (see...). Figure 5 The left light-emitting diode Del, located on the left sub-pixel SP1, is used to display the left image to the user, and the right lens 180, in a hemispherical or semi-cylindrical shape, is positioned along the right direction towards the front focusing light (see...). Figure 5 It is set on the right LED Der of the right sub-pixel SPr to display the right image to the user.

[0071] The gate of the first transistor T1, the first capacitor electrode of the storage capacitor Cs, and the drain of the third transistor T3 constitute the first node N1, and the drain of the first transistor T1, the source of the second transistor T2, and the source of the third transistor T3 constitute the second node N2. The second capacitor electrode of the storage capacitor Cs, the source of the fifth transistor T5, and the source of the sixth transistor T6 constitute the third node, and the drain of the second transistor T2, the source of the fourth transistor T4, and the source of the seventh transistor T7 constitute the fourth node N4.

[0072] In the dual-view display device 110 according to the first embodiment of the present invention, the seventh transistor T7 of the left sub-pixel SP1 switches according to the left light emission control signal Ec1 to drive the left light-emitting diode Del using a dimming method and adjust the brightness of the left image. Furthermore, the seventh transistor T7 of the right sub-pixel SPr switches according to the right light emission control signal Ecr to drive the right light-emitting diode Del using a dimming method and adjust the brightness of the right image.

[0073] As a result, by using a dimming method to independently drive the left LED Del and the right LED Der, the brightness of the left and right images can be adjusted independently.

[0074] exist Figure 3 In the first embodiment of the present invention, each of the left sub-pixel SP1 and the right sub-pixel SPr of the dual-view display device 110 is driven via the first to fourth time periods TP1 to TP4.

[0075] During the first time period TP1, which serves as the initialization period, transistors T2, T3, T4, T5, and T7 are turned on due to the second scan signal Sc2 (logic low voltage Vl), the light emission signal Em, the left light emission control signal Ec1, and the right light emission control signal Ecr. Conversely, transistor T6 is turned off due to the first scan signal Sc1 (logic high voltage Vh). Since the reference signal Vrf is applied to nodes N1, N2, N3, and N4, the first and second capacitor electrodes of the storage capacitor Cs, the gate of the first transistor T1, the anode of the left light emission diode Del, and the anode of the right light emission diode Del are initialized by the reference signal Vrf.

[0076] During the second sampling period TP2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are turned on due to the first scan signal Sc1, the second scan signal Sc2, the left light emission control signal Ec1, and the right light emission control signal Ecr at a logic low voltage Vl. The second transistor T2 and the fifth transistor T5 are turned off due to the light emission signal Em at a logic high voltage Vh. The left data signal Vdal or the right data signal Vdar ​​is applied to the third node N3, the high-level signal Vdd is applied to the first node N1, and the reference signal Vrf is applied to the fourth node N4. As a result, the second capacitor electrode of the storage capacitor Cs has either the left data signal Vdal or the right data signal Vdar, and the first capacitor electrode of the storage capacitor Cs has the sum of the difference between the left data signal Vdal and the reference signal Vrf and the threshold voltage Vth (Vdal - Vrf + Vth), or the sum of the difference between the right data signal Vdar ​​and the reference signal Vrf and the threshold voltage Vth (Vdar - Vrf + Vth). Therefore, the threshold voltage Vth is stored in the storage capacitor Cs, and the anodes of the left LED Del and the right LED Der are held as the reference signal Vrf.

[0077] During the third time period TP3, which serves as the hold period, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off due to the first scan signal Sc1, the second scan signal Sc2, and the light emission signal Em at the logic high voltage Vh. Conversely, the seventh transistor T7 is turned on due to the left light emission control signal Ec1 and the right light emission control signal Ecr at the logic low voltage Vl. As a result, the second capacitor electrode of the storage capacitor Cs is held at either the left data signal Vdal or the right data signal Vdar, and the first capacitor electrode of the storage capacitor Cs is held at the sum of the difference between the left data signal Vdal and the reference signal Vrf and the threshold voltage Vth (Vdal - Vrf + Vth), or the sum of the difference between the right data signal Vdar ​​and the reference signal Vrf and the threshold voltage Vth (Vdar - Vrf + Vth). Furthermore, the anode of the left light-emitting diode Del and the anode of the right light-emitting diode Der are held at the reference signal Vrf.

[0078] During the fourth period TP4, which is the light-emitting period, the second transistor T2, the fifth transistor T5, and the seventh transistor T7 are turned on due to the low logic voltage Vl light-emitting signal Em, the left light-emitting control signal Ec1, and the right light-emitting control signal Ecr. The third transistor T3, the fourth transistor T4, and the sixth transistor T6 are turned off due to the high logic voltage Vh first scan signal Sc1 and the second scan signal Sc2. The reference signal Vrf is applied to the third node N3. As a result, a current proportional to the square of the value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs ((Vdal-Vrf+Vth-Vdd)-Vth=Vdal-Vrf-Vdd or (Vdar-Vrf+Vth-Vdd)-Vth=Vdar-Vrf-Vdd) flows through the first transistor T1, and the left light-emitting diode Del and the right light-emitting diode Der emit light with a brightness corresponding to the current flowing through the first transistor T1.

[0079] The off section corresponding to the logic high voltage Vh of the left light emission control signal Ec1 and the right light emission control signal Ecr can be defined as part of the fourth time period TP4. The width of the off section of the left light emission control signal Ec1 and the width of the off section of the right light emission control signal Ecr can be changed independently. By independently changing the width of the off section, the brightness of the light emitted from the left light emission diode Del and the brightness of the light emitted from the right light emission diode Der can be adjusted independently.

[0080] For example, the duty cycle can be defined as the ratio of the on section to the sum of the off section and the on section, and by setting the duty cycles of the left emission control signal Ec1 and the right emission control signal Ecr to approximately 50% and approximately 25%, respectively, the brightness of the left image caused by the left sub-pixel SP1 can be adjusted to twice the brightness of the right image caused by the right sub-pixel SPr.

[0081] Despite Figure 2 In one implementation, each of the left sub-pixel SP1 and the right sub-pixel SPr has a 7T1C structure (which has seven transistors and a storage capacitor), but in another implementation, each of the left sub-pixel SP1 and the right sub-pixel SPr may have one of a 4T1C structure (which has four transistors and a storage capacitor), an 8T1C structure (which has eight transistors and a storage capacitor), or a 9T1C structure (which has nine transistors and a storage capacitor).

[0082] The planar and cross-sectional structures of the left sub-pixel SP1 and the right sub-pixel SPr of the dual-view display device 110 will be illustrated with reference to the accompanying drawings.

[0083] Figure 4 This is a plan view showing the left and right sub-pixels of a dual-view display device according to a first embodiment of the present invention, and Figure 5 This is a cross-sectional view showing the left and right sub-pixels of a dual-view display device according to a first embodiment of the present invention.

[0084] exist Figure 4 According to the first embodiment of the present invention, the gate line GL for transmitting the first scan signal Sc1, the gate line GL for transmitting the light emission signal Em, the gate line GL for transmitting the second scan signal Sc2, the reference line RL for transmitting the reference signal Vrf, and the gate line GL for transmitting the second scan signal Sc2 are arranged sequentially in the horizontal direction, and the power line PL for transmitting the high-level signal Vdd is arranged in each of the left sub-pixel SP1 and the right sub-pixel SPr of the dual-view display device 110 in the vertical direction.

[0085] The first transistor T1 is connected to the power supply line PL, the second transistor T2 and the fifth transistor T5 are connected to the gate line GL that transmits the light emission signal Em, and the third transistor T3 and the fourth transistor T4 are connected to the gate line GL that transmits the second scan signal Sc2.

[0086] The sixth transistor T6 of the left sub-pixel SP1 is connected to the gate line that transmits the first scan signal Sc1 and the data line DL that transmits the left data signal Vdal. The sixth transistor T6 of the right sub-pixel SPr is connected to the gate line GL that transmits the first scan signal Sc1 and the data line DL that transmits the right data signal Vdar.

[0087] The seventh transistor T7 of the left sub-pixel SP1 is connected to the gate line GL that transmits the left light emission control signal Ec1, and the seventh transistor T7 of the right sub-pixel SPr is connected to the gate line that transmits the right light emission control signal Ecr.

[0088] exist Figure 5 In the substrate 130, a light-shielding pattern 132 is disposed in each of the left sub-pixel SP1 and the right sub-pixel SPr, and a first buffer layer 134 is disposed on the light-shielding pattern 132 over the entire substrate 130.

[0089] The light-shielding pattern 132 can block light incident from the lower part of the substrate 130. For example, the light-shielding pattern 132 may have a single layer or multiple layers of metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0090] The first buffer layer 134 can block moisture or oxygen from penetrating from the outside. For example, the first buffer layer 134 may have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0091] In each of the left sub-pixel SP1 and the right sub-pixel SPr, a semiconductor layer 136 is disposed on the first buffer layer 134 corresponding to the light-shielding pattern 132, and a gate insulating layer 138 is disposed on the semiconductor layer 136 over the entire substrate 130.

[0092] Semiconductor layer 136 includes a channel region with no impurities at its central portion and source and drain regions with impurities on both sides of the channel region. For example, semiconductor layer 136 may include polycrystalline semiconductor materials such as polycrystalline silicon, or oxide semiconductor materials such as indium gallium zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO2), copper oxide (Cu2O), nickel oxide (NiO), indium tin zinc oxide (ITZO), and indium aluminum zinc oxide (IAZO).

[0093] For example, the gate insulating layer 138 may have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0094] In each of the left sub-pixel SP1 and the right sub-pixel SPr, the gate 140 is disposed on the gate insulating layer 138 corresponding to the channel region of the semiconductor layer 136; in each of the left sub-pixel SP1 and the right sub-pixel SPr, a first capacitor electrode 142 separated from the gate 140 is disposed on the gate insulating layer 138, and a first interlayer insulating layer 144 is disposed over the entire substrate 130 on the gate 140 and the first capacitor electrode 142.

[0095] The first capacitor electrode 142 can be connected to the light-shielding pattern 132 through contact holes in the gate insulating layer 138 and the first buffer layer 134.

[0096] The gate 140 and the first capacitor electrode 142 may have the same layers and the same materials. For example, the gate 140 and the first capacitor electrode 142 may have single or multiple layers of metallic materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0097] For example, the first interlayer insulating layer 144 may have a single or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0098] In each of the left sub-pixel SP1 and the right sub-pixel SPr, a second capacitor electrode 146 is disposed on the first interlayer insulating layer 144 corresponding to the first capacitor electrode 142, and a second interlayer insulating layer 148 is disposed on the second capacitor electrode 146 over the entire substrate 130.

[0099] For example, the second capacitor electrode 146 may have a single layer or multiple layers of metallic material, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) and their alloys.

[0100] The first capacitor electrode 142, the first interlayer insulating layer 144, and the second capacitor electrode 146 can constitute a storage capacitor Cs.

[0101] In each of the left sub-pixel SP1 and the right sub-pixel SPr, source and drain electrodes 150 spaced apart from each other are disposed on the second interlayer insulating layer 148, and a first planarization layer 152 is disposed over the source and drain electrodes 150 over the entire substrate 130.

[0102] The source and drain 150 are connected to the source and drain regions of the semiconductor layer 136 through contact holes in the second interlayer insulating layer 148, the first interlayer insulating layer 144 and the gate insulating layer 138, respectively.

[0103] The source and drain 150 may have the same layers and the same materials. For example, the source and drain 150 may have single or multiple layers of metallic materials, such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys.

[0104] For example, the first planarization layer 152 may have a single or multiple layers of organic insulating material, such as photoacryl and benzocyclobutene (BCB).

[0105] Semiconductor layer 136, gate 140, source and drain 150 can form the seventh transistor T7.

[0106] In each of the left sub-pixel SP1 and the right sub-pixel SPr, the connection electrode 154 is disposed on the first planarization layer 152 corresponding to the drain 150, and the second planarization layer 156 is disposed on the connection electrode 154 over the entire substrate 130.

[0107] The connecting electrode 154 is connected to the drain electrode 150 through a contact hole in the first planarization layer 152.

[0108] For example, the connecting electrode 154 may have three layers of metallic materials such as aluminum (Al) and titanium (Ti).

[0109] For example, the second planarization layer 156 may have a single or multiple layers of organic insulating material, such as optical acrylic and benzocyclobutene (BCB).

[0110] In each of the left sub-pixel SP1 and the right sub-pixel SPr, the first electrode 158 is disposed on the second planarization layer 156 corresponding to the connecting electrode 154; and in each of the left sub-pixel SP1 and the right sub-pixel SPr, the embankment layer 160 is disposed on the first electrode 158.

[0111] For example, in each of the left sub-pixel SP1 and the right sub-pixel SPr, a groove may be formed in the top surface of the second planarization layer 156, and the first electrode 158 may be disposed in the groove of the second planarization layer 156.

[0112] The first electrode 158 is connected to the connecting electrode 154 through a contact hole in the second planarization layer 156.

[0113] For example, the first electrode 158 may be an anode and may have a single or multiple layers of transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO), or opaque metallic material such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti) and their alloys.

[0114] The embankment 160 covers the edge portion of the first electrode 158 and has an opening that exposes the central portion of the first electrode 158.

[0115] For example, the dam layer 160 may have a single or multiple layers of organic insulating material, such as optical acrylic and benzocyclobutene (BCB).

[0116] In each of the left sub-pixel SP1 and the right sub-pixel SPr, the light-emitting layer 162 is disposed on the first electrode 158 exposed through the opening of the dam layer 160, and the second electrode 164 is disposed on the light-emitting layer 162 over the entire substrate 130.

[0117] For example, the light-emitting layer 162 may be disposed in the groove of the second planarization layer 156, such that the top surface of the light-emitting layer 162 is flush with the top surface of the second planarization layer 156.

[0118] The light-emitting layer 162 may include a hole auxiliary layer (such as a hole injection layer and a hole transport layer), a light-emitting material layer, and an electron auxiliary layer (such as an electron transport layer and an electron injection layer).

[0119] For example, the second electrode 164 may be a cathode and may have a single or multiple layers of transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO), or semi-transparent or opaque metallic material such as aluminum (Al), silver (Ag), copper (Cu), lead (Pb), magnesium (Mg), molybdenum (Mo), titanium (Ti) and their alloys.

[0120] The first electrode 158, the light-emitting layer 162, and the second electrode 164 of the left sub-pixel SP1 and the right sub-pixel SPr can respectively form the left light-emitting diode Del and the right light-emitting diode Der.

[0121] The first encapsulation layer 166, the second encapsulation layer 168, and the third encapsulation layer 170 are sequentially disposed on the second electrode 164 above the entire substrate 130. The first encapsulation layer 166, the second encapsulation layer 168, and the third encapsulation layer 170 constitute an encapsulation layer to prevent moisture penetration.

[0122] For example, the first encapsulation layer 166 and the third encapsulation layer 170 may have single or multiple layers of inorganic insulating materials, such as silicon oxide (SiO2) and silicon nitride (SiNx); and the second encapsulation layer 168 may include organic insulating materials, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and polyimide resin.

[0123] The second buffer layer 172 is disposed on the third encapsulation layer 170 over the entire substrate 130, and the black matrix 174 is disposed on the second buffer layer 172 in the edge portion of each of the left sub-pixel SP1 and the right sub-pixel SPr.

[0124] The second buffer layer 172 can block moisture or oxygen from penetrating from the outside. For example, the second buffer layer 172 can have a single layer or multiple layers of inorganic insulating material, such as silicon oxide (SiO2) and silicon nitride (SiNx).

[0125] The black matrix 174 prevents interference between light emitted from the light-emitting layer 162 of the left sub-pixel SP1 and the right sub-pixel SPr. For example, the black matrix 174 may include an organic insulating material, such as black resin.

[0126] The third interlayer insulating layer 176 is disposed on the black matrix 174 above the entire substrate 130, and the left lens 178 and the right lens 180 are disposed on the third interlayer insulating layer 176 in the left sub-pixel SP1 and the right sub-pixel SPr, respectively.

[0127] For example, the third interlayer insulation layer 176 may have a single or multiple inorganic insulating material such as silicon oxide (SiO2) and silicon nitride (SiNx), or an organic insulating material such as optical acrylic and benzocyclobutene (BCB).

[0128] The left lens 178 can focus light emitted from the light-emitting layer 162 of the left sub-pixel SP1 along the left direction, and the right lens 180 can focus light emitted from the light-emitting layer 162 of the right sub-pixel SPr along the right direction.

[0129] Although not shown, a third planarization layer of single or multiple organic insulating materials (such as optical acrylic and benzocyclobutene (BCB)) may be disposed over the entire substrate 130 on the left lens 178 and the right lens 180.

[0130] In the dual-view display device 110 according to the first embodiment of the present invention, a seventh transistor T7 is disposed in each of the left sub-pixel SP1 displaying the left image and the right sub-pixel SPr displaying the right image. The seventh transistor T7 of the left sub-pixel SP1 and the seventh transistor T7 of the right sub-pixel SPr are switched according to the independent left light emission control signal Ec1 and the right light emission control signal Ecr, respectively. As a result, by driving the left light emission diode Del and the right light emission diode Del using a dimming method with independent duty cycles, the brightness of the left and right images is independently adjusted and low power consumption is achieved.

[0131] In another embodiment, the light-emitting transistor can be switched based on an independent light-emitting signal.

[0132] Figure 6 This is a circuit diagram showing the left and right sub-pixels of a dual-view display device according to a second embodiment of the present invention. Figure 7 This is a view showing multiple signals of the left and right sub-pixels of a dual-view display device according to a second embodiment of the present invention.

[0133] exist Figure 6In the dual-view display device according to the second embodiment of the present invention, each of the left sub-pixel SP1 and the right sub-pixel SPr of the display panel includes a first transistor T1 to a sixth transistor T6, a storage capacitor Cs, and one of a left light-emitting diode Del and a right light-emitting diode Del.

[0134] Despite Figure 6 In one embodiment, the first transistor T1 to the sixth transistor T6 are positive, but in another embodiment, at least one of the first transistor T1 to the sixth transistor T6 may be negative.

[0135] The first transistor T1, acting as the driving transistor, switches according to the voltage of the first node N1. The gate of the first transistor T1 is connected to the first node N1, the source of the first transistor T1 is connected to the high-level signal (high-level voltage) Vdd, and the drain of the first transistor T1 is connected to the second node N2.

[0136] The second transistor T2, which acts as a light-emitting transistor, is switched according to the left light-emitting signal Em1 or the right light-emitting signal Emr. The gate of the second transistor T2 is connected to the left light-emitting signal Em1 or the right light-emitting signal Emr, the source of the second transistor T2 is connected to the second node N2, and the drain of the second transistor T2 is connected to the fourth node N4.

[0137] The third transistor T3, which acts as a sensing transistor, is switched according to the second scan signal Sc2. The gate of the third transistor T3 is connected to the second scan signal Sc2, the source of the third transistor T3 is connected to the second node N2, and the drain of the third transistor T3 is connected to the first node N1.

[0138] The fourth transistor T4 is switched according to the second scan signal Sc2. The gate of the fourth transistor T4 is connected to the second scan signal Sc2, the source of the fourth transistor T4 is connected to the fourth node N4, and the drain of the fourth transistor T4 is connected to the reference signal (reference voltage) Vrf.

[0139] The fifth transistor T5 is switched according to the left light emission signal Em1 or the right light emission signal Emr. The gate of the fifth transistor T5 is connected to the left light emission signal Em1 or the right light emission signal Emr, the source of the fifth transistor T5 is connected to the third node N3, and the drain of the fifth transistor T6 is connected to the reference signal Vrf.

[0140] The sixth transistor T6, acting as a switching transistor, is switched according to the first scan signal Sc1. The gate of the sixth transistor T6 is connected to the first scan signal Sc1, the source of the sixth transistor T6 is connected to the third node N3, and the drain of the sixth transistor T6 is connected to either the left data signal Vdal or the right data signal Vdar.

[0141] The storage capacitor Cs stores either the left data signal Vdal or the right data signal Vdar ​​and the threshold voltage (Vth) of the first transistor T1. The first capacitor electrode of the storage capacitor Cs is connected to the first node N1, and the second capacitor electrode of the storage capacitor Cs is connected to the third node N3.

[0142] Each of the left LED Del and the right LED Der is connected between the second transistor T2 and the fourth transistor T4 and a low-level signal (low-level voltage) Vss, and emits light with a brightness proportional to the current of the first transistor T1. The anode of each of the left LED Del and the right LED Der is connected to the fourth node N4, and the cathode of each of the left LED Del and the right LED Der is connected to the low-level signal Vss.

[0143] The left lens 178, which is hemispherical or semi-cylindrical in shape and focuses light towards the front along the left direction (see...). Figure 5 The left light-emitting diode Del, located on the left sub-pixel SP1, is used to display the left image to the user, and the right lens 180, in a hemispherical or semi-cylindrical shape, is positioned along the right direction towards the front focusing light (see...). Figure 5 It is set on the right LED Der of the right sub-pixel SPr to display the right image to the user.

[0144] The gate of the first transistor T1, the first capacitor electrode of the storage capacitor Cs, and the drain of the third transistor T3 constitute the first node N1. The drain of the first transistor T1, the source of the second transistor T2, and the source of the third transistor T3 constitute the second node N2. The second capacitor electrode of the storage capacitor Cs, the source of the fifth transistor T5, and the source of the sixth transistor T6 constitute the third node N3. The drain of the second transistor T2 and the anode of the left light-emitting diode Del or the right light-emitting diode Der constitute the fourth node N4.

[0145] In the dual-view display device according to the second embodiment of the present invention, the second transistor T2 of the left sub-pixel SP1 switches according to the left light emission signal Em1 to drive the left light emission diode Del using a dimming method and adjust the brightness of the left image. Furthermore, the second transistor T2 of the right sub-pixel SPr switches according to the right light emission signal Emr to drive the right light emission diode Der using a dimming method and adjust the brightness of the right image.

[0146] As a result, by using a dimming method to independently drive the left LED Del and the right LED Der, the brightness of the left and right images can be adjusted independently.

[0147] exist Figure 7In the dual-view display device according to the second embodiment of the present invention, each of the left sub-pixel SP1 and the right sub-pixel SPr is driven via the first to fourth time periods TP1 to TP4.

[0148] During the first time period TP1, which serves as the initialization period, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on due to the second scan signal Sc2 (logic low voltage Vl), the left LED Em1, and the right LED Emr. Conversely, the sixth transistor T6 is turned off due to the first scan signal Sc1 (logic high voltage Vh). Since the reference signal Vrf is applied to the first node N1, the second node N2, the third node N3, and the fourth node N4, the first and second capacitor electrodes of the storage capacitor Cs, the gate of the first transistor T1, the anode of the left LED Del, and the anode of the right LED Del are initialized by the reference signal Vrf.

[0149] During the second time period TP2, which is the sampling period, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are turned on due to the first scan signal Sc1 and the second scan signal Sc2 of the logic low voltage Vl, and the second transistor T2 and the fifth transistor T5 are turned off due to the left light emission signal Em1 and the right light emission signal Emr of the logic high voltage Vh. The left data signal Vdal or the right data signal Vdar ​​is applied to the third node N3, the high-level signal Vdd is applied to the first node N1, and the reference signal Vrf is applied to the fourth node N4. As a result, the second capacitor electrode of the storage capacitor Cs has the left data signal Vdal or the right data signal Vdar, and the first capacitor electrode of the storage capacitor Cs has the sum of the difference between the left data signal Vdal and the reference signal Vrf and the threshold voltage Vth (Vdal-Vrf+Vth), or the sum of the difference between the right data signal Vdar ​​and the reference signal Vrf and the threshold voltage Vth (Vdar-Vrf+Vth). Therefore, the threshold voltage Vth is stored in the storage capacitor Cs, and the anodes of the left LED Del and the right LED Der are held as the reference signal Vrf.

[0150] During the third time period TP3, which serves as the hold period, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off due to the logic high voltage Vh, the first scan signal Sc1, the second scan signal Sc2, the left light-emitting signal Em1, and the right light-emitting signal Emr. As a result, the second capacitor electrode of the storage capacitor Cs is held at either the left data signal Vdal or the right data signal Vdar, and the first capacitor electrode of the storage capacitor Cs is held at the sum of the difference between the left data signal Vdal and the reference signal Vrf and the threshold voltage Vth (Vdal-Vrf+Vth), or the sum of the difference between the right data signal Vdar ​​and the reference signal Vrf and the threshold voltage Vth (Vdar-Vrf+Vth). Furthermore, the anode of the left light-emitting diode Del and the anode of the right light-emitting diode Der are held at the reference signal Vrf.

[0151] During the fourth period TP4, which is the light-emitting period, the second transistor T2 and the fifth transistor T5 are turned on due to the left light-emitting signal Em1 and the right light-emitting signal Emr at the logic low voltage Vl, and the third transistor T3, the fourth transistor T4, and the sixth transistor T6 are turned off due to the first scan signal Sc1 and the second scan signal Sc2 at the logic high voltage Vh. The reference signal Vrf is applied to the third node N3. As a result, a current proportional to the square of the value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs ((Vdal-Vrf+Vth-Vdd)-Vth=Vdal-Vrf-Vdd or (Vdar-Vrf+Vth-Vdd)-Vth=Vdar-Vrf-Vdd) flows through the first transistor T1, and the left light-emitting diode Del and the right light-emitting diode Der emit light with a brightness corresponding to the current flowing through the first transistor T1.

[0152] The cutoff segment corresponding to the logic high voltage Vh of the left light-emitting signal Em1 and the right light-emitting signal Emr can be defined as part of the fourth time period TP4. The width of the cutoff segment of the left light-emitting signal Em1 and the width of the cutoff segment of the right light-emitting signal Emr can be changed independently, and the brightness of the light emitted from the left light-emitting diode Del and the brightness of the light emitted from the right light-emitting diode Der can be adjusted independently by changing the width of the cutoff segment.

[0153] For example, the duty cycle can be defined as the ratio of the conducting segment to the sum of the cut-off segment and the conducting segment, and by setting the duty cycles of the left emission signal Em1 and the right emission signal Emr to approximately 50% and approximately 25%, respectively, the brightness of the left image caused by the left sub-pixel SP1 can be adjusted to twice the brightness of the right image caused by the right sub-pixel SPr.

[0154] Despite Figure 6In one implementation, each of the left sub-pixel SP1 and the right sub-pixel SPr has a 6T1C structure (which has six transistors and a storage capacitor), but in another implementation, each of the left sub-pixel SP1 and the right sub-pixel SPr may have one of a 3T1C structure (which has three transistors and a storage capacitor), a 7T1C structure (which has seven transistors and a storage capacitor), and an 8T1C structure (which has eight transistors and a storage capacitor).

[0155] In the dual-view display device according to the second embodiment of the present invention, the second transistor T2 of the left sub-pixel SP1 displaying the left image and the second transistor T2 of the right sub-pixel SPr displaying the right image are switched according to the independent left light emission signal Em1 and the right light emission signal Emr, respectively. As a result, by driving the left light emission diode Del and the right light emission diode Der using a dimming method with independent duty cycles, the brightness of the left and right images is independently adjusted and low power consumption is achieved.

[0156] It will be apparent to those skilled in the art that various modifications and variations can be made to this invention without departing from its scope. Therefore, this invention is intended to cover any modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A dual view display apparatus comprising: a display panel including a display area having a left sub-pixel and a right sub-pixel, and a non-display area at a periphery of the display area; a first transistor in each of the left sub-pixel and the right sub-pixel, the first transistor being switched according to a voltage of a first node and connected to a high level signal and a second node; a second transistor in each of the left sub-pixel and the right sub-pixel, the second transistor being switched according to a light emitting signal and connected to the second node and a fourth node; a third transistor in each of the left sub-pixel and the right sub-pixel, the third transistor being switched according to a second scan signal and connected to the first node and the second node; a fourth transistor in each of the left sub-pixel and the right sub-pixel, the fourth transistor being switched according to the second scan signal and connected to the fourth node; a fifth transistor in each of the left sub-pixel and the right sub-pixel, the fifth transistor being switched according to the light emitting signal and connected to a third node and a reference signal; a sixth transistor in each of the left sub-pixel and the right sub-pixel, the sixth transistor being switched according to a first scan signal and connected to the third node; and a seventh transistor in each of the left sub-pixel and the right sub-pixel, the seventh transistor being connected to the fourth node, wherein the seventh transistor of the left sub-pixel and the seventh transistor of the right sub-pixel are switched according to a left light emitting control signal and a right light emitting control signal, respectively. 2.The dual view display apparatus of claim 1, further comprising: a storage capacitor in each of the left sub-pixel and the right sub-pixel, and connected between the first node and the third node; and a left light emitting diode and a right light emitting diode located in the left sub-pixel and the right sub-pixel, respectively, and each of the left light emitting diode and the right light emitting diode being connected between the seventh transistor and a low level signal. 3.The dual view display apparatus of claim 2, wherein a gate of the first transistor, a first capacitor electrode of the storage capacitor, and a drain of the third transistor constitute the first node, wherein a drain of the first transistor, a source of the second transistor, and a source of the third transistor constitute the second node, wherein a second capacitor electrode of the storage capacitor, a source of the fifth transistor, and a source of the sixth transistor constitute the third node, wherein a drain of the second transistor, a source of the fourth transistor, and a source of the seventh transistor constitute the fourth node. ​ ​ 4. The dual-view display device according to claim 1, wherein during a first time period, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the seventh transistor are turned on by a logic low-voltage second scan signal, a light-emitting signal, a left light-emitting control signal, and a right light-emitting control signal, and the sixth transistor is turned off by a logic high-voltage first scan signal. During the second time period, the third, fourth, sixth, and seventh transistors are turned on by a logic low-voltage first scan signal, a second scan signal, a left light emission control signal, and a right light emission control signal, while the second and fifth transistors are turned off by a logic high-voltage light emission signal. During the third time period, the second, third, fourth, fifth, and sixth transistors are turned off by the first and second scan signals and the light emission signal at logic high voltage, while the seventh transistor is turned on by the left and right light emission control signals at logic low voltage. During the fourth time period, the second transistor, the fifth transistor, and the seventh transistor are turned on by a logic low voltage light emission signal, a left light emission control signal, and a right light emission control signal, while the third transistor, the fourth transistor, and the sixth transistor are turned off by a logic high voltage first scan signal and a second scan signal.

5. The dual-view display device according to claim 4, wherein the fourth time period includes a cutoff segment corresponding to a logic high voltage of the left light emission control signal and the right light emission control signal. The width of the cutoff segment of the left light emission control signal and the width of the cutoff segment of the right light emission control signal are changed independently.

6. A dual-view display device, comprising: The display panel includes a display area having a left sub-pixel and a right sub-pixel, and a non-display area surrounding the display area; A first transistor, in each of the left and right sub-pixels, switches according to the voltage of a first node and is connected to a high-level signal and a second node; A second transistor, in each of the left and right sub-pixels, is connected to the second node and the fourth node; A third transistor, in each of the left and right sub-pixels, is switched and connected to the first and second nodes according to a second scan signal; A fourth transistor, in each of the left and right sub-pixels, is switched and connected to the fourth node according to the second scan signal; A fifth transistor, in each of the left and right sub-pixels, is connected to a third node and a reference signal; as well as A sixth transistor, in each of the left and right sub-pixels, switches and connects to the third node according to a first scan signal. The second transistor of the left sub-pixel and the second transistor of the right sub-pixel switch according to the left light emission signal and the right light emission signal, respectively.

7. The dual-view display device according to claim 6, further comprising: A storage capacitor is provided in each of the left and right sub-pixels, and the storage capacitor is connected between the first node and the third node. as well as A left light-emitting diode and a right light-emitting diode are respectively located in the left sub-pixel and the right sub-pixel, and each of the left light-emitting diode and the right light-emitting diode is connected between the second transistor and the fourth transistor and a low-level signal.

8. The dual-view display device according to claim 7, wherein the gate of the first transistor, the first capacitor electrode of the storage capacitor, and the drain of the third transistor constitute the first node. The drain of the first transistor, the source of the second transistor, and the source of the third transistor constitute the second node. The second capacitor electrode of the storage capacitor, the source of the fifth transistor, and the source of the sixth transistor constitute the third node. The drain of the second transistor and the source of the fourth transistor constitute the fourth node.

9. The dual-view display device according to claim 6, wherein during a first time period, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are turned on by a logic low-voltage second scan signal, a left light-emitting signal, and a right light-emitting signal, and the sixth transistor is turned off by a logic high-voltage first scan signal. During the second time period, the third, fourth, and sixth transistors are turned on by a first and second scan signal with logic low voltage, while the second and fifth transistors are turned off by a left and right light-emitting signal with logic high voltage. During the third time period, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are turned off by the first scan signal, the second scan signal, the left light-emitting signal, and the right light-emitting signal, all of which are at logic high voltage. During the fourth time period, the second transistor and the fifth transistor are turned on by the left and right light-emitting signals with logic low voltage, while the third transistor, the fourth transistor, and the sixth transistor are turned off by the first and second scan signals with logic high voltage.

10. The dual-view display device according to claim 9, wherein the fourth time period includes a cutoff segment corresponding to a logic high voltage of the left light-emitting signal and the right light-emitting signal. The width of the cutoff segment of the left light-emitting signal and the width of the cutoff segment of the right light-emitting signal are changed independently.

Images