Viewing angle switchable display device

Abstract

A view-switching display device includes: a first transistor connected to a second node; a second transistor connected to the second node and a fourth node; a third transistor connected to the fourth node and a fifth node; a fourth transistor connected to the fourth node and a sixth node; a fifth transistor connected to the first node and the second node; a sixth transistor connected to the fifth node; a seventh transistor connected to the sixth node; an eighth transistor connected to the third node; a ninth transistor connected to the third node; a first light-emitting diode and a second light-emitting diode connected to the fifth node and the sixth node; a tenth transistor connected to the first light-emitting diode and the second light-emitting diode; and an eleventh transistor connected to the first light-emitting diode and the second light-emitting diode.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0171185, filed on November 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device, and more specifically, to a view-switching display device, wherein a reference signal or a low-level signal is selectively applied to a selection transistor connected to a light-emitting diode. Background Technology

[0003] In recent years, with the emergence of an information-oriented society, interest in information displays for processing and displaying large amounts of information, as well as the demand for portable information media, has increased. Furthermore, with the growing demand for portable information media, various thin and light flat panel display devices have been developed and are gaining attention.

[0004] Among various flat panel display devices, organic light-emitting diode (OLED) displays are emission-type devices that do not include backlight units used in non-emission devices such as liquid crystal displays (LCDs). As a result, OLED displays offer advantages in viewing angle, contrast ratio, and power consumption, making them applicable to a wide range of fields.

[0005] Specifically, OLED displays are already being used in vehicle dashboards. In the automotive field, a viewing angle-switching OLED display has been researched and developed, allowing drivers and passengers to selectively view images.

[0006] In OLED displays with switchable viewing angles, because a subpixel is divided into an area for a wide-viewing-angle LED and an area for a narrow-viewing-angle LED, the capacitance of the LED is reduced, and the LED emits light even with a relatively low voltage. As a result, the brightness of blacks increases and the contrast decreases. Summary of the Invention

[0007] Therefore, this disclosure relates to a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0008] More specifically, this disclosure provides a view-switching display device in which the emission of a light-emitting diode is blocked during periods other than the emission period to prevent an increase in the brightness of black, and contrast is improved by connecting a selection transistor to the light-emitting diode and selectively applying a reference signal or a low-level signal to the light-emitting diode.

[0009] Additional features and advantages of this disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of this disclosure. These and other advantages of this disclosure will be realized and obtained by means of the structures particularly pointed out in the written description and claims and the accompanying drawings.

[0010] To achieve these and other advantages, and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a view-switching display device includes sub-pixels. The sub-pixels include: a first transistor, which switches according to a voltage of a first node and is connected to a high-level signal and a second node; a second transistor, which switches according to a first transmission signal and is connected to the second node and a fourth node; a third transistor, which switches according to a second transmission signal and is connected to the fourth node and a fifth node; a fourth transistor, which switches according to a third transmission signal and is connected to the fourth node and a sixth node; a fifth transistor, which switches according to a second scan signal and is connected to the first node and the second node; a sixth transistor, which switches according to the second scan signal and is connected to the fifth node and a reference signal; and a seventh transistor, which... The transistor is switched according to the second scan signal and connected to the sixth node and the reference signal; the eighth transistor is switched according to the first transmit signal and connected to the third node and the reference signal; the ninth transistor is switched according to the first scan signal and connected to the third node and the data signal; the first light-emitting diode and the second light-emitting diode are respectively connected to the fifth node and the sixth node; the tenth transistor is connected to at least one of the first light-emitting diode and the second light-emitting diode and the reference signal; and the eleventh transistor is connected to at least one of the first light-emitting diode and the second light-emitting diode and a low-level signal.

[0011] It should be understood that the foregoing general description and the following detailed description are illustrative and intended to provide a further explanation of the claimed disclosure. Attached Figure Description

[0012] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated into and form part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0013] In the attached diagram:

[0014] Figure 1 This is a view illustrating a view-switching display device according to a first embodiment of the present disclosure;

[0015] Figure 2 This is a circuit diagram illustrating the sub-pixels of a view-switching display device according to a first embodiment of the present disclosure;

[0016] Figure 3 This is a view showing multiple signals of sub-pixels of a view-switching display device according to a first embodiment of the present disclosure;

[0017] Figures 4A to 4D This is a view showing the operating state of a sub-pixel of a view-switchable display device according to a first embodiment of the present disclosure;

[0018] Figure 5A This is a view showing the first gate driving unit and the second gate driving unit of a view-switchable display device according to a first embodiment of the present disclosure;

[0019] Figure 5B This is a view showing multiple signals of a selection block of a view-switchable display device according to a first embodiment of the present disclosure;

[0020] Figure 5C This is a view showing the input and output signals of the generation portion of the selection block of the view-switching display device according to a first embodiment of the present disclosure;

[0021] Figure 6A This is a view showing the first gate driving unit and the second gate driving unit of a view-switchable display device according to a second embodiment of the present disclosure; and

[0022] Figure 6B This is a view showing multiple signals of a selection block of a view-switchable display device according to a second embodiment of the present disclosure. Detailed Implementation

[0023] The advantages and features of this disclosure and its implementation methods will be illustrated by the exemplary aspects described below with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the exemplary aspects set forth herein. Rather, these exemplary aspects are provided so that this disclosure may be thorough and complete, assisting those skilled in the art in fully understanding the scope of this disclosure. Furthermore, this disclosure is limited only by the scope of the claims.

[0024] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings to describe various exemplary aspects of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the illustrations in the drawings. Unless otherwise stated, the same reference numerals refer to the same elements throughout the specification.

[0025] In the following description, where a detailed description of a known function or configuration may unnecessarily obscure a feature or aspect of this disclosure, a detailed description of such a known function or configuration may be omitted, or a brief description may be provided.

[0026] When using terms such as “including,” “having,” or “containing,” one or more additional elements may be added unless a term such as “only” is used. Elements described in the singular are intended to include multiple elements, and vice versa, unless the context explicitly indicates otherwise.

[0027] When constructing features, features should be interpreted as including a range of errors or tolerances, even if no explicit description of such a range of errors or tolerances is provided.

[0028] When describing positional relationships, such as using terms like "on top of," "above," "below," "above," "below," "next to," or "next to" to describe the positional relationship between two parts, one or more other parts may be located between the two parts unless more restrictive terms such as "immediately," "directly," or "nearly" are used. For example, if an element or layer is set "on" another element or layer, a third layer or element may be inserted between them.

[0029] Although the terms “first,” “second,” A, B, (a), (b), etc., may be used herein to refer to various elements, these elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0030] The term "at least one" should be understood to include all combinations of one or more related elements. For example, the term "at least one of the first element, the second element, and the third element" can include all combinations of the first element, the second element, and the third element, as well as two or more elements of the first element, the second element, or the third element.

[0031] The term "display device" can include display devices in a narrow sense, such as liquid crystal modules (LCMs), organic light-emitting diode (OLED) modules, and quantum dot (QD) modules, which include a display panel and driving units for driving the display panel. Furthermore, the term "display device" can include complete products (or final products) that include LCMs, OLED modules, and QD modules, such as notebook computers, televisions, computer monitors, equipment display devices including automotive display devices or other shapes besides vehicles, and mobile electronic devices such as smartphones or electronic pads.

[0032] Therefore, the display device disclosed herein may include application products or setting devices for end-user devices, including LCMs, OLED modules and QD modules, as well as display devices in a narrow sense, such as LCMs, OLED modules and QD modules.

[0033] Depending on the context, an LCM, OLED, and QD module having a display panel and a driving unit can be described as a "display device," and an electronic device comprising a complete product including an LCM, OLED, and QD module can be described as a "setting device." For example, a display device in a narrow sense can include a liquid crystal display panel, organic light-emitting diodes and quantum dots, and a source printed circuit board (PCB) for a control unit for driving the display panel, and a setting device can also include a setting PCB electrically connected to the source PCB for controlling the setting control unit of the entire setting device.

[0034] The display panel disclosed herein may include all kinds of display panels such as liquid crystal display panels, organic light-emitting diode display panels, quantum dot display panels, and electroluminescent display panels. The display panel disclosed herein is not limited to a specific display panel having a bezel curvature for a flexible substrate for an organic light-emitting diode display panel and a lower backplate support. The shape or size of the display panel used in the display device of this disclosure is not limited thereto.

[0035] For example, when the display panel is an organic light-emitting diode (OLED) display panel, the display panel may include multiple gate lines, multiple data lines, and sub-pixels located at the intersection regions of the multiple gate lines and multiple data lines. The display panel may include an array of thin-film transistors having elements for selectively applying voltage to each sub-pixel, an emitter layer on the array, and an encapsulation substrate or encapsulation portion covering the emitter layer. The encapsulation portion may protect the thin-film transistors and emitter layer from external influences and may prevent or at least reduce the penetration of moisture or oxygen into the emitter layer. Furthermore, the emitter layer on the array may include an inorganic light-emitting layer, such as a nanoscale material layer or quantum dots.

[0036] The thin-film transistors disclosed herein may include one of oxide thin-film transistors, amorphous silicon thin-film transistors, and low-temperature polycrystalline silicon thin-film transistors.

[0037] Features of the various embodiments of this disclosure may be coupled partially or completely to each other or combined with each other. As will be fully appreciated by those skilled in the art, they can be technically linked and operated in various ways. Aspects may be performed independently of each other or in association with each other in various combinations.

[0038] In the following, a display device according to various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, wherein the effect on the oxide semiconductor layer of the thin-film transistor in the driving element portion is reduced by shielding light emitted and transmitted from the sub-pixels and / or light input from the outside.

[0039] Figure 1 This is a view illustrating a view-switching display device according to a first embodiment of the present disclosure. While the display device may be an organic light-emitting diode (OLED) display device, it is not limited thereto. For example, the display device may be a quantum dot display device, a micro-light-emitting diode (LED) display device, or a miniature light-emitting diode (LED) display device.

[0040] exist Figure 1 In the first embodiment of the present disclosure, the view-switching display device 110 includes a timing control unit 120 (e.g., a circuit), a data driving unit 122 (e.g., a circuit), first and second gate driving units 124 and 126 (e.g., circuits), and a display panel 128.

[0041] The timing control unit 120 uses the image signal IS and multiple timing signals to generate image data RGB, data control signal DCS, and gate control signal GCS. The timing signals include a data enable signal DE, a horizontal synchronization signal HSY, a vertical synchronization signal VSY, and a clock signal CLK transmitted from an external system such as a graphics card or a television system.

[0042] The timing control unit 120 transmits the image data RGB and the data control signal DCS to the data driving unit 122, and transmits the gate control signal GCS to the first and second gate driving units 124 and 126.

[0043] Data drive unit 122 uses image data RGB and data control signal DCS transmitted from timing control unit 120 to generate data signal (data voltage) Vda. Figure 2 And apply the data signal Vda to the data line DL of the display panel 128.

[0044] The first and second gate drive units 124 and 126 use the gate control signal GCS transmitted from the timing control unit 120 to generate gate signals (gate voltages) Sc1, Sc2, Em1, Em2, Em3, Se1, and Se2. Figure 2 And apply gate signals Sc1, Sc2, Em1, Em2, Em3, Se1 and Se2 to the gate line GL of the display panel 128.

[0045] The first and second gate driving units 124 and 126 may have gate types in a panel (GIP) to be formed in the non-display area NDA of the substrate of the display panel 128 having gate lines GL, data lines DL and pixels P.

[0046] Although Figure 1 In the first embodiment, the first and second gate driving units 124 and 126 are disposed in two side portions of the display panel 128, but in another embodiment, a gate driving unit may be disposed in one side portion of the display panel 128.

[0047] Display panel 128 includes a display area DA located in its central portion and a non-display area NDA surrounding the display area DA. Display panel 128 uses gate signals Sc1, Sc2, Em1, Em2, Em3, Se1, and Se2, and a data signal Vda to display images. For displaying images, display panel 128 includes multiple pixels P in the display area DA, multiple gate lines GL, and multiple data lines DL.

[0048] Each of the plurality of pixels P includes first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4. Gate line GL and data line DL intersect each other to define the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4, and each of the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 is connected to gate line GL and data line DL.

[0049] For example, the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 can correspond to red, green, blue, and white, respectively.

[0050] Despite Figure 1 In a first embodiment, a pixel P exemplarily includes first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4, but in another embodiment, a pixel P may include first, second, and third sub-pixels SP1, SP2, and SP3 corresponding to red, green, and blue, respectively.

[0051] When the viewing angle switchable display device 110 is an organic light-emitting diode (OLED) display device, each of the first, second, third, and fourth sub-pixels SP1, SP2, SP3, and SP4 may include multiple transistors, such as switching transistors, driving transistors and sensing transistors, storage capacitors, and light-emitting diodes.

[0052] The structure of the sub-pixels of the view-switching display device 110 will be described with reference to the accompanying drawings.

[0053] Figure 2 This is a circuit diagram illustrating a sub-pixel of a view-switching display device according to a first embodiment of the present disclosure.

[0054] exist Figure 2 In the first embodiment of the present disclosure, each of the first, second, third and fourth sub-pixels SP1, SP2 and SP3 and SP4 of the display panel 128 of the view-switching display device 110 includes first to eleventh transistors T1 to T11, a storage capacitor Cs and first and second light-emitting diodes De1 and De2.

[0055] Despite Figure 2 In the first embodiment, the first to eleventh transistors T1 to T11 have positive types, but in another embodiment, at least one of the first to eleventh transistors T1 to T11 may have negative types.

[0056] The first transistor T1, acting as the driving transistor, switches according to the voltage of the first node N1. The gate electrode of the first transistor T1 is connected to the first node N1, the source electrode of the first transistor T1 is connected to the high-level signal (high-level voltage) Vdd, and the drain electrode of the first transistor T1 is connected to the second node N2.

[0057] The second transistor T2, which acts as the emitter transistor, is switched according to the first emitter signal Em1. The gate electrode of the second transistor T2 is connected to the first emitter signal Em1, the source electrode of the second transistor T2 is connected to the second node N2, and the drain electrode of the second transistor T2 is connected to the fourth node N4.

[0058] The third transistor T3, which acts as the emitter transistor, is switched according to the second emitter signal Em2. The gate electrode of the third transistor T3 is connected to the second emitter signal Em2, the source electrode of the third transistor T3 is connected to the fourth node N4, and the drain electrode of the third transistor T3 is connected to the fifth node N5.

[0059] The fourth transistor T4, which acts as the emitter transistor, is switched according to the third emitter signal Em3. The gate electrode of the fourth transistor T4 is connected to the third emitter signal Em3, the source electrode of the fourth transistor T4 is connected to the fourth node N4, and the drain electrode of the fourth transistor T4 is connected to the sixth node N6.

[0060] The fifth transistor T5, which acts as a sensing transistor, is switched according to the second scan signal Sc2. The gate electrode of the fifth transistor T5 is connected to the second scan signal Sc2, the source electrode of the fifth transistor T5 is connected to the second node N2, and the drain electrode of the fifth transistor T5 is connected to the first node N1.

[0061] The sixth transistor T6 is switched according to the second scan signal Sc2. The gate electrode of the sixth transistor T6 is connected to the second scan signal Sc2, the source electrode of the sixth transistor T6 is connected to the fifth node N5, and the drain electrode of the sixth transistor T6 is connected to the reference signal (reference voltage) Vrf.

[0062] The seventh transistor T7 is switched according to the second scan signal Sc2. The gate electrode of the seventh transistor T7 is connected to the second scan signal Sc2, the source electrode of the seventh transistor T7 is connected to the sixth node N6, and the drain electrode of the seventh transistor T7 is connected to the reference signal Vrf.

[0063] The eighth transistor T8 is switched according to the first transmit signal Em1. The gate electrode of the eighth transistor T8 is connected to the first transmit signal Em1, the source electrode of the eighth transistor T8 is connected to the third node N3, and the drain electrode of the eighth transistor T8 is connected to the reference signal Vrf.

[0064] The ninth transistor T9, acting as a switching transistor, is switched according to the first scan signal Sc1. The gate electrode of the ninth transistor T9 is connected to the first scan signal Sc1, the source electrode of the ninth transistor T9 is connected to the third node N3, and the drain electrode of the ninth transistor T9 is connected to the data signal Vda.

[0065] The tenth transistor T10, acting as the selection transistor, is switched according to the first selection signal Se1. The gate electrode of the tenth transistor T10 is connected to the first selection signal Se1, the source electrode of the tenth transistor T10 is connected to the seventh node N7, and the drain electrode of the tenth transistor T10 is connected to the reference signal Vrf.

[0066] The eleventh transistor T11, acting as the selection transistor, is switched according to the second selection signal Se2. The gate electrode of the eleventh transistor T11 is connected to the second selection signal Se2, the source electrode of the eleventh transistor T11 is connected to the seventh node N7, and the drain electrode of the eleventh transistor T11 is connected to the low-level signal (low-level voltage) Vss.

[0067] For example, the first selection signal Se1 and the second selection signal Se2 can be signals that are opposite in phase to each other.

[0068] The storage capacitor Cs stores the data signal Vda and the threshold voltage (Vth) of the first transistor T1. The first capacitor electrode of the storage capacitor Cs is connected to the first node N1, and the second capacitor electrode of the storage capacitor Cs is connected to the third node N3.

[0069] The first light-emitting diode De1 is connected between the fifth node N5 and the low-level signal (low-level voltage) Vss, and emits light with a brightness proportional to the current of the first transistor T1. The anode of the first light-emitting diode De1 is connected to the fifth node N5, and the cathode of the first light-emitting diode De1 is connected to the low-level signal Vss.

[0070] The second light-emitting diode De2 is connected between the sixth and seventh nodes N6 and N7, and emits light with a brightness proportional to the current of the first transistor T1. The anode of the second light-emitting diode De2 is connected to the sixth node N6, and the cathode of the second light-emitting diode De2 is connected to the seventh node N7.

[0071] The first light-emitting diode De1 is provided with a semi-cylindrical lens that focuses light along the up and down direction but not along the left and right direction, so as to display a wide-viewing-angle image to the left and right users, and the second light-emitting diode De2 is provided with a hemispherical lens that focuses light along the up, down, left and right directions, so as to display a narrow-viewing-angle image to one of the left and right users.

[0072] The gate electrode of the first transistor T1, the first capacitor electrode of the storage capacitor Cs, and the drain electrode of the fifth transistor T5 constitute the first node N1. The drain electrode of the first transistor T1, the source electrode of the second transistor T2, and the source electrode of the fifth transistor T5 constitute the second node N2. The second capacitor electrode of the storage capacitor Cs, the source electrode of the eighth transistor T8, and the source electrode of the ninth transistor T9 constitute the third node N3. The drain electrode of the second transistor T2, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4 constitute the fourth node N4. The drain electrode of the third transistor T3, the source electrode of the sixth transistor T6, and the anode of the first light-emitting diode De1 constitute the fifth node N5. The drain electrode of the fourth transistor T4, the source electrode of the seventh transistor T7, and the anode of the second light-emitting diode De2 constitute the sixth node N6. The cathode of the second light-emitting diode De2, the source electrode of the tenth transistor T10, and the source electrode of the eleventh transistor T11 constitute the seventh node N7.

[0073] In the view-switching display device 110 according to the first embodiment of the present disclosure, tenth and eleventh transistors T10 and T11, which are switched according to a first selection signal Se1 and a second selection signal Se2 respectively, are connected to the cathode of the second light-emitting diode De2, and the tenth transistor T10 is switched during a first time period TP1, which is an initialization period. Figure 3 ), and the second sampling period TP2 ( Figure 3 ) and the third period TP3 as the holding period ( Figure 3 During this period, the diode is turned on to connect the cathode of the second LED De2 to the reference signal Vrf. Since the anode and cathode of the second LED De2 have the same potential, emission of the second LED De2 is prevented, and an increase in the brightness of black is prevented.

[0074] Furthermore, the eleventh transistor T11 is in the fourth period TP4, which is the emission period ( Figure 3 During this period, the second LED De2 is turned on to connect its cathode to the low-level signal Vss. As a result, the second LED De2 emits light corresponding to the brightness of the data signal Vda to display an image with a narrow viewing angle.

[0075] Despite Figure 2 In the first embodiment, a sub-pixel has an 11T1C structure with eleven transistors and a storage capacitor. However, in another embodiment, a sub-pixel may have one of an 8T1C structure, a 12T1C structure, and a 13T1C structure, wherein the 8T1C structure has eight transistors and a storage capacitor, the 12T1C structure has twelve transistors and a storage capacitor, and the 13T1C structure has thirteen transistors and a storage capacitor.

[0076] Despite Figure 2 In the first embodiment, the tenth and eleventh transistors T10 and T11 are exemplarily connected to the second light-emitting diode De2, but the tenth and eleventh transistors T10 and T11 may be connected to each of the first and second light-emitting diodes De1 and De2 to prevent abnormal emission, or in another embodiment, the tenth and eleventh transistors T10 and T11 may be connected to the first light-emitting diode De1 to prevent abnormal emission of the first light-emitting diode De1.

[0077] The operation of the sub-pixels of the view-switching display device 110 will be described with reference to the accompanying drawings.

[0078] Figure 3 This is a view illustrating multiple signals of sub-pixels of a view-switching display device according to a first embodiment of the present disclosure, and Figures 4A to 4D This is a view showing the operating state of a sub-pixel of a display device that can be switched from a perspective according to a first embodiment of the present disclosure.

[0079] exist Figure 3 In the first embodiment of the present disclosure, each of the first, second, third and fourth sub-pixels SP1, SP2, SP3 and SP4 of the view-switching display device 110 is driven to experience the first to fourth time periods TP1 to TP4.

[0080] exist Figure 3 and Figure 4A During the first time period TP1, which serves as the initialization period, transistors T2, T5, T6, T7, T8, and T10 are turned on due to the second scan signal Sc2, the first transmit signal Em1, the third transmit signal Em3, and the first selection signal Se1 at a logic low voltage Vl. Conversely, transistors T3, T9, and T11 are turned off due to the first scan signal Sc1, the second transmit signal Em2, and the second selection signal Se2 at a logic high voltage Vh. Since a reference signal Vrf is applied to nodes N1, N2, N3, N4, N5, N6, and N7, transistor T1 is turned off, and the first and second capacitor electrodes of storage capacitor Cs, the gate electrode of transistor T1, the anode of first LED De1, and the anode and cathode of second LED De2 are initialized by the reference signal Vrf.

[0081] Here, a reference signal Vrf is applied to the anode and cathode of the second light-emitting diode De2 to prevent the second light-emitting diode De2 from emitting.

[0082] exist Figure 3 and Figure 4B During the second time period TP2, which is the sampling period, transistors T4, T5, T6, T7, T9, and T10 are turned on due to the first scan signal Sc1, the second scan signal Sc2, the third transmit signal Em3, and the first selection signal Se1 at the logic low voltage Vl. Conversely, transistors T2, T3, T8, and T11 are turned off due to the first transmit signal Em1, the second transmit signal Em2, and the second selection signal Se2 at the logic high voltage Vh. Data signal Vda is applied to the third node N3, and reference signal Vrf is applied to the fifth node N5, the sixth node N6, and the seventh node N7. As a result, first transistor T1 is turned on, the second capacitor electrode of storage capacitor Cs has data signal Vda, and the first capacitor electrode of storage capacitor Cs has the sum of the difference between data signal Vda and reference signal Vrf and the threshold voltage Vth (Vda - Vrf + Vth). Therefore, the threshold voltage Vth is stored in the storage capacitor Cs, and the anode of the first light-emitting diode De1 and the anode and cathode of the second light-emitting diode De2 are kept as the reference signal Vrf.

[0083] exist Figure 3 and Figure 4C During the third time period TP3, which serves as the holding period, the fourth transistor T4 and the tenth transistor T10 are turned on due to the third transmit signal Em3 and the first selection signal Se1 at the logic low voltage Vl, and the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 are turned off due to the first scan signal Sc1, the second scan signal Sc2, the first transmit signal Em1, the second transmit signal Em2, and the second selection signal Se2 at the logic high voltage Vh. As a result, the reference signal Vrf is applied to the seventh node N7, the second capacitor electrode of the storage capacitor Cs is held at the data signal Vda, and the first capacitor electrode of the storage capacitor Cs is held at the sum of the difference between the data signal Vda and the reference signal Vrf and the threshold voltage Vth (Vda-Vrf+Vth). Therefore, the threshold voltage Vth is stored in the storage capacitor Cs, and the anode and cathode of the second light-emitting diode De2 are held at the reference signal Vrf.

[0084] exist Figure 3 and Figure 4DDuring the fourth transmission period TP4, due to the logic low voltage Vl, the first transmission signal Em1, the third transmission signal Em3, and the second selection signal Se2 turn on the second transistor T2, the fourth transistor T4, the eighth transistor T8, and the eleventh transistor T11. Conversely, due to the logic high voltage Vh, the first scan signal Sc1, the second scan signal Sc2, the second transmission signal Em2, and the first selection signal Se1 turn off the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10. As a result, the reference signal Vrf is applied to the third node N3, and a current proportional to the square of the value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs ((Vda-Vrf+Vth-Vdd)-Vth=Vda-Vrf-Vdd) flows through the first transistor T1. The second light-emitting diode De2 emits light with a brightness corresponding to the current flowing through the first transistor T1.

[0085] In the view-switching display device 110 according to the first embodiment of this disclosure, a tenth transistor T10 connected to a reference signal Vrf and an eleventh transistor T11 connected to a low-level signal Vss are connected to the cathode of at least one of the first light-emitting diodes De1 and De2. During a first time period TP1, a second time period TP2, and a third time period TP3 corresponding to an initialization time period, a sampling time period, and a hold time period, the reference signal Vrf is supplied to the cathode of at least one of the first light-emitting diodes De1 and De2. Since emission from at least one of the first light-emitting diodes De1 and De2 is prevented, an increase in black brightness is prevented, and contrast is improved.

[0086] During the fourth period TP4 corresponding to the emission period, at least one of the first light-emitting diodes De1 and De2 can emit light normally because a low-level signal Vss is supplied to the cathode of at least one of the first light-emitting diodes De1 and De2.

[0087] The generation of the first selection signal Se1 and the second selection signal Se2 in the first gate driving unit 124 and the second gate driving unit 126 of the view-switching display device 110 will be described with reference to the accompanying drawings.

[0088] Figure 5A This is a view showing the first and second gate driving units of a view-switching display device according to a first embodiment of the present disclosure. Figure 5B This is a view showing multiple signals of a selection block of a view-switchable display device according to a first embodiment of the present disclosure, and Figure 5CThis is a view showing the input and output signals of the generation portion of the selection block of the view-switching display device according to a first embodiment of the present disclosure.

[0089] exist Figure 5A In the first embodiment of the present disclosure, at least one of the first gate driving unit 124 and the second gate driving unit 126 of the view-switching display device 110 includes a first scan block Bsc1, a second scan block Bsc2, a first emission block Bem1, and a selection block Bse.

[0090] The first scan block Bsc1 uses the first start signal VST1, the (n-1)th first clock signal CLK1(n-1), the nth first clock signal CLK1(n), and the (n+1)th first clock signal CLK1(n+1) to generate the first scan signal Sc1, and transmits the first scan signal Sc1 to the display panel 128 and the selection block Bse.

[0091] The second scan block Bsc2 uses the second start signal VST2, the (n-1)th second clock signal CLK2(n-1), the nth second clock signal CLK2(n), and the (n+1)th second clock signal CLK2(n+1) to generate the second scan signal Sc2, and transmits the second scan signal Sc2 to the display panel 128 and the selection block Bse.

[0092] In another embodiment, the (n-1)th second clock signal CLK2(n-1), the nth second clock signal CLK2(n), and the (n+1)th second clock signal CLK2(n+1) can be the same as the (n-1)th first clock signal CLK1(n-1), the nth first clock signal CLK1(n), and the (n+1)th first clock signal CLK1(n+1), respectively.

[0093] The first transmitting block Bm1 uses the transmission start signal VSTe, the nth transmission clock signal CLKe(n), and the (n+1)th transmission clock signal CLKe(n+1) to generate the first transmission signal Em1, and transmits the first transmission signal Em1 to the display panel 128 and the selection block Bse.

[0094] In another embodiment, the nth transmit clock signal CLKe(n) and the (n+1)th transmit clock signal CLKe(n+1) can be the same as the first first clock signal CLK1(1) and the second first clock signal CLK1(2), respectively.

[0095] The selection block Bse uses the first scan signal Sc1, the second scan signal Sc2 and the first transmit signal Em1 to generate the first selection signal Se1 and the second selection signal Se2, and transmits the first selection signal Se1 and the second selection signal Se2 to the display panel 128.

[0096] The selection block Bse includes a generation part Gen that generates a second selection signal Se2 using a first scan signal Sc1, a second scan signal Sc2, and a first transmit signal Em1, and an inverted part Inv that generates a first selection signal Se1 using the second selection signal Se2.

[0097] For example, the first selection signal Se1 and the second selection signal Se2 can be inverted signals, and the inverted part Inv can be an inverter.

[0098] Although not shown, at least one of the first gate driving unit 124 and the second gate driving unit 126 may further include a second transmitting block for generating the second transmitting signal Em2 and a third transmitting block for generating the third transmitting signal Em3.

[0099] exist Figure 5B and Figure 5C During the first time period TP1, the Gen part receives the first scan signal Sc1 of logic high voltage Vh, the second scan signal Sc2 of logic low voltage Vl, and the first transmit signal Em1 of logic low voltage Vl, and outputs the second selection signal Se2 of logic high voltage Vh. The Inverting part Inv receives the second selection signal Se2 of logic high voltage Vh and outputs the first selection signal Se1 of logic low voltage Vl.

[0100] During the second time period TP2, the Gen part receives the first scan signal Sc1 of logic low voltage Vl, the second scan signal Sc2 of logic low voltage Vl, and the first transmit signal Em1 of logic high voltage Vh, and outputs the second selection signal Se2 of logic high voltage Vh. The Inverting part Inv receives the second selection signal Se2 of logic high voltage Vh and outputs the first selection signal Se1 of logic low voltage Vl.

[0101] During the third time period TP3, the Gen part receives the first scan signal Sc1, the second scan signal Sc2, and the first transmit signal Em1 of the logic high voltage Vh, and outputs the second selection signal Se2 of the logic high voltage Vh. The Inverting part Inv receives the second selection signal Se2 of the logic high voltage Vh and outputs the first selection signal Se1 of the logic low voltage Vl.

[0102] During the fourth time period TP4, the Gen part receives the first scan signal Sc1 of logic high voltage Vh, the second scan signal Sc2 of logic high voltage Vh, and the first transmit signal Em1 of logic low voltage Vl, and outputs the second selection signal Se2 of logic low voltage Vl. The Inverting part Inv receives the second selection signal Se2 of logic low voltage Vl and outputs the first selection signal Se1 of logic high voltage Vh.

[0103] In the view-switching display device 110 according to the first embodiment of the present disclosure, the Gen portion of the selection block Bse of the first gate driving unit 124 and the second gate driving unit 126 can generate a second selection signal Se2 using a first scan signal Sc1, a second scan signal Sc2 and a first transmit signal Em1, and the Inverting portion Inv of the selection block Bse of the first gate driving unit 124 and the second gate driving unit 126 can generate a first selection signal Se1 by inverting the second selection signal Se2.

[0104] In another embodiment, an additional selection start signal and an additional selection clock signal can be used to generate a first selection signal Se1 and a second selection signal Se2.

[0105] Figure 6A Figure 6A is a view showing the first and second gate driving units of a view-switching display device according to a second embodiment of the present disclosure, and Figure 6B is a view showing multiple signals of a selection block of a view-switching display device according to a second embodiment of the present disclosure. Descriptions of parts identical to those in the first embodiment may be omitted.

[0106] exist Figure 6A In the second embodiment of the present disclosure, at least one of the first gate driving unit 124 and the second gate driving unit 126 of the view-switching display device 110 includes a first scan block Bsc1, a second scan block Bsc2, a first emission block Bem1, and a selection block Bse.

[0107] The first scan block Bsc1 uses the first start signal VST1, the (n-1)th first clock signal CLK1(n-1), the nth first clock signal CLK1(n), and the (n+1)th first clock signal CLK1(n+1) to generate the first scan signal Sc1, and transmits the first scan signal Sc1 to the display panel 128.

[0108] The second scan block Bsc2 uses the second start signal VST2, the (n-1)th second clock signal CLK2(n-1), the nth second clock signal CLK2(n), and the (n+1)th second clock signal CLK2(n+1) to generate the second scan signal Sc2, and transmits the second scan signal Sc2 to the display panel 128.

[0109] In another embodiment, the (n-1)th second clock signal CLK2(n-1), the nth second clock signal CLK2(n), and the (n+1)th second clock signal CLK2(n+1) can be the same as the (n-1)th first clock signal CLK1(n-1), the nth first clock signal CLK1(n), and the (n+1)th first clock signal CLK1(n+1), respectively.

[0110] The first transmitting block Bm1 uses the transmission start signal VSTe, the nth transmission clock signal CLKe(n), and the (n+1)th transmission clock signal CLKe(n+1) to generate the first transmission signal Em1, and transmits the first transmission signal Em1 to the display panel 128.

[0111] In another embodiment, the nth transmit clock signal CLKe(n) and the (n+1)th transmit clock signal CLKe(n+1) can be the same as the first first clock signal CLK1(1) and the second first clock signal CLK1(2), respectively.

[0112] The selection block Bse uses the selection start signal VSTs, the nth selection clock signal CLKs(n), and the (n+1)th selection clock signal CLK(n+1) to generate the first selection signal Se1 and the second selection signal Se2, and transmits the first selection signal Se1 and the second selection signal Se2 to the display panel 128.

[0113] The selection block Bse includes a generation part Gen that uses the selection start signal VSTs, the nth selection clock signal CLKs(n), and the (n+1)th selection clock signal CLK(n+1) to generate the first selection signal Se1, and an inverted part Inv that uses the first selection signal Se1 to generate the second selection signal Se2.

[0114] For example, the first selection signal Se1 and the second selection signal Se2 can be inverted signals, and the inverted part Inv can be an inverter.

[0115] Although not shown, at least one of the first gate driving unit 124 and the second gate driving unit 126 may further include a second transmitting block for generating the second transmitting signal Em2 and a third transmitting block for generating the third transmitting signal Em3.

[0116] exist Figure 6B In this process, the rising timing of the nth selection clock signal CLKs(n) and the falling timing of the (n+1)th selection clock signal CLK(n+1) are synchronized with the rising timing of the selection start signal VSTs.

[0117] During the first time period TP1, the generation part Gen receives the selection start signal VSTs of logic high voltage Vh, the nth selection signal CLKs(n) of logic high voltage Vh, and the (n+1)th selection clock signal CLKs(n+1) of logic low voltage Vl, and outputs the first selection signal Se1 of logic low voltage Vl. The inverting part Inv receives the first selection signal Se1 of logic low voltage Vl and outputs the second selection signal Se2 of logic high voltage Vh.

[0118] During the second time period TP2, the Gen part receives the start signal VSTs for selecting the logic high voltage Vh, the nth selection clock signal CLKs(n) for the logic high voltage Vh, and the (n+1)th selection clock signal CLKs(n+1) for the logic low voltage Vl, and outputs the first selection signal Se1 for the logic low voltage Vl. The Inverting part Inv receives the first selection signal Se1 for the logic low voltage Vl and outputs the second selection signal Se2 for the logic high voltage Vh.

[0119] During the third time period TP3, the Gen part receives the start signal VSTs for selecting the logic high voltage Vh, the nth selection clock signal CLKs(n) for the logic high voltage Vh, and the (n+1)th selection clock signal CLKs(n+1) for the logic low voltage Vl, and outputs the first selection signal Se1 for the logic low voltage Vl. The Inverting part Inv receives the first selection signal Se1 for the logic low voltage Vl and outputs the second selection signal Se2 for the logic high voltage Vh.

[0120] During the fourth time period TP4, the Gen part receives the start signal VSTs for selecting logic high voltage Vh, the nth selection clock signal CLKs(n) for logic low voltage Vl, and the (n+1)th selection clock signal CLKs(n+1) for logic high voltage Vh, and outputs the first selection signal Se1 for logic high voltage Vh. The Inverting part Inv receives the first selection signal Se1 for logic high voltage Vh and outputs the second selection signal Se2 for logic low voltage Vl.

[0121] In the view-switching display device 110 according to the second embodiment of the present disclosure, the Gen portion of the selection block Bse of the first gate driving unit 124 and the second gate driving unit 126 can generate a first selection signal Se1 using the selection start signal VSTs, the nth selection clock signal CLKs(n) and the (n+1)th selection clock signal CLKs(n+1), and the inverting portion Inv of the selection block Bse of the first gate driving unit 124 and the second gate driving unit 126 can generate a second selection signal Se2 by inverting the first selection signal Se1.

[0122] In the view-switching display device according to this disclosure, since a reference signal Vrf is provided to the cathode of at least one of the first light-emitting diodes De1 and De2 during the initialization period, sampling period, and holding period, emission of at least one of the first light-emitting diodes De1 and De2 is prevented, an increase in black brightness is prevented, and contrast is improved. Furthermore, since a low-level signal Vss is supplied to the cathode of at least one of the first light-emitting diodes De1 and De2 during the emission period, at least one of the first light-emitting diodes De1 and De2 emits light normally.

[0123] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its scope. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A view-switchable display apparatus comprising a sub-pixel, the sub-pixel comprising: a first transistor switched according to a voltage of a first node and connected to a high level signal and a second node; a second transistor switched according to a first emission signal and connected to the second node and a fourth node; a third transistor switched according to a second emission signal and connected to the fourth node and a fifth node; a fourth transistor switched according to a third emission signal and connected to the fourth node and a sixth node; a fifth transistor switched according to a second scan signal and connected to the first node and the second node; a sixth transistor switched according to the second scan signal and connected to the fifth node and a reference signal; a seventh transistor switched according to the second scan signal and connected to the sixth node and the reference signal; an eighth transistor switched according to the first emission signal and connected to a third node and the reference signal; a ninth transistor switched according to a first scan signal and connected to the third node and a data signal; a first light emitting diode and a second light emitting diode connected to the fifth node and the sixth node, respectively; a tenth transistor connected to at least one of the first light emitting diode and the second light emitting diode and the reference signal; and an eleventh transistor connected to at least one of the first light emitting diode and the second light emitting diode and a low level signal. the tenth transistor and the eleventh transistor are switched according to a first selection signal and a second selection signal, respectively; 2. The view-angle switchable display device according to claim 1, wherein and wherein the first selection signal and the second selection signal are inverse signals to each other. a generating portion configured to generate the second selection signal using the first scan signal, the second scan signal, and the first emission signal; 3. The view-angle switchable display device of claim 2, further comprising a selection block, the selection block comprising: and an inverting portion configured to generate the first selection signal using the second selection signal. a generating portion configured to generate the first selection signal using a selection start signal, an nth selection clock signal, and an nth+1 selection clock signal; 4. The view-angle switchable display device of claim 2, further comprising a selection block, the selection block comprising: and an inverting portion configured to generate the second selection signal using the first selection signal. 5.The view-switchable display apparatus of claim 1, further comprising a storage capacitor in the sub-pixel, the storage capacitor connected between the first node and the third node. a gate electrode of the first transistor, a first capacitor electrode of the storage capacitor, and a drain electrode of the fifth transistor constitute the first node; 6. The view-angle switchable display device according to claim 5, wherein, wherein a drain electrode of the first transistor, a source electrode of the second transistor, and a source electrode of the fifth transistor constitute the second node; ​ The second capacitor electrode of the storage capacitor, the source electrode of the eighth transistor, and the source electrode of the ninth transistor constitute the third node. The drain electrode of the second transistor, the source electrode of the third transistor, and the source electrode of the fourth transistor constitute the fourth node. The drain electrode of the third transistor, the source electrode of the sixth transistor, and the anode of the first light emitting diode constitute the fifth node; and The drain electrode of the fourth transistor, the source electrode of the seventh transistor, and the anode of the second light emitting diode constitute the sixth node.

7. The view-angle switchable display device according to claim 2, wherein, The first light emitting diode is connected between the fifth node and the low-level signal; The second light emitting diode is connected between the sixth node and the seventh node; and The cathode of the second light emitting diode, the source electrode of the tenth transistor, and the source electrode of the eleventh transistor constitute the seventh node.

8. The view-angle switchable display device according to claim 7, wherein, During a first period, the second transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the tenth transistor are turned on due to the second scan signal, the first emission signal, the third emission signal, and the first selection signal being a logic low voltage, and the third transistor, the ninth transistor, and the eleventh transistor are turned off due to the first scan signal, the second emission signal, and the second selection signal being a logic high voltage; During a second period, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the ninth transistor, and the tenth transistor are turned on due to the first scan signal, the second scan signal, the third emission signal, and the first selection signal being a logic low voltage, and the second transistor, the third transistor, the eighth transistor, and the eleventh transistor are turned off due to the first emission signal, the second emission signal, and the second selection signal being a logic high voltage; During a third period, the fourth transistor and the tenth transistor are turned on due to the third emission signal and the first selection signal being a logic low voltage, and the second transistor, the third transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the eleventh transistor are turned off due to the first scan signal, the second scan signal, the first emission signal, the second emission signal, and the second selection signal being a logic high voltage; and During the fourth time period, the second transistor, the fourth transistor, the eighth transistor, and the eleventh transistor are turned on because the first transmit signal, the third transmit signal, and the second selection signal are at logic low voltage, and the third transistor, the fifth transistor, the sixth transistor, the seventh transistor, the ninth transistor, and the tenth transistor are turned off because the first scan signal, the second scan signal, the second transmit signal, and the first selection signal are at logic high voltage.

9. The view-angle switchable display device according to claim 8, wherein, The reference signal is applied to the cathode of the second light-emitting diode during the first time period, the second time period, and the third time period; and The low-level signal is applied to the cathode of the second light-emitting diode during the fourth time period.

10. The view-switching display device according to claim 7, further comprising: A semi-cylindrical lens that focuses light along the upward and downward directions and is disposed above the first light-emitting diode; as well as A hemispherical lens that focuses light along the upward, downward, leftward, and rightward directions, and is disposed above the second light-emitting diode.

11. The view-switching display device according to claim 1, further comprising a display panel, the display panel including a display area having the sub-pixels.

12. The view-switching display device according to claim 11, wherein the display panel further includes a non-display area surrounding the display area.

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