A display driver chip

Abstract

This invention discloses a display driver chip, comprising: a receiver, a digital register, and a high-voltage rail-to-rail operational amplifier; the digital register is connected to the receiver and is used to temporarily store digital image data converted by the receiver; the high-voltage rail-to-rail operational amplifier comprises: a plurality of PMOS transistors and a plurality of NMOS transistors, which form a complementary architecture and a layered structure design in the high-voltage rail-to-rail operational amplifier to accommodate circuit designs with different voltage ratings. The high-voltage rail-to-rail operational amplifier ensures full-amplitude output, and the combination of low-voltage and high-voltage devices reduces the size of the chip circuit structure, improves the circuit integration of the display driver chip, thereby reducing the power consumption of the display driver chip and improving the reliability of the display device.

Description

Technical Field

[0001] This invention relates to the field of display chip technology, and more specifically to a display driver chip. Background Technology

[0002] With the rapid development and continuous iteration of electronic devices, there is an urgent need for displays with higher resolution, higher brightness, and higher reliability. This requires display driver chips to maintain strong driving and data transmission capabilities under complex operating conditions in order to meet the severe challenges posed by the stability and reliability of display driver chips under different operating conditions.

[0003] Current electronic paper displays mainly use electrowetting display technology. With the development of electronic device integration, the driving output voltage range of integrated circuits is narrow, resulting in insufficient brightness in electrowetting display technology. In addition, in order to increase the output voltage of the display driver chip, an external boost device is configured for the display driver chip, which increases the overall structural size of the display device and the power consumption of the overall device, and poses a risk of reduced reliability of the display device. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a display driver chip that ensures full-amplitude output through a high-voltage rail-to-rail operational amplifier and adopts a combination design of low-voltage and high-voltage devices to reduce the size of the chip circuit structure, improve the circuit integration of the display driver chip, thereby reducing the power consumption of the display driver chip and improving the reliability of the display device.

[0005] This invention provides a display driver chip, which includes: a receiver, a digital register, and a high-voltage rail-to-rail operational amplifier; The digital register is connected to the receiver and is used to temporarily store the digital image data converted by the receiver. The high-voltage rail-to-rail operational amplifier includes several PMOS transistors and several NMOS transistors, which form a complementary architecture and form a layered structure design in the high-voltage rail-to-rail operational amplifier to adapt to different voltage ratings.

[0006] Furthermore, a differential input structure is formed at the input terminal of the high-voltage rail-to-rail operational amplifier circuit based on two of the several PMOS transistors. A rail-to-rail push-pull architecture is formed by using one PMOS transistor from a group of PMOS transistors and one NMOS transistor from a group of NMOS transistors.

[0007] Furthermore, the plurality of PMOS transistors includes: a first PMOS transistor and a second PMOS transistor; the plurality of NMOS transistors includes: a first NMOS transistor and a second NMOS transistor; The first PMOS transistor and the second PMOS transistor form a differential input pair at the input terminal of the high-voltage rail-to-rail operational amplifier circuit, and the sources of the first PMOS transistor and the second PMOS transistor are connected to the power supply VDD. The gate of the first PMOS transistor is connected to the inverting input terminal VINN, the gate of the second PMOS transistor is connected to the non-inverting input terminal VINP, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drains of the second PMOS transistor and the second NMOS transistor are connected to each other.

[0008] Furthermore, the plurality of PMOS transistors also includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor; The third and fourth PMOS transistors form a PMOS current mirror, with their sources both connected to the high-voltage power supply terminal HVDD. The gate and drain of the third PMOS transistor are shorted, and the gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor, forming a mirror load. The sources of the fifth and sixth PMOS transistors are connected to the drains of the third and fourth PMOS transistors, respectively. The drains of the fifth and sixth PMOS transistors are connected to the drains of the seventh and eighth PMOS transistors. The gates of the fifth and sixth PMOS transistors share a bias voltage VB1. The sources of the seventh and eighth PMOS transistors are connected to the drains of the fifth and sixth PMOS transistors, respectively, and the gates of the seventh and eighth PMOS transistors are respectively connected to the drain nodes of the second and first PMOS transistors, forming a relay amplification structure for the input stage signal.

[0009] Furthermore, the plurality of PMOS transistors also includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor NM6 constitute the lower branch load; The sources of the third and fourth NMOS transistors are connected to the drains of the fifth and sixth NMOS transistors, respectively. The drains of the third and fourth NMOS transistors are connected to the drains of the seventh and eighth PMOS transistors; The third NMOS transistor and the fourth NMOS transistor share a common bias voltage VB2. The sources of the fifth and sixth NMOS transistors are grounded to VSS, and the gates of the fifth and sixth NMOS transistors are connected to the bias node, forming a folded common-source and common-gate amplification structure with the PMOS branch.

[0010] Furthermore, the display driver chip also includes an analog-to-digital converter (ADC), which is used to convert the digital image data of the digital register into an analog voltage signal. The output of the ADC is connected to the non-inverting input of the high-voltage rail-to-rail operational amplifier.

[0011] Furthermore, the receiver includes: a preamplifier, a hysteresis comparator, a latch, a current comparator, and a buffer cascaded in sequence; The input terminal of the preamplifier is coupled to the differential input signal, and the output terminal of the preamplifier is coupled to the input terminal of the hysteresis comparator. The output of the hysteresis comparator is coupled to the input of the latch. The output of the latch is coupled to the input of the current comparator; The output of the current comparator is coupled to the input of the buffer; The output terminal of the buffer is the output terminal of the receiver circuit.

[0012] Furthermore, the preamplifier is used to perform preliminary amplification and level conversion on the differential input signal; The hysteresis comparator is used to eliminate input noise interference and convert analog signals into digital levels; The latch is used to latch the digital level; The current comparator is used to perform current domain processing and decision-making on the latched signal. The buffer is used to drive the output.

[0013] Furthermore, the display driver chip also includes a gamma correction circuit, which includes an interpolation operational amplifier module with linear enhancement differential pairs.

[0014] Furthermore, the display driver chip also includes a 4-bit voltage selector, which outputs multiple discrete gamma reference voltages according to the configuration information of the serial interface, and the gamma reference voltages are sent to the interpolation operational amplifier module.

[0015] This invention provides a display driver chip, including a high-voltage rail-to-rail operational amplifier. The high-voltage rail-to-rail operational amplifier operates in a dual-supply environment of ±19.2V. It rationally distributes the voltage amplitude of approximately 40V by employing a combination of high-voltage and low-voltage MOSFETs, and uses Zener diodes to further protect the low-voltage MOSFETs within a safe voltage range. The analog-to-digital converter in this invention uses a dual-output, tree-structured digital-to-analog converter, utilizing the compact area provided by a voltage interpolation scheme. This effectively alleviates the exponential increase in layout area typically associated with increased bit resolution, enabling a small-size circuit design. Attached Figure Description

[0016] Figure 1 This is a structural block diagram of the display driver chip in an embodiment of the present invention; Figure 2 This is a circuit diagram of the receiver in an embodiment of the present invention; Figure 3 This is a data input timing diagram of the receiver in an embodiment of the present invention; Figure 4 This is a circuit diagram of the high-voltage rail-to-rail operational amplifier in an embodiment of the present invention; Figure 5 This is a bias circuit diagram of the low-voltage rail-to-rail operational amplifier in an embodiment of the present invention; Figure 6 This is a structural block diagram of the digital-to-analog converter in an embodiment of the present invention; Figure 7 This is a circuit schematic diagram of the digital-to-analog converter in an embodiment of the present invention; Figure 8 This is a circuit schematic diagram of the bandgap reference circuit in an embodiment of the present invention; Figure 9 This is a schematic diagram of the interpolation operational amplifier circuit in an embodiment of the present invention; Figure 10 This is the equivalent circuit diagram of the interpolation operational amplifier in the embodiment of the present invention; Figure 11 This is a block diagram of the negative voltage charge pump circuit structure in an embodiment of the present invention; Figure 12 This is a circuit diagram of the charge pump in an embodiment of the present invention; Figure 13 This is a schematic diagram of the principle of the NAND gate non-overlapping clock generator in an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example: Please refer to Figures 1 to 13 This invention provides a display driver chip, which includes: a receiver 1, a digital register 2, an analog-to-digital converter, and a high-voltage rail-to-rail operational amplifier 4; the receiver 1 is a Mini-LVDS receiver 1, which receives the raw image data transmitted through the LVDS interface, completes the reception and level conversion of the LVDS signal, and outputs standard digital image data to subsequent modules.

[0019] The digital register 2 is connected to the receiver 1. The digital register 2 is used to temporarily store the digital image data converted by the receiver 1. By temporarily storing the digital image data based on the digital register 2, the digital register 2 can buffer and synchronize the digital signal of the data source of the analog-to-digital converter.

[0020] Specifically, external image data enters the chip in high-speed differential form through MiniLVDS receiver 1. This analog receiver 1 converts the differential signal into a parallel digital signal and transmits it to digital register 2 for timing synchronization and temporary storage, providing precise timing matching for subsequent digital-to-analog conversion and drive output. Simultaneously, external gamma correction data is input through a serial interface. This digital interface transmits configuration information to the 4-bit voltage selector 8, providing the basic configuration for grayscale correction. At the power supply level, a low-dropout linear regulator 5 (LDO) obtains energy from an external power source and outputs a stable low-voltage power supply V_OP to power MiniLVDS receiver 1 and bandgap reference circuit 6. Bandgap reference circuit 6 generates a reference current I unaffected by temperature and power fluctuations. This current serves as the current reference for the entire system and also drives a negative voltage charge pump 7 to generate a negative power supply, providing negative voltage support for analog modules such as the 4-bit voltage selector 8 that require dual power supplies.

[0021] Furthermore, in the gamma correction path, the 4-bit voltage selector 8 outputs multiple sets of discrete gamma reference voltages (ranging from approximately -2.4V to 2.4V) according to the configuration information of the serial interface. These voltages are fed into the interpolation operational amplifier module, which generates a continuous, smooth gamma correction voltage curve that supports slope adjustment through interpolation operations. This curve is used to compensate for the grayscale nonlinearity of the display panel, ensuring natural color reproduction. In the image data processing and output drive path, the image data buffered in the digital register 2 is distributed to the 6-bit digital-to-analog converter 3 (DAC) and the high-voltage rail-to-rail operational amplifier 4. The 6-bit DAC converts the digital image data into analog voltages corresponding to the grayscale levels and inputs them to the inverting input of the high-voltage operational amplifier. The gamma correction voltage output by the interpolation operational amplifier is connected to the non-inverting input of the high-voltage operational amplifier. The operational amplifier is set to a gain of approximately 8 times through a feedback network consisting of resistors R and 7R, and finally outputs a drive signal with a high voltage range of ±19.2V to the display panel.

[0022] Furthermore, digital register 2 directly outputs control signals to the input of the high-voltage operational amplifier, further optimizing the driving timing and accuracy. The entire architecture, through the collaborative work of analog and digital circuits, achieves a complete link between high-speed image data reception, precise gamma correction, digital-to-analog conversion, and high-voltage driving. The analog circuits are responsible for continuous signal processing and high-voltage output, while the digital circuits handle the buffering and configuration transmission of discrete data. This combination ensures that the display panel can present high-quality images with accurate grayscale and natural colors, meeting the performance requirements of high-voltage driven display technology.

[0023] The analog-to-digital converter is used to convert the digital image data of the digital register 2 into an analog voltage signal. The output terminal of the analog-to-digital converter is connected to the non-inverting input terminal of the high-voltage rail-to-rail operational amplifier 4. Based on the non-inverting amplification architecture of the high-voltage rail-to-rail operational amplifier 4, it can realize high-voltage amplification of analog signals.

[0024] Specifically, the display driver chip adopts a strict mixed-signal architecture: the digital system includes an I²C bus interface controller that supports protocol parsing, a cascaded shift register array that implements data stream allocation, and a latch circuit that ensures sampling timing accuracy; the analog system constructs a five-stage continuous signal processing link: a 250MHz mini-LVDS differential receiver 1 implements anti-interference data acquisition, and its output is fed into a programmable 2-to-4 level selector to provide gain configuration flexibility; this selector drives a 4-bit embedded operational amplifier DAC to complete the core digital-to-analog conversion, and then the dynamic range is extended by two cascaded DACs; finally, a high-voltage output buffer 15 outputs a high-voltage signal to form a complete signal path.

[0025] Based on the synergistic optimization of the low-voltage folded cascode input stage and the high-voltage output stage, the source-drain withstand voltage of the differential pair input structure at the input terminal is designed to be 24V, enabling the display driver chip to operate normally in a voltage range up to 19.2V.

[0026] Specifically, the receiver 1 includes a preamplifier 11, a hysteresis comparator 12, a latch 13, a current comparator 14, and a buffer 15. The preamplifier 11 adopts a rail-to-rail folded structure design to ensure that the circuit input has sufficient bandwidth and gain, thereby enabling sensitive capture and amplification of signals. The receiver 1 is constructed by cascading five core modules: a preamplifier 11, a hysteresis comparator 12, a latch 13, a current comparator 14, and a buffer 15. The differential input signals LVP and LVN first enter the preamplifier 11, which can use a differential pair and current mirror load structure with a 20μA bias current to perform preliminary amplification and level conversion on the weak input signals. Its output directly drives the hysteresis comparator 12. The hysteresis comparator 12 operates with a 100μA bias current and eliminates input noise interference through its internal cross-coupled hysteresis structure, converting the analog signal into a digital level and outputting it to the latch 13. The latch 13 latches the compared digital signal under a 100μA bias, and after ensuring signal stability, it is sent to the current comparator 14. The current comparator 14 further processes and decides the signal in the current domain, and finally outputs a stable digital signal OUT after being driven by the output buffer 15, realizing the signal conditioning and decision function from differential analog input to single-ended digital output.

[0027] During the design process, the folded rail-to-rail circuit uses a symmetrical structure, which can prevent the channel length of the input transistor from being too large, which may cause channel length modulation effect and ensure the input performance of the display driver chip. Since the rail-to-rail input of the amplifier circuit has a symmetrical structure, the gain is calculated based on half of the circuit.

[0028] The gain calculation formula is as follows: ; ; ; in, This represents the gain of the amplifier circuit. The gain of the amplifier for the NMOS input pair; The gain of the amplifier for the PMOS input pair; Transconductance of the PMOS input pair; Transconductance of the NMOS input pair; This is the body transconductance of the PMOS transistor; This is the body transconductance of the NMOS transistor; Small-signal resistance for the NMOS input pair; Small-signal resistance for the PMOS input pair; The small-signal resistance of NM2; The small-signal resistance of PM3.

[0029] Specifically, the mini-LVDS signal is amplified through a rail-to-rail differential pair, and the resulting differential outputs need to be compared to generate a digital signal. This conversion process is implemented using a hysteresis comparator 12 with threshold hysteresis. Due to noise, and if the comparator input is close to the threshold point, the comparator may misjudge the comparison, resulting in an error signal. To address this issue, a hysteresis comparator 12 is used, the schematic of which is shown below. Figure 4 As shown. This hysteresis effect is used to eliminate the output oscillation effect caused by the instability of the input signal. The device consists of a differential input pair, a diode load, and a negative resistance diode. The differential input hysteresis voltage is determined by the values ​​of the diode load transistor M3 and the negative resistance diode M4. However, the hysteresis comparator 12 can also affect the performance of the LVDS. If the hysteresis window is too large, the signals from the preamplifier circuit cannot be compared. Therefore, the hysteresis comparator 12 proposed in this circuit has a window of approximately 10mV to 20mV, which can eliminate the influence of noise and avoid affecting the normal operation of the LVDS.

[0030] The gain calculation formula for this structure is as follows: ; ; in, for; for; For; W is; L is; α is.

[0031] Furthermore, after passing through the preamplifier and the hysteresis comparator 12, the signal is converted from double-ended to single-ended by the differential amplifier. The latch 13 features wide bandwidth, low noise, high slew rate, large output swing, and simple structure. This structure uses mirrored poles, resulting in a rapid drop in gain at high frequencies. The substantial output swing keeps the steady-state output level far from the flip-flop of the lower comparator. Combined with low gain and high-frequency suppression characteristics, signal glitches and noise are effectively reduced.

[0032] Furthermore, the current comparator 14 has the characteristics of high sensitivity, fast response and low power consumption, which can meet the low voltage conditions of the receiver 1.

[0033] Specifically, the demodulated signal is digitized by the high-speed data conversion module and then transmitted to the digital subsystem. The digital circuit first temporarily stores the data in the first-stage latch 13. After the current frame data is demodulated and stored, the data is transferred to the output latch 13 through timing control. This two-stage latch architecture ensures that the output latch 13 maintains stable display data during the grayscale value output by the display driver, avoiding interference with screen refresh during subsequent data reception.

[0034] The receiver 1 provided in this embodiment integrates six mini-LVDS data channels. Each pair of differential channels continuously transmits 6 bits of data to determine the output channel voltage value. The parallel architecture significantly improves the system sampling rate. At the same time, the display uniformity is optimized through an intelligent DC balancing strategy: when the input binary data is less than the median value "011111", a negative voltage is output; when the input data is greater than the median value "011111", a positive voltage is output.

[0035] Specifically, the high-voltage rail-to-rail operational amplifier 4 includes several PMOS transistors and several NMOS transistors. Based on the complementary architecture formed between the several PMOS transistors and several NMOS transistors, a hierarchical structure design is formed in the high-voltage rail-to-rail operational amplifier 4, which can adapt to circuit designs with different voltage ratings and realize the core circuit functions of wide input common-mode range, high gain, and full power rail output.

[0036] Furthermore, based on two PMOS transistors among several PMOS transistors forming a differential input structure at the input terminal of the high-voltage rail-to-rail operational amplifier 4 circuit, the input terminal of the high-voltage rail-to-rail operational amplifier 4 operating circuit is in the low voltage range; based on one PMOS transistor among several PMOS transistors and one NMOS transistor among several NMOS transistors forming a rail-to-rail push-pull architecture, the output voltage at the output terminal can approach the power rail, realizing the full voltage range output swing.

[0037] Specifically, in the high-voltage rail-to-rail operational amplifier 4 circuit, the plurality of PMOS transistors include: first PMOS transistor PM1, second PMOS transistor PM2, third PMOS transistor PM3, fourth PMOS transistor PM4, fifth PMOS transistor PM5, sixth PMOS transistor PM6, seventh PMOS transistor PM7, eighth PMOS transistor PM8, ninth PMOS transistor PM9, tenth PMOS transistor PM10, eleventh PMOS transistor PM11, and twelfth PMOS transistor PM12.

[0038] The plurality of NMOS transistors include: first NMOS transistor NM1, second NMOS transistor NM2, third NMOS transistor NM3, fourth NMOS transistor NM4, fifth NMOS transistor NM5, sixth NMOS transistor NM6, seventh NMOS transistor NM7, eighth NMOS transistor NM8, ninth NMOS transistor NM9, tenth NMOS transistor NM10, eleventh NMOS transistor NM11, and twelfth NMOS transistor NM12.

[0039] Furthermore, the first PMOS transistor PM1 and the second PMOS transistor PM2 form a differential input pair at the input terminal of the high-voltage rail-to-rail operational amplifier 4 circuit. The sources of both the first PMOS transistor PM1 and the second PMOS transistor PM2 are connected to the power supply VDD. The gate of the first PMOS transistor PM1 is connected to the inverting input terminal VINN, and the gate of the second PMOS transistor PM2 is connected to the non-inverting input terminal VINP. The drain of the first PMOS transistor PM1 is connected to the drain of the first NMOS transistor NM1, and the drain of the second NMOS transistor NM2 of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2.

[0040] The first NMOS transistor NM1 and the second NMOS transistor NM2 form the active load branch of the input stage. The sources of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected to a grounded constant current source. The gates of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected to a bias node. The drains of the first NMOS transistor NM1 and the second NMOS transistor NM2 are respectively matched with the drains of the first PMOS transistor PM1 and the second PMOS transistor PM2, thus forming the core branch of the differential amplifier input stage.

[0041] The differential input signals VINN and VINP of the high-voltage rail-to-rail operational amplifier 4 circuit drive the gates of PM1 and PM2 respectively. PM1 / PM2 and NM1 / NM2 form a differential amplifier pair. VDD supplies power to the PMOS source, and a grounded constant current source provides bias current to the NMOS branch. When a voltage difference occurs between VINP and VINN, the drain currents of PM1 and PM2 change differentially, converting the differential voltage signal into a current signal, completing the first stage of voltage-to-current conversion and weak signal amplification.

[0042] The high-voltage rail-to-rail operational amplifier 4 circuit is based on the synergistic optimization of the low-voltage folded common-source cascode input stage and the high-voltage output stage. The input stage integrates two pairs of differential input transistors, with a source-drain withstand voltage design of 24V, enabling it to operate normally in a voltage range up to 19.2V, which meets the circuit design requirements of electrowetting display technology.

[0043] Furthermore, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 form a PMOS current mirror, with their sources both connected to the high-voltage power supply terminal HVDD; the gate and drain of the third PMOS transistor PM3 are shorted, and the gate of the fourth PMOS transistor PM4 is connected to the gate of the third PMOS transistor PM3, providing a mirror load for the amplification stage. The sources of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are connected to the drains of the third PMOS transistor PM3 and the fourth PMOS transistor PM4, respectively. The drains of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are connected to the drains of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8. The gates of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 share a bias voltage VB1. The sources of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are connected to the drains of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6, respectively. The gates of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are respectively connected to the drain nodes of the second PMOS transistor PM2 and the first PMOS transistor PM1, respectively, to complete the intermediate amplification of the input stage signal.

[0044] The third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, and the sixth NMOS transistor NM6 constitute the lower branch load.

[0045] The sources of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are connected to the drains of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6, respectively.

[0046] The drains of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are connected to the drains of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8.

[0047] The gates of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 share a common bias voltage VB2.

[0048] The sources of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are grounded to VSS, and the gates of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are connected to the bias node, forming a folded cascode amplifier structure with the PMOS branch.

[0049] Specifically, the ninth PMOS transistor PM9, the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11, and the twelfth PMOS transistor PM12 are connected in series to form the output stage pull-up path of the high-voltage rail-to-rail operational amplifier 4 circuit; The source of the ninth PMOS transistor PM9 is connected to HVDD, and the gate of the ninth PMOS transistor PM9 is connected to the bias VB3.

[0050] The source of the tenth PMOS transistor PM10 is connected to HVDD, and the gate of the tenth PMOS transistor PM10 is connected to the gate of the twelfth PMOS transistor PM12.

[0051] The source of the eleventh PMOS transistor PM11 is connected to the drain of the tenth PMOS transistor PM10, and the drain of the eleventh PMOS transistor PM11 is connected to the source of the twelfth PMOS transistor PM12.

[0052] The source of the twelfth PMOS transistor PM12 is connected to the drain of the eleventh PMOS transistor PM11, the drain of the twelfth PMOS transistor PM12 is connected to the output terminal OUT, and the gate of the twelfth PMOS transistor PM12 is connected to the output node of the intermediate amplification stage.

[0053] Specifically, the ninth NMOS transistor NM9, the tenth NMOS transistor NM10, the eleventh NMOS transistor NM11, and the twelfth NMOS transistor NM12 are connected in series to form the output stage pull-down path; the source of the ninth NMOS transistor NM9 is grounded to VSS, the drain of the ninth NMOS transistor NM9 is connected to the drain of the tenth NMOS transistor NM10, and the gate of the ninth NMOS transistor is connected to the bias node; The source of the tenth NMOS transistor NM10 is connected to the drain of the ninth NMOS transistor NM9, the drain of the tenth NMOS transistor NM10 is connected to the drain of the eleventh NMOS transistor NM11, and the gate of the eleventh NMOS transistor NM11 is connected to the bias VB4. The source of the eleventh NMOS transistor NM11 is connected to the drain of the tenth NMOS transistor NM10, and the drain of the eleventh NMOS transistor NM11 is connected to the source of the twelfth NMOS transistor NM12. The source of the twelfth NMOS transistor NM12 is connected to the drain of the eleventh NMOS transistor NM11, the drain of the twelfth NMOS transistor NM12 is connected to the output terminal OUT, and the gate of the twelfth NMOS transistor NM12 is connected to the output node of the intermediate amplification stage.

[0054] Specifically, in this embodiment, the breakdown voltage of the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, and the second NMOS transistor NM2 is 24V. The withstand voltage of the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11, the third NMOS transistor NM3, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the tenth NMOS transistor NM10, and the ninth NMOS transistor NM9 is 5V; The withstand voltage of the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, the ninth PMOS transistor PM9, the twelfth PMOS transistor PM12, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, the eleventh NMOS transistor NM11, and the twelfth NMOS transistor NM12 is 40V.

[0055] Specifically, under certain operating conditions, the source-drain voltage of a low-voltage transistor may exceed its maximum withstand limit of 5.5V, requiring the deployment of a high-voltage protection mechanism. This design uses a Zener diode to construct a voltage clamping topology: when the reverse bias exceeds the 5.5V breakdown threshold, the device enters the reverse breakdown operating region, generating an avalanche current to stabilize the reverse voltage near the breakdown value. By establishing a parallel low-resistance path, the source-drain voltage of the transistor is strictly limited to below 5.5V.

[0056] Furthermore, by mixing and arranging MOSFETs with different voltage ratings, the low-voltage domain can be used only for bias circuits and small-signal processing stages (such as PM3 / PM4, NM3 / NM4, NM7 / NM8, etc.). Low-voltage MOSFETs have smaller process unit sizes, lower parasitic parameters, and a much higher integration density than high-voltage MOSFETs, and do not require a large high-voltage process area.

[0057] The high-voltage domain (24V / 40V MOS transistors) is used in the high-voltage main path to form the circuit structure of input stage differential pair PM1 / PM2, output stage PM12 / NM12, high-voltage gain stage PM9 / PM10, etc. Based on the low-voltage and high-voltage transistor pairing structure, the use of high-voltage MOS transistors in the whole chip is avoided. High-voltage transistors are only used in the critical high-voltage path, which greatly reduces the core chip area and thus reduces the package size.

[0058] Specifically, the high-voltage rail-to-rail operational amplifier 4 also includes a bias circuit, which generates a bias voltage and provides the bias voltage to the high-voltage operational amplifier.

[0059] The bias circuit includes: the thirteenth PMOS transistor PM13, the fourteenth PMOS transistor PM14, the fifteenth PMOS transistor PM15, the sixteenth PMOS transistor PM16, the seventeenth PMOS transistor PM17, the eighteenth PMOS transistor PM18, and the nineteenth PMOS transistor PM19.

[0060] The bias circuit further includes: the thirteenth NMOS transistor NM13, the fourteenth NMOS transistor NM14, the fifteenth NMOS transistor NM15, the sixteenth NMOS transistor NM16, the seventeenth NMOS transistor NM17, and the eighteenth NMOS transistor NM18.

[0061] The thirteenth PMOS transistor PM13 is connected to the current mirror of the bandgap reference circuit 6, and the fourteenth PMOS transistor PM14 replicates the current of the thirteenth PMOS transistor PM13 to provide a tail current source for the high-voltage operational amplifier.

[0062] The sixteenth PMOS transistor PM16 and the seventeenth PMOS transistor PM17 are high-voltage PMOS transistors. The seventeenth PMOS transistor PM17, the fifteenth NMOS transistor NM15, and the seventeenth NMOS transistor NM17 are arranged on the same branch, which can generate negative voltages VB2 and VB4 with relatively high absolute values. The seventeenth PMOS transistor PM17 is used to clamp VB2 so that the fifteenth NMOS transistor NM15 and the seventeenth NMOS transistor NM17 can operate normally under low voltage. Similarly, the high-voltage NMOS transistor sixteenth NMOS transistor NM16 is used to clamp VB1 to generate positive voltages VB1 and VB3 with relatively high absolute values.

[0063] Specifically, the digital-to-analog converter 3 is a two-stage cascaded structure used to convert the high three bits of the digital signal, which are input to two adjacent node voltages VH and VL. It selects one output voltage between the high voltage (VH) and low voltage (VL) established by the previous stage. The selection by the analog-to-digital converter is represented by the lower three bits, and the interaction of these bits with the operation of the first stage ultimately produces a voltage value VOUT, which is determined by a DAC with 6-bit resolution.

[0064] The digital-to-analog converter 3 is based on multiple series resistors connected between the high reference voltage and the low reference voltage. When all resistor values ​​are equal, that is, the voltage difference between any two adjacent nodes is fixed, it equals... Where N is the total number of resistors, corresponding to the DAC's resolution. For high reference voltage, Low reference voltage.

[0065] The working circuit of the digital-to-analog converter 3 divides the input voltage into a series of uniformly distributed discrete voltage values, with each node corresponding to a unique voltage divider value.

[0066] Furthermore, the binary digital signal input to the digital-to-analog converter 3 is decoded and used to control analog switches or multiplexers. Different digital codes correspond to different nodes on the voltage divider chain.

[0067] The analog switch outputs the selected voltage divider node voltage as Vout based on the digital control signal, thus mapping the discrete digital signal into a continuously changing analog voltage and completing the digital-to-analog conversion.

[0068] Specifically, the display driver chip also includes: a bandgap reference circuit 6 and an LDO (low dropout linear stabilizer) circuit. The bandgap reference circuit 6 includes a startup circuit, a current reference circuit, two current mirrors, and a voltage multiplier circuit. A high-gain self-biased amplifier ensures that the sum of the voltage drops across R5 and Q2 equals the voltage drop across Q1. Utilizing the negative temperature coefficient of the base-emitter voltage of a bipolar transistor and the positive temperature coefficient of the difference between the base-emitter voltages of bipolar transistors operating at different current densities, a PTAT current and a CTAT current flow through R5 and R6, respectively. The superposition of these two currents gives the PM4 transistor a zero-temperature coefficient current. The current mirror replicates this "zero-temperature" current, generating a reference voltage across the resistor.

[0069] Specifically, the working principle of the bandgap reference circuit 6 is as follows: Upon power-up, the left self-starting circuit quickly establishes a bias through a positive feedback mechanism, driving the middle bandgap reference circuit 6 to leave the initial locked state and enter a stable working mode; the bandgap reference circuit 6 then uses the negative feedback of the operational amplifier A1 to force a balance at the node potential, and combines the negative temperature coefficient of the emitter junction voltage of bipolar transistors Q1 and Q2 with the positive temperature coefficient of the resistor to cancel each other out, generating a precise reference voltage VREF that is independent of power supply and temperature; subsequently, the right low-dropout linear regulator 5 uses VREF as a reference, compares the voltage divider feedback signal of the output voltage LVDD through the error amplifier A2, and dynamically adjusts the conduction degree of the power adjustment transistor, so that even when the load changes or the input voltage fluctuates, it can still output a stable low-voltage power supply LVDD, while the compensation capacitors ensure the stability of the circuit under startup and steady-state operation.

[0070] Specifically, the interpolation circuit employs a 4-bit embedded operational amplifier. Its core architecture integrates a four-stage signal conditioning module, which includes a voltage selector, five sets of differential input pairs, a common-gate gain stage, and an output buffer stage. The global negative feedback loop is established by interconnecting all inverting inputs with the amplifier output. The output of the voltage selector drives the non-inverting inputs of each differential pair, but the non-inverting input of the leftmost differential pair (labeled VINP<0:3>) has a crucial difference in configuration. It directly receives the reference voltage VL or VH from the voltage selector, and this voltage value is dynamically configured by the input data.

[0071] When the differential pairs are designed to operate in the subthreshold region, their transconductance (gm) is proportional to their tail current. The voltage interpolation schemes for positive and negative voltages are also proportional to their tail currents. Therefore, the transconductance values ​​of the five differential pairs also follow a ratio of 1:1:2:4:8. When the differential pairs operate in strong inversion, the tail current and transistor size ratio are similarly designed to be 1:1:2:4:8. Assuming that the gm of a differential pair is proportional to the square root of the product of the tail current Itail and the transistor size W / L, the gm ratio of the five differential pairs remains 1:1:2:4:8. Therefore, the current from all five differential pairs flows to the output stage.

[0072] Specifically, Figure 10 This is the equivalent circuit diagram of the interpolation operation circuit. and These represent the output resistance of the first stage and the voltage gain of the output stage, respectively. Total differential current. The relationship between the input data and the input data can be represented as: ; ; in, The output resistor of the first stage; This refers to the voltage gain of the output stage. This represents the total differential current in the equivalent circuit. This refers to the output voltage. The initial voltage of the voltage node controlled by the current interpolation operational amplifier; The transconductance of the first-stage differential input pair transistor; The initial voltage of the voltage node controlled by the next higher-level interpolation operational amplifier; These are control signals for high and low levels.

[0073] Furthermore, the expression for the output voltage is: ; in, For output voltage, The initial voltage of the voltage node controlled by the current interpolation operational amplifier; These are control signals for high and low levels; This is the initial voltage of the voltage node controlled by the next higher-level interpolation operational amplifier.

[0074] In addition, an interpolation operational amplifier can be used to modify the voltage at the nodes of the reference resistor string, thereby adjusting the slope of the output curve for gamma correction.

[0075] Specifically, the negative voltage charge pump 7 structure of the display chip mainly consists of a charge pump circuit, a comparator, a non-overlapping NAND gate clock generator, and an RC ring oscillator. The oscillator circuit is an RC ring oscillator that generates a periodic square wave clock signal with a 50% duty cycle. The clock signal generated by the oscillator is processed by the non-overlapping clock circuit to generate non-overlapping clock signals. The non-overlapping clock signal controls the switching MOSFETs of the charge pump circuit, avoiding charge leakage caused by simultaneous switching of MOSFETs. The charge pump circuit uses the non-overlapping clock signal to drive the switching MOSFETs to turn on and off to transfer charge, thereby achieving the purpose of voltage reduction and boost. The output voltage is divided by two voltage divider resistors R1 and R2 and compared with the reference voltage VREF through a comparator circuit. When the divided voltage is higher than the reference voltage, the comparator outputs a high-level control signal. At this time, the clock signal generated by the oscillator enters the non-overlapping clock circuit to generate a non-overlapping clock control signal, the charge pump circuit starts working, and the output voltage continuously decreases. When the voltage divider is lower than the reference voltage, the comparator outputs a low-level control signal, the clock control signal generated by the non-overlapping clock circuit is shielded, and the charge pump stops working.

[0076] Furthermore, based on the design requirements of the display driver chip, the number of charge pump stages is determined. The input power supply voltage of the charge pump circuit is 3.3V. Considering voltage loss during circuit operation, the actual output voltage VOUT of the single-stage charge pump circuit is approximately -2.4V. This design only requires a negative voltage of 0.8 times the input voltage. Considering the rise time of the charge pump, a single-stage charge pump is designed. Next is the design of the switching transistor size. The core of the circuit consists of a switching MOSFET. When a MOSFET is turned on, its on-resistance is affected, causing voltage loss. The on-resistance Ron of the switching MOSFET in the linear region is: ; Where μ is the carrier mobility It is the capacitance per unit area of ​​gate oxide layer. It is the width-to-length ratio of the switching MOSFET. It is the gate-source voltage of the switching MOSFET. It is the threshold voltage.

[0077] The width-to-length ratio of the switching MOSFET needs to be determined based on the specific specifications of the system to avoid excessive size leading to increased gate parasitic capacitance of the switching MOSFET, which in turn increases the voltage loss of the switch.

[0078] Furthermore, the switching MOSFET can be considered equivalent to a linear resistor when it is turned on. With the addition of the pump capacitor, the charge pump circuit can be simplified to an RC circuit. Since the charging and discharging speed of the capacitor in an RC circuit depends only on the values ​​of the resistance and capacitance (R and C), the larger the values ​​of R and C, the longer the charging time, regardless of the power supply voltage. The charging and discharging time of the capacitor can be expressed as the product of the resistance R and capacitance C, which is the time constant τ, i.e., τ = RC. According to existing theoretical results, the charging and discharging process of the capacitor is an exponential process. Within 1τ, the voltage across the capacitor can reach 63.2% of the input voltage, and within 3τ, the voltage across the capacitor can reach 95% of the input voltage. Therefore, to meet the charging time requirements of the RC circuit and to control the size of the pump capacitor, a pump capacitor of 3μF is chosen.

[0079] Specifically, the NAND gate non-overlapping clock generator includes a delay unit composed of multiple inverters. The aspect ratio and number of MOS transistors that make up the inverters are determined by the delay time required by the circuit. When the NMOS transistor of the inverter is working, the PMOS transistor is off, and when the PMOS transistor of the inverter is working, the NMOS transistor is off. This ensures that only one MOS transistor generates power consumption when the inverter is working, which also reduces the power consumption of the entire non-overlapping clock circuit and improves the conversion efficiency of the charge pump.

[0080] Furthermore, the two inputs of the leftmost NAND gate in the circuit are the input clock signal CLK. IN The enable signal EN controls the operation and shutdown of the entire clock circuit module and generates an initial state when the clock circuit starts working. The delay unit composed of NAND gates and multi-stage inverters in the middle of the circuit can obtain clock signals with the same frequency but different duty cycles. The LV module uses a level shifting structure, which can convert the clock signal voltage level. Therefore, it is used to convert a low-level (0) clock signal into a low-level (negative) signal, allowing the clock signals CLK2 and CLK4 to transition from power supply voltage to 0 to negative voltage, thus enabling the normal opening and closing of the switching MOSFETs. After the four clock signals CLK1, CLK2, CLK3, and CLK4, a buffer 15 consisting of several stages of inverters with gradually increasing aspect ratios is added. This increases the driving capability of the clock signals. The stronger the driving capability, the larger the swing of the clock signal and the faster the rise time, resulting in better rising and falling edges, ensuring a more complete output waveform. It also increases the delay time to meet the hold time requirements.

[0081] This invention provides a display driver chip, including a high-voltage rail-to-rail operational amplifier 4. The high-voltage rail-to-rail operational amplifier 4 operates in a dual-supply environment of ±19.2V. It rationally distributes the voltage amplitude of approximately 40V by employing a combination of high-voltage and low-voltage MOSFETs, and uses Zener diodes to further protect the low-voltage MOSFETs within a safe voltage range. The analog-to-digital converter in this invention uses a dual-output, tree-structured digital-to-analog converter 3, utilizing the compact area provided by a voltage interpolation scheme. This effectively alleviates the exponential increase in layout area that typically accompanies increased bit resolution, achieving a small-size circuit design.

[0082] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.

[0083] Furthermore, the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display driver chip, characterized in that, The display driver chip includes: a receiver, a digital register, and a high-voltage rail-to-rail operational amplifier; The digital register is connected to the receiver and is used to temporarily store the digital image data converted by the receiver. The high-voltage rail-to-rail operational amplifier includes several PMOS transistors and several NMOS transistors, which form a complementary architecture and form a layered structure design in the high-voltage rail-to-rail operational amplifier to adapt to different voltage ratings.

2. The display driver chip as described in claim 1, characterized in that, A differential input structure is formed at the input terminal of the high-voltage rail-to-rail operational amplifier circuit based on two PMOS transistors out of several PMOS transistors. A rail-to-rail push-pull architecture is formed by using one PMOS transistor from a group of PMOS transistors and one NMOS transistor from a group of NMOS transistors.

3. The display driver chip as described in claim 1, characterized in that, The plurality of PMOS transistors includes: a first PMOS transistor and a second PMOS transistor; the plurality of NMOS transistors includes: a first NMOS transistor and a second NMOS transistor; The first PMOS transistor and the second PMOS transistor form a differential input pair at the input terminal of the high-voltage rail-to-rail operational amplifier circuit, and the sources of the first PMOS transistor and the second PMOS transistor are connected to the power supply VDD. The gate of the first PMOS transistor is connected to the inverting input terminal VINN, the gate of the second PMOS transistor is connected to the non-inverting input terminal VINP, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drains of the second PMOS transistor and the second NMOS transistor are connected to each other.

4. The display driver chip as described in claim 3, characterized in that, The plurality of PMOS transistors further includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor; The third and fourth PMOS transistors form a PMOS current mirror, with their sources both connected to the high-voltage power supply terminal HVDD. The gate and drain of the third PMOS transistor are shorted, and the gate of the fourth PMOS transistor is connected to the gate of the third PMOS transistor, forming a mirror load. The sources of the fifth and sixth PMOS transistors are connected to the drains of the third and fourth PMOS transistors, respectively. The drains of the fifth and sixth PMOS transistors are connected to the drains of the seventh and eighth PMOS transistors. The gates of the fifth and sixth PMOS transistors share a bias voltage VB1. The sources of the seventh and eighth PMOS transistors are connected to the drains of the fifth and sixth PMOS transistors, respectively, and the gates of the seventh and eighth PMOS transistors are respectively connected to the drain nodes of the second and first PMOS transistors, forming a relay amplification structure for the input stage signal.

5. The display driver chip as described in claim 3, characterized in that, The plurality of PMOS transistors further include: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor NM6 constitute the lower branch load; The sources of the third and fourth NMOS transistors are connected to the drains of the fifth and sixth NMOS transistors, respectively. The drains of the third and fourth NMOS transistors are connected to the drains of the seventh and eighth PMOS transistors; The third NMOS transistor and the fourth NMOS transistor share a common bias voltage VB2. The sources of the fifth and sixth NMOS transistors are grounded to VSS, and the gates of the fifth and sixth NMOS transistors are connected to the bias node, forming a folded common-source and common-gate amplification structure with the PMOS branch.

6. The display driver chip as described in claim 1, characterized in that, The display driver chip also includes an analog-to-digital converter (ADC), which is used to convert the digital image data of the digital register into an analog voltage signal. The output of the ADC is connected to the non-inverting input of the high-voltage rail-to-rail operational amplifier.

7. The display driver chip as described in claim 1, characterized in that, The receiver includes: a preamplifier, a hysteresis comparator, a latch, a current comparator, and a buffer cascaded in sequence; The input terminal of the preamplifier is coupled to the differential input signal, and the output terminal of the preamplifier is coupled to the input terminal of the hysteresis comparator. The output of the hysteresis comparator is coupled to the input of the latch. The output of the latch is coupled to the input of the current comparator; The output of the current comparator is coupled to the input of the buffer; The output terminal of the buffer is the output terminal of the receiver circuit.

8. The display driver chip as described in claim 7, characterized in that, The preamplifier is used to perform preliminary amplification and level conversion on the differential input signal; The hysteresis comparator is used to eliminate input noise interference and convert analog signals into digital levels; The latch is used to latch the digital level; The current comparator is used to perform current domain processing and decision-making on the latched signal. The buffer is used to drive the output.

9. The display driver chip as described in claim 1, characterized in that, The display driver chip also includes a gamma correction circuit, which contains an interpolation operational amplifier module with linear enhancement differential pairs.

10. The display driver chip as described in claim 9, characterized in that, The display driver chip also includes a 4-bit voltage selector, which outputs multiple discrete gamma reference voltages according to the configuration information of the serial interface. The gamma reference voltages are then sent to the interpolation operational amplifier module.

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