Controller and control method for sram erase protection check in mcu architecture

Abstract

This invention discloses a controller and control method for SRAM erase protection verification in an MCU architecture, belonging to the field of memory technology. This invention solves the problem that existing devices cannot simultaneously include multiple functions. By employing an SRAM erase protection verification device, write protection can be configured for each page individually, achieving write protection for SRAM data. The entire SRAM data is erased, and after erasure, write protection and data verification functions continue to be executed, improving read / write efficiency. Furthermore, SRAM data can be verified. When the SRAM controller reads any address, it latches that address and pulls up the read verification flag for that address. Then, an even-number verification is performed on the byte with the verification bit and the latched address. If the verification result is low, the verification passes; otherwise, it indicates a data error, and the error verification result is fed back to the system, thereby meeting the high requirements of the system for the SRAM controller.

Description

Technical Field

[0001] This invention relates to the field of memory technology, specifically to a controller and control method for SRAM erase protection verification in MCU architecture. Background Technology

[0002] Static random access memory (SRAM) is a type of random access memory that retains its data as long as it is powered on. SRAM, on the other hand, is a high-speed, refresh-free memory that offers faster access speeds but is more expensive. It is primarily used for caching or small-capacity applications requiring fast access.

[0003] However, current SRAM control devices do not yet include control logic such as a high-performance bus, write protection control module, checksum module, and erase module.

[0004] Therefore, it does not meet the existing requirements. In response, we propose a controller and control method for SRAM erase protection verification in MCU architecture. Summary of the Invention

[0005] The purpose of this invention is to provide a controller and control method for SRAM erase protection verification in an MCU architecture. By employing an SRAM erase protection verification device, write protection function can be configured for each page individually, thereby achieving write protection for SRAM data and preventing accidental tampering. Simultaneously, the entire SRAM data can be erased, and after erasure, write protection and data verification functions can continue to be executed, thereby improving read / write efficiency. Furthermore, SRAM data can be verified. When the SRAM controller reads any address, it latches that address and pulls up the read verification flag for that address. Then, an even-number verification is performed on the byte with the verification bit and the latched address. If the verification result is low, the verification passes; otherwise, it indicates a data error, and the error verification result is fed back to the system. This meets the high requirements of the system for the SRAM controller and solves the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: The controller for SRAM erase protection verification in the MCU architecture includes: AHB advanced high-performance bus, SRAM controller and SRAM memory; The AHB high-performance bus is configured as a communication channel connecting the processor, memory and high-speed peripherals. It is used to receive commands and data information sent from the processor and return the status information fed back by the SRAM controller to the processor. The SRAM controller is responsible for managing the reading, writing, erasing, and error checking operations of SRAM data. SRAM memory is used to store SRAM data, forming an SRAM database.

[0007] Furthermore, the SRAM controller includes: The erase module is responsible for erasing the entire block of SRAM data. By pre-setting the correct key value, the erase function can be started by writing the correct key value. The write protection module is used to configure write protection for each page of SRAM data individually. If write protection is enabled, no SRAM data can be written to that page. The verification module is responsible for reporting verification error results to the system, promptly detecting and correcting any potential errors.

[0008] Furthermore, the SRAM controller has two functions, including: normal mode and erase mode; In normal mode, when reading and writing SRAM data, performing write protection and data verification functions, the erase mode exits the IDLE state and enters the ERASE state; the write protection and data verification functions are both types of normal mode.

[0009] Furthermore, the SRAM controller has 16 pages of independent write protection, each page being 1KB, for a total of 16KB.

[0010] Furthermore, when the SRAM controller executes the write protection function, based on the write protection control logic, the check bit and data byte of each byte are concatenated, and the SRAM data is written to the corresponding address. When the SRAM controller reads any address, it latches the address, raises the read parity flag of the address, and then performs an even-number check on the byte with the parity bit and the latched address. If the verification result is low, the verification is successful; if it is high, it indicates a data error; and the verification error flag will be reported to the system as a circuit breaker operation for the peripheral device.

[0011] The control method for SRAM erase protection verification in MCU architecture includes the following steps: Step 1: By configuring the communication channels of the AHB (Advanced High-Performance Bus), a communication connection is established between the processor, memory, and high-speed peripherals. The AHB is used to receive commands and data from the processor and upload the status information fed back by the SRAM controller to the processor. Step 2: Configure the SRAM controller as multiple SRAM cells and determine the configuration signal of cfg_sram when the chip is loaded; Step 3: Determine the number of SRAM pages that the SRAM controller writes to and the model number configured for each page, and configure write protection for each page of the SRAM controller individually; if the write protection function of the SRAM controller is enabled, no SRAM data can be written to that page. Step 4: Determine the key value for SRAM controller erasure. When SRAM controller performs an erasure task, write the correct key value to obtain permission to enable the erasure function. Step 5: When the SRAM controller performs the verification function, it writes SRAM data to the address corresponding to the SRAM controller, and the data READYOUT and RESP will be extended by one cycle; it reads the written SRAM data from the address corresponding to the SRAM controller, and the data READYOUT and RESP will be extended by one cycle; if an error occurs in RESP, the error verification result is fed back to the system, and the SRAM data is re-uploaded.

[0012] Furthermore, step three involves configuring write protection for each page of the SRAM controller individually, specifically including the following steps: By configuring write protection for each page of the SRAM controller separately, when the write protection function of the SRAM controller is enabled and the erase function is disabled, the address of the SRAM controller's home page is protected from being written to the SRAM. Similarly, write protection is provided for each page of the SRAM controller.

[0013] Furthermore, step two, which involves configuring the SRAM controller as multiple SRAM cells and determining the cfg_sram configuration signal during chip loading, includes the following steps: In the SRAM controller, set the access permissions and encryption algorithm for each page, and then write the data to be written to the SRAM into the corresponding address of each page in page order. The SRAM data to be read is read out one by one. If an error is detected during the SRAM data reading process, the reading is stopped immediately and the error is reported to the system.

[0014] Furthermore, after the SRAM data is read, the location and content that need to be rewritten are determined according to the error type and location; then the new SRAM data is written to the corresponding address and encrypted again.

[0015] Furthermore, when writing new SRAM data to the corresponding address, the original SRAM data is copied, modified based on the copy, and then parity check is used to repair the error location.

[0016] Compared with the prior art, the beneficial effects of the present invention are: This invention employs an SRAM erase protection verification device, which allows for individual write protection configuration for each page. When write protection is enabled on any page, no data can be written to that page, thus achieving write protection for SRAM data and preventing accidental tampering. Simultaneously, it enables block-level erasure of SRAM data, raising the `ccm_busy` flag during the erasure process and lowering it upon completion, reporting the erasure completion signal to the system. After returning to the `IDLE` state, write protection and data verification functions can continue, improving read / write efficiency. Furthermore, it verifies SRAM data. When the SRAM controller reads any address, it latches that address and raises its read verification flag. An even-number verification is then performed on the byte with the check bit and the latched address. If the verification result is low, the verification passes; otherwise, it indicates a data error, and the error verification result is fed back to the system for other applications, thus meeting the high requirements of the system for the SRAM controller. Attached Figure Description

[0017] Figure 1 A schematic diagram of the overall framework of an existing SRAM controller; Figure 2 This is a control diagram for the SRAM erase signal in one embodiment of the present invention; Figure 3 This is a state machine flowchart of SRAM normal mode and erase mode according to an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] To address the technical issue that current SRAM control devices do not simultaneously include control logic such as a high-performance bus, write protection control module, checksum module, and erase module, please refer to [link to relevant documentation]. Figure 1-3 This embodiment provides the following technical solution: The controller for SRAM erase protection verification in the MCU architecture includes: AHB advanced high-performance bus, SRAM controller and SRAM memory; AHB (Advanced High-Performance Bus) is a high-performance, high-bandwidth bus protocol configured as a communication channel connecting the processor, memory, and high-speed peripherals. It receives commands and data from the processor and returns status information from the SRAM controller to the processor, thereby enabling fast data transfer and communication. Specifically, by employing advanced bus protocols and bus interfaces, it can achieve higher data transfer rates and lower latency.

[0020] The SRAM controller, the core component of the controller, is responsible for managing the reading, writing, erasing, and error checking operations of SRAM data. The SRAM controller includes: The erase module is responsible for erasing the entire SRAM data. By pre-setting the correct key value, the erase function can be started by writing the correct key value. Specifically, the erase function can only be opened by writing the correct key value. If the writing order is incorrect or the wrong key value is written, the erase function's ccmer control signal will not be opened. When the system clock is at 16MHz, the erase module only needs 256us to complete the SRAM data erasure operation.

[0021] The write protection module is designed to ensure that the SRAM controller has page protection capabilities, protecting each page of SRAM data from tampering. The SRAM controller has 16 independent page write protection functions, each page being 1KB, for a total of 16KB. It is used to configure write protection for each page of SRAM data individually. If write protection is enabled, no SRAM data can be written to that page, thus ensuring the security and reliability of the SRAM data. Specifically, the write protection module executes write protection on the SRAM controller, ensuring that data cannot overwrite the data in the SRAM controller, thereby preventing SRAM data tampering. Since the SRAM controller has a 32-bit bus, even parity can be used to perform parity checks on the addresses sram_addr[11:0] and sram_wdata[7:0] as the first byte's parity bit wbyte0_prty, on sram_wdata[15:8] as the second byte's parity bit wbyte1_prty, on sram_wdata[23:16] as the third byte's parity bit wbyte2_prty, and on sram_wdata[31:24] as the fourth byte's parity bit wbyte3_prty; in S... When the RAM controller executes write protection, based on the write protection control logic, it concatenates the parity bit and data byte for each byte and writes the SRAM data to the corresponding address. When the SRAM controller reads any address, it latches that address and pulls up the read parity flag for that address. Then, it performs an even-number check on the byte with the parity bit and the latched address. If the check result is low, the check passes; if it is high, it indicates a data error. The check error flag is then reported to the system as a peripheral circuit breaker operation. Specifically, when the SRAM controller issues an erase command, the verification module parses the command to determine the required... The target address range to be erased is determined; subsequently, the verification module checks the SRAM data from the target address up to the Nth address. If any error is detected, the error type, location, and other relevant information are immediately recorded in the error log and fed back to the system for the relevant applications. If the verification module does not detect any errors, it waits for the erase state to return to the IDLE state after the erasure is complete and continues to execute the write protection and data verification functions. Based on this, the verification module can monitor the usage of the SRAM controller in real time, promptly detect and correct any possible errors, and ensure the normal operation of the system and the security of the data.

[0022] The verification module is responsible for reporting verification error results to the system, promptly detecting and correcting any potential errors.

[0023] Secondly, the SRAM controller has two functions, including: normal mode and erase mode; In normal mode, when reading and writing SRAM data, performing write protection, and data verification, erase mode exits the IDLE state and enters the ERASE state. Furthermore, write protection and data verification are both functions of normal mode. Figure 3 As shown: The erase function will erase 16KB of the entire SRAM area, requiring 4096 cycles to erase the entire SRAM area. During the erase process, the ccm_busy status flag is pulled high; when the erase is complete, the ccm_busy status flag is pulled low and entered into the system register to report that the erase is complete; after the erase module returns to the IDLE state, the write protection function and data verification function continue to be executed.

[0024] SRAM memory is used to store SRAM data, forming an SRAM database. Specifically, the SRAM memory organizes itself into a logical address space according to different application requirements. Each address space includes multiple pages, and each page contains multiple SRAM data. The mapping relationship between pages and SRAM data is stored in the page table within the SRAM memory. Secondly, the SRAM data inside the SRAM memory includes various types of data that need to be stored, such as control instructions, user code, and status information. Each SRAM data includes information such as data length, starting address, and the actual data bytes. Finally, to ensure the reliability of the SRAM data, the SRAM memory also uses error correction coding techniques, such as parity checking, to detect and correct any errors that may exist in the SRAM data.

[0025] To further demonstrate the operation flow of the controller for SRAM erase protection verification in the MCU architecture, this invention also provides a control method for SRAM erase protection verification in the MCU architecture, including the following steps: Step 1: By configuring the communication channels of the AHB (Advanced High-Performance Bus), a communication connection is established between the processor, memory, and high-speed peripherals. The AHB is used to receive commands and data information sent from the processor and to upload the status information fed back by the SRAM controller to the processor, thereby realizing data transmission and sharing. Step 2: Configure the SRAM controller as multiple SRAM cells and determine the configuration signal of cfg_sram during chip loading. The signal can be configured as 8KB or 16KB. This includes the following steps: Configure the access permissions and encryption algorithm for each page in the SRAM controller, then write the data to be written to the SRAM in page order to the corresponding address of each page; and wait for a period of time after each page is written to ensure that all data has been written. The SRAM data to be read is read out one by one. Before each read, a period of time is required to ensure that all relevant pages are in a working state. If an error response, such as an RESP error, is detected during the SRAM data reading process, the reading is stopped immediately and the error is reported to the system. After the SRAM data reading is completed, the location and content to be rewritten are determined according to the error type and location. The new SRAM data is then written to the corresponding address and encrypted again to further ensure the security of the SRAM data and prevent unauthorized access. Next, when writing the new SRAM data to the corresponding address, the original SRAM data is copied and modified based on the copy. This ensures that the modification process does not affect the original SRAM data. Finally, parity checking is used to repair the error location to ensure that if an SRAM data writing error occurs, it can be corrected by subsequent error correction algorithms.

[0026] Step 3: Determine the number of SRAM pages to be written to by the SRAM controller and the model number configured for each page, and configure write protection for each page of the SRAM controller individually; if the write protection function of the SRAM controller is enabled, no SRAM data can be written to that page; specifically, this includes the following steps: By configuring write protection for each page of the SRAM controller individually, when the write protection function of the home page sram_p0wp is enabled and the erase function ccmer is disabled, the address of the home page of the SRAM controller is protected from being written to the SRAM. When the home page 16 of the SRAM controller is enabled, when the write protection function of the page sram_p15wp is enabled and the erase function ccmer is disabled, the address of the home page 16 of the SRAM controller is protected from being written to the SRAM. And so on, providing write protection for each page of the SRAM controller.

[0027] Step 4: Determine the key value for erasing the SRAM controller. When the SRAM controller performs an erasure task, it can obtain permission to enable the erasure function by writing the correct key value. For example, set its start command to write the key value 0xca the first time and the key value 0x53 the second time. It must be executed according to the above preset key value and writing order. If the writing order is incorrect or the wrong key value is written, the erasure function ccmer control signal cannot be enabled.

[0028] Step 5: When the SRAM controller performs the verification function, it writes SRAM data to the corresponding address of the SRAM controller, and the data READYOUT and RESP will be extended by one cycle. It then reads the written SRAM data from the corresponding address of the SRAM controller, and the data READYOUT and RESP will be extended by one cycle. If an error occurs in RESP, the error verification result is fed back to the system, and the SRAM data is re-uploaded. Specifically, during the verification process, if the verification fails, a limited number of retries are allowed. For example, by setting the maximum number of retries to N, if it still fails after N retries, the data is discarded and an error status is returned. This avoids system instability caused by multiple consecutive retries. Each time a data verification error occurs, the error is recorded in a dedicated error log for easy analysis and troubleshooting. When an anomaly is detected, it is immediately reported to the system for notification.

[0029] The technical effect of the above solution is as follows: through the above operation, write protection function can be achieved for SRAM data, preventing accidental tampering, improving read and write efficiency, and meeting the high requirements of the system for the SRAM controller.

[0030] Working Principle: By employing an SRAM erase protection verification device, write protection can be configured for each page individually. When write protection is enabled on any page, no data can be written to that page. Simultaneously, the entire SRAM data can be erased. During the erasure process, the ccm_busy status flag is pulled high. After erasure is complete, the ccm_busy status flag is pulled low, and an erasure completion signal is reported to the system. After returning to the IDLE state after erasure, the write protection and data verification functions continue to be executed. SRAM data can also be verified. When the SRAM controller reads any address, it latches that address and pulls high the read verification flag for that address. Then, an even-number verification is performed on the byte with the check bit and the latched address. If the verification result is low, the verification passes; otherwise, it indicates a data error, and the error verification result is fed back to the system for other applications.

[0031] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0032] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. The controller for SRAM erase protection verification in the MCU architecture includes: AHB advanced high-performance bus, SRAM controller, and SRAM memory, characterized by: The AHB high-performance bus is configured as a communication channel connecting the processor, memory and high-speed peripherals. It is used to receive commands and data information sent from the processor and return the status information fed back by the SRAM controller to the processor. The SRAM controller is responsible for managing the reading, writing, erasing, and error checking operations of SRAM data. SRAM memory is used to store SRAM data, forming an SRAM database.

2. The controller for SRAM erase protection verification in the MCU architecture according to claim 1, characterized in that: The SRAM controller includes: The erase module is responsible for erasing the entire block of SRAM data. By pre-setting the correct key value, the erase function is started by writing the correct key value. The write protection module is used to configure write protection for each page of SRAM data individually. If write protection is enabled, no SRAM data can be written to that page. The verification module is responsible for reporting verification error results to the system, so as to detect and correct potential errors in a timely manner.

3. The controller for SRAM erase protection verification in the MCU architecture according to claim 1, characterized in that: The SRAM controller has two functions, including: normal mode and erase mode; In normal mode, when reading and writing SRAM data, performing write protection and data verification functions, the erase mode exits the IDLE state and enters the ERASE state; the write protection and data verification functions are both types of normal mode.

4. The controller for SRAM erase protection verification in the MCU architecture according to claim 3, characterized in that: The SRAM controller has 16 pages of independent write protection, each page is 1KB, for a total of 16KB.

5. The controller for SRAM erase protection verification in the MCU architecture according to claim 3, characterized in that: When the SRAM controller performs write protection, based on the write protection control logic, the check bit and data byte of each byte are concatenated and the SRAM data is written to the corresponding address. When the SRAM controller reads any address, it latches the address, raises the read parity flag of the address, and then performs an even-number check on the byte with the parity bit and the latched address. If the verification result is low, the verification passes; if it is high, the data is incorrect. The error flag is then reported to the system as a circuit breaker operation for the peripheral device.

6. A control method for SRAM erase protection verification in an MCU architecture, implemented based on the controller for SRAM erase protection verification in an MCU architecture as described in any one of claims 1-5, characterized in that, Includes the following steps: Step 1: By configuring the communication channels of the AHB (Advanced High-Performance Bus), a communication connection is established between the processor, memory, and high-speed peripherals. The AHB is used to receive commands and data from the processor and upload the status information fed back by the SRAM controller to the processor. Step 2: Configure the SRAM controller as multiple SRAM cells and determine the configuration signal of cfg_sram when the chip is loaded; Step 3: Determine the number of SRAM pages that the SRAM controller writes to and the model number configured for each page, and configure write protection for each page of the SRAM controller individually; if the write protection function of the SRAM controller is enabled, no SRAM data can be written to that page. Step 4: Determine the key value for SRAM controller erasure. When SRAM controller performs an erasure task, write the correct key value to obtain permission to enable the erasure function. Step 5: When the SRAM controller performs the verification function, the SRAM data is written to the corresponding address of the SRAM controller, and the data READYOUT and RESP are extended by one cycle. The written SRAM data is read from the address corresponding to the SRAM controller, and the data READYOUT and RESP are extended by one cycle. If an error occurs in RESP, the error verification result is fed back to the system, and the SRAM data is re-uploaded.

7. The control method for SRAM erase protection verification in the MCU architecture according to claim 6, characterized in that: Step three involves configuring write protection for each page of the SRAM controller individually, which specifically includes the following steps: By configuring write protection for each page of the SRAM controller separately, when the write protection function of the SRAM controller is enabled and the erase function is disabled, the address of the SRAM controller's home page is protected from being written to the SRAM.

8. The control method for SRAM erase protection verification in the MCU architecture according to claim 6, characterized in that: Step two, which configures the SRAM controller as multiple SRAM cells and determines the cfg_sram configuration signal during chip loading, includes the following steps: In the SRAM controller, set the access permissions and encryption algorithm for each page, and then write the data to be written to the SRAM into the corresponding address of each page in page order. The SRAM data to be read is read out one by one. If an error is detected during the SRAM data reading process, the reading is stopped immediately and the error is reported to the system.

9. The control method for SRAM erase protection verification in the MCU architecture according to claim 8, characterized in that: After the SRAM data is read, determine the location and content that need to be rewritten based on the error type and location; The new SRAM data is then written to the corresponding address and encrypted again.

10. The control method for SRAM erase protection verification in the MCU architecture according to claim 9, characterized in that: When writing new SRAM data to the corresponding address, the original SRAM data is copied, modified based on the copy, and then parity check is used to repair the error location.

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