Voltage control circuits, memory systems, and voltage control methods

Abstract

This disclosure provides a voltage control circuit, a memory system, and a voltage control method. The voltage control circuit includes a first sub-voltage control circuit and a second sub-voltage control circuit. The first sub-voltage control circuit is coupled to a first power supply pin and a first voltage node, and the second sub-voltage control circuit is coupled to a second power supply pin and the first voltage node. The first sub-voltage control circuit outputs a first target voltage in response to a first voltage signal received from the first power supply pin as a first power supply voltage, while the second sub-voltage control circuit disconnects a first current path between the second power supply pin and the first voltage node in response to a first control signal. Alternatively, the second sub-voltage control circuit outputs a first target voltage in response to a second voltage signal received from the second power supply pin as a second power supply voltage, while the first sub-voltage control circuit disconnects a second current path between the first power supply pin and the first voltage node in response to a second control signal.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to voltage control circuits, memory systems, and voltage control methods. Background Technology

[0002] Universal Flash Storage (UFS) uses serial data transmission technology and operates in full-duplex mode, allowing both read and write data transmission on the same channel. Furthermore, UFS supports multi-channel data transmission, enabling simultaneous read and write data transmission on multiple channels, resulting in high transmission efficiency and making it suitable for mobile devices such as smartphones, tablets, and computers. Mobile devices and UFS products can communicate via the UFS protocol. However, due to the rapid development of mobile devices, different devices may follow different UFS protocols and provide different power supply methods to UFS products. Therefore, storage manufacturers need to prepare UFS products with multiple power supply options, leading to higher development costs. Summary of the Invention

[0003] This disclosure provides a voltage control circuit, a memory system, and a voltage control method.

[0004] The first aspect of this disclosure provides a voltage control circuit, comprising:

[0005] The first sub-voltage control circuit is coupled to the first power supply pin and the first voltage node;

[0006] The second sub-voltage control circuit is coupled to the second power supply pin and the first voltage node;

[0007] Wherein, the first sub-voltage control circuit is configured to: output a first target voltage in response to a first voltage signal received from the first power supply pin as a first power supply voltage; simultaneously, the second sub-voltage control circuit is configured to: disconnect a first current path between the second power supply pin and the first voltage node in response to a first control signal; and / or,

[0008] The second sub-voltage control circuit is configured to: output the first target voltage in response to a second voltage signal received by the second power supply pin as a second power supply voltage; simultaneously, the first sub-voltage control circuit is configured to: disconnect the second current path between the first power supply pin and the first voltage node in response to a second control signal.

[0009] A second aspect of this disclosure provides a memory system comprising: a voltage control circuit, the voltage control circuit comprising:

[0010] The first sub-voltage control circuit is coupled to the first power supply pin and the first voltage node;

[0011] The second sub-voltage control circuit is coupled to the second power supply pin and the first voltage node;

[0012] Wherein, the first sub-voltage control circuit is configured to: output a first target voltage in response to a first voltage signal received from the first power supply pin as a first power supply voltage; simultaneously, the second sub-voltage control circuit is configured to: disconnect a first current path between the second power supply pin and the first voltage node in response to a first control signal; and / or,

[0013] The second sub-voltage control circuit is configured to: output the first target voltage in response to a second voltage signal received by the second power supply pin as a second power supply voltage; simultaneously, the first sub-voltage control circuit is configured to: disconnect the second current path between the first power supply pin and the first voltage node in response to a second control signal.

[0014] A third aspect of this disclosure provides a voltage control method applied to a memory system, the memory system comprising: a first sub-voltage control circuit coupled to a first power supply pin and a first voltage node, and a second sub-voltage control circuit coupled to a second power supply pin and the first voltage node; the voltage control method comprising:

[0015] The first sub-voltage control circuit, in response to a first voltage signal received at the first power supply pin being a first power supply voltage, outputs a first target voltage; simultaneously, the second sub-voltage control circuit, in response to a first control signal, disconnects the first current path between the second power supply pin and the first voltage node; and / or,

[0016] The second sub-voltage control circuit responds to the second voltage signal received by the second power supply pin as the second power supply voltage and outputs the first target voltage; at the same time, the first sub-voltage control circuit responds to the second control signal and disconnects the second current path between the first power supply pin and the first voltage node.

[0017] In this disclosure, at least one of the first power supply voltage and the second power supply voltage received by the voltage control circuit is different from the first target voltage, and the voltage control circuit can adjust both the first power supply voltage and the second power supply voltage to the first target voltage. Therefore, when a memory system including the voltage control circuit is integrated into an application platform, regardless of whether the application platform's power supply scheme provides the first power supply voltage to the first power supply pin or the second power supply pin, the voltage control circuit within the memory system can provide the first target voltage to the device. In this way, one memory system can simultaneously support two power supply schemes without requiring two separate memory systems for each scheme, thereby reducing R&D investment, saving R&D costs, and improving the product's platform compatibility and competitiveness. Attached Figure Description

[0018] Figure 1a A block diagram of an exemplary system including a memory, provided for embodiments of this disclosure.

[0019] Figure 1b This is a schematic diagram of a memory card provided in an embodiment of the present disclosure.

[0020] Figure 1c This is a schematic diagram of an SSD provided in an embodiment of the present disclosure.

[0021] Figure 2 This is a schematic diagram of a memory device including peripheral circuitry provided for an embodiment of this disclosure.

[0022] Figure 3 A schematic diagram of the peripheral circuit provided in an embodiment of this disclosure.

[0023] Figure 4 This is a schematic diagram of a memory system including a memory controller, provided for an embodiment of this disclosure.

[0024] Figure 5 This is a schematic diagram of a memory system product provided in an embodiment of the present disclosure.

[0025] Figure 6 A schematic diagram of another memory system product provided for implementation of this disclosure.

[0026] Figure 7 A schematic diagram of a memory system including a voltage control circuit provided for an embodiment of this disclosure.

[0027] Figure 8 A schematic diagram of a voltage control circuit provided in an embodiment of this disclosure.

[0028] Figure 9 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 2 .

[0029] Figure 10 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 3 .

[0030] Figure 11 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 4 .

[0031] Figure 12 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 5 .

[0032] Figure 13 A schematic diagram of a memory system including a voltage control circuit provided for embodiments of this disclosure. Figure 2 .

[0033] Figure 14 A schematic diagram of a memory system including a voltage control circuit provided for embodiments of this disclosure. Figure 3 .

[0034] Figure 15 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 6 .

[0035] Figure 16 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 7 .

[0036] Figure 17 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 8 .

[0037] Figure 18 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 9 .

[0038] Figure 19 A schematic diagram of a memory system including a voltage control circuit provided for embodiments of this disclosure. Figure 4 .

[0039] Figure 20 A schematic diagram of a memory system including a voltage control circuit provided for embodiments of this disclosure. Figure 5 .

[0040] Figure 21 This is a schematic diagram of a general-purpose flash memory provided in an embodiment of this disclosure.

[0041] Figure 22 A schematic flowchart of the voltage control method provided in this embodiment is shown below.

[0042] Figure 23 Flowchart of the voltage control method provided in the embodiments of this disclosure Figure 2 .

[0043] Figure 24 Flowchart of the voltage control method provided in the embodiments of this disclosure Figure 3 .

[0044] Figure 25 Flowchart of the voltage control method provided in the embodiments of this disclosure Figure 4 .

[0045] Figure 26 Flowchart of the voltage control method provided in the embodiments of this disclosure Figure 5 .

[0046] Figure 27 Flowchart of the voltage control method provided in the embodiments of this disclosure Figure 6 . Detailed Implementation

[0047] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0048] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0049] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0050] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0052] Figure 1a This is a block diagram of an exemplary system including memory, provided for embodiments of the present disclosure. The exemplary system 10 may include a host 11 and a memory system 12. The exemplary system 10 may include, but is not limited to, a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device 22 therein; the host 11 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)).

[0053] In one embodiment of this disclosure, the host 11 may be configured to send data to or receive data from the memory system 12. Here, the memory system 12 may include a memory controller 21 and one or more memory devices 22. The memory device 22 may include, but is not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), and nano random access memory (NRAM).

[0054] In one embodiment of this disclosure, a memory controller 12 may be coupled to the memory device 22 and the host 11 and is used to control the memory device 22. Exemplarily, the memory controller 21 may be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, and mobile phones. In some embodiments, the memory controller 21 may also be designed to operate in a high duty cycle environment, such as a Solid State Disk (SSD) or an embedded Multi-Media Card (eMMC), and the SSD or eMMC may be used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0055] Furthermore, the memory controller 21 can manage the data in the memory device 22 and communicate with the host. The memory controller 21 can be configured to control operations such as reading, erasing, and programming of the memory device 22; it can also be configured to manage various functions related to data stored or to be stored in the memory device 22, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.; and it can also be configured to process error checking and correction (ECC) codes related to data read from or written to the memory device 22. In addition, the memory controller 21 can perform any other suitable functions, such as formatting the memory device 22, or communicating with external devices (e.g., according to a specific communication protocol) according to a specific communication protocol. Figure 1a Communication with the host 11). For example, the memory controller 21 can communicate with the external host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI-E protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Development Equipment (IDE) protocol, FireWire protocol, etc.

[0056] In one embodiment of this disclosure, the memory controller 21 and one or more memory devices 22 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 1bAs shown, the memory controller 21 and a single memory device 22 can be integrated together to form a memory card 30. The memory card 30 may include PC cards (Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, Multimedia Cards (MMC, RS-MMC (Reduced-Size MMC), MMCmicro), SD cards (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), UFS, etc. The memory card 30 may also include a connector for connecting the memory card 30 to a host computer (e.g., Figure 1a The host 11) is coupled to the memory card connector 31. In such a way... Figure 1c In another embodiment shown, the memory controller 21 and a plurality of memory devices 22 may be integrated together to form an SSD 40. The SSD 40 may also include a connection between the SSD 40 and a host (e.g., Figure 1a The host 11 is coupled to the SSD connector 41. In some embodiments, the storage capacity and / or operating speed of the SSD 40 is greater than that of the memory card 30.

[0057] It should be noted that the memory involved in one embodiment of this disclosure can be a semiconductor memory, which is a solid-state electronic device for storing data information manufactured using semiconductor integrated circuit technology. Figure 2 This is a schematic diagram of a memory device including peripheral circuitry provided in an embodiment of the present disclosure, wherein the memory device 50 may be... Figures 1a to 1c Memory device 22 in the middle. For example Figure 2 As shown, the memory device 50 may include a memory cell array 51 and peripheral circuitry 52 coupled to the memory cell array 51. Here, the memory cell array may be a NAND flash memory cell array, wherein the memory cells are arranged in the form of an array of NAND memory strings 53, each NAND memory string 53 extending vertically above the substrate. In some embodiments, each NAND memory string 53 may include a plurality of memory cells 54 coupled in series and stacked vertically. Each memory cell 54 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the memory cell region. Additionally, each memory cell 54 in the aforementioned memory cell array 51 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0058] In one embodiment of this disclosure, the memory cell 54 may be a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first threshold voltage range, and a second storage state "1" may correspond to a second threshold voltage range. In other embodiments, each memory cell 54 may be a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC may store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to a range of possible nominal storage values. Exemplarily, if each MLC stores two bits of data, the MLC may be programmed to change from an erase state to one of three possible storage states by writing one of the three possible nominal storage values ​​to the memory cell. A fourth nominal storage value may be used for the erase state.

[0059] like Figure 2 As shown, each NAND memory string 53 may include a source select transistor 55 at its source terminal and a drain select transistor 56 at its drain terminal. The source select transistor 55 may also be referred to as the lower select transistor, and the drain select transistor 56 may also be referred to as the upper select transistor. The source select transistor 55 and the drain select transistor 56 may be configured to activate the selected NAND memory string 53 (column of the array) during read and program operations.

[0060] In some implementations, the sources of NAND memory strings 53 within the same block 57 are coupled via a common source line (SL) 61 (e.g., a common source line). In other words, according to some implementations, all NAND memory strings 53 within the same block 57 have an array common source (ACS). According to some implementations, the drain selection transistor 56 of each NAND memory string 53 is coupled to a corresponding bit line 62, allowing data to be read from or written to the bit line 62 via an output bus (not shown).

[0061] In some embodiments, each NAND memory string 53 is configured to be selected or deselected by applying a selection voltage (e.g., higher than a threshold voltage having a drain-select transistor 56) or a deselect voltage (e.g., 0V) to the gate of the corresponding drain-select transistor 56 via one or more drain-select gate lines (DSG lines) 63; and / or by applying a selection voltage (e.g., higher than a threshold voltage having a source-select transistor 55) or a deselect voltage (e.g., 0V) to the gate of the corresponding source-select transistor 55 via one or more source-select gate lines 64. The NAND memory strings 53 can thus be distinguished as selected NAND memory strings or unselected NAND memory strings. The selection voltage can also be referred to as a control turn-on voltage, used to turn on the corresponding transistor, and the deselect voltage can also be referred to as a control turn-off voltage, used to turn off the corresponding transistor.

[0062] In some embodiments, memory cells 54 of adjacent NAND memory strings 53 can be coupled via word lines 65, which select which row of memory cells 54 is affected by read and program operations.

[0063] like Figure 2 As shown, peripheral circuitry 52 can be coupled to memory cell array 51 via bit line 62, word line 65, source line 61, source select gate line 64, and drain select gate line 63. Peripheral circuitry 52 can include any suitable analog, digital, and mixed-signal circuitry for implementing write and read operations on memory cell array 51 by applying voltage and / or current signals to each target memory cell 54 via bit line 62, word line 65, source line 61, source select gate line 64, and drain select gate line 63, and by sensing voltage and / or current signals from each target memory cell 54. Peripheral circuitry 52 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 This is a schematic diagram of the peripheral circuitry provided in an embodiment of the present disclosure. The peripheral circuitry includes a page buffer / sensor amplifier 71, a column decoder / BL driver 72, a row decoder / WL driver 73, a voltage generator 74, a control logic unit 75, a register 76, an input / output 77, and a data bus 78. It should be understood that in some examples, it may also include... Figure 3 Additional peripheral circuitry not shown.

[0064] Page buffer / sensor amplifier 71 can be configured to read data from memory cell array 51 and program (write) data to memory cell array 51 according to control signals from control logic unit 75. In one example, page buffer / sensor amplifier 71 can store a page of programming data (write data) to be programmed into a page of memory cell array 51. In another example, page buffer / sensor amplifier 71 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 54 coupled to selected word line 65. In yet another example, page buffer / sensor amplifier 71 can also sense a low-power signal from bit line 62 representing a data bit stored in memory cell 54 and amplify a small voltage swing to a recognizable logic level during a read operation.

[0065] The column decoder / BL driver 72 can be configured to be controlled by the control logic unit 75 and to select one or more NAND memory strings 53 by applying a bit line voltage generated from the voltage generator 74.

[0066] The row decoder / word WL driver 73 can be configured to be controlled by the control logic unit 75, and to select / deselect block 57 of the memory cell array 51, and select / deselect word lines 65 in block 57, according to control signals generated by the control logic unit. The row decoder / WL driver 73 can also be configured to drive word lines 65 using different word line voltages generated from the voltage generator 74. In some embodiments, the row decoder / WL driver 73 can also select / deselect source select gate line 64 and drain select gate line 63. The row decoder / WL driver 73 is configured to drive source select gate line 64 using different SSG line voltages generated from the voltage generator 74, and / or drive drain select gate line 63 using different DSG line voltages generated from the voltage generator 74.

[0067] The voltage generator 74 can be configured to be controlled by the control logic unit 75 and generate various word line voltages (e.g., read voltage, program voltage, pass voltage, verification voltage, etc.), bit line voltages, ground voltages, various SSG line voltages (e.g., select voltage, deselect voltage) and various DSG line voltages (e.g., select voltage, deselect voltage) to be supplied to the memory cell array 51.

[0068] Control logic unit 75 can be coupled to each of the peripheral circuit sections described above and is configured to control the operation of each peripheral circuit section. Register 76 can be coupled to control logic unit 75 and includes a status register, a command register, and an address register to store status information, command opcodes, and command addresses for controlling the operation of the peripheral circuits. In some embodiments, control logic unit 75 can receive commands from a memory controller (e.g., Figures 1a to 1c The memory controller 21 in any one of the circuits issues programming commands and sends control signals to various peripheral circuit sections, such as row decoder / WL driver 73, column decoder / BL driver 72 and voltage generator 74, to perform programming operations on the source selection transistor coupled to the source selection gate line.

[0069] Input / output (I / O) 77 can be coupled to control logic unit 75 and act as a control buffer to buffer control commands (e.g., programming commands) received from memory controller or host and relay them to control logic unit 75, as well as to buffer status information received from control logic unit 75 and relay it to memory controller or host. I / O 77 can also be coupled to column decoder / BL driver 72 via data bus 78 and act as a data input / output interface and data buffer to buffer data and relay it to or from memory cell array 51.

[0070] Figure 4 This is a schematic diagram of a memory system including a memory controller provided in an embodiment of the present disclosure, wherein the memory system 13 may be... Figure 1a Memory system 12 Figure 1b Memory card 30 in Figure 1c The SSD 40 and storage system 13 can also be general-purpose flash storage (UFS), etc. Figure 4 As shown, the memory system 13 may include a memory device 50 and a host coupled to the memory device 50 and a host (e.g., Figure 1a The host 11 in the system has a memory controller 80. The memory controller 80 may include a processor 81, a front-end I / O 82, and a back-end I / O 83. The front-end I / O 82 communicates with the host, receives commands and data information sent by the host, and parses the commands. The front-end I / O 82 and the host can communicate via PCIe protocol, NVMe (Non-Volatile Memory Express) protocol, UFS protocol, etc.

[0071] Back-end I / O 83 is used to manage data writing to or reading from memory device 50. The peripheral circuitry of memory device 50 includes I / O (e.g., ...). Figure 3The input / output 77 in the memory system 13 allows communication between the I / O in the peripheral circuitry and the back-end I / O 83 in the memory controller via protocols such as ONFI (Opening NAND Flash Interface) and Toggle. For example, the back-end I / O 83 of the memory controller can be configured with multiple channels, coupled to multiple memory devices 50, to control data reading and writing to the multiple memory devices. The processor 81 is coupled to the front-end I / O 82 and the back-end I / O 83, and can control the overall operation of the memory system 13. The processor 81 can use firmware to control the overall operation of the memory system 13, such as performing tasks like garbage collection, wear leveling, bad block management, and read interference management.

[0072] Universal flash memory (UFS) is a memory system that encapsulates flash memory chips (such as NAND flash memory chips, or memory devices) and a flash memory controller (such as a memory controller) together. UFS communicates with the host via the Universal Flash Memory (UFS) standard, enabling the host to access data. Early UFS standards specified three power supply voltages: Vcc, Vccq, and Vccq2. Vcc powers the flash memory chips, Vccq powers the flash input / output and controller core, and Vccq2 powers low-voltage modules such as the M-PHY.

[0073] The controller core can handle various operations for performing memory operations on a memory device. In some embodiments, the controller core can decrypt commands from the host and handle various operations such as memory allocation, signal generation, and storing and retrieving data for memory operations (e.g., read, write, or erase operations) corresponding to commands. For example, the controller core may be... Figure 4 The processor 81 in the system.

[0074] The UFS standard comprises the UFS Command Set Layer (USC), the UFS Transport Layer (UTP), and the UFS Interconnect Layer (UIC). The UIC further includes a link layer and a physical layer (M-PHY). The physical layer of the UIC is defined according to the MIPI (Mobile Industry Processor Interface) specification.

[0075] M-PHY is front-end I / O (e.g., Figure 4The physical layer module (M-PHY) in the front-end I / O (82) of the memory controller enables the interconnection between the host and the memory system at the physical layer. The M-PHY of the memory controller includes a transmitter and a receiver, which are coupled to the receiver and transmitter in the M-PHY layer of the host to establish a data channel with the host for data transmission and reception.

[0076] With the continuous iteration of UFS products, in some UFS products, such as those based on the UFS 2.2 standard, the power supply scheme has changed to Vcc = 3.3V and Vccq2 = 1.8V. Figure 5 This is a schematic diagram of a memory system product provided in an embodiment of the present disclosure. Figure 5 The M-PHY 91, controller core 92, memory device I / O 93, and four voltage regulators LDO1, LDO2, LDO3, and LDO4, which are not included in memory device 94, all belong to the memory controller. For example... Figure 5 As shown, Vcc is 3.3V, which is stepped down to 2.5V by voltage regulator LDO4 to power the peripheral circuits 96 in memory device 94, excluding memory device I / O (input / output) 95. Vccq2 is 1.8V, which is stepped down to 0.8V by voltage regulator LDO1 to power low-voltage modules such as M-PHY 91, stepped down to 0.8V by voltage regulator LDO2 to power the controller core 92, and stepped down to 1.2V by voltage regulator LDO3 to power the memory device I / O 93 in the memory controller and the memory device I / O 95 in memory device 94.

[0077] In some newer generation UFS products, such as those based on the UFS 3.1 standard, the power supply scheme has changed to Vcc = 2.5V and Vccq = 1.2V. Figure 6 This is a schematic diagram of another memory system product provided in an embodiment of the present disclosure. Figure 6 The M-PHY 91, controller core 92, memory device I / O 93, and two voltage regulators LDO1 and LDO2, which are not included in memory device 94, all belong to the memory controller. Figure 6 As shown, Vcc is 2.5V, directly powering the peripheral circuits 96 in memory device 94 except for memory device I / O 95. Vccq is 1.2V, directly powering memory device I / O 95 in memory device 94, and also powering low-voltage modules such as M-PHY91 after being stepped down to 0.8V by voltage regulator LDO1, and powering the controller core 92 after being stepped down to 0.8V by voltage regulator LDO2. Memory device I / O 93 in the memory controller can also be powered by Vccq. For example, Figure 5 and Figure 6The memory device I / O 93 within the memory controller can be Figure 4 Backend I / O 83. Figure 5 and Figure 6 The memory device I / O 95 within the memory device 94 can be Figure 3 Input / output 77. Figure 5 and Figure 6 The memory device I / O 95 and peripheral circuitry 96 within the memory device 94 share a common structure. Figure 2 or Figure 4 The peripheral circuit 52 shown is illustrated.

[0078] The two UFS products are from adjacent generations and should ideally be interchangeable. However, due to significant differences in power supply schemes, application platforms (such as mobile phone motherboards) cannot switch between Vcc voltage and Vccq / Vccq2. Designing application platforms compatible with both generations of UFS products would incur substantial additional costs. Therefore, the typical solution is for storage companies to design two UFS products for the same generation of NAND flash memory, supplying different customers and application platforms.

[0079] In addition, when designing two UFS products, we wanted to quickly complete the design of the previous generation UFS product using the controller of the more mature and newer generation UFS product. However, there are some problems: First, it is necessary to redesign the packaging scheme, such as adding voltage regulators LDO3 and LDO4, which will increase the design cost; Second, although the newer generation product is more mature, if we want to design the previous generation product using the same controller, the usual practice is to start from the packaging design, start a new project, and go through trial production, testing, debugging, etc., which consumes a lot of manpower and resources.

[0080] Therefore, embodiments of this disclosure provide a memory system that can simultaneously support the two power supply schemes described above. Figure 7 A schematic diagram of a memory system including a voltage control circuit provided in an embodiment of this disclosure is shown below. Figure 7 As shown, the memory system 1000 includes a first device 210 and a voltage control circuit 100. The first device 210 is coupled to a first voltage node Node1. The voltage control circuit 100 includes a first sub-voltage control circuit 110 and a second sub-voltage control circuit 120. The first sub-voltage control circuit 110 is coupled to a first power supply pin Vccq2 and the first voltage node Node1, and the second sub-voltage control circuit 120 is coupled to a second power supply pin Vccq and the first voltage node Node1.

[0081] The first sub-voltage control circuit 110 is configured to: output a first target voltage (e.g., 1.2V) in response to a first voltage signal received at the first power supply pin Vccq2 being a first power supply voltage (e.g., 1.8V); simultaneously, the second sub-voltage control circuit 120 is configured to: disconnect a first current path between the second power supply pin Vccq and the first voltage node Node1 in response to a first control signal En_1. And / or, the second sub-voltage control circuit 120 is configured to: output a first target voltage in response to a second voltage signal received at the second power supply pin Vccq being a second power supply voltage (e.g., 1.2V); simultaneously, the first sub-voltage control circuit 110 is configured to: disconnect a second current path between the first power supply pin Vccq2 and the first voltage node Node1 in response to a second control signal En_2.

[0082] The first target voltage is the operating voltage of the first device 210. At least one of the first power supply voltage and the second power supply voltage differs from the first target voltage, and the purpose of the voltage control circuit is to adjust both the first power supply voltage and the second power supply voltage to the first target voltage. Therefore, when the memory system is integrated into an application platform, regardless of whether the application platform's power supply scheme provides the first power supply voltage to the first power supply pin or the second power supply pin, the voltage control circuit within the memory system can provide the first target voltage to the first device. In this way, one memory system can be compatible with two power supply schemes without requiring two separate memory systems for each scheme, thereby reducing R&D investment, saving R&D costs, and improving the product's platform compatibility and competitiveness.

[0083] In some embodiments, the application platform's power supply scheme is fixed; that is, the application platform can only select either power supply scheme one or power supply scheme two. In power supply scheme one, the application platform provides a first power supply voltage to the first power supply pin, and the memory system correspondingly and fixedly selects the first sub-voltage control circuit to output the first target voltage. In power supply scheme two, the application platform provides a second power supply voltage to the second power supply pin, and the memory system correspondingly and fixedly selects the second sub-voltage control circuit to output the first target voltage. In other embodiments, if the application platform can switch between power supply scheme one and power supply scheme two, the memory system can correspondingly switch between selecting the first sub-voltage control circuit and the second sub-voltage control circuit to output the first target voltage.

[0084] See also Figure 7In power supply scheme one, while the first sub-voltage control circuit 110 outputs the first target voltage, the second sub-voltage control circuit 120, under the action of the first control signal En1, disconnects the first current path between the second power supply pin Vccq and the first voltage node Node1. This is to prevent the second voltage signal of the second power supply pin Vccq from affecting the voltage of the first voltage node Node1 and causing additional voltage rise or drop, thus preventing the accurate output of the first target voltage. For example, Figure 7 In this configuration, when the first power supply pin Vccq2 receives the first power supply voltage, the input voltage of the second power supply pin Vccq is 0V. At this time, if the first current path is not interrupted, current may flow from the first voltage node to the second power supply pin, causing a voltage drop at the first voltage node. In other words, interrupting the first current path from the second power supply pin to the first voltage node effectively prevents current from flowing back from the first voltage node to the second power supply pin, avoiding an additional voltage drop.

[0085] The first control signal En_1 can be generated internally by the memory system or provided by the application platform. In some embodiments, the first control signal En_1 is generated internally by the memory system. For example, when power supply scheme one is determined to be used, the controller within the memory system can control the disconnection of the first current path via the first control signal En_1.

[0086] In other embodiments, the first control signal En_1 is provided by the application platform. For example, the first control signal En_1 is a second voltage signal received from the second power supply pin, and the second sub-voltage control circuit 120 disconnects the first current path in response to the second voltage signal being a first idle voltage.

[0087] In power supply scheme one, the application platform synchronously provides a first power supply voltage to the first power supply pin Vccq2 and a first idle voltage (e.g., 0V) to the second power supply pin Vccq. Upon receiving the first idle voltage, the second sub-voltage control circuit 120 disconnects the first current path. This configuration eliminates the need for additional control circuitry and signals within the application platform and memory system, simplifying circuit design and minimizing modifications to existing products, thus saving on testing and debugging costs.

[0088] It should be understood that, in another example, the first control signal En_1 could also be a first voltage signal received by the first power supply pin, and the second sub-voltage control circuit 120 would disconnect the first current path in response to the first voltage signal being the first power supply voltage. That is, when the application platform provides the first power supply voltage to the first power supply pin, the first sub-voltage control circuit 110 outputs the first target voltage, while the second sub-voltage control circuit 120 simultaneously disconnects the first current path. This configuration eliminates the need for additional control circuitry and control signals within the application platform and memory system, simplifying circuit design and saving area.

[0089] See also Figure 7 In power supply scheme two, while the second sub-voltage control circuit 120 outputs the first target voltage, the first sub-voltage control circuit 110, under the action of the second control signal En_2, disconnects the second current path between the first power supply pin Vccq2 and the first voltage node Node1. This is to prevent the first voltage signal of the first power supply pin Vccq2 from affecting the voltage of the first voltage node Node1 and causing additional voltage rise or drop, thus preventing the accurate output of the first target voltage. For example, Figure 7 In this embodiment, when the second power supply pin Vccq receives the second power supply voltage (e.g., 1.2V), the input voltage of the first power supply pin Vccq2 is 0V. At this time, if the first current path is not interrupted, current may flow from the first voltage node Node1 to the first power supply pin Vccq2, causing a voltage drop at the first voltage node Node1. In this embodiment, interrupting the second current path from the first power supply pin Vccq2 to the first voltage node Node1 effectively prevents current from flowing back from the first voltage node Node1 to the first power supply pin Vccq2, thus avoiding an additional voltage drop.

[0090] The second control signal En_2 can be provided by the application platform or by the memory system itself. In some embodiments, the second control signal is generated internally by the memory system. For example, when power supply scheme two is determined to be used, the controller within the memory system can control the disconnection of the second current path via the second control signal En_2.

[0091] In other embodiments, the second control signal En_2 is provided by the application platform. For example, the second control signal En_2 is a first voltage signal received from the first power supply pin, and the first sub-voltage control circuit 110 disconnects the second current path in response to the first voltage signal being a second idle voltage.

[0092] In this embodiment, the second control signal En_2 is not an additional signal provided by the application platform. Instead, it utilizes the second idle voltage synchronously received from the first power supply pin Vccq2 to control the disconnection of the second current path. This eliminates the need for additional control circuitry or signals within the application platform and memory system, simplifying circuit design and minimizing modifications to existing products, thus saving on testing and debugging costs. For example, the second idle voltage is the ground voltage, 0V.

[0093] It should be understood that, in another example, the second control signal En_2 could also be a second voltage signal. Specifically, the first sub-voltage control circuit 110 is also coupled to the second power supply pin Vccq, and in response to the second voltage signal being the second power supply voltage, disconnects the second current path. This configuration eliminates the need for additional control circuitry and control signals within the application platform and memory system, simplifying circuit design and saving area.

[0094] It should be noted that, in actual operation, in a specific implementation, the first control signal En_1 can be the first control signal in any of the above embodiments, and the second control signal En_2 can be the second control signal in any of the above embodiments; this disclosure does not impose any limitations on this. For example, in implementation one, the first control signal En_1 can be a second voltage signal, and the second control signal En_2 can be a first voltage signal. In implementation two, both the first control signal En_1 and the second control signal En_2 are first voltage signals. In implementation three, both the first control signal En_1 and the second control signal En_2 are second voltage signals. In implementation four, the first control signal En_1 can be a first voltage signal, and the second control signal En_2 can be a second voltage signal.

[0095] Figure 8 A schematic diagram of a voltage control circuit provided in an embodiment of this disclosure. In some embodiments, such as Figure 8 As shown, the first sub-voltage control circuit includes: a first voltage regulator 111, the input terminal of the first voltage regulator 111 is coupled to a first power supply pin Vccq2, and the output terminal of the first voltage regulator 111 is coupled to a first voltage node Node1; the first voltage regulator 111 is configured to: in response to a first voltage signal being a first power supply voltage, convert the first power supply voltage into a first target voltage.

[0096] In this embodiment, the first power supply voltage is different from the first target voltage. Typically, the first power supply voltage is greater than the first target voltage. For example, Figure 8As shown, the first supply voltage is 1.8V and the first target voltage is 1.2V. The first voltage regulator can be any voltage regulator commonly used in the art, and this disclosure is not limited thereto. For example, the first voltage regulator can be a low-dropout linear regulator (LDO).

[0097] In some embodiments, such as Figure 8 As shown, the second sub-voltage control circuit includes: a first switch 121, the first terminal Vin and the control terminal EN of the first switch 121 being coupled to the second power supply pin Vccq, and the second terminal Vout of the first switch 121 being coupled to the first voltage node Node1. The first switch 121 is configured to be in an open state in response to the second voltage signal being a first idle voltage, thereby disconnecting the first current path.

[0098] In this embodiment, the control terminal EN of the first switch is coupled to the second power supply pin Vccq, meaning that the first control signal En_1 is the second voltage signal. When the second voltage signal is the first idle voltage (e.g., ground voltage), the first switch is in the open state, which disconnects the second power supply pin from the first voltage node, effectively preventing the current from the first voltage node from flowing back to the second power supply pin Vccq without generating an additional voltage drop.

[0099] The first switch 121 is a load switch; its basic principle is to turn the power supply on and off through control pins. For example... Figure 4 As shown, a load switch typically includes four pins: a control pin (EN), an input voltage pin (Vin), an output voltage pin (Vout), and a ground pin (GND). The ground pin (GND) is grounded. However, some load switches may not have a ground pin (GND). For example, the first switch is an N-channel field-effect transistor, or NMOS transistor for short. When the control terminal of the NMOS transistor receives a low voltage less than its threshold voltage, the NMOS transistor is in the off state. In this embodiment, the threshold voltage of the NMOS transistor is greater than a first idle voltage.

[0100] In power supply scheme one, the first power supply pin receives a first power supply voltage (e.g., 1.8V), and the first voltage regulator converts the first power supply voltage into a first target voltage (e.g., 1.2V); at the same time, the second power supply pin receives a first idle voltage (e.g., 0V), and the first switch is in the off state in response to the first idle voltage, so that the first voltage node has the first target voltage of 1.2V.

[0101] In some embodiments, the first switch 121 is configured to be in an on state in response to a second voltage signal being a second power supply voltage, so as to output the second power supply voltage as a first target voltage. The first voltage regulator 111 is configured to stop operating in response to a first voltage signal being a second idle voltage, so as to disconnect a second current path; wherein the second idle voltage is outside the input range of the first voltage regulator.

[0102] See also Figure 8 The second sub-voltage control circuit provided in this embodiment is applicable when the second power supply voltage is equal to the first target voltage. For example... Figure 8 In this configuration, both the second power supply voltage and the first target voltage are 1.2V. When the second power supply pin Vccq receives the second power supply voltage (e.g., 1.2V), the first switch 121 is turned on, and the second power supply voltage is output as the first target voltage.

[0103] The selection of the first voltage regulator 111 satisfies the following condition: the second idle voltage is outside the input voltage range of the first voltage regulator. That is, when the input terminal of the first voltage regulator is the second idle voltage, the first voltage regulator cannot operate. At this time, there is no current between the input and output terminals of the first voltage regulator, and the second current path can be considered disconnected. In this embodiment, the second idle voltage is the ground voltage 0V. The first voltage regulator does not operate and will not affect the voltage magnitude of the first voltage node. In this embodiment, the second control signal En_2 can be considered as the first voltage signal. The first voltage signal can control the first voltage regulator to stop operating and disconnect the second current path.

[0104] In some embodiments, such as Figure 9 As shown, the first voltage regulator is an LDO 111 with an enable terminal EN. The enable terminal EN of the LDO 111 controls whether the LDO 111 is operating or de-operating. For example, the enable terminal of the LDO 111 is active high; it operates when it receives a high level (e.g., greater than 1.2V) and de-operates when it receives a low level (e.g., 0V). Figure 9 As shown, the enable pin EN of the LDO 111 can be directly connected to its input, or in other examples, the enable pin EN can be connected to its input after a series resistor. This way, the LDO 111 operates when the first power supply pin Vccq2 receives the first power supply voltage, and stops operating and disconnects the second current path when the first power supply pin receives the second idle voltage. In practical applications, either type of LDO can be selected as needed.

[0105] In summary, in the power supply scheme 2, the second power supply pin Vccq receives a second power supply voltage (e.g., 1.2V), the first switch is turned on in response to the second power supply voltage, and outputs a first target voltage (e.g., 1.2V) equal to the second power supply voltage. The input of the first voltage regulator receives a second idle voltage (e.g., 0V) and stops operating.

[0106] Figure 10 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 3 Compared to Figure 8 The first sub-voltage control circuit shown is Figure 10 The first sub-voltage control circuit shown also includes a fourth switch 113. The first terminal Vin and the control terminal EN of the fourth switch 113 are coupled to a first power supply pin Vccq2, and the second terminal Vout of the fourth switch 113 is coupled to a first voltage regulator 111. The fourth switch 113 is configured to: be in an ON state in response to a first voltage signal being a first power supply voltage (e.g., 1.8V) to allow the first voltage regulator 111 to receive the first power supply voltage; and be in an OFF state in response to a first voltage signal being a second idle voltage (e.g., 0V) to disconnect a second current path. For example, the fourth switch 113 is an NMOS transistor.

[0107] With the inclusion of the fourth switch 113, this disclosure does not restrict whether the first voltage regulator needs to satisfy the condition that the second idle voltage is not within its input range, thus expanding the selection range of the first voltage regulator. However, if the fourth switch 113 is used simultaneously and the first voltage regulator satisfies the condition that the second idle voltage is not within its input range, the second current path can be disconnected more reliably. It is understood that this embodiment illustrates the case where the second control signal En_2 is the first voltage signal.

[0108] Figure 11 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 4 ,like Figure 11 As shown, in some embodiments, the first sub-voltage control circuit includes a first voltage regulator 111, whose input and output terminals are coupled to a first power supply pin Vccq2 and a first voltage node Node1, respectively. The second sub-voltage control circuit includes a fifth switch 122, whose first terminal Vin and second terminal Vout are coupled to a second power supply pin Vccq and the first voltage node Node1, respectively. The control terminal EN of the fifth switch 122 is coupled to the first power supply pin Vccq2. The fifth switch 122 is configured to be open in response to a first voltage signal being a first power supply voltage and to be open in response to a second idle voltage. For example, the fifth switch 122 is a PMOS transistor.

[0109] This embodiment illustrates a scenario where the first control signal En_1 is a first voltage signal, and the second control signal En_2 is also a first voltage signal. Specifically, in power supply scheme one, when the first power supply pin Vccq2 receives a first power supply voltage (e.g., 1.8V), the first voltage regulator 111 converts the first power supply voltage into a first target voltage (e.g., 1.2V). Simultaneously, the fifth switch 122 responds to the first power supply voltage and is in an open state to disconnect the first current path.

[0110] In power supply scheme two, when the second power supply pin Vccq receives the second power supply voltage (e.g., 1.2V), the first power supply pin Vccq2 receives the second idle voltage (e.g., 0V). The fifth switch 122 is turned on in response to the second idle voltage, outputting a first target voltage equal to the second power supply voltage. Simultaneously, the first voltage regulator 111 disconnects the second current path in response to the second idle voltage being outside its input range.

[0111] Figure 12 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 5 Compared to Figure 11 The first sub-voltage control circuit in this voltage control circuit also includes a sixth switch 114. The first terminal Vin and the second terminal Vout of the sixth switch 114 are coupled to the first power supply pin Vccq2 and the first voltage regulator 111, respectively. The control terminal EN of the sixth switch is coupled to the second power supply pin Vccq. The sixth switch 114 is configured to: be in an ON state in response to a second voltage signal being a first idle voltage, to turn on the first voltage regulator 111 and the first power supply pin Vccq2, so that the first voltage regulator 111 receives the first power supply voltage; and be in an OFF state in response to a second voltage signal being a second power supply voltage, to disconnect the second current path. For example, the sixth switch 114 is a PMOS transistor.

[0112] With the inclusion of the sixth switch 114, this disclosure does not restrict whether the first voltage regulator needs to satisfy the condition that the second idle voltage is not within its input range, thus expanding the selection range of the first voltage regulator. However, if the sixth switch 114 is used simultaneously and the first voltage regulator satisfies the condition that the second idle voltage is not within its input range, the second current path can be disconnected more reliably. It is understood that this embodiment illustrates the case where the first control signal En_1 is the second voltage signal, and the second control signal En_1 is the first voltage signal.

[0113] In summary, the first sub-voltage control circuit and the second sub-voltage control circuit provided in the embodiments of this disclosure can support two power supply schemes, and can provide the first target voltage to the first device under both power supply schemes, thereby improving the compatibility and competitiveness of the product.

[0114] Figure 13 A schematic diagram of a memory system including a voltage control circuit provided for embodiments of this disclosure. Figure 2 .like Figure 13 As shown, the memory system 1000 also includes a third power supply pin Vcc and a second device 220. The third power supply pin Vcc receives a third voltage signal, which includes a third power supply voltage and / or a fourth power supply voltage. For example, in power supply scheme one, the third voltage signal is a third power supply voltage (e.g., 3.3V), and in power supply scheme two, the third voltage signal is a fourth power supply voltage (e.g., 2.5V). In other embodiments, the third voltage signal can switch between a third power supply voltage and a fourth power supply voltage.

[0115] In some embodiments, such as Figure 13 As shown, if the second device 220 can simultaneously support operation under the third power supply voltage and the fourth power supply voltage, then the third power supply pin Vcc can be directly coupled to the second device 220 through the second voltage node Node2.

[0116] In other embodiments, if the second device only supports operation at one of the power supply voltages, the voltage control circuit also needs to regulate the power supply voltage received by the third power supply pin. Figure 14 A schematic diagram of a memory system including a voltage control circuit provided for embodiments of this disclosure. Figure 3 ,like Figure 14 As shown, the voltage control circuit further includes a third sub-voltage control circuit 130, coupled to the third power supply pin Vcc and the second voltage node Node2; the third sub-voltage control circuit 130 is configured to: output a second target voltage in response to the third control signal En_3 being at a first level and the third voltage signal received by the third power supply pin Vcc being a third power supply voltage; and / or, output a second target voltage in response to the third control signal En_3 being at a second level and the third voltage signal being a fourth power supply voltage. The second device 220 is coupled to the second voltage node Node2, and the second target voltage is the operating voltage of the second device 220.

[0117] The third sub-voltage control circuit in this embodiment can unify the third power supply voltage and the fourth power supply voltage to the second target voltage. In this way, regardless of whether the application platform provides the third power supply voltage or the fourth power supply voltage, it can provide the second target voltage to the second device, thereby improving the platform compatibility and competitiveness of the memory system.

[0118] In some embodiments, the third control signal En_3 may be provided internally by the memory system. For example, when the memory system determines that the application platform provides power supply scheme one, the controller within the memory system may set the third control signal EN_3 to a first level, while when the application platform provides power supply scheme two, the controller may set the third control signal EN_4 to a second level.

[0119] In other embodiments, the third control signal En_3 may be provided by the application platform. For example, the third sub-voltage control circuit 130 is coupled to the second power supply pin Vccq, and the third control signal En_3 is a second voltage signal; wherein, the third control signal En_3 at the first level indicates that the second voltage signal is a first idle voltage (e.g., 0V), and the third control signal En_3 at the second level indicates that the second voltage signal is a second power supply voltage (e.g., 1.2V).

[0120] In specific operations, in power supply scheme one, the application platform simultaneously provides a first idle voltage to the second power supply pin Vccq and a third power supply voltage (e.g., 3.3V) to the third power supply pin Vcc. The third sub-voltage control circuit 130 responds to the first idle voltage and obtains a second target voltage based on the third power supply voltage. In power supply scheme two, the application platform simultaneously provides a second power supply voltage (e.g., 1.2V) to the second power supply pin Vccq and a fourth power supply voltage (e.g., 2.5V) to the third power supply pin Vcc. The third sub-voltage control circuit 130 responds to the second power supply voltage and obtains a second target voltage based on the fourth power supply voltage.

[0121] Figure 15 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 6 In some embodiments, such as Figure 15 As shown, the third sub-voltage control circuit 130 includes: a second voltage regulator 131 and a second switch 132. The input terminal of the second voltage regulator 131 is coupled to the third power supply pin Vcc, and the output terminal of the second voltage regulator 131 is coupled to the second voltage node Node2. The second voltage regulator 131 is configured to convert the third power supply voltage into a second target voltage in response to the third voltage signal being the third power supply voltage. The two terminals Vin and Vout of the second switch 132 are connected in parallel across the two terminals of the second voltage regulator 131. The control terminal EN of the second switch 132 is coupled to the second power supply pin Vccq. The second switch 132 is configured to be in an open state in response to the second voltage signal being the first idle voltage; and / or, in an on state in response to the second voltage signal being the second power supply voltage, so as to output the fourth power supply voltage as the second target voltage.

[0122] At least one of the third and fourth power supply voltages differs from the second target voltage. The third sub-voltage control circuit 130 provided in this embodiment is suitable for cases where the second target voltage is equal to the fourth power supply voltage. For example, such as... Figure 15 As shown, the second target voltage is equal to the fourth power supply voltage and is equal to 2.5V; the third power supply voltage is different from the second target voltage, for example, 3.3V. This embodiment illustrates the case where the third control signal En_3 is the second voltage signal.

[0123] like Figure 15 As shown, in power supply scheme one, the second power supply pin Vccq receives a first idle voltage (e.g., 0V), while the third power supply pin Vcc receives a third power supply voltage. At this time, the second switch 132 is opened under the control of the first idle voltage, and the second voltage regulator 131 operates, converting the third power supply voltage to a second target voltage. For example, if the third power supply voltage is greater than the second target voltage, the second voltage regulator reduces the third power supply voltage to the second target voltage.

[0124] In power supply scheme two, the second power supply pin Vccq receives the second power supply voltage (e.g., 1.2V), while the third power supply pin Vcc receives the fourth power supply voltage. At this time, the second switch 132 is turned on under the control of the second power supply voltage, short-circuiting the second voltage regulator 131, so that the fourth power supply voltage is transmitted to the second voltage node Node2 through the second switch 132 as the second target voltage.

[0125] For example, the second switch 132 is an NMOS transistor, whose threshold voltage is less than or equal to the second power supply voltage and greater than the first idle voltage. The NMOS transistor turns on in response to the second power supply voltage being greater than or equal to its threshold voltage and turns off in response to the first idle voltage being less than its threshold voltage. The second voltage regulator 131 is an LDO, the third power supply voltage is within the input range of the LDO, and the LDO satisfies the condition that when the input voltage is the third power supply voltage, the output voltage is the second target voltage.

[0126] In some embodiments, such as Figure 16 As shown, the second voltage regulator is an LDO 131 with an enable terminal EN. For example, the enable terminal EN of the LDO 131 is active high; it operates when the enable terminal receives a high level (e.g., greater than 1.2V) and stops operating when it receives a low level (e.g., 0V). Figure 16As shown, the enable terminal EN of LDO 131 is connected to the first power supply pin Vccq2, or in other examples, the enable terminal EN of LDO 131 is connected to the first power supply pin Vccq2 after a series resistor. Thus, in power supply scheme one, when the application platform synchronously provides a first power supply voltage to the first power supply pin Vccq2, a first idle voltage to the second power supply pin Vccq, and a third power supply voltage to the third power supply pin Vcc, the second switch 132 is open, and LDO 131 operates, converting the third power supply voltage into a second target voltage. In power supply scheme two, when the application platform synchronously provides a second idle voltage to the first power supply pin Vccq2, a second power supply voltage to the second power supply pin Vccq, and a fourth power supply voltage to the third power supply pin Vcc, LDO 131 stops operating, and the second switch 132 is turned on, outputting the fourth power supply voltage as the second target voltage to the second voltage node Node2. When the first power supply pin receives the second idle voltage, LDO 111 stops operating, thus disconnecting the second current path. Compared to... Figure 15 In power supply scheme two, the LDO is short-circuited by the second switch 132 and does not operate. This type of LDO with an enable terminal can stop working in power supply scheme two, more reliably ensuring that the path where the LDO is located does not participate in current transmission, so that the second target voltage is equal to the fourth power supply voltage. In practical applications, either of the two types of LDOs can be selected as needed.

[0127] Another implementation of the third control signal En_3 provided by the application platform is as follows: the third sub-voltage control circuit 130 is coupled to the first power supply pin Vccq2, and the third control signal En_3 is the first voltage signal. Specifically, the third control signal En_3 being at the first level indicates that the first voltage signal is the first power supply voltage (e.g., 1.8V), and the third control signal being at the second level indicates that the first voltage signal is the second idle voltage (e.g., 0V).

[0128] In specific operations, in power supply scheme one, the application platform simultaneously provides a first power supply voltage to the first power supply pin Vccq2 and a third power supply voltage (e.g., 3.3V) to the third power supply pin Vcc. The third sub-voltage control circuit 130 responds to the first power supply voltage and obtains a second target voltage based on the third power supply voltage. In power supply scheme two, the application platform simultaneously provides a second idle voltage (e.g., 0V) to the first power supply pin Vccq2 and a fourth power supply voltage (e.g., 2.5V) to the third power supply pin Vcc. The third sub-voltage control circuit 130 responds to the second power supply voltage and obtains a second target voltage based on the fourth power supply voltage.

[0129] Figure 17 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 8 In some embodiments, such as Figure 17As shown, the third sub-voltage control circuit 130 includes a second voltage regulator 131 and a third switch 133. The input terminal of the second voltage regulator 131 is coupled to the third power supply pin Vcc, and the output terminal of the second voltage regulator 131 is coupled to the second voltage node Node2. The second voltage regulator 131 is configured to convert the third power supply voltage into a second target voltage in response to a third voltage signal being the third power supply voltage. The two terminals Vin and Vout of the third switch 133 are connected in parallel across the two terminals of the second voltage regulator 131. The control terminal EN of the third switch 133 is coupled to the first power supply pin Vccq2. The third switch 133 is configured to be in an open state in response to a first voltage signal being the first power supply voltage; and / or, in an on state in response to a first voltage signal being the second idle voltage, so as to output a fourth power supply voltage as the second target voltage.

[0130] This embodiment also applies to the case where the fourth power supply voltage is equal to the second target voltage. For example, the second switch is a PMOS transistor, which turns off in response to a first power supply voltage greater than its threshold voltage and turns on in response to a second idle voltage less than or equal to its threshold voltage.

[0131] like Figure 17 As shown, in power supply scheme one, the first power supply pin Vccq2 receives a first power supply voltage (e.g., 1.8V), while the third power supply pin Vcc receives a third power supply voltage. At this time, the third switch 133 is opened under the control of the first power supply voltage, and the second voltage regulator 131 operates, converting the third power supply voltage into a second target voltage. In power supply scheme two, the first power supply pin Vccq2 receives a second idle voltage (e.g., 0V), while the third power supply pin Vcc receives a fourth power supply voltage. At this time, the third switch 133 is turned on under the control of the second idle voltage, short-circuiting the second voltage regulator 131, so that the fourth power supply voltage is transmitted to the second voltage node Node2 through the third switch 133.

[0132] Figures 15 to 17 The third sub-voltage control circuit shown is suitable for situations where the second target voltage is equal to the fourth power supply voltage. In some embodiments, the second target voltage may also be equal to the third power supply voltage. Figure 18 Schematic diagram of the voltage control circuit provided in the embodiments of this disclosure Figure 9 .like Figure 18As shown, the third sub-voltage control circuit includes a fourth voltage regulator 134 and a second switch 132. The input terminal of the fourth voltage regulator 134 is coupled to the third power supply pin Vcc, and the output terminal of the fourth voltage regulator 134 is coupled to the second voltage node Node2. The fourth voltage regulator 134 is configured to convert the fourth power supply voltage into a second target voltage in response to the third voltage signal being the fourth power supply voltage. The two ends of the second switch 132 are connected in parallel across the two ends of the third voltage regulator 134. The control terminal of the second switch 132 is coupled to the second power supply pin. The second switch 132 is configured to be in an on state in response to the first voltage signal being the first power supply voltage, so as to output the third power supply voltage as the second target voltage; and / or, in an off state in response to the first voltage signal being the second idle voltage.

[0133] like Figure 18 As shown, the second target voltage is equal to the third power supply voltage, and is equal to 3.3V; the fourth power supply voltage is different from the second target voltage, and the fourth power supply voltage is, for example, 2.5V. This embodiment illustrates the case where the third control signal En_3 is the first voltage signal.

[0134] like Figure 18 As shown, in power supply scheme one, the first power supply pin Vccq2 receives a first power supply voltage (e.g., 1.8V), while the third power supply pin Vcc receives a third power supply voltage. At this time, the second switch 132 is turned on under the control of the first power supply voltage, short-circuiting the fourth voltage regulator 134, so that the third power supply voltage is transmitted to the second voltage node Node2 via the second switch 132 as the second target voltage. In power supply scheme two, the first power supply pin Vccq2 receives a second idle voltage (e.g., 0V), while the third power supply pin Vcc receives a fourth power supply voltage. At this time, the second switch 132 is turned off under the control of the second idle voltage, and the fourth voltage regulator 134 operates, converting the fourth power supply voltage to the second target voltage. For example, if the fourth power supply voltage is less than the second target voltage, the fourth voltage regulator 134 boosts the fourth power supply voltage to the second target voltage. The fourth voltage regulator 134 can be any voltage regulator capable of boosting voltage commonly used in the art.

[0135] It should be understood that in another embodiment, when the second target voltage is equal to the third power supply voltage, the third control signal En_3 can also be the second voltage signal. In this case, the second switch 132 is replaced with the third switch 133 (PMOS transistor), and the control terminal EN of the third switch is connected to the second power supply pin Vccq.

[0136] In summary, the third sub-voltage control circuit provided in this disclosure can support two power supply schemes and can provide a second target voltage to the second device under both power supply schemes, thereby improving the compatibility and competitiveness of the product.

[0137] Figure 19 A schematic diagram of a memory system including a voltage control circuit provided for embodiments of this disclosure. Figure 4 In some embodiments, such as Figure 19 As shown, the memory system also includes a packaging substrate 2000 and a bare chip 3000 located on the packaging substrate 2000; wherein, the voltage control circuit 100 is located on the packaging substrate 2000.

[0138] exist Figure 5 In the UFS product shown, all four voltage controllers (LDOs) are housed within the bare die. For example, all four voltage controllers (LDOs) are housed within the memory controller's bare die. Because Vccq2 = 1.8V, which is much higher than the controller's 0.8V operating voltage, the excessive voltage difference causes the LDO voltage drop to generate a large amount of heat, leading to severe overheating of the bare die. In this embodiment, two voltage regulators (the first voltage regulator and the second voltage regulator (or the fourth voltage regulator)) are placed on the packaging substrate outside the bare die, which facilitates heat dissipation, significantly reducing the heat dissipation requirements of the memory system and ensuring greater reliability.

[0139] Figure 20 A schematic diagram of a memory system including a voltage control circuit provided for embodiments of this disclosure. Figure 5 In some embodiments, the first device 210 and the second device 220 are located within the bare die 3000. The bare die 3000 further includes a third voltage regulator 140 and a third device 230, the third voltage regulator 140 being coupled to a first voltage node Node1 and configured to convert a first target voltage into a third target voltage. The third device 230 is coupled to the third voltage regulator 140. The operating voltage of the third device 230 is the third target voltage.

[0140] It is understandable that the operating voltage of some devices on the bare die may differ from the first and second target voltages, necessitating a third voltage regulator 140 to further convert the first target voltage into a third target voltage. For example, the third target voltage may be lower than the first target voltage. Figure 20 In this embodiment, the third target voltage is 0.8V, which is less than the first target voltage of 1.2V. Compared to directly converting the first or second power supply voltage into the third target voltage, this embodiment first converts the first power supply voltage into the first target voltage and then further converts it into the third target voltage. This reduces the voltage difference at each conversion step, thereby reducing the heat dissipation of the voltage regulator and ensuring greater reliability.

[0141] In some embodiments, the third voltage regulator 140 is an LDO.

[0142] In some embodiments, the memory controller and the memory device may be integrated on a single bare die. In other embodiments, the memory controller and the memory device may be formed on separate bare dies. For example, a memory controller bare die and one or more memory bare dies may be formed. The memory controller includes front-end I / O for communicating with an external host, memory device I / O for communicating with the memory device, and a controller core, etc. The memory device includes memory device I / O for communicating with the memory controller, a memory cell array, and peripheral circuitry other than the memory device I / O for controlling the memory cell array, etc.

[0143] For example, memory devices include, but are not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), and nano random access memory (NRAM). Memory devices can be... Figures 1a to 6 The memory device described in any of the embodiments.

[0144] A memory controller can be coupled to both the memory device and the host computer, and is used to control the memory device. The memory controller can be... Figures 1a to 6 The memory controller described in any of the embodiments.

[0145] In some embodiments, the memory controller and one or more memory devices may be included in the same package, such as a UFS package or an eMMC package. In this package, the memory controller die and the memory die may be disposed side-by-side on the package substrate or in a stacked configuration. For example, voltage control circuitry may be disposed separately on the package substrate.

[0146] This disclosure uses UFS products as an example to describe the solution in detail, but this does not limit the technical solution of this disclosure to be applied only to UFS products. Figure 21This is a schematic diagram of a general-purpose flash memory storage provided according to an embodiment of the present disclosure. In some embodiments, such as Figure 21 As shown, the general-purpose flash memory includes a memory controller 3100 and a memory device 3200, with the memory controller 3100 coupled to the memory device 3200. The first device 210, the second device 220, and the third device 230 in the above embodiments can be any device in the memory controller and / or the memory device.

[0147] In some embodiments, the first device 210 includes a memory device input / output (I / O) 310 within the memory controller 3100 and a memory device input / output (I / O) 350 within the memory device 32, both coupled to a first voltage node Node1. For example, the operating voltage of the two memory device inputs / outputs 310 and 350 is 1.2V. For example, both memory device inputs / outputs 310 and 350 are flash memory inputs / outputs, communicating based on the ONFI protocol or the NVMe protocol. For example, the memory device inputs / outputs 310 and 350 in this embodiment can correspond to... Figure 5 and Figure 6 The memory device I / O 93, 95.

[0148] In some embodiments, the second device 220 includes a physical layer (M-PHY) 320, a controller core 330, and is coupled to a third voltage regulator 140. In one example, such as Figure 21 As shown, the physical layer 320 and the controller core 330 can be coupled to different third voltage regulators 140. In another example, the physical layer and the controller core can also be coupled to the same third voltage regulator 140. For example, in this embodiment, the physical layer 320 and the controller core 330 can be... Figure 5 and Figure 6 The M-PHY 91 and controller core 92 are included.

[0149] In some embodiments, the peripheral circuitry of the memory device supports operation at both a third and a fourth power supply voltage. In this case, the third sub-voltage control circuitry 130 may not be included in the voltage control circuitry. In other embodiments, the peripheral circuitry of the memory device supports operation at only one power supply voltage. Figure 21 As shown, the voltage control circuit also includes a third sub-voltage control circuit. The peripheral circuits 340 in the memory device, excluding the memory device input / output 350, are coupled to the third sub-voltage control circuit via the second voltage node Node2. For example, the peripheral circuits in this embodiment may be... Figure 5 and Figure 6 The peripheral circuitry 96 is included. For example, the memory device may be a flash memory.

[0150] In some embodiments, UFS products can be integrated into application platforms, including but not limited to mobile electronic products such as mobile phones, tablets, and computers. The application platform and the UFS product communicate via the UFS protocol. The general-purpose flash storage provided in this embodiment can simultaneously support multiple UFS standards with different power supply schemes. For example, it can simultaneously support UFS 2.2 and UFS 3.1 standards.

[0151] Compared to Figure 5 In the UFS product described in this embodiment, the two voltage regulators are placed on the packaging substrate, which significantly reduces the product's heat dissipation requirements and ensures greater reliability. Compared to... Figure 6 In the UFS products described in this embodiment, when the UFS products use the same power supply scheme, only the two third voltage regulators within the bare chip operate, similar to... Figure 6 The UFS products in the series are the same, and the number of voltage regulators used has not increased, so the heat generation is basically the same.

[0152] Furthermore, when the memory controller used by the memory system is Figure 6 When the memory controller of the next-generation UFS product (e.g., a product supporting the UFS 3.1 standard) is shown, the memory system can be used even when applied to a memory controller that is designed for... Figure 5 When the host is powered by the previous generation UFS product (e.g., a product that supports the UFS 2.2 standard) on the application platform, it can also switch the speed to HS_Gear4 and overclock it to use the new generation UFS product. There are no protocol or compatibility limitations. That is, this memory system can support the UFS 2.1 standard and can also be overclocked to use UFS 3.1, which improves the competitiveness of the product.

[0153] In summary, the memory system provided in this embodiment adds an LDO to the Vccq2 circuit, reducing the Vccq2 voltage from 1.8V to 1.2V, while simultaneously merging it with the Vccq circuit. Adding an LDO at the Vcc terminal, reducing the voltage from 3.3V to 2.5V, ensures that the voltage at the Vcc terminal is regulated to 2.5V regardless of whether it is 3.3V or 2.5V. This approach, by adding only a few components, achieves compatibility with two standards, significantly reducing R&D costs, greatly improving market applicability, increasing customer acceptance, and enhancing competitiveness.

[0154] This disclosure also provides a voltage control method applied to a memory system, the memory system including: a first sub-voltage control circuit coupled to a first power supply pin and a first voltage node, and a second sub-voltage control circuit coupled to a second power supply pin and the first voltage node. Figure 22 , Figure 23 and Figure 24This is a flowchart illustrating various voltage control methods provided in embodiments of this disclosure. In some embodiments, such as Figure 22 As shown, the voltage control method includes:

[0155] S110: The first sub-voltage control circuit responds to the first voltage signal received by the first power supply pin as the first power supply voltage and outputs the first target voltage;

[0156] S120: At the same time, the second sub-voltage control circuit responds to the first control signal and disconnects the first current path between the second power supply pin and the first voltage node.

[0157] In other embodiments, such as Figure 23 As shown, the voltage control method includes:

[0158] S210: Second sub-voltage control circuit response: The second voltage signal received by the second power supply pin is the second power supply voltage, and the first target voltage is output;

[0159] S220: Simultaneously, the first sub-voltage control circuit responds to the second control signal by disconnecting the second current path between the first power supply pin and the first voltage node.

[0160] In some other embodiments, such as Figure 24 As shown, the voltage control method includes:

[0161] S310: The first sub-voltage control circuit responds to the first voltage signal received by the first power supply pin as the first power supply voltage and outputs the first target voltage; at the same time, the second sub-voltage control circuit responds to the first control signal and disconnects the first current path between the second power supply pin and the first voltage node.

[0162] S320: The second sub-voltage control circuit responds to the second voltage signal received by the second power supply pin as the second power supply voltage and outputs the first target voltage; at the same time, the first sub-voltage control circuit responds to the second control signal and disconnects the second current path between the first power supply pin and the first voltage node.

[0163] The voltage control method provided in this disclosure adjusts both the first power supply voltage and the second power supply voltage to a first target voltage. Therefore, when a memory system including the voltage control circuit is integrated into an application platform, regardless of whether the application platform's power supply scheme provides the first power supply voltage to the first power supply pin or the second power supply pin, the voltage control circuit within the memory system can provide the first target voltage to the device. In this way, a single memory system can support two power supply schemes simultaneously, eliminating the need for two separate memory systems for each scheme. This reduces R&D investment, saves R&D costs, and improves the product's platform compatibility and competitiveness.

[0164] In some embodiments, the first control signal is a second voltage signal. The second sub-voltage control circuit in step S120 or S310, in response to the first control signal, disconnects the first current path between the second power supply pin and the first voltage node, specifically including: the second sub-voltage control circuit disconnects the first current path in response to the second voltage signal being a first idle voltage.

[0165] In some embodiments, the second control signal is a first voltage signal. The first sub-voltage control circuit in step S220 or S320, in response to the second control signal, disconnects the second current path between the first power supply pin and the first voltage node, specifically including: the first sub-voltage control circuit disconnects the second current path in response to the first voltage signal being a second idle voltage.

[0166] In some embodiments, the first sub-voltage control circuit includes a first voltage regulator, whose input terminal is coupled to a first power supply pin and whose output terminal is coupled to a first voltage node; the second sub-voltage controller includes a first switch, whose first terminal and control terminal are coupled to a second power supply pin and whose second terminal is coupled to the first voltage node. In step S110 or step S310, the first sub-voltage control circuit, in response to a first voltage signal received from the first power supply pin as a first power supply voltage, outputs a first target voltage, specifically including: the first voltage regulator receiving the first power supply voltage and converting the first power supply voltage into the first target voltage.

[0167] In step S210 or step S310, the second sub-voltage control circuit responds to the second voltage signal as the first idle voltage and disconnects the first current path. Specifically, the first switch responds to the first idle voltage and is in an open state to disconnect the first current path.

[0168] In some embodiments, the second sub-voltage control circuit in step S210 or step S320 outputs a first target voltage in response to the second voltage signal received by the second power supply pin being the second power supply voltage. Specifically, this includes: the first switch being in a conducting state in response to the second power supply voltage, so as to output the second power supply voltage as the first target voltage.

[0169] In step S220 or step S320, the first sub-voltage control circuit responds to the first voltage signal as the second idle voltage and disconnects the second current path. Specifically, the first voltage regulator stops operating in response to the second idle voltage to disconnect the second current path; wherein the second idle voltage is outside the input range of the first voltage regulator.

[0170] In some embodiments, the memory system further includes a third sub-voltage control circuit coupled to a third power supply pin and a second voltage node. For example... Figure 25As shown, in addition to steps S110 and S120, the voltage control method also includes step S130: the third sub-voltage control circuit outputs a second target voltage in response to the third control signal being at a first level and the third voltage signal being a third power supply voltage. For example, steps S110, S120, and S130 are executed simultaneously.

[0171] In other embodiments, such as Figure 26 As shown, in addition to steps S210 and S220, the voltage control method also includes step S230: the third sub-voltage control circuit outputs a second target voltage in response to the third control signal being at the second level and the third voltage signal being the fourth power supply voltage. For example, steps S210, S220, and S230 are executed simultaneously.

[0172] In some other embodiments, such as Figure 27 As shown, the voltage control method includes:

[0173] S410: The first sub-voltage control circuit responds to the first voltage signal received by the first power supply pin as the first power supply voltage and outputs the first target voltage; at the same time, the second sub-voltage control circuit responds to the first control signal and disconnects the first current path between the second power supply pin and the first voltage node; the third sub-voltage control circuit responds to the third control signal being at the first level and the third voltage signal being the third power supply voltage and outputs the second target voltage.

[0174] S420: Second sub-voltage control circuit response: The second voltage signal received by the second power supply pin is the second power supply voltage, and the first target voltage is output; at the same time, the first sub-voltage control circuit responds to the second control signal and disconnects the second current path between the first power supply pin and the first voltage node; the third sub-voltage control circuit responds to the third control signal being at the second level and the third voltage signal being the fourth power supply voltage, and outputs the second target voltage.

[0175] For example, the first sub-voltage control circuit, the second sub-voltage control circuit, and the third sub-voltage control circuit perform operations synchronously in S410 and synchronously in S420.

[0176] In some embodiments, the third sub-voltage control circuit is coupled to the second power supply pin, and the third control signal is the second voltage signal. In step S130 or S140, the third sub-voltage control circuit, in response to the third control signal being at a first level and the third voltage signal being the third power supply voltage, outputs a second target voltage, specifically including: in response to the second voltage signal being a first idle voltage, outputting a second target voltage based on the third power supply voltage.

[0177] In step S230 or step S240, in response to the third control signal being at the second level and the third voltage signal being the fourth power supply voltage, the second target voltage is output, specifically including: in response to the second voltage signal being the second power supply voltage, the second target voltage is output based on the fourth power supply voltage.

[0178] In some embodiments, the third sub-voltage control circuit includes a second voltage regulator and a second switch. The input terminal of the second voltage regulator is coupled to a third power supply pin, and the output terminal is coupled to a second voltage node. The two ends of the second switch are connected in parallel across the two ends of the second voltage regulator, and the control terminal is coupled to the second power supply pin.

[0179] The above step "in response to the second voltage signal being the first idle voltage, outputting the second target voltage based on the third power supply voltage" specifically includes: the second switch being in the open state in response to the first idle voltage, and the second voltage regulator converting the third power supply voltage into the second target voltage.

[0180] The above step "responding to the second voltage signal as the second power supply voltage, outputting the second target voltage based on the fourth power supply voltage" specifically includes: the second switch responding to the second power supply voltage and being in the on state, so as to output the fourth power supply voltage as the second target voltage.

[0181] In some embodiments, the memory system further includes a third voltage regulator coupled to the first voltage node. The voltage control method further includes the third voltage regulator converting the first target voltage into a third target voltage.

[0182] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0183] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0184] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A voltage control circuit, characterized by, The voltage control circuit comprises: a first sub-voltage control circuit coupled to a first power pin and a first voltage node; a second sub-voltage control circuit coupled to a second power pin and the first voltage node; wherein the first sub-voltage control circuit is configured to output a first target voltage in response to a first voltage signal received by the first power pin being a first power voltage; and / or the second sub-voltage control circuit is configured to output the first target voltage in response to a second voltage signal received by the second power pin being a second power voltage; and the first sub-voltage control circuit is configured to disconnect a second current path between the first power pin and the first voltage node in response to a second control signal.

2. The voltage control circuit of claim 1, wherein, The first control signal is the second voltage signal, and the second sub-voltage control circuit disconnects the first current path in response to the second voltage signal being a first idle voltage; and / or The second control signal is the first voltage signal, and the first sub-voltage control circuit disconnects the second current path in response to the first voltage signal being a second idle voltage.

3. The voltage control circuit of claim 2, wherein, The first sub-voltage control circuit comprises a first voltage regulator, an input terminal of the first voltage regulator being coupled to the first power pin, and an output terminal of the first voltage regulator being coupled to the first voltage node; The first voltage regulator is configured to convert the first power voltage into the first target voltage in response to the first voltage signal being the first power voltage.

4. The voltage control circuit of claim 3, wherein, The second sub-voltage control circuit comprises a first switch, a first terminal and a control terminal of the first switch being coupled to the second power pin, and a second terminal of the first switch being coupled to the first voltage node; The first switch is configured to be in an off state in response to the second voltage signal being the first idle voltage, so as to disconnect the first current path.

5. The voltage control circuit of claim 4, wherein: The first switch is configured to be in an on state in response to the second voltage signal being the second power voltage, so as to output the second power voltage as the first target voltage; The first voltage regulator is configured to stop running in response to the first voltage signal being the second idle voltage, so as to disconnect the second current path; wherein the second idle voltage is outside an input range of the first voltage regulator.

6. The voltage control circuit according to claim 1 or 4, characterized by The voltage control circuit further comprises: a third sub-voltage control circuit coupled to a third power pin and a second voltage node, and configured to: output a second target voltage in response to a third control signal being at a first level and a third voltage signal received by the third power pin being a third power voltage; and / or output the second target voltage in response to the third control signal being at a second level and the third voltage signal being a fourth power voltage.

7. The voltage control circuit of claim 6, wherein, The third sub-voltage control circuit is coupled to the second power pin, and the third control signal is the second voltage signal. Wherein, the third control signal being at the first level means that the second voltage signal is the first idle voltage, and the third control signal being at the second level means that the second voltage signal is the second power supply voltage.

8. The voltage control circuit of claim 7, wherein, The fourth power supply voltage is equal to the second target voltage; the third sub-voltage control circuit includes: A second voltage regulator, whose input is coupled to the third power supply pin and whose output is coupled to the second voltage node, is configured to convert the third power supply voltage into the second target voltage in response to the third voltage signal being the third power supply voltage. The second switch, with its two ends connected in parallel to the two ends of the second voltage regulator, and its control terminal coupled to the second power supply pin, is configured to: be in an off state in response to the second voltage signal being the first idle voltage; and / or be in an on state in response to the second voltage signal being the second power supply voltage, so as to output the fourth power supply voltage as the second target voltage.

9. The voltage control circuit of claim 8, wherein, Both the first switch and the second switch are NMOS transistors; Both the first voltage regulator and the second voltage regulator are low-dropout linear regulators.

10. The voltage control circuit of claim 6, wherein, The third sub-voltage control circuit is coupled to the first power supply pin, and the third control signal is the first voltage signal; Wherein, the third control signal being at the first level means that the first voltage signal is the first power supply voltage, and the third control signal being at the second level means that the first voltage signal is the second idle voltage.

11. The voltage control circuit of claim 10, wherein, The fourth power supply voltage is equal to the second target voltage; the third sub-voltage control circuit includes: A second voltage regulator, whose input is coupled to the third power supply pin and whose output is coupled to the second voltage node, is configured to convert the third power supply voltage into the second target voltage in response to the third voltage signal being the third power supply voltage. A third switch, the two ends of which are connected in parallel to the two ends of the second voltage regulator, the control terminal of which is coupled to the first power supply pin, is configured to: be in an off state in response to the first voltage signal being the first power supply voltage; and / or be in an on state in response to the first voltage signal being the second idle voltage, so as to output the fourth power supply voltage as the second target voltage.

12. A memory system, comprising: include: Voltage control circuit, the voltage control circuit comprising: The first sub-voltage control circuit is coupled to the first power supply pin and the first voltage node; The second sub-voltage control circuit is coupled to the second power supply pin and the first voltage node; Wherein, the first sub-voltage control circuit is configured to: output a first target voltage in response to a first voltage signal received from the first power supply pin as a first power supply voltage; simultaneously, the second sub-voltage control circuit is configured to: disconnect a first current path between the second power supply pin and the first voltage node in response to a first control signal; and / or, The second sub-voltage control circuit is configured to: output the first target voltage in response to a second voltage signal received by the second power supply pin as a second power supply voltage; simultaneously, the first sub-voltage control circuit is configured to: disconnect the second current path between the first power supply pin and the first voltage node in response to a second control signal.

13. The memory system of claim 12, wherein, The memory system further includes: a packaging substrate, and a bare chip located on the packaging substrate; The voltage control circuit is located on the packaging substrate.

14. The memory system of claim 13, wherein, The bare chip also includes: A third voltage regulator, coupled to the first voltage node, is configured to convert the first target voltage into a third target voltage.

15. The memory system of claim 14, wherein, The memory system is a general-purpose flash memory; The bare chip includes: The physical layer and controller core are coupled to the third voltage regulator; The memory device input / output in the memory controller and the memory device input / output in the memory device are coupled to the first voltage node.

16. The memory system of claim 15, wherein, The voltage control circuit further includes: The third sub-voltage control circuit, coupled to the third power supply pin and the second voltage node, is configured to: output a second target voltage in response to the third control signal being at a first level and the third voltage signal received by the third power supply pin being a third power supply voltage; and / or, output the second target voltage in response to the third control signal being at a second level and the third voltage signal being a fourth power supply voltage; The bare chip also includes: peripheral circuitry of the memory device coupled to the second voltage node.

17. A voltage control method, characterized by, Applied to a memory system, the memory system includes: a first sub-voltage control circuit coupled to a first power supply pin and a first voltage node, and a second sub-voltage control circuit coupled to a second power supply pin and the first voltage node; the voltage control method includes: The first sub-voltage control circuit, in response to a first voltage signal received at the first power supply pin being a first power supply voltage, outputs a first target voltage; simultaneously, the second sub-voltage control circuit, in response to a first control signal, disconnects the first current path between the second power supply pin and the first voltage node; and / or, The second sub-voltage control circuit responds to the second voltage signal received by the second power supply pin as the second power supply voltage and outputs the first target voltage; at the same time, the first sub-voltage control circuit responds to the second control signal and disconnects the second current path between the first power supply pin and the first voltage node.

18. The voltage control method according to claim 17, characterized in that, The first control signal is the second voltage signal; the second sub-voltage control circuit responds to the first control signal by disconnecting the first current path between the second power supply pin and the first voltage node, including: the second sub-voltage control circuit responds to the second voltage signal being a first idle voltage by disconnecting the first current path; The second control signal is the first voltage signal; the first sub-voltage control circuit responds to the second control signal by disconnecting the second current path between the first power supply pin and the first voltage node, including: the first sub-voltage control circuit responds to the first voltage signal being a second idle voltage by disconnecting the second current path.

19. The voltage control method according to claim 18, wherein, The first sub-voltage control circuit includes a first voltage regulator, whose input terminal is coupled to the first power supply pin and whose output terminal is coupled to the first voltage node; the second sub-voltage controller includes a first switch, whose first terminal and control terminal are coupled to the second power supply pin and whose second terminal is coupled to the first voltage node; The first sub-voltage control circuit responds to the first voltage signal received by the first power supply pin as a first power supply voltage and outputs a first target voltage, including: the first voltage regulator receives the first power supply voltage and converts the first power supply voltage into the first target voltage; The second sub-voltage control circuit disconnects the first current path in response to the second voltage signal being a first idle voltage, including: the first switch being in an open state in response to the first idle voltage to disconnect the first current path.

20. The voltage control method according to claim 19, characterized in that, The second sub-voltage control circuit responds to the second voltage signal received by the second power supply pin as the second power supply voltage and outputs the first target voltage, including: the first switch responds to the second power supply voltage and is in the on state so as to output the second power supply voltage as the first target voltage; The first sub-voltage control circuit disconnects the second current path in response to the first voltage signal being a second idle voltage, including: the first voltage regulator stopping operation in response to the second idle voltage to disconnect the second current path; wherein the second idle voltage is outside the input range of the first voltage regulator.

21. The voltage control method of claim 17, wherein, The memory system further includes a third sub-voltage control circuit coupled to a third power supply pin and a second voltage node; the method further includes: The third sub-voltage control circuit, in response to the third control signal being at the first level and the third voltage signal being the third power supply voltage, outputs the second target voltage; and / or The third sub-voltage control circuit outputs the second target voltage in response to the third control signal being at the second level and the third voltage signal being the fourth power supply voltage.

22. The voltage control method of claim 21, wherein, The third sub-voltage control circuit is coupled to the second power supply pin, and the third control signal is the second voltage signal; The third sub-voltage control circuit outputs a second target voltage in response to a third control signal being at a first level and the third voltage signal being a third power supply voltage, including: in response to the second voltage signal being a first idle voltage, outputting the second target voltage based on the third power supply voltage; Responding to the third control signal being at a second level and the third voltage signal being a fourth power supply voltage, outputting the second target voltage includes: responding to the second voltage signal being the second power supply voltage, outputting the second target voltage based on the fourth power supply voltage.

23. The voltage control method of claim 22, wherein, The third sub-voltage control circuit includes a second voltage regulator and a second switch. The input terminal of the second voltage regulator is coupled to the third power supply pin, and the output terminal is coupled to the second voltage node. The two ends of the second switch are connected in parallel to the two ends of the second voltage regulator, and the control terminal is coupled to the second power supply pin. The step of responding to the second voltage signal as the first idle voltage and outputting the second target voltage based on the third power supply voltage includes: the second switch being in an open state in response to the first idle voltage, and the second voltage regulator converting the third power supply voltage into the second target voltage; The step of responding to the second voltage signal as the second power supply voltage and outputting the second target voltage based on the fourth power supply voltage includes: the second switch being in a conducting state in response to the second power supply voltage, so as to output the fourth power supply voltage as the second target voltage.

24. The voltage control method of claim 17, wherein, The memory system further includes: a third voltage regulator coupled to the first voltage node; The voltage control method further includes: The third voltage regulator converts the first target voltage into a third target voltage.

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