Pixel driving circuit, driving method and display panel

Abstract

A pixel driving circuit (PC), driving method, and display panel are disclosed. The pixel driving circuit (PC) includes a driving transistor (T3), a compensation circuit (2), a first initialization circuit (100), a writing circuit (4), and an energy storage circuit (10). The writing circuit (4) is connected to a first terminal of the energy storage circuit (10), and the second terminal of the energy storage circuit (10) is connected to a control terminal of the driving transistor (T3). The first terminal of the energy storage circuit (10) is connected to the first terminal of the driving transistor (T3) through the first initialization circuit (100). The control terminal and the second terminal of the driving transistor (T3) are connected through the compensation circuit (2). 3) The second end is connected to the light-emitting device (LD); the first initialization circuit (100) is used to transmit the first initialization signal (Vinit3) to the first end of the driving transistor (T3) and the first end of the energy storage circuit (10); the writing circuit (4) is connected to the writing control terminal (G4) and is used to transmit the data signal (Data) to the energy storage circuit (10) in response to the signal of the writing control terminal (G4); the energy storage circuit (10) is used to couple the data signal (Data) to the control terminal of the driving transistor (T3); the compensation circuit (2) is connected to the compensation control terminal (G2) and is used to turn on and off in response to the signal of the compensation control terminal (G2).

Description

Pixel driving circuit, driving method and display panel

[0001] Cross-references

[0002] This disclosure claims priority to Chinese Patent Application No. 202411035144.0, filed on July 30, 2024, entitled "Pixel Driving Circuit, Driving Method and Display Panel", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more specifically, to a pixel driving circuit, a driving method for the pixel driving circuit, and a display panel. Background Technology

[0004] Active-matrix organic light-emitting diodes (AMOLEDs) have become the best choice for future display technology due to their advantages such as high image quality, short mobile image response time, low power consumption, wide viewing angle, and ultra-thin design. Currently, the pixel driving circuits of AMOLED panels typically perform data writing and threshold voltage compensation simultaneously.

[0005] However, in high-frequency driving, the data voltage writing time is getting shorter and shorter, while the threshold voltage compensation requires a longer time. The limitation of the data writing time on the threshold voltage compensation time results in insufficient threshold voltage compensation time at high frequency and high resolution, which affects image quality.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] This disclosure provides a pixel driving circuit, a driving method for the pixel driving circuit, and a display panel.

[0008] According to one aspect of this disclosure, a pixel driving circuit is provided, including a driving transistor, a compensation circuit, a first initialization circuit, a writing circuit, and an energy storage circuit.

[0009] The writing circuit is connected to the first end of the energy storage circuit, and the second end of the energy storage circuit is connected to the control end of the driving transistor; the first end of the energy storage circuit is connected to the first end of the driving transistor through the first initialization circuit; the control end and the second end of the driving transistor are connected through the compensation circuit, and the second end of the driving transistor is connected to the light-emitting device.

[0010] The first initialization circuit is used to transmit a first initialization signal to the first terminal of the driving transistor and the first terminal of the energy storage circuit;

[0011] The writing circuit is connected to the writing control terminal and is used to transmit data signals to the energy storage circuit in response to the signals from the writing control terminal.

[0012] The energy storage circuit is used to couple the data signal to the control terminal of the driving transistor;

[0013] The compensation circuit is connected to the compensation control terminal and is used to respond to the signal turn-on and turn-off of the compensation control terminal.

[0014] In one exemplary embodiment of this disclosure, the first initialization circuit includes a first initialization sub-circuit and an adjustment sub-circuit;

[0015] The first initialization sub-circuit is connected to the first terminal and the first initialization control terminal of the driving transistor, and is used to transmit a first initialization signal to the first terminal of the driving transistor in response to the signal of the first initialization control terminal;

[0016] The adjustment sub-circuit is connected to the first terminal of the driving transistor and the first terminal of the energy storage circuit, and is connected to the adjustment control terminal to turn on and off in response to the signal from the adjustment control terminal.

[0017] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a second initialization circuit, a first light emission control circuit, and a second light emission control circuit.

[0018] The second initialization circuit is connected to the control terminal of the driving transistor and to the second initialization control terminal, and is used to transmit a second initialization signal to the control terminal of the driving transistor in response to the signal of the second initialization control terminal;

[0019] The first light-emitting control circuit is connected to the first terminal of the driving transistor and to the first light-emitting control terminal, and is used to transmit a first power signal to the first terminal of the driving transistor in response to the signal of the first light-emitting control terminal.

[0020] The second light-emitting control circuit is connected to the second terminal of the driving transistor and the light-emitting device, and is connected to the second light-emitting control terminal to turn on and off in response to the signal from the second light-emitting control terminal.

[0021] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a third initialization circuit, which is connected to the light-emitting device and to a third initialization control terminal, for transmitting a third initialization signal to the light-emitting device in response to a signal from the third initialization control terminal.

[0022] In one exemplary embodiment of this disclosure, the first initialization sub-circuit includes a first initialization transistor, the adjustment sub-circuit includes an adjustment transistor, the writing circuit includes a writing transistor, the compensation circuit includes a compensation transistor, and the energy storage circuit includes a coupling capacitor.

[0023] The control terminal of the first initialization transistor is connected to the first initialization control terminal, the first terminal is used to receive the first initialization signal, and the second terminal is connected to the first terminal of the driving transistor.

[0024] The control terminal of the adjustment transistor is connected to the adjustment control terminal, the first terminal is connected to the first terminal of the driving transistor, and the second terminal is connected to the first terminal of the coupling capacitor; the second terminal of the coupling capacitor is connected to the control terminal of the driving transistor.

[0025] The control terminal of the write transistor is connected to the write control terminal, the first terminal is used to receive the data signal, and the second terminal is connected to the first terminal of the coupling capacitor.

[0026] The control terminal of the compensation transistor is connected to the compensation control terminal, the first terminal is connected to the second terminal of the driving transistor, and the second terminal is connected to the control terminal of the driving transistor.

[0027] In one exemplary embodiment of this disclosure, the first light-emitting control circuit includes a first light-emitting control transistor, the second light-emitting control circuit includes a second light-emitting control transistor, and the second initialization circuit includes a second initialization transistor.

[0028] The control terminal of the first light-emitting control transistor is connected to the first light-emitting control terminal, the first terminal is used to receive the first power signal, and the second terminal is connected to the first terminal of the driving transistor.

[0029] The control terminal of the second light-emitting control transistor is connected to the second light-emitting control terminal, the first terminal is connected to the second terminal of the driving transistor, and the second terminal is connected to the light-emitting device;

[0030] The control terminal of the second initialization transistor is connected to the second initialization control terminal, the first terminal is used to receive the second initialization signal, and the second terminal is connected to the control terminal of the driving transistor.

[0031] In one exemplary embodiment of this disclosure, the third initialization circuit includes a third initialization transistor, the control terminal of the third initialization transistor is connected to the third initialization control terminal, the first terminal is used to receive the third initialization signal, and the second terminal is connected to the light-emitting device.

[0032] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a voltage regulator circuit, which is connected to a first terminal of the energy storage circuit and to a voltage regulation control terminal, for transmitting a constant voltage signal to the first terminal of the energy storage circuit in response to a signal from the voltage regulation control terminal.

[0033] In one exemplary embodiment of this disclosure, the voltage regulator circuit includes a voltage regulator capacitor, the first terminal of which is used to receive the constant voltage signal, and the second terminal is connected to the first terminal of the energy storage circuit.

[0034] In one exemplary embodiment of this disclosure, the compensation transistor includes a first sub-compensation transistor and a second sub-compensation transistor;

[0035] The control terminal of the first sub-compensation transistor is connected to the control terminal of the second sub-compensation transistor, and is also connected to the compensation control terminal. The first terminal of the first sub-compensation transistor is connected to the second terminal of the driving transistor, and the second terminal is connected to the first terminal of the second sub-compensation transistor. The second terminal of the second sub-compensation transistor is connected to the control terminal of the driving transistor.

[0036] In one exemplary embodiment of this disclosure, the second initialization transistor includes a first sub-initialization transistor and a second sub-initialization transistor;

[0037] The control terminal of the first sub-initialization transistor is connected to the control terminal of the second sub-initialization transistor, and is also connected to the second initialization control terminal. The first terminal of the first sub-initialization transistor is used to receive the second initialization signal, and the second terminal is connected to the first terminal of the second sub-initialization transistor. The second terminal of the second sub-initialization transistor is connected to the control terminal of the driving transistor.

[0038] The second terminal of the first sub-initialization transistor and the first terminal of the second sub-initialization transistor are connected to the light-emitting device.

[0039] In one exemplary embodiment of this disclosure, the second terminal of the first sub-initialization transistor and the first terminal of the second sub-initialization transistor are connected to the light-emitting device.

[0040] In one exemplary embodiment of this disclosure, the adjustment transistor includes a first sub-adjustment transistor and a second sub-adjustment transistor;

[0041] The control terminals of the first sub-adjustment transistor and the second sub-adjustment transistor are connected and connected to the adjustment control terminal. The first terminal of the first sub-adjustment transistor is connected to the first terminal of the driving transistor, and the second terminal is connected to the first terminal of the second sub-adjustment transistor. The second terminal of the second sub-adjustment transistor is connected to the first terminal of the coupling capacitor.

[0042] In one exemplary embodiment of this disclosure, the second light-emitting control circuit includes a second light-emitting control transistor; the control terminal of the second light-emitting control transistor is connected to the second light-emitting control terminal, the first terminal is connected to the second terminal of the driving transistor, and the second terminal is connected to the light-emitting device;

[0043] The third initialization transistor is an N-type transistor, the second light-emitting control transistor is a P-type transistor, and the third initialization control terminal and the second light-emitting control terminal are connected.

[0044] In one exemplary embodiment of this disclosure, the driving transistor, the writing transistor, and the first initialization transistor are polysilicon transistors;

[0045] At least one of the compensation transistor and the adjustment transistor is a metal-oxide transistor.

[0046] In one exemplary embodiment of this disclosure, the driving transistor, the first light-emitting control transistor, and the second light-emitting control transistor are polysilicon transistors;

[0047] The second light-emitting control transistor is a metal-oxide transistor.

[0048] In one exemplary embodiment of this disclosure, the first initialization control terminal is connected to the third initialization control terminal, and the adjustment control terminal is connected to the compensation control terminal.

[0049] In one exemplary embodiment of this disclosure, the first light-emitting control terminal and the second light-emitting control terminal are connected.

[0050] According to one aspect of this disclosure, a driving method for a pixel driving circuit is provided. The pixel driving circuit includes a driving transistor, a compensation circuit, a first initialization sub-circuit, an adjustment sub-circuit, a writing circuit, and an energy storage circuit. The first initialization sub-circuit is connected to a first terminal and a first initialization control terminal of the driving transistor. The adjustment sub-circuit is connected to the first terminal of the driving transistor and the first terminal of the energy storage circuit. The writing circuit is connected to the first terminal of the energy storage circuit, and the second terminal of the energy storage circuit is connected to the control terminal of the driving transistor. The control terminal and the second terminal of the driving transistor are connected through the compensation circuit, and the second terminal of the driving transistor is connected to a light-emitting device.

[0051] The driving method includes:

[0052] During the compensation phase, the first initialization sub-circuit, the adjustment sub-circuit, and the compensation circuit are turned on, and the writing circuit is turned off; the threshold voltage of the driving transistor and the first initialization signal are written to the control terminal of the driving transistor through the first initialization sub-circuit and the compensation circuit, and the first initialization signal is written to the first terminal of the energy storage circuit through the adjustment sub-circuit.

[0053] During the writing phase, the writing circuit is turned on, and the first initialization sub-circuit, the adjustment sub-circuit, and the compensation circuit are turned off; data signals are transmitted to the energy storage circuit through the writing circuit, and the voltage of the data signals is coupled to the control terminal of the driving transistor through the energy storage circuit.

[0054] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a second initialization circuit and a third initialization circuit, wherein the second initialization circuit is connected to the control terminal of the driving transistor; and the third initialization circuit is connected to the light-emitting device.

[0055] The driving method further includes:

[0056] During the initialization phase, the second initialization circuit is turned on, and the second initialization signal is transmitted to the control terminal of the driving transistor through the second initialization circuit.

[0057] During the compensation phase and / or the writing phase, the third initialization circuit is turned on, and a third initialization signal is transmitted to the light-emitting device through the third initialization circuit.

[0058] According to one aspect of this disclosure, a display panel is provided, including the pixel driving circuit described in any of the preceding claims.

[0059] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0060] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0061] Figure 1 is a top view schematic diagram of one embodiment of the display panel of this disclosure.

[0062] Figure 2 is a schematic diagram of some embodiments of the pixel driving circuit of this disclosure.

[0063] Figure 3 is a timing diagram of the pixel driving circuit in Figure 2.

[0064] Figures 4-7 show the schematic diagrams of the pixel driving circuit in Figure 2 at various stages.

[0065] Figure 8 is a schematic diagram of one embodiment of the pixel driving circuit of this disclosure.

[0066] Figure 9 is a timing diagram of the pixel driving circuit in Figure 8 in the holding frame.

[0067] Figure 10 is a schematic diagram of another embodiment of the pixel driving circuit of this disclosure.

[0068] Figure 11 is a timing diagram of the pixel driving circuit in Figure 10 in the holding frame.

[0069] Figure 12 is a schematic diagram of some embodiments of the pixel driving circuit of this disclosure.

[0070] Figure 13 is a timing diagram of the pixel driving circuit in Figure 12.

[0071] Figure 14 is a schematic diagram of some embodiments of the pixel driving circuit of this disclosure.

[0072] Figure 15 is a timing diagram of the pixel driving circuit in Figure 14.

[0073] Figure 16 is a schematic diagram of some embodiments of the pixel driving circuit of this disclosure.

[0074] Figure 17 is a timing diagram of the pixel driving circuit in Figure 16.

[0075] Figure 18 is a schematic diagram of some embodiments of the pixel driving circuit of this disclosure.

[0076] Figure 19 is a timing diagram of the pixel driving circuit in Figure 18.

[0077] Figure 20 is a schematic diagram of some embodiments of the pixel driving circuit of this disclosure.

[0078] Figure 21 is a timing diagram of the pixel driving circuit in Figure 20. Detailed Implementation

[0079] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0080] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0081] In this article, nTmC represents a circuit (e.g., a pixel driving circuit, a gate driving circuit, etc.) consisting of n transistors (represented by the letter "T") and m capacitors (represented by the letter "C").

[0082] In the circuit structures described herein (e.g., pixel driving circuits), the transistors used in the circuit structure can be thin-film transistors (TFTs), metal-oxide-semiconductor (MOS) transistors, or other switching devices with similar characteristics. The embodiments described herein all use thin-film transistors as an example. Furthermore, nodes such as the first node and the second node do not represent actual existing components, but rather represent relevant connecting points in the circuit diagram. In other words, these nodes are equivalent to relevant connecting points in the circuit diagram.

[0083] The transistor described in this article includes a control terminal, a first terminal, and a second terminal. The switching on and off of the first and second terminals can be achieved by controlling the voltage at the control terminal. The control terminal can be the gate, the first terminal can be the source, and the second terminal can be the drain; of course, the first terminal can also be the drain, and the second terminal can also be the source. Specifically, if a signal is input from the first terminal, then the first terminal is the source and the second terminal is the drain; if a signal is input from the second terminal, then the second terminal is the source and the first terminal is the drain. In other words, the source and drain can be interchanged depending on the change in the input signal.

[0084] For a P-type transistor, when a high level is received at the control terminal, both terminals are turned off; when a low level is received at the control terminal, both terminals are turned on. For an N-type transistor, when a high level is received at the control terminal, both terminals are turned on; when a low level is received, both terminals are turned off.

[0085] As shown in Figure 1, this embodiment of the present disclosure provides a display panel, which may include a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA may be a continuous annular area surrounding the display area AA, or it may be a discontinuous area surrounding the display area AA.

[0086] The display panel may include a driving backplate and multiple light-emitting devices disposed on one side of the driving backplate. The light-emitting devices are arranged in an array, and the light-emitting devices (LDs) can be driven to emit light through the driving circuit in the driving backplate to display images.

[0087] As shown in Figure 1, the light-emitting device LD can be located within the display area AA. It can be an OLED (organic light-emitting diode) using organic light-emitting materials; or an LED (light-emitting diode) using inorganic light-emitting materials, such as Micro LED (micron light-emitting diode) and Mini LED (sub-millimeter light-emitting diode); or a QLED (quantum dot diode), etc. No specific restrictions are placed on the specific structure of the display panel, as long as it can display images.

[0088] Taking an OLED as an example, the light-emitting device may include a first electrode, a light-emitting layer, and a second electrode stacked sequentially in a direction away from the driving backplane. By applying an electrical signal to the first and second electrodes, the light-emitting layer can be excited to emit light; the specific principle will not be detailed here. Meanwhile, to define the range of the light-emitting device (LD), a pixel definition layer can be provided on the driving backplane. The pixel definition layer and the first electrode are located on the same surface of the driving backplane, and the pixel definition layer may have pixel openings exposing each of the first electrodes, thereby defining the range of the light-emitting device (LD) through each pixel opening.

[0089] As shown in Figure 1, the driving circuit may include a pixel driving circuit PC located in the display area AA and peripheral circuits located in the peripheral area WA. The pixel driving circuits PC may be arrayed, and one pixel driving circuit PC may be connected to the first electrode of a light-emitting device LD. A row of pixel driving circuits PC may be connected to the first electrode of each of the light-emitting devices LD in a row. Of course, the same pixel driving circuit PC may be connected to the first electrodes of multiple light-emitting devices LD. The pixel driving circuit PC may include multiple transistors and may also include capacitors, which may be of a 2T1C, 3T1C, 7T1C, or other structures.

[0090] The peripheral circuit WP can be connected to the first electrode of the light-emitting device LD through the pixel driving circuit PC. The peripheral circuit WP can also be connected to the second electrode of the light-emitting device LD and apply a second power signal to the second electrode. The current passing through the light-emitting device LD can be controlled by the pixel driving circuit PC, thereby controlling the brightness of the light-emitting device LD.

[0091] The peripheral circuit WP may include at least one gate driving circuit and a light-emitting control circuit for scanning some transistors in the pixel driving circuit PC, that is, outputting a scan signal to the control terminal of the transistor to control the transistor's on and off states. The signals output by the aforementioned gate driving circuit and light-emitting driving circuit can realize the on and off states of the transistors in the pixel driving circuit PC, thus achieving scanning of the pixel driving circuit PC and controlling the light-emitting device LD to emit light.

[0092] Each gate driving circuit and light emission control circuit may include multiple cascaded shift registers. That is, the output of the nth-stage shift register is connected to the gate of the transistor in at least one row of pixel driving circuits (PC), and also to the input of the (n+1)th-stage shift register, so that the output signal of the previous stage shift register serves as the input signal of the next stage shift register. Any shift register may include multiple transistors and capacitors, and its structure can be 7T2C, 8T2C, etc., without special limitation. Furthermore, the structures of the shift registers in the gate driving circuit and the light emission control circuit can be different.

[0093] As shown in Figure 1, the output signal of the shift register is the scanning signal mentioned above. The gate of some transistors in the row pixel driving circuit PC can be connected to the output of the first-level shift register. Of course, the first-level shift register can be connected to multiple row pixel driving circuits PC and scan multiple row pixel driving circuits PC at the same time. However, the output signal of the same shift register can have different effects in different row pixel driving circuits PC.

[0094] In addition, the peripheral area WA of the display panel can be provided with a source drive circuit DP for transmitting data signals to the pixel drive circuit PC. This can be a chip or a circuit integrated on the display panel.

[0095] The pixel driving circuit of this disclosure is described below by way of example:

[0096] As shown in Figure 2, the pixel driving circuit may include a driving transistor T3, a compensation circuit 2, a first initialization circuit 100, a writing circuit 4, and an energy storage circuit 10, wherein:

[0097] The writing circuit 4 can be connected to the first end of the energy storage circuit 10, and the second end of the energy storage circuit 10 is connected to the control end of the driving transistor T3; the first end of the energy storage circuit 10 is connected to the first end of the driving transistor T3 through the first initialization circuit 100; the control end and the second end of the driving transistor T3 are connected through the compensation circuit 2, and the second end of the driving transistor T3 is connected to the light-emitting device LD.

[0098] For example, the second terminal of the energy storage circuit 10 is connected to the control terminal of the driving transistor T3 at the first node N1, the first initialization circuit 100 is connected to the first terminal of the driving transistor T3 at the second node N2, the compensation circuit 2 is connected to the second terminal of the driving transistor T3 at the third node N3, the light-emitting device LD (first electrode) is connected to the fourth node N4, the fourth node N4 is connected to the third node N3, and the writing circuit 4 is connected to the first terminal of the energy storage circuit 10 at the fifth node N5.

[0099] The first initialization circuit 100 can transmit a constant-potential first initialization signal Vinit3 to the first terminal of the driving transistor T3 and the first terminal of the energy storage circuit 10 when it is turned on. The write circuit 4 is connected to the write control terminal G4 that provides the write scan signal, and can be turned on and off under the control of the signal from the write control terminal G4; the write circuit 4 can receive the data signal Data, and can transmit the data signal Data to the energy storage circuit 10 when it is turned on. The energy storage circuit 10 can couple the data signal Data to the control terminal of the driving transistor T3.

[0100] The compensation circuit 2 is connected to the compensation control terminal G2 and can be turned on and off under the control of the signal of the compensation control terminal G2. When it is turned on, it makes the control terminal and the second terminal of the driving transistor T3 turn on.

[0101] The pixel driving circuit of this disclosure can control the voltage of the control terminal of the driving transistor T3 to make it work in the linear region, thereby controlling the current of the driving transistor T3 by controlling the voltage of its control terminal, and then controlling the brightness of the light-emitting device LD by the current.

[0102] A first initialization signal Vinit3 can be written to the first terminal of the driving transistor T3 through the first initialization circuit 100. The voltage difference between the first initialization signal Vinit3 and the control terminal of the driving transistor T3 is greater than the threshold voltage of the driving transistor T3, causing the driving transistor T3 to conduct. Simultaneously, the compensation circuit 2 conducts, and as the voltage at the first terminal of the driving transistor T3 decreases, the driving transistor T3 turns off, thereby writing the threshold voltage and the first initialization signal Vinit3 to the control terminal of the driving transistor T3. Based on the current formula of the driving transistor T3, the influence of the threshold voltage on the current can be eliminated simultaneously. When the first initialization signal Vinit3 is a constant voltage signal, the current can be controlled only through the data signal Data, thereby controlling the brightness of the light-emitting device LD. This avoids the problem of uneven brightness caused by threshold voltage deviation due to process, materials, etc. In addition, the first initialization circuit can also write the first initialization signal Vinit3 to the first terminal of the energy storage circuit 10 for initialization.

[0103] As shown in Figure 2, in some embodiments of this disclosure, the first initialization circuit 100 includes a first initialization sub-circuit 8 and an adjustment sub-circuit 9, wherein:

[0104] The first initialization sub-circuit 8 is connected to the first terminal of the driving transistor T3 and the first initialization control terminal G8, and can be turned on and off under the control of the signal of the first initialization control terminal G8. When it is turned on, it can transmit the first initialization signal Vinit3 to the first terminal of the driving transistor T3.

[0105] The adjustment sub-circuit 9 is connected to the first terminal of the driving transistor T3 and the first terminal of the energy storage circuit 10, and is also connected to the adjustment control terminal G9. The adjustment sub-circuit 9 can be turned on and off under the control of the signal from the adjustment control terminal G9.

[0106] For example, the first initialization sub-circuit 8 and the first terminal of the driving transistor T3 are connected to the second node N2, the adjustment sub-circuit 9 is connected to the second node N2, and is also connected to the fifth node N5.

[0107] When driving the pixel driving circuit, the first initialization sub-circuit 8 can be turned on, transmitting the first initialization signal Vinit3 to the first terminal of the driving transistor T3 and the first terminal of the energy storage circuit 10. By making the voltage difference between the first initialization signal Vinit3 and the control terminal of the driving transistor T3 greater than the threshold voltage of the driving transistor T3, the driving transistor T3 can be turned on. The first initialization signal Vinit3 and the threshold voltage can be written to the control terminal of the driving transistor T3 through the turned-on compensation circuit 2 until the driving transistor T3 is turned off. At the same time, the first initialization signal Vinit3 can reset the first terminal of the energy storage circuit 10. That is to say, the first initialization signal Vinit3 simultaneously realizes the reset and the writing of the threshold voltage.

[0108] As shown in Figure 2, in some embodiments of this disclosure, the pixel driving circuit may further include a second initialization circuit 1, a first light emission control circuit 5, and a second light emission control circuit 6, wherein:

[0109] The second initialization circuit 1 is connected to the control terminal of the driving transistor T3 and to the second initialization control terminal G1. The second initialization circuit 1 can be turned on and off under the control of the signal of the second initialization control terminal G1. When it is turned on, it can transmit the second initialization signal Vinit1 to the control terminal of the driving transistor T3.

[0110] The first light-emitting control circuit 5 is connected to the first terminal of the driving transistor T3 and to the first light-emitting control terminal G5. The first light-emitting control circuit 5 can also be connected to the first power supply terminal, which can provide a constant potential first power supply signal VDD. The first light-emitting control circuit 5 can be turned on and off under the control of the signal from the first light-emitting control terminal G5. When it is turned on, it can transmit the first power supply signal VDD to the first terminal of the driving transistor T3.

[0111] The second light-emitting control circuit 6 is connected to the second terminal of the driving transistor T3 and the first electrode of the light-emitting device LD. The second light-emitting control circuit 6 is connected to the second light-emitting control terminal G6 and can be turned on and off under the control of the signal from the second light-emitting control terminal G6. When turned on, it connects the second terminal of the driving transistor T3 and the light-emitting device LD. The second electrode of the light-emitting device LD can be connected to the second power supply signal VSS.

[0112] For example, the second initialization circuit 1 is connected to the first node N1, the first light-emitting control circuit 5 is connected to the second node N2, and the second light-emitting control circuit 6 is connected to the third node N3 and the fourth node N4.

[0113] As shown in Figure 2, in some embodiments of this disclosure, the pixel driving circuit may further include a third initialization circuit 7, which can be connected to the first electrode of the light-emitting device LD and, correspondingly, to the second light-emitting control circuit 6. Simultaneously, the third initialization circuit 7 can receive a third initialization signal Vinit2, and is connected to a third initialization control terminal G7. The third initialization circuit 7 can be turned on and off under the control of the signal from the third initialization control terminal G7, and when turned on, it can transmit the third initialization signal Vinit2 to the first electrode of the light-emitting device LD.

[0114] As shown in Figure 2, in some embodiments of this disclosure, the pixel driving circuit may further include a voltage regulator circuit 11. The voltage regulator circuit 11 is connected to the first terminal of the energy storage circuit 10 and can transmit a constant voltage signal to the first terminal of the energy storage circuit 10. For example, the voltage regulator circuit 11 and the first terminal of the energy storage circuit 10 may be connected to the fifth node N5, and the constant voltage signal may be the first power supply signal VDD. When the write circuit 4 is turned on, the voltage of the fifth node is the voltage of the data signal Data and can be coupled to the first node N1; after the write circuit 4 is turned off, the voltage of the fifth node N5 can be kept stable by the voltage regulator circuit 11, and correspondingly, the voltage of the first node N1 can be kept stable.

[0115] The pixel driving circuits described above can all include at least one transistor or capacitor. The specific structure of the pixel driving circuits described above is illustrated below:

[0116] As shown in Figure 2, the first initialization sub-circuit 8 includes a first initialization transistor T8, and the adjustment sub-circuit 9 includes an adjustment transistor T9; the writing circuit 4 includes a writing transistor T4, and the compensation circuit 2 includes a compensation transistor T2; the energy storage circuit 10 includes a coupling capacitor Cst1; wherein:

[0117] The control terminal of the first initialization transistor T8 is connected to the first initialization control terminal G8 and is used to receive the first initialization scan signal scan1; the first terminal of the first initialization transistor T8 can receive the first initialization signal Vinit3; the second terminal of the first initialization transistor T8 and the first terminal of the driving transistor T3 are connected to the second node N2.

[0118] The control terminal of the adjusting transistor T9 is connected to the adjusting control terminal G9 to receive the scanning signal An; the first terminal of the adjusting transistor T9 is connected to the first terminal of the driving transistor T3 at the second node N2; the second terminal of the adjusting transistor T9 can be connected to the first terminal of the coupling capacitor Cst1 at the fifth node N5; the second terminal of the coupling capacitor Cst1 is connected to the control terminal of the driving transistor T3 at the first node N1.

[0119] The control terminal of the write transistor T4 is connected to the write control terminal G4 to receive the write scan signal scan2; the first terminal of the write transistor T4 is used to receive the data signal Data, and the second terminal of the write transistor T4 is connected to the first terminal of the coupling capacitor Cst1 at the fifth node N5.

[0120] The control terminal of the compensation transistor T2 is connected to the compensation control terminal G2 to receive the scan signal An; the first terminal of the compensation transistor T2 can be connected to the second terminal of the driving transistor T3 at the third node N3, and the second terminal of the compensation transistor T2 can be connected to the control terminal of the driving transistor T3 at the first node N1.

[0121] As shown in Figure 2, in some embodiments of this disclosure, the first light-emitting control circuit 5 includes a first light-emitting control transistor T5, the second light-emitting control circuit 6 includes a second light-emitting control transistor T6, and the second initialization circuit 1 includes a second initialization transistor T1; wherein:

[0122] The control terminal of the first light-emitting control transistor T5 is connected to the first light-emitting control terminal G5 to receive the first light-emitting scanning signal EM1; the first terminal of the first light-emitting control transistor T5 is connected to the first power supply terminal to receive the first power supply signal VDD; and the second terminal of the first light-emitting control transistor T5 is connected to the first terminal of the driving transistor T3 at the second node N2.

[0123] The control terminal of the second light-emitting control transistor T6 is connected to the second light-emitting control terminal G6 to receive the first light-emitting scanning signal EM1; the first terminal of the second light-emitting control transistor T6 is connected to the second terminal of the driving transistor T3 at the third node N3, and the second terminal of the second light-emitting control transistor T6 is connected to the first electrode of the light-emitting device LD at the fourth node N4.

[0124] The control terminal of the second initialization transistor T1 is connected to the second initialization control terminal G1 and is used to receive the second initialization scan signal scan; the first terminal of the second initialization transistor T1 is used to receive the second initialization signal Vinit1, and the second terminal of the second initialization transistor T1 is connected to the control terminal of the driving transistor T3 at the first node N1.

[0125] As shown in Figure 2, in some embodiments of this disclosure, the third initialization circuit 7 includes a third initialization transistor T7. The control terminal of the third initialization transistor T7 is connected to the third initialization control terminal G7 and is used to receive the first initialization scan signal scan1. The first terminal of the third initialization transistor T7 can receive the third initialization signal Vinit2, and the second terminal of the third initialization transistor T7 is connected to the first electrode of the light-emitting device LD at the fourth node N4. Of course, in some embodiments of this disclosure, the pixel driving circuit may not include the third initialization circuit 7.

[0126] As shown in Figure 2, in some embodiments of this disclosure, the voltage regulator circuit 11 includes a voltage regulator capacitor Cst2. The first terminal of the voltage regulator capacitor Cst2 can receive a constant voltage signal, and the second terminal of the voltage regulator capacitor Cst2 is connected to the first terminal of the energy storage circuit 10. For example, the first terminal of the voltage regulator capacitor Cst2 is connected to the first power supply terminal, and the constant voltage signal is the first power supply signal VDD. The second terminal of the voltage regulator capacitor Cst2 can be connected to the second terminal of the writing transistor T4 and the first terminal of the coupling capacitor Cst1 at the fifth node N5. The voltage of the first node N1 can be stabilized through the voltage regulator capacitor Cst2.

[0127] As shown in Figures 2 and 3, the following section takes a pixel driving circuit where all transistors are P-type transistors as an example, and explains its specific working principle in detail, combined with its driving method:

[0128] As shown in Figure 4, during the initialization phase t1: the first initialization scan signal scan1, scan signal An, adjustment scan signal An, write scan signal scan2, and the first light-emitting scan signal EM1 are at high levels, while the second initialization scan signal scan is at a low level. This turns on the second initialization transistor T1, writes the second initialization signal Vinit1 to the first node N1, resets the control terminal of the driving transistor T3, and eliminates the influence of the previous frame image. Simultaneously, the first initialization transistor T8, compensation transistor T2, adjustment transistor T9, write transistor T4, third initialization transistor T7, first light-emitting control transistor T5, and second light-emitting control transistor T6 are all turned off. During this phase, the light-emitting device LD does not emit light.

[0129] As shown in Figure 5, during the compensation phase t2: the first initialization scan signal scan1 and scan signal An are at low levels; the second initialization scan signal scan, the write scan signal scan2, and the first light emission scan signal EM1 are all at high levels; this turns on the first initialization transistor T8, the adjustment transistor T9, the third initialization transistor T7, and the compensation transistor T2. The voltage difference between the first initialization signal Vinit3 and the second initialization signal Vinit1 turns on the driving transistor T3, transmitting the first initialization signal Vinit3 to the first node N1 via the first initialization transistor T8, the driving transistor T3, and the compensation transistor T2. During this process, the voltage of the first node N1 gradually changes until the driving transistor T3 turns off, thus writing the threshold voltage of the driving transistor T3 into the first node N1, achieving threshold voltage compensation. At this time, the voltage of the first node N1 is the sum of the first initialization voltage Vinit3 and the threshold voltage Vth of the driving transistor T3. Meanwhile, the first initialization signal Vinit3 can be written to the fifth node N5 by adjusting transistor T9, resetting the first end of the coupling capacitor Cst1, so that the voltage of the fifth node N5 is the voltage of the first initialization signal Vinit3. In this way, the voltage difference across the coupling capacitor Cst1 is the threshold voltage Vth of the driving transistor T3, thereby storing the threshold voltage Vth in the coupling capacitor Cst1.

[0130] The third initialization signal Vinit2 can be written to the first electrode of the light-emitting device LD through the third initialization transistor T7 to achieve reset. Of course, in some embodiments of this disclosure, the reset process of the light-emitting device LD can also be performed in the initialization stage t1 or the writing stage t3 below.

[0131] In addition, during the compensation phase t2, the write transistor T4, the second initialization transistor T1, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are all turned off.

[0132] As shown in Figure 6, during the writing stage t3: the write scan signal scan2 is low; the first initialization scan signal scan1, scan signal An, the second initialization scan signal scan, and the first light emission scan signal EM1 are all high; the write transistor T4 is turned on, and the data signal Data is written to the fifth node N6. Through the coupling effect of the coupling capacitor Cst1, the voltage of the data signal Data can be coupled into the first node N1. At this time, the voltage of the first node N1 is the sum of the voltage of the data signal Data and the threshold voltage Vth of the driving transistor T3.

[0133] Based on this scheme, the threshold voltage Vth is compensated by writing the first initial signal Vinit3 to the first node N1, while the voltage of the data signal Data is written to the first node N1 through coupling capacitor Cst1. The two processes are independent of each other, that is, the compensation and writing are separated. Therefore, even if the writing time of the data signal Data is shortened, it will not limit the compensation of the threshold voltage Vth, and sufficient compensation time for the threshold voltage Vth can be guaranteed, thereby supporting higher frequency driving. For example, the frequency can generally reach 120Hz without the aforementioned compensation and writing separation circuit, while the frequency can reach 240Hz or even higher with the aforementioned separation circuit.

[0134] Furthermore, during the writing phase t3, the second initialization transistor T1, the first initialization transistor T8, the compensation transistor T2, the adjustment transistor T9, the third initialization transistor T7, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are all turned off. During this phase, the light-emitting device LD does not emit light.

[0135] As shown in Figure 7, during the light emission stage t4: the first light emission scanning signal EM1 is at a low level, and the first initialization scanning signal scan1, the scanning signal An, the write scanning signal scan2, and the second initialization scanning signal scan are all at a high level; this turns on the first light emission control transistor T5 and the second light emission control transistor T6, while the first initialization transistor T8, the second initialization transistor T1, the compensation transistor T2, the adjustment transistor T9, the write transistor T4, and the third initialization transistor T7 are turned off.

[0136] The voltage of the first power supply signal VDD can be output to the second node N2, and the voltage of the third node N3 can be output to the fourth node N4. The driving transistor T3 can control the current flowing from the first power supply terminal (VDD) to the second power supply terminal (VSS) through the light-emitting device LD in response to the voltage of the first node N1. Accordingly, the light-emitting device LD can emit light with corresponding brightness based on the current output from the driving transistor T3.

[0137] During this process, the voltage Vg at the control terminal of the driving transistor T3 can be stabilized at Vdata+Vth, and the voltage Vs at the first terminal can be the voltage of the first power supply signal VDD. Then, the current I of the light-emitting device LD satisfies the following formula:

[0138] I = (μWCox / 2L) × (Vgs - Vth) 2

[0139] =(μWCox / 2L)×((Vdata+Vth)-VDD-Vth) 2

[0140] = (μWCox / 2L) × (Vdata - VDD) 2 ;

[0141] Where μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the channel width of the driving transistor T3; L is the channel length of the driving transistor T3; Vdata is the voltage of the data signal Data; and Vth is the threshold voltage of the driving transistor T3.

[0142] It can be seen that the current magnitude can be controlled by adjusting the voltage Vdata of the data signal Data, thereby adjusting the brightness and avoiding the influence of the threshold voltage Vth. This is beneficial for maintaining the voltage stability of the gate of the driving transistor T3 and ensuring uniform brightness.

[0143] In other embodiments of this disclosure, the first light-emitting control transistor T5 can be turned on during the compensation stage t2, and the first power supply signal VDD can be used to replace the first initialization signal Vinit3 mentioned above to achieve compensation of the threshold voltage Vth. Therefore, the first initialization circuit 100 may not be equipped with the first initialization transistor T8.

[0144] Furthermore, in some embodiments of this disclosure, to reduce leakage current in some transistors, a dual-channel dual-gate structure can be used. A dual-channel dual-gate transistor can be considered as two transistors connected in series, with their control terminals (gates) connected. They can be synchronously turned on and off under the control of the same scan signal, thus reducing leakage current. For example, the channel portion of the transistors can be different semiconductor portions within the same semiconductor layer, and their gates can be different gates within the same gate layer. The two gates overlap with the two semiconductor portions, forming two transistors, and the two semiconductor portions are connected as a single structure, realizing the series connection of the two transistors. Of course, in some embodiments of this disclosure, metal-oxide transistors can also be used to reduce leakage current.

[0145] The following is an exemplary description of a transistor that can employ the above-described dual-channel dual-gate structure:

[0146] As shown in Figure 8, in some embodiments of this disclosure, the second initialization transistor T1 includes a first sub-initialization transistor T11 and a second sub-initialization transistor T12; wherein:

[0147] The control terminals of the first sub-initialization transistor T11 and the second sub-initialization transistor T12 are connected and also connected to the second initialization control terminal G1. This connection is used to receive the second initialization scan signal (scan), and the first and second sub-initialization transistors T11 and T12 are turned on and off under the control of this scan signal. The first terminal of the first sub-initialization transistor T11 receives the second initialization signal (Vinit1), and the second terminal of the first sub-initialization transistor T11 is connected to the first terminal of the second sub-initialization transistor T12, thus connecting the first and second sub-initialization transistors T11 and T12 in series. The second terminal of the second sub-initialization transistor T22 is connected to the control terminal of the driving transistor T3 at the first node N1. Compared to transistors using only a single-channel, single-gate configuration, the first and second sub-initialization transistors T11 and T12 can reduce leakage current.

[0148] As shown in Figure 14, the compensation transistor T2 can adopt a dual-channel dual-gate structure, that is, the compensation transistor T2 may include a first sub-compensation transistor T21 and a second sub-compensation transistor T22; wherein:

[0149] The control terminals of the first sub-compensation transistor T21 and the second sub-compensation transistor T22 are connected and also connected to the compensation control terminal G2. The first and second sub-compensation transistors T21 and T22 can be synchronously turned on and off via a compensation scan signal. The first terminal of the first sub-compensation transistor T21 is connected to the second terminal of the driving transistor T3 at the third node N3, and the second terminal of the first sub-compensation transistor T21 is connected to the first terminal of the second sub-compensation transistor T22. The second terminal of the second sub-compensation transistor T22 is connected to the control terminal of the driving transistor T3 at the third node N3. Thus, the first and second sub-compensation transistors T21 and T22 are connected in series between the third node N3 and the first node N1. Compared to using only a single-channel, single-gate transistor, the first and second sub-compensation transistors T21 and T22 can reduce leakage current.

[0150] As shown in Figure 14, in some embodiments of this disclosure, the adjustment transistor T9 includes a first sub-adjustment transistor T91 and a second sub-adjustment transistor T92; wherein:

[0151] The control terminals of the first sub-adjustment transistor T91 and the second sub-adjustment transistor T92 are connected and also connected to the adjustment control terminal G9 to receive the scan signal An. The first and second sub-adjustment transistors T91 and T92 can be turned on and off under the control of this scan signal. The first terminal of the first sub-adjustment transistor T91 is connected to the first terminal of the driving transistor T3, and the second terminal of the first sub-adjustment transistor T91 is connected to the first terminal of the second sub-adjustment transistor T92, thus connecting the first and second sub-adjustment transistors T91 and T92 in series. The second terminal of the second sub-adjustment transistor T92 is connected to the first terminal of the coupling capacitor Cst1 at the fifth node N5. Compared to transistors using only a single-channel but gate-only design, the first and second sub-adjustment transistors T91 and T92 can reduce leakage current.

[0152] In some embodiments of this disclosure, the driving transistor T3, the first light-emitting control transistor T5, the writing transistor T4, the first initialization transistor T8, and the third initialization transistor T7 may be polysilicon transistors, and all of them are P-type polysilicon transistors. Meanwhile, at least one of the second initialization transistor T1, the compensation transistor T2, the adjustment transistor T9, and the second light-emitting control transistor T6 is a metal-oxide transistor, and specifically an N-type metal-oxide transistor; by utilizing the lower mobility of metal-oxide transistors compared to polysilicon transistors, leakage current can be reduced.

[0153] Of course, in other embodiments of this disclosure, all transistors in the pixel driving circuit may also be polysilicon transistors or metal oxide transistors.

[0154] Based on the above explanation, the following examples illustrate various pixel driving circuits and their working principles:

[0155] In some embodiments of this disclosure, as shown in Figures 2 and 3, the pixel driving circuit includes the first initialization transistor T8, the second initialization transistor T1, the third initialization transistor T7, the compensation transistor T2, the write transistor T4, the driving transistor T3, the first light-emitting control transistor T5, the adjustment transistor T9, the second light-emitting control transistor T6, the coupling capacitor Cst1, and the voltage stabilizing capacitor Cst2 mentioned above. Each transistor is a P-type polysilicon transistor. The specific connection relationship can be referred to the embodiments described above, and will not be repeated here.

[0156] To reduce the number of scan signals, thereby reducing the number of gate drive circuits and light emission control circuits, the compensation control terminal G2 and the adjustment control terminal G9 can be connected and share the same scan signal An, so that the compensation transistor T2 and the adjustment transistor T9 are turned on and off synchronously; the first light emission control terminal G5 and the second light emission control terminal G6 can be connected and share the first light emission scan signal EM1, so that the first light emission control transistor T5 and the second light emission control transistor T6 are turned on and off synchronously.

[0157] Of course, in other embodiments, the compensation control terminal G2 and the adjustment control terminal G9 can receive different scanning signals respectively, and the first light emission control terminal G5 and the second light emission control terminal G6 can also be connected to different scanning signals.

[0158] The driving method described above can be referred to the implementation method described above, and will not be described in detail here.

[0159] In some embodiments of this disclosure, as shown in Figures 8-11, the pixel driving circuit includes the first initialization transistor T8, the second initialization transistor T1, the third initialization transistor T7, the compensation transistor T2, the write transistor T4, the driving transistor T3, the first light-emitting control transistor T5, the adjustment transistor T9, the second light-emitting control transistor T6, the coupling capacitor Cst1, and the voltage stabilizing capacitor Cst2 mentioned above. The second initialization transistor T1 is a dual-channel dual-gate transistor as described above, the third initialization transistor T7 is an N-type metal-oxide transistor, and the other transistors are all P-type polysilicon transistors. Their connection relationships are the same as those in the embodiments shown in Figures 2 and 3 above, and will not be repeated here.

[0160] Furthermore, as shown in Figures 8 and 9, the third initialization control terminal G7 and the second light-emitting control terminal G6 can be connected, allowing the control terminal of the third initialization transistor T7 to be connected to the control terminal of the second light-emitting control transistor T6. The first light-emitting scan signal EM1 can control the conduction and cutoff of the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the third initialization transistor T7. The first terminal of the third initialization transistor T7 can be connected to the third initialization signal Vinit2. Simultaneously, since the third initialization transistor T7 is an N-type transistor and the second light-emitting control transistor T6 is a P-type transistor, their conduction states are opposite: when the third initialization transistor T7 is on, the second light-emitting control transistor T6 is off; when the third initialization transistor T7 is off, the second light-emitting control transistor T6 is on. This avoids synchronous conduction, ensuring complementary interference between the light-emitting and initialization processes, and reduces the number of scan signals, which is beneficial for reducing the number of gate drive circuits and light-emitting control circuits.

[0161] Furthermore, as shown in Figures 10 and 11, the first terminal of the third initialization transistor T7 can be connected to the second initialization signal Vinit1 instead of the third initialization signal Vinit2, thus realizing the multiplexing of the initialization signal; the second terminal of the first sub-initialization transistor T11 and the first terminal of the second sub-initialization transistor T12 are connected to node Nt, which is connected to the fourth node N4, thereby connecting node Nt to the first electrode of the light-emitting device LD. Under different gray levels, the leakage current of the second initialization transistor T1 can be dynamically adjusted by the voltage of the second initialization signal Vinit1, and in the holding frame when displaying the image, the voltage of the dual-gate node of the second initialization transistor T1, i.e., the voltage of node Nt, can be reset, which helps to adjust the brightness retention rate within a frame in low-frequency driving.

[0162] The driving method described above can be referred to the implementation methods in Figures 2 and 3 above, and will not be described in detail here.

[0163] In some embodiments of this disclosure, as shown in Figures 12 and 13, the pixel driving circuit includes the first initialization transistor T8, the second initialization transistor T1, the third initialization transistor T7, the compensation transistor T2, the write transistor T4, the driving transistor T3, the first light-emitting control transistor T5, the adjustment transistor T9, the second light-emitting control transistor T6, the coupling capacitor Cst1, and the voltage stabilizing capacitor Cst2 mentioned above. The second initialization transistor T1 is a dual-channel dual-gate transistor, the third initialization transistor T7 is an N-type metal-oxide-semiconductor transistor, and the other transistors are all P-type polysilicon transistors. Their connections are similar to those described in the second type of embodiment above and will not be repeated here. In this embodiment, the first terminal of the third initialization transistor T7 is connected to the third initialization signal Vinit2, instead of the second initialization signal Vinit1. At the same time, the third initialization control terminal G7 and the second light-emitting control terminal G6 can be connected, and the second light-emitting control transistor T6 and the third initialization transistor T7 can be turned on and off by the second light-emitting scan signal EM2. The first light-emitting control terminal G5 is not connected to the second light-emitting control terminal G6, but can be connected to the first light-emitting scan signal EM1, and the second light-emitting control transistor T6 can be turned on and off independently by the first light-emitting scan signal EM1.

[0164] In some embodiments of this disclosure, as shown in Figures 14 and 15, the pixel driving circuit includes the first initialization transistor T8, the second initialization transistor T1, the compensation transistor T2, the write transistor T4, the driving transistor T3, the first light-emitting control transistor T5, the adjustment transistor T9, the second light-emitting control transistor T6, the coupling capacitor Cst1, and the voltage stabilizing capacitor Cst2 mentioned above; but without the third initialization transistor T7; wherein, the second initialization transistor T1, the compensation transistor T2, and the adjustment transistor T9 are all transistors with a dual-channel dual-gate structure as described above; each transistor is a P-type polysilicon transistor, and the connection relationship can be referred to the embodiments in Figures 2 and 3 above, which will not be repeated here.

[0165] The second terminal of the first sub-initialization transistor T11 and the first terminal of the second sub-initialization transistor T12 are connected to node Nt, which is connected to the fourth node N4, thereby connecting node Nt to the first electrode of the light-emitting device (LD). At different grayscale levels, the leakage current of the second initialization transistor T1 can be dynamically adjusted by the voltage of the fourth node N4, i.e., the voltage of the first electrode of the LD. Furthermore, during the holding frame when displaying an image, the voltage of the dual-gate node of the second initialization transistor T1, i.e., the voltage of node Nt, can be reset, which helps to adjust the brightness retention rate within a frame during low-frequency driving.

[0166] The driving method of the above implementation is as follows:

[0167] During initialization phase t1: the second initialization transistor T1 is turned on, and the second initialization signal Vinit1 resets the first node N1; at the same time, the first light-emitting control transistor T5 is turned off, while the second light-emitting control transistor T6 is turned on, and the second initialization signal Vinit1 can be written to the fourth node N4 and the third node N3 through node Nt, thus resetting the fourth node N4 and the third node N3.

[0168] During the compensation phase t2: the second initialization transistor T1 and the second light-emitting control transistor T6 are turned off, and the first initialization transistor T8, the driving transistor T3 and the compensation transistor T2 are turned on. The first initialization signal Vinit3 compensates the threshold voltage Vth through the first initialization transistor T8, the driving transistor T3 and the compensation transistor T2, and at the same time resets the fifth node N5. For the specific principle, please refer to the explanation of the driving method above, which will not be repeated here.

[0169] The conduction and turn-off states of each transistor in the writing stage t3 and the light emission stage t4 can be the same as those described in the above implementation method. For details, please refer to the driving method described above.

[0170] In some embodiments of this disclosure, as shown in Figures 16 and 17, the pixel driving circuit includes the first initialization transistor T8, the second initialization transistor T1, the third initialization transistor T7, the compensation transistor T2, the write transistor T4, the driving transistor T3, the first light-emitting control transistor T5, the adjustment transistor T9, the second light-emitting control transistor T6, the coupling capacitor Cst1, and the voltage stabilizing capacitor Cst2. The second initialization transistor T1, the compensation transistor T2, and the adjustment transistor T9 are N-type metal-oxide transistors, while the other transistors are P-type polysilicon transistors. Their connections are as described in the embodiments above and will not be repeated here.

[0171] N-type transistors and P-type transistors can use different paths to provide the scan signal. The compensation control terminal G2 and the adjustment control terminal G9 are connected and can share the scan signal An, allowing the compensation transistor T2 and the adjustment transistor T9 to turn on and off synchronously. The second initialization control terminal G1 can be connected to the same gate drive circuit as the compensation control terminal G2 and the adjustment control terminal G9. However, the compensation control terminal G2 and the adjustment control terminal G9 can be connected to the same level shift register, while the second initialization control terminal G1 can be connected to another shift register at a different level to receive the scan signal An-n. For example, the compensation control terminal G2 and the adjustment control terminal G9 can be connected to the nth level shift register, while the second initialization control terminal G1 can be connected to the nith level shift register preceding the nth level shift register, where n and i are both positive integers and i is less than n. This allows the second initialization transistor T1 to turn on before the compensation transistor T2 and the adjustment transistor T9. Therefore, the second initialization transistor T1, compensation transistor T2 and adjustment transistor T9 can be scanned through the same gate drive circuit without adding a shift register, which helps to reduce the width of the peripheral area WA and achieve a narrower bezel.

[0172] Based on the above implementation method, the initialization phase can be divided into two first initialization sub-phases t11 and second initialization sub-phases t12. In the first initialization sub-phase t11, the first node N1 is reset, and in the second initialization sub-phase, the third node N3 is reset, as follows:

[0173] In the first initialization sub-stage t11: the second initialization transistor T1 is turned on, and the second initialization signal Vinit1 resets the first node N1.

[0174] In the second initialization sub-stage t12, the second initialization transistor T1 and the compensation transistor T2 are turned on simultaneously, and the second initialization signal Vinit1 resets the third node N3.

[0175] During the compensation phase t2: the first initialization transistor T8, the driving transistor T3, and the compensation transistor T2 are turned on. The first initialization signal Vinit3 compensates the threshold voltage Vth through the first initialization transistor T8, the driving transistor T3, and the compensation transistor T2, and at the same time resets the fifth node N5. For details on the specific principle, please refer to the explanation of the driving method above, which will not be repeated here.

[0176] The conduction and turn-off states of each transistor in the writing stage t3 and the light emission stage t4 can be the same as those described in the above implementation method. For details, please refer to the driving method described above.

[0177] In some embodiments of this disclosure, as shown in Figures 18 and 19, the pixel driving circuit includes the first initialization transistor T8, the second initialization transistor T1, the third initialization transistor T7, the compensation transistor T2, the write transistor T4, the driving transistor T3, the first light-emitting control transistor T5, the adjustment transistor T9, the second light-emitting control transistor T6, the coupling capacitor Cst1, and the voltage stabilizing capacitor Cst2. The second initialization transistor T1, the compensation transistor T2, the adjustment transistor T9, and the second light-emitting control transistor T6 are N-type metal-oxide transistors, while the other transistors are P-type polysilicon transistors. Their connections are shown in the embodiments in Figures 2 and 3 above, and will not be repeated here.

[0178] The compensation control terminal G2 and the adjustment control terminal G9 are connected and can share the scan signal An, enabling the compensation transistor T2 and the adjustment transistor T9 to turn on and off synchronously. The second initialization control terminal G1 and the second light-emitting control terminal G6 are connected and can share the scan signal An-n. The scan signal An and the scan signal An-n can be provided by the same gate driving circuit, but the output scan signals An and An-n are not from the same level shift register. For example, the compensation control terminal G2 and the adjustment control terminal G9 can be connected to the nth level shift register, while the second initialization control terminal G1 and the second light-emitting control terminal G6 can be connected to the nith level shift register before the nth level shift register, where n and i are both positive integers and i is less than n. This allows the second initialization transistor T1 and the second light-emitting control transistor T6 to turn on before the compensation transistor T2 and the adjustment transistor T9. Thus, the second initialization transistor T1, the compensation transistor T2, the adjustment transistor T9, and the second light-emitting control transistor T6 can be scanned using the same gate driving circuit without adding a new shift register, which helps to reduce the width of the outer region WA and achieve a narrower bezel.

[0179] P-type transistors can be driven by other gate drive circuits and light-emitting control circuits; wherein, the third initialization control terminal G7 and the first initialization control terminal G8 can be connected to shift registers of different stages of the same gate drive circuit, the first initialization control terminal G8 receives the first initialization scan signal scan1, and the third initialization control terminal G7 receives the third initialization scan signal scan1-n.

[0180] The first terminal of the third initialization transistor T7 is connected to the third initialization signal Vinit2.

[0181] Based on the above implementation method, the initialization phase can be divided into two sub-phases: a first initialization phase t11 and a second initialization phase t12. In the first initialization phase t11, the first node N1, the third node N3, and the fourth node N4 are reset. In the second initialization phase, the third node N3 is reset, as follows:

[0182] In the first initialization sub-stage t11: the second initialization transistor T1, the third initialization transistor T7, and the second light-emitting control transistor T6 are turned on, the third initialization signal Vinit2 resets the third node N3 and the fourth node N4, and the second initialization signal Vinit1 resets the first node N1.

[0183] In the second initialization sub-stage t12, the second initialization transistor T1 and the compensation transistor T2 are turned on simultaneously, and the second initialization signal Vinit1 resets the third node N3.

[0184] The conduction and turn-off states of each transistor in the compensation stage t2, writing stage t3, and light emission stage t4 can be the same as in the implementation method described above. For details, please refer to the driving method described above. This implementation method only requires four sets of scanning signals to control each transistor, that is, four sets of gate driving circuits or light emission control circuits are needed to achieve scanning, which helps to reduce the width of the peripheral area WA and achieve a narrower bezel.

[0185] In some embodiments of this disclosure, as shown in Figures 20 and 21, the pixel driving circuit includes the first initialization transistor T8, the second initialization transistor T1, the compensation transistor T2, the write transistor T4, the driving transistor T3, the first light-emitting control transistor T5, the adjustment transistor T9, the second light-emitting control transistor T6, the coupling capacitor Cst1, and the voltage stabilizing capacitor Cst2 mentioned above; but without the third initialization transistor T7; wherein, the second initialization transistor T1, the compensation transistor T2, and the adjustment transistor T9 are all transistors with a dual-channel dual-gate structure as described above; each transistor is a P-type polysilicon transistor, and the connection relationship can be referred to the embodiments in Figures 2 and 3 above, which will not be repeated here.

[0186] The first initialization control terminal G8 is connected to the first initialization scan signal scan1, the second initialization control terminal G1 is connected to the second initialization scan signal scan, the write control terminal G4 is connected to the write scan signal scan+n, and the third initialization control terminal G7 is connected to the third initialization scan signal scan1+n; the first light emission control terminal G5 is connected to the first light emission scan signal EM1, and the second light emission control terminal G6 is connected to the second light emission scan signal EM2. The first initialization scan signal scan1 and the third initialization scan signal scan1+n come from shift registers at different stages of the same gate drive circuit.

[0187] The initialization stage t1, compensation stage t2, and light emission stage t4 in the driving method of the above embodiment can be the same as those in the driving methods of the embodiments in Figures 14 and 15 above. The difference is that in this embodiment, during the writing stage t3, when the data signal Data is written to the fifth node N5, the third initialization scan signal scan1+n and the second light emission scan signal EM2 are at a low level, which turns on the third initialization transistor T7 and the second light emission control transistor T6. The third initialization signal Vinit2 can reset the third node N3 and the fourth node N4.

[0188] The embodiments of this disclosure also provide a driving method for a pixel driving circuit. The pixel driving circuit adopts any of the pixel driving circuits described in the above embodiments, and its specific structure will not be detailed here. The driving method includes:

[0189] During the compensation phase, the first initialization sub-circuit, adjustment sub-circuit, and compensation circuit are turned on, and the write circuit is turned off. The threshold voltage and first initialization signal of the driving transistor are written to the control terminal of the driving transistor through the first initialization sub-circuit and compensation circuit, and the first initialization signal is written to the first terminal of the energy storage circuit through the adjustment sub-circuit.

[0190] During the writing phase, the writing circuit is turned on, and the first initialization sub-circuit, adjustment sub-circuit, and compensation circuit are turned off. Data signals are transmitted to the energy storage circuit through the writing circuit, and the voltage of the data signals is coupled to the control terminal of the driving transistor through the energy storage circuit.

[0191] Furthermore, in some embodiments of this disclosure, the driving method further includes:

[0192] During the initialization phase, the second initialization circuit is turned on, and the second initialization signal is transmitted to the control terminal of the driving transistor through the second initialization circuit.

[0193] In at least one of the compensation phase and the writing phase, the third initialization circuit is turned on, and the third initialization signal is transmitted to the light-emitting device through the third initialization circuit.

[0194] The specific principle of the driving method has been explained in detail in the above implementation of the pixel driving circuit, and will not be repeated here.

[0195] It should be noted that although the steps of the driving method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0196] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A pixel driving circuit, comprising a driving transistor, a compensation circuit, a first initialization circuit, a write-in circuit and an energy storage circuit; the write-in circuit is connected with a first end of the energy storage circuit, a second end of the energy storage circuit is connected with a control end of the driving transistor; the first end of the energy storage circuit is connected with a first end of the driving transistor through the first initialization circuit; the control end and a second end of the driving transistor are connected through the compensation circuit, and the second end of the driving transistor is connected with a light emitting device; the first initialization circuit is used for transmitting a first initialization signal to the first end of the driving transistor and the first end of the energy storage circuit; the write-in circuit is connected with a write-in control end, and is used for transmitting a data signal to the energy storage circuit in response to a signal of the write-in control end; the energy storage circuit is used for coupling the data signal to the control end of the driving transistor; the compensation circuit is connected with a compensation control end, and is used for turning on and off in response to a signal of the compensation control end.

2. The pixel driving circuit according to claim 1, wherein the first initialization circuit comprises a first initialization sub-circuit and an adjustment sub-circuit; the first initialization sub-circuit is connected with the first end of the driving transistor and a first initialization control end, and is used for transmitting the first initialization signal to the first end of the driving transistor in response to a signal of the first initialization control end; the adjustment sub-circuit is connected with the first end of the driving transistor and the first end of the energy storage circuit, and is connected with an adjustment control end, and is used for turning on and off in response to a signal of the adjustment control end.

3. The pixel driving circuit of claim 2, wherein, the pixel driving circuit further comprises a second initialization circuit, a first light emitting control circuit and a second light emitting control circuit; the second initialization circuit is connected with the control end of the driving transistor, and is connected with a second initialization control end, and is used for transmitting a second initialization signal to the control end of the driving transistor in response to a signal of the second initialization control end; the first light emitting control circuit is connected with the first end of the driving transistor, and is connected with a first light emitting control end, and is used for transmitting a first power signal to the first end of the driving transistor in response to a signal of the first light emitting control end; the second light emitting control circuit is connected with the second end of the driving transistor and the light emitting device, and is connected with a second light emitting control end, and is used for turning on and off in response to a signal of the second light emitting control end.

4. The pixel driving circuit of claim 3, wherein, the pixel driving circuit further comprises a third initialization circuit, the third initialization circuit is connected with the light emitting device, and is connected with a third initialization control end, and is used for transmitting a third initialization signal to the light emitting device in response to a signal of the third initialization control end.

5. The pixel driving circuit of claim 2, wherein, the first initialization sub-circuit comprises a first initialization transistor, the adjustment sub-circuit comprises an adjustment transistor; the write-in circuit comprises a write-in transistor, the compensation circuit comprises a compensation transistor; the energy storage circuit comprises a coupling capacitor; a control end of the first initialization transistor is connected with the first initialization control end, a first end is used for receiving the first initialization signal, and a second end is connected with the first end of the driving transistor; The control end of the adjusting transistor is connected with the adjusting control end, the first end is connected with the first end of the driving transistor, and the second end is connected with the first end of the coupling capacitor; the second end of the coupling capacitor is connected with the control end of the driving transistor; The control end of the writing transistor is connected with the writing control end, the first end is used for receiving the data signal, and the second end is connected with the first end of the coupling capacitor; The control end of the compensation transistor is connected with the compensation control end, the first end is connected with the second end of the driving transistor, and the second end is connected with the control end of the driving transistor.

6. The pixel driving circuit of claim 3, wherein, The first light-emitting control circuit comprises a first light-emitting control transistor, the second light-emitting control circuit comprises a second light-emitting control transistor, and the second initialization circuit comprises a second initialization transistor; The control end of the first light-emitting control transistor is connected with the first light-emitting control end, the first end is used for receiving the first power signal, and the second end is connected with the first end of the driving transistor; The control end of the second light-emitting control transistor is connected with the second light-emitting control end, the first end is connected with the second end of the driving transistor, and the second end is connected with the light-emitting device; The control end of the second initialization transistor is connected with the second initialization control end, the first end is used for receiving the second initialization signal, and the second end is connected with the control end of the driving transistor.

7. The pixel driving circuit of claim 4, wherein, The third initialization circuit comprises a third initialization transistor, the control end of the third initialization transistor is connected with the third initialization control end, the first end is used for receiving the third initialization signal, and the second end is connected with the light-emitting device.

8. The pixel driving circuit according to any one of claims 1-7, wherein, The pixel driving circuit further comprises a voltage stabilizing circuit, the voltage stabilizing circuit is connected with the first end of the energy storage circuit and connected with a voltage stabilizing control end, and is used for transmitting a constant voltage signal to the first end of the energy storage circuit in response to a signal of the voltage stabilizing control end.

9. The pixel driving circuit of claim 8, wherein, The voltage stabilizing circuit comprises a voltage stabilizing capacitor, the first end of the voltage stabilizing capacitor is used for receiving the constant voltage signal, and the second end is connected with the first end of the energy storage circuit.

10. The pixel driving circuit of claim 5, wherein, The compensation transistor comprises a first sub-compensation transistor and a second sub-compensation transistor; The control end of the first sub-compensation transistor and the control end of the second sub-compensation transistor are connected and connected with the compensation control end, the first end of the first sub-compensation transistor is connected with the second end of the driving transistor, the second end is connected with the first end of the second sub-compensation transistor, and the second end of the second sub-compensation transistor is connected with the control end of the driving transistor.

11. The pixel driving circuit of claim 6, wherein, The second initialization transistor comprises a first sub-initialization transistor and a second sub-initialization transistor; The control end of the first sub-initialization transistor and the control end of the second sub-initialization transistor are connected and connected with the second initialization control end, the first end of the first sub-initialization transistor is used for receiving the second initialization signal, the second end is connected with the first end of the second sub-initialization transistor, and the second end of the second sub-initialization transistor is connected with the control end of the driving transistor; The second end of the first sub-initialization transistor and the first end of the second sub-initialization transistor are connected with the light-emitting device.

12. The pixel driving circuit of claim 11, wherein, A second end of the first initialization transistor and a first end of the second initialization transistor are connected to the light emitting device.

13. The pixel driving circuit of claim 5, wherein, The adjustment transistor comprises a first sub-adjustment transistor and a second sub-adjustment transistor. A control end of the first sub-adjustment transistor and a control end of the second sub-adjustment transistor are connected to the adjustment control end, a first end of the first sub-adjustment transistor is connected to a first end of the drive transistor, a second end of the first sub-adjustment transistor is connected to a first end of the second sub-adjustment transistor, and a second end of the second sub-adjustment transistor is connected to a first end of the coupling capacitor.

14. The pixel driving circuit of claim 7, wherein, The second light emitting control circuit comprises a second light emitting control transistor, a control end of the second light emitting control transistor is connected to the second light emitting control end, a first end of the second light emitting control transistor is connected to a second end of the drive transistor, and a second end of the second light emitting control transistor is connected to the light emitting device. The third initialization transistor is an N-type transistor, the second light emitting control transistor is a P-type transistor, and the third initialization control end is connected to the second light emitting control end.

15. The pixel driving circuit of claim 5, wherein, The drive transistor, the write transistor, and the first initialization transistor are polycrystalline silicon transistors. At least one of the compensation transistor and the adjustment transistor is a metal oxide transistor.

16. The pixel driving circuit of claim 6, wherein, The drive transistor, the first light emitting control transistor, and the second light emitting control transistor are polycrystalline silicon transistors. The second light emitting control transistor is a metal oxide transistor.

17. The pixel driving circuit of claim 4, wherein, The first initialization control end is connected to the third initialization control end, and the adjustment control end is connected to the compensation control end.

18. The pixel driving circuit of claim 3, wherein, The first light emitting control end is connected to the second light emitting control end.

19. A driving method of a pixel driving circuit, the pixel driving circuit comprising a driving transistor, a compensation circuit, a first initialization sub-circuit, an adjusting sub-circuit, a writing circuit and an energy storage circuit; the first initialization sub-circuit being connected with a first end of the driving transistor and a first initialization control end; the adjusting sub-circuit being connected with the first end of the driving transistor and a first end of the energy storage circuit; the writing circuit being connected with the first end of the energy storage circuit, and a second end of the energy storage circuit being connected with a control end of the driving transistor. A control end and a second end of the drive transistor are connected through the compensation circuit, and the second end of the drive transistor is connected to the light emitting device. The driving method comprises: In the compensation stage, the first initialization sub-circuit, the adjustment sub-circuit, and the compensation circuit are turned on, and the write circuit is turned off. The threshold voltage of the drive transistor and the first initialization signal are written into the control end of the drive transistor through the first initialization sub-circuit and the compensation circuit, and the first initialization signal is written into the first end of the energy storage circuit through the adjustment sub-circuit. In the write stage, the write circuit is turned on, and the first initialization sub-circuit, the adjustment sub-circuit, and the compensation circuit are turned off; a data signal is transmitted to the energy storage circuit through the write circuit, and the voltage of the data signal is coupled to the control end of the drive transistor through the energy storage circuit.

20. The driving method according to claim 19, wherein The pixel driving circuit further comprises a second initialization circuit and a third initialization circuit, and the second initialization circuit is connected to the control end of the drive transistor. The third initialization circuit is connected to the light emitting device. The driving method further comprises: In the initialization stage, the second initialization circuit is turned on, and a second initialization signal is transmitted to the control end of the drive transistor through the second initialization circuit. In the compensation stage and / or the write stage, the third initialization circuit is turned on, and a third initialization signal is transmitted to the light emitting device through the third initialization circuit.

21. A display panel comprising the pixel driving circuit of any one of claims 1-18.

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