A power distribution network ground fault detection device and method

Abstract

The application relates to a power distribution network grounding fault detection device and method. The power distribution network grounding fault precise detection device is composed of an incoming line end signal acquisition device and an outgoing line end signal acquisition device which are respectively installed in an incoming line section and an outgoing line section of a measured area. The two sets of acquisition devices are respectively provided with a microprocessor module, a Beidou timing module, a three-phase current transformer, a signal conditioning module and an FPGA module. The output end of the three-phase current transformer is further connected with an electric quantity metering module. The metal shell of the transformer has a voltage sensing electrode function and can non-contact sense the voltage signal of a three-phase high-voltage cable. The microprocessor module relies on the Beidou timing to synchronously compare the current vector sum of the incoming line end and the outgoing line end, so as to judge whether the fault exists, and meanwhile, the precise positioning of the fault phase is completed according to the high-frequency component in the voltage signal. Compared with the prior art, the application has the advantages of realizing low-cost, high-precision double-criterion detection and the like.

Description

Technical Field

[0001] This invention relates to the field of power distribution network technology, and in particular to a power distribution network grounding fault detection device and method. Background Technology

[0002] The power distribution network, as a transportation channel for transmitting electrical energy to various sectors, plays a vital role in industrial production and daily life. When a ground fault occurs in the power distribution network, it can cause serious hazards such as power outages and system disconnection. When a ground fault occurs, it is necessary to accurately select the fault point. Current methods for fault point selection mainly include signal injection, impedance, and traveling wave methods, but these methods are not very effective in diagnosing ground faults.

[0003] Currently, with the development of smart distribution networks, fault location technology based on wide-area synchronous measurement is gradually becoming mainstream. For example, invention patent CN116840609A discloses a distributed grounding fault location method and system based on shared zero-sequence voltage. This scheme synchronously collects the zero-sequence voltage and three-phase current of the distribution line through BeiDou / GPS timing. After the zero-sequence voltage acquisition unit detects that the zero-sequence voltage exceeds the limit, it sends the voltage data to each distributed current and electric field sensor. The current and electric field sensors combine the shared zero-sequence voltage with the locally acquired current / electric field waveforms and use the transient power direction method to determine the location of the grounding fault.

[0004] However, the aforementioned existing technologies still have the following limitations and technical challenges in practical applications: Acquiring voltage signals is difficult, and sensor deployment costs are high: The above solutions rely on current-electric field sensors to obtain voltage or electric field signals, or on the zero-sequence voltage shared by the entire network. In actual distribution network environments, the internal space is extremely limited, and installing dedicated contact-type voltage transformers requires high insulation and is bulky; even installing non-contact electric field sensors often requires specific installation locations and additional insulating supports, resulting in high modification costs and difficult construction.

[0005] The scheme is highly dependent on communication quality and involves complex data processing. Its core lies in sharing zero-sequence voltage, requiring real-time transmission of voltage waveform data from substations or main lines to various distributed nodes via a communication network for transient power direction calculation. This necessitates extremely high bandwidth and extremely low latency in the communication network. In remote areas or distribution sites with poor signal strength, waveform data transmission often suffers from packet loss or delay, preventing distributed nodes from obtaining accurate voltage references in a timely manner, thus affecting the accuracy of transient power direction determination.

[0006] The existing transient power direction method relies primarily on the phase relationship between voltage and current to determine the fault direction. However, in high-resistance grounding or intermittent arcing grounding scenarios, the power frequency or low-frequency transient signals are weak, and the direction criterion is easily interfered with. This method does not fully utilize the unique high-frequency partial discharge characteristics that accompany grounding faults, making it difficult to accurately locate specific fault phases and quantitatively determine the relative distance to the fault point under weak fault signals.

[0007] In summary, current technologies generally suffer from the following problems: the traditional zero-sequence current method is prone to misjudgment when the three-phase load of the distribution network is unbalanced, resulting in low detection accuracy; while emerging distributed detection technologies suffer from high installation and maintenance costs of voltage sensors, heavy reliance on communication bandwidth, and a lack of ability to perform fine analysis of weak fault signals. Summary of the Invention

[0008] The purpose of this invention is to overcome the defects of the prior art and provide a power distribution network grounding fault detection device and method.

[0009] The objective of this invention can be achieved through the following technical solutions: According to one aspect of the present invention, a grounding fault detection device for a power distribution network is provided. The device includes an incoming signal acquisition device and an outgoing signal acquisition device respectively installed at the incoming and outgoing sections of the area under test. Both include a microprocessor module, a Beidou time synchronization module, a three-phase current transformer, a signal conditioning module, and an FPGA module. The output terminal of the three-phase current transformer is connected to a power metering module. The metal casing of the three-phase current transformer serves as a voltage sensing electrode for non-contact sensing of the voltage signal of the three-phase high-voltage cable; the metal casing is connected to the input terminal of the signal conditioning module, and the output terminal of the signal conditioning module is connected to the FPGA module. The microprocessor module is configured to: compare the current vector sum of the incoming and outgoing terminals according to the BeiDou time synchronization to determine whether there is a fault, and locate the fault phase based on the high-frequency component in the voltage signal sensed by the metal casing.

[0010] As a preferred technical solution, the principle of using the metal casing of the three-phase current transformer as a voltage sensing electrode includes: utilizing the first stray capacitance C1 between the metal casing and the high-voltage cable, and the second stray capacitance C2 between the metal casing and the ground to form a series voltage divider structure, thereby generating an induced voltage on the metal casing that is proportional to the voltage of the high-voltage cable.

[0011] As a preferred technical solution, the signal conditioning module includes a high-pass filter circuit and a high-frequency signal amplification circuit connected in sequence; the cutoff frequency of the high-pass filter circuit is set to 100kHz, which is used to filter out power frequency signals and retain high-frequency partial discharge signals; the high-frequency signal amplification circuit is used to adjust the AC inductive signal into a unipolar voltage signal that is compatible with the A / D acquisition chip.

[0012] As a preferred technical solution, the high-frequency signal amplification circuit specifically includes a voltage follower, an inverting proportional amplifier, and an addition / subtraction circuit; the voltage follower is used to output a stable reference voltage; the addition / subtraction circuit performs calculations on the high-pass filtered signal and the processed reference voltage, amplifies the weak AC high-frequency signal input, and superimposes a DC bias to make its output range between 0V and 2V.

[0013] As a preferred technical solution, the input terminal of the high-frequency signal amplification circuit is provided with a protection circuit. The protection circuit includes two diodes connected in reverse parallel. The diodes are connected between the input signal terminal and ground and are used to conduct when the amplitude of the input signal exceeds the diode conduction threshold to protect the subsequent operational amplifier.

[0014] As a preferred technical solution, the data processing architecture of the device adopts a collaborative working mode of FPGA and microprocessor; the FPGA module is externally connected to an SRAM storage chip for high-speed caching of high-frequency partial discharge data sensed by the metal casing; the FPGA module and the microprocessor module communicate through the FSMC parallel bus.

[0015] As a preferred technical solution, the incoming signal acquisition device and the outgoing signal acquisition device also include a power supply module. The power supply module includes a negative voltage generation circuit, which is used to convert the DC voltage of the single power supply input into a negative voltage to provide dual power supply for the operational amplifier in the signal conditioning module to process the negative half-axis part of the AC inductive signal.

[0016] As a preferred technical solution, both the incoming signal acquisition device and the outgoing signal acquisition device are equipped with a 4G communication module. The microprocessor module is connected to the cloud server through the 4G communication module to upload the acquired current difference data and high-frequency discharge signal characteristics to the cloud.

[0017] According to another aspect of the present invention, a method for detecting grounding faults in a power distribution network is provided, the method comprising the following steps: The incoming and outgoing signal acquisition devices use the BeiDou time synchronization system for time synchronization. Simultaneously measure the vector sum of the three-phase currents at the incoming end and the vector sum of the three-phase currents at the outgoing end of the measured area; Calculate the difference between the vector sum of the three-phase currents at the incoming end of the measured area and the vector sum of the three-phase currents at the outgoing end of the measured area; Determine if the difference is zero; if the difference is zero, determine that no ground fault has occurred and return to the time synchronization step to continue monitoring; otherwise, determine that a ground fault has occurred and initiate partial discharge signal detection. The partial discharge signals of the three-phase high-voltage line voltages are measured separately. During the measurement, it is determined whether there is a discharge signal in each phase. If there is no discharge signal in a certain phase, it is determined that no ground fault has occurred in that phase; otherwise, it is determined that a ground fault has occurred in that phase.

[0018] As a preferred technical solution, the method steps further include: comparing the intensity of the high-frequency discharge signal of the fault phase collected at the input end and the output end; if the signal intensity at the input end is greater than that at the output end, it is determined that the fault point is closer to the input side; otherwise, it is determined that the fault point is closer to the output side.

[0019] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention establishes acquisition devices at both the incoming and outgoing ends, achieving microsecond-level synchronization using BeiDou time synchronization, and employs a method of calculating the vector sum and difference of currents at the incoming and outgoing ends for fault diagnosis. This effectively overcomes the shortcomings of traditional zero-sequence current methods, which are prone to misjudgment when the three-phase load is unbalanced in the distribution network, greatly improving the accuracy of fault detection. Simultaneously, this invention innovatively reuses the metal casing of the current transformer as the voltage sensing electrode, eliminating the need for additional contact-type voltage transformers or dedicated electric field sensors, enabling non-contact acquisition of voltage signals. Combined with the analysis of high-frequency discharge signals, it can further pinpoint the faulty phase based on the identified faulty section, achieving low-cost, high-precision dual-criteria detection.

[0020] 2. This invention utilizes the stray capacitance (C1) between the metal casing and the high-voltage cable, and the stray capacitance (C2) between the metal casing and the ground to form a series voltage divider structure. It fully leverages the physical characteristics of existing equipment, eliminating the need to damage the cable insulation layer or add expensive high-voltage coupling devices, thus creating a natural capacitive voltage divider sensor. This non-contact sensing method is not only extremely easy to install, but also achieves electrical isolation between the measurement circuit and the high-voltage line, significantly ensuring the safety of the detection device and personnel.

[0021] 3. This invention employs a high-pass filter circuit with a cutoff frequency of 100kHz in the signal conditioning module. The beneficial effect of this technical feature is that, since the high-frequency partial discharge signal generated by the grounding fault is very weak and easily submerged by the power frequency voltage, the high-pass filter effectively filters out the 50Hz power frequency main signal and low-frequency harmonic interference, significantly improving the signal-to-noise ratio and ensuring that subsequent circuits can extract pure fault characteristic signals, thereby improving the sensitivity of fault phase selection.

[0022] 4. This invention employs a high-frequency signal amplification circuit comprising a voltage follower, an inverting proportional amplifier, and an addition / subtraction circuit, specifically adjusting the signal to between 0V and 2V. This solves the problem that the induced AC high-frequency signal has a negative half-axis and a weak amplitude, making it impossible to directly acquire by conventional unipolar A / D chips. By introducing DC bias through the addition / subtraction circuit, the bipolar AC signal is raised and amplified as a whole, ensuring the integrity of the signal waveform and avoiding the loss of fault characteristics caused by the truncation of the negative half-wave.

[0023] This invention incorporates a reverse-parallel diode protection circuit at the input terminal. Transient overvoltages can occur in power distribution networks during lightning strikes or switching operations, potentially causing a sudden spike in voltage induced in the metal casing. The reverse-parallel diode clamps the input voltage within a safe range, preventing excessively high induced voltage from damaging the precision operational amplifiers and FPGA chips in subsequent stages. This significantly improves the reliability and lifespan of the device in harsh electromagnetic environments.

[0024] 5. This invention employs an architecture where an FPGA is connected to an external SRAM memory chip and communicates with a microprocessor via the FSMC bus. Partial discharge signals are transient high-frequency signals ranging from nanoseconds to microseconds, and the sampling and processing speed of ordinary microcontrollers (MCUs) is insufficient to capture the full picture. By utilizing the high-speed parallel processing capability of the FPGA and the large-capacity high-speed cache of the SRAM, it is possible to completely capture the high-frequency waveform data at the moment of the fault occurrence, and then efficiently transmit it to the microprocessor for analysis via the FSMC bus, thus solving the problems of large data volume and difficulty in capturing high-frequency fault signals.

[0025] Furthermore, the power supply module of this invention includes a negative voltage generation circuit. The beneficial effect of this technical feature is that it provides a true dual-power supply (positive and negative voltage) environment for the operational amplifier in the signal conditioning circuit. Compared to single-power supply, dual-power supply ensures that the operational amplifier can linearly process weak signals near zero and negative signals when processing AC induced signals, avoiding the "crossover distortion" or zero-point dead zone problems common in single-power op-amps, and guaranteeing high fidelity amplification of high-frequency discharge signals.

[0026] 6. The detection method in this invention first utilizes BeiDou time synchronization to measure the vector sum of the incoming and outgoing line currents and calculate the difference. If the difference is not zero, a fault is determined. This step utilizes the differential current principle to effectively eliminate the interference of three-phase unbalanced current during normal operation and accurately locate the fault section. Secondly, the method further combines the measurement of high-frequency discharge signals of each phase, utilizing the physical characteristic that only the faulty phase will produce a violent high-frequency discharge, thus solving the difficulty of phase selection in the current differential method (especially when there is high resistance grounding), and realizing accurate detection of section location and specific phase selection.

[0027] The method also includes comparing the intensity of the high-frequency discharge signals of the faulty phase at the incoming and outgoing ends. High-frequency signals attenuate rapidly during transmission. Utilizing this characteristic, by comparing the amplitude of the same discharge signal captured at both ends of the line, it is possible to infer whether the fault point is closer to the incoming or outgoing side within the current section. This provides repair personnel with more precise guidance on the physical location of the fault, thereby shortening troubleshooting and power outage times. Attached Figure Description

[0028] Figure 1 This is a main frame diagram of a power distribution network grounding fault detection device according to the present invention; Figure 2 This is a block diagram illustrating the principle of the signal acquisition device in this invention. Figure 3 This is a circuit diagram of the signal conditioning circuit in the embodiment; Figure 4 This is a diagram of a second-order high-pass filter circuit in the embodiment; Figure 5 This is a diagram of the FPGA core circuit in the embodiment; Figure 6 This is a circuit diagram of the SRAM storage in the embodiment; Figure 7 This is a circuit diagram of the microprocessor module in the embodiment; Figure 8 This is a circuit diagram of the FSMC communication circuit in the embodiment; Figure 9 This is a schematic diagram of the GPS module in the embodiment; Figure 10 This is a schematic diagram of the ATK-IDM750C module in the embodiment; Figure 11 This is the hardware circuit diagram of the RN8302 power metering module in the embodiment; Figure 12 This is a diagram of the SPI communication circuit in the embodiment; Figure 13 This is a circuit diagram for converting 220V to 5V in the embodiment; Figure 14 The circuit diagram for converting 5V to 3.3V in the embodiment is shown below; Figure 15 The circuit diagram for converting 5V to 2.5V in the embodiment is shown below; Figure 16 The circuit diagram for converting 5V to 1.2V in the embodiment is shown below; Figure 17 This is a voltage reversal circuit diagram in the embodiment; Figure 18 This is a flowchart illustrating a method for detecting grounding faults in a power distribution network according to the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0030] The power distribution network, as a transportation channel for transmitting electrical energy to various sectors, plays a vital role in industrial production and daily life. When a ground fault occurs in the power distribution network, it can cause serious hazards such as power outages and system disconnection. When a ground fault occurs, precise segment selection of the fault point is required. Current segment selection methods mainly include signal injection, impedance, and traveling wave methods, but these methods are not effective in judging ground faults. Therefore, this solution proposes a distribution network ground fault detection device and method. This method involves installing an incoming signal acquisition device at the incoming section of the distribution network under test and an outgoing signal acquisition device at the outgoing section of the distribution network under test. The incoming and outgoing signal acquisition devices can simultaneously acquire the current at the incoming and outgoing ends of the tested area using BeiDou time synchronization. The difference between the incoming and outgoing currents in the tested area is used to determine whether a ground fault has occurred in the tested distribution network line section. At the same time, the metal shell of the current transformer is used as the induction electrode to indirectly acquire the voltage signal of the three-phase high-voltage cable in a non-contact manner. Combined with whether the voltage of each phase at the incoming and outgoing ends of the tested area contains high-frequency discharge signals, the system can further locate which phase of the tested area has a ground fault. The strength of the high-frequency discharge signal in each phase at the incoming and outgoing ends of the tested area determines whether the ground fault is closer to the incoming end or the outgoing end.

[0031] Example 1 A grounding fault detection device for power distribution networks, the device as follows Figure 1 As shown, the system includes an incoming line signal acquisition device and an outgoing line signal acquisition device, which transmit data wirelessly via 4G communication. The incoming line signal acquisition device is installed at the incoming line section of the distribution network under test, and the outgoing line signal acquisition device is installed at the outgoing line section of the distribution network under test. The incoming line signal acquisition device and the outgoing line signal acquisition device can simultaneously acquire the current at the incoming line and outgoing line of the test area using Beidou time synchronization. Based on the difference between the incoming line and outgoing line currents of the test area, it can determine whether a ground fault has occurred in the tested distribution network line section. At the same time, the metal shell of the current transformer is used as the induction electrode to indirectly acquire the voltage signal of the three-phase high-voltage cable in a non-contact manner. Combined with whether the voltage of each phase at the incoming line and outgoing line of the test area contains high-frequency discharge signals, it can further locate which phase of the line in the test area has a ground fault. Based on the strength of the high-frequency discharge signals in the voltage of each phase at the incoming line and outgoing line of the test area, it can be determined whether the ground fault is closer to the incoming line or the outgoing line.

[0032] Signal acquisition devices such as Figure 2 As shown, it includes an A-phase current transformer, a B-phase current transformer, a C-phase current transformer, a microprocessor module, an A-phase signal conditioning module, a B-phase signal conditioning module, a C-phase signal conditioning module, an FPGA (Field-Programmable Gate Array) module, an A-phase voltage acquisition module, a B-phase voltage acquisition module, a C-phase voltage acquisition module, a GPS (Global Positioning System) module, a 4G (4th Generation Mobile Communication Technology) module, a power metering module, and a power supply module. The output terminals of phase A current transformer, phase B current transformer, and phase C current transformer are respectively connected to the input terminal of the power metering module. The output terminals of the phase A voltage acquisition module, phase B voltage acquisition module, and phase C voltage acquisition module are respectively connected to the input terminals of the corresponding phase A signal conditioning module, phase B signal conditioning module, and phase C signal conditioning module; The outputs of the A-phase signal conditioning module, B-phase signal conditioning module, and C-phase signal conditioning module are respectively connected to the input of the FPGA module. The output of the GPS module is connected to the I / O port of the microprocessor module; The 4G module input terminal is connected to the microprocessor module output terminal via a communication interface. The power module output is connected to the power interface corresponding to the microprocessor module. The output of the FPGA module is connected to the I / O port of the microprocessor module.

[0033] The current transformer uses a 5A:5mA current transformer and can be connected to an external current transformer with any ratio, such as 630A:5A, 1200A:5A, etc.

[0034] The voltage acquisition module uses the metal casing of a current transformer as the voltage sensing electrode. There is a certain first stray capacitance C1 between the metal casing of the current transformer and the cable, and a certain second stray capacitance C2 between the metal casing of the current transformer and the ground. These two capacitors are essentially connected in series. According to the series impedance, they have a certain voltage division effect. If there is AC 10-220kV high voltage in the cable, a certain induced voltage will be generated across capacitor C2, realizing non-contact acquisition of high voltage line voltage signals, and sharing a current transformer for both current acquisition and voltage signal acquisition.

[0035] The signal conditioning module includes a high-pass filter circuit and a high-frequency signal amplification circuit, with the output of the high-pass filter circuit connected to the input of the high-frequency signal amplification circuit. The high-pass filter circuit uses a second-order RC (Resistor-Capacitor) passive high-pass filter circuit with a cutoff frequency of 100kHz. Since the A / D (Analog-to-Digital) acquisition chip operates within a range of 0~2V, and the high-frequency signal after capacitive voltage division is an AC signal with an amplitude of less than 100mV, a signal conditioning circuit is needed to adjust the input signal's voltage amplitude to a suitable effective input range for the 3PA1030 and amplify the signal amplitude to improve signal acquisition accuracy. In this embodiment, an operational amplifier is used to form a voltage follower circuit, an inverting proportional amplifier circuit, and an addition / subtraction circuit to convert the signal from the A / D acquisition chip's internal 1V reference to within the 0~2V range. The circuit schematic is shown below. Figure 3 As shown.

[0036] VREF_A (Voltage Reference A) is the reference voltage of the 3PA1030. After inputting into a voltage follower composed of U13A, the output is... Uvref Although the input and output voltages remain unchanged, the high input impedance and low output impedance characteristics of the voltage follower circuit can enhance the load-driving capability of the reference voltage and prevent it from being pulled low. Subsequently... Uvref As input, after voltage division by R39 (10kΩ) and R40 (1kΩ), the inverting amplifier circuit composed of U13B... U Let 1 be the output voltage. The mathematical relationship between input and output can be expressed as: ; U 1. The high-frequency signal to be acquired U A As the input to the addition / subtraction circuit composed of U10, the output voltage is U o As the analog signal input of the A / D chip, the relationship between input and output is as follows: ; By combining the above equations, Uvref= Substituting VREF_A=1V, we get: ; In summary, the signal conditioning circuit amplifies the high-frequency AC signal to be acquired by 11 times and raises it by 1V to make its range meet the acquisition range of the A / D acquisition chip.

[0037] Figure 3In the diagram, A_IN is the analog signal input, ADCIN_A is the A-channel analog-to-digital conversion input, AGND is the analog ground, +2.5VA and -2.5VA are the analog positive power supply 2.5V and analog negative power supply 2.5V, Uvref is the reference voltage output, U1 is the intermediate node voltage, and Uo is the output voltage. U13A and U13B (Operational Amplifier Units A and B): These use TPH2502 operational amplifiers, which feature low offset voltage, low noise, and high common-mode rejection ratio. They serve as reference buffers and signal amplification units, ensuring stable reference voltage and sufficient drive capability.

[0038] U10 (Operational Amplifier U10): This is a differential operational amplifier that supports dual power supply (+2.5VA / -2.5VA), can handle bipolar input signals, and has built-in gain adjustment and filtering networks to improve the flexibility of signal conditioning and anti-interference capabilities.

[0039] Diodes D1 and D2: SS34 Schottky diodes are used to clamp and protect the input signal UA, preventing overvoltage or surge damage to subsequent circuits and ensuring that the signal input range is safe and controllable.

[0040] Resistors R39 (10kΩ) and R40 (1kΩ) form a voltage divider network, which divides Uvref and uses it as the non-inverting input reference of U13B, stabilizing the DC bias point of the output U1 of U13B and providing a reliable reference level for subsequent differential operations.

[0041] This bias design ensures that after the high-frequency AC signal UA is superimposed on U1, the DC component of the overall output Uo is raised to the center of the common-mode input range of the A / D chip, avoiding signal saturation or distortion.

[0042] Capacitors C84, C90, C74, and C81 (all 0.1μF) are decoupling / filtering capacitors. Capacitors C84 and C90 are used to filter out high-frequency noise in the reference voltage and op-amp power supply, thereby improving reference stability. Capacitors C74 and C81 are used to suppress high-frequency interference in the output and feedback loop of U10, and to prevent noise from being misjudged by A / D sampling.

[0043] The feedback capacitor C81 and the internal resistor of U10 form an RC low-pass filter network, which can effectively filter out high-frequency interference in UA and retain the effective signal components.

[0044] Because the signal to be conditioned has a small amplitude and high frequency, the operational amplifier used to construct the conditioning circuit needs to have low noise and a wide bandwidth. In this embodiment, the TPH2501 / 2 chip from Silergy is selected. These correspond to single-channel and dual-channel CMOS operational amplifier chips, respectively. It boasts a bandwidth-gain product of 120MHz and low noise of 6.5nV / √Hz. For signals with frequencies of 10MHz and below, it can amplify 11 times without signal distortion, and the large difference between noise and signal amplitude will not interfere with the signal. The TPH2501 / 2 has a voltage slew rate of up to 180V / μs, and can promptly respond to signal changes with an amplitude range of 200mV and a frequency of 10MHz. Therefore, this operational amplifier chip is suitable for high-frequency signal processing circuits. The TPH2501 / 2 is supplied with a voltage of 2.5~5V. Since the input signal is an AC signal, a dual power supply is selected. At the signal input terminal, diodes D1 and D2 are connected in reverse parallel to protect the operational amplifier from damage. Under normal circumstances, the input signal will not exceed the diode's forward voltage threshold, and the diodes remain in the off state. Since the input signal is connected to the busbar, if a fault in the ring main unit causes a voltage surge that makes the amplitude of the coupled input signal exceed the diode's forward voltage threshold, the diode will immediately conduct, preventing the energy surge from flowing into the operational amplifier and thus protecting it. In this embodiment, a Schottky diode SS34 is selected, characterized by a low forward voltage drop and fast switching speed. The forward voltage drop is 550mV, ensuring that the operational amplifier's input voltage will not exceed this value. Simultaneously, the short switching time allows for timely conduction to protect downstream circuits. The amplification factor of the conditioning circuit is related to the resistor value. Deviations in the resistor value will cause signal errors. Therefore, in this embodiment, a thin-film resistor with an accuracy of ±0.1% and a temperature coefficient of ±25ppm / ℃ is selected. Its resistance value is low-affected by temperature, ensuring the stability of the signal conditioning circuit.

[0045] Based on their circuit configuration, filter circuits can be broadly classified into two categories: passive and active. Passive filter circuits are entirely constructed from passive components, typically including basic electronic components such as resistors, capacitors, and inductors. Their characteristic is that they can operate without an external power supply, and signal processing relies entirely on the characteristics of the passive components. Active filters, on the other hand, are composed of both active and passive components, with commonly used active components including operational amplifiers and transistors. Because they include operational amplifiers or other amplifying components, active filters can provide gain and better control over frequency response. However, they also introduce power supply interference and power consumption. For example, the power supply ripple of the operational amplifier can be superimposed on the signal, interfering with the output signal and increasing power loss. For signals with small amplitudes, it is necessary to minimize the impact of interference sources. Therefore, this solution uses a second-order passive high-pass RC filter circuit with a cutoff frequency of 100kHz. Its circuit diagram is shown below. Figure 4 As shown.

[0046] Figure 4 In the diagram, C75 and C76 are capacitors, R33 and R34 are resistors, A is the input signal A, A_IN is the analog signal input (filtered output), and GGND is the protective ground (or analog ground). The circuit consists of two cascaded RC high-pass filter units: the first stage is composed of C75 (39pF capacitor) and R33 (200kΩ resistor), and the second stage is composed of C76 (39pF capacitor) and R34 (200kΩ resistor).

[0047] The input signal A is coupled through C75, then through R33 to GGND for voltage division, and then coupled through C76 to the A_IN terminal, effectively filtering out low-frequency interference below 100kHz and retaining high-frequency effective signals.

[0048] The cutoff frequency is related to the product of the resistance and capacitance. Since the signal to be acquired is a high-frequency signal, it is advisable to use a capacitor with a smaller capacitance value to speed up the signal transmission.

[0049] The FPGA module uses the EP4CE10E22C8N chip, a Cyclone IV FPGA, currently the lowest power FPGA chip on the market. It achieves high performance while maintaining low cost and power consumption, offering excellent cost-effectiveness. Due to the size limitations of the ring main unit, the online monitoring device requires minimizing its design size, making this chip suitable for the system. Furthermore, this chip has been widely used in recent years, facilitating purchase and maintenance. The EP4CE10E22C8N has 91 inputs / outputs, sufficient for peripheral use. Its clock management uses a PLL, ensuring the normal operation of high-frequency devices. A stable, high-frequency clock signal is obtained using a phase-locked loop. Its core supply voltage range is 1.15V~1.25V, and it is packaged in a TQFP144 package with ample pins for easy debugging. The maximum operating frequency can reach 402MHz, meeting the requirements of the partial discharge online monitoring system. The design of the FPGA's clock and reset modules is crucial in the entire FPGA hardware design. Since the FPGA does not have an internal oscillation clock circuit, the EP4CE10E22C8N chip is selected as the clock module. An active crystal oscillator is used for clock circuit design. The active crystal oscillator provides a high-precision frequency reference, supplying the system with the basic clock signal. The core circuit diagram of the FPGA is shown below. Figure 5 As shown in the figure, the circuit, with the EP4CE10E22C8N chip as its core, is divided into the following functional modules: I / O grouping module: The chip is divided into 8 I / O banks (BANK1~8), which communicate with peripherals through differential I / O pins (IO_DIFIO) and support high-speed differential signal transmission.

[0050] Power supply module: core power supply VCC is 1.2V, analog power supply AVCC is 2.5V, and I / O Bank power supply VCCO is 3.3V, ensuring stable operation of the chip.

[0051] Clock management module: Provides a reference clock through a 50MHz active crystal oscillator, which is multiplied by a PLL to generate a stable high-frequency clock to drive the internal logic circuit.

[0052] Configuration and debugging module: Includes JTAG interface (TDI, TDO, TMS) and Flash configuration circuit (W25Q64), supporting chip configuration and online debugging.

[0053] Among them, EP4CE10E22C8N is the Cyclone IV series FPGA chip model; IO_DIFIO is the differential input / output pin; R8p, R9p, R8n, and R9n are the receiver differential pair pins (p is positive, n is negative); T8p, T9p, T8n, and T9n are the transmitter differential pair pins (p is positive, n is negative); BANK1~8 are the FPGA's I / O groups 1 to 8, used for group management of I / O pins; VCC is the core power supply voltage (1.2V); AVCC is the analog power supply voltage (2.5V); GNDA is the analog ground; PLL is the phase-locked loop, used for clock management and frequency multiplication; CLK is the clock signal; CLKOUT is the clock output; VCCO is the I / O Bank power supply voltage (3.3V); TDI is the test data input; TDO is the test data output; and TMS is the test mode selection. Select), nCE is the chip enable pin (active low), nCONFIG is the configuration control pin (low level resets configuration), CONF_DONE is the configuration completion indicator pin, nSTATUS is the status indicator pin (low level indicates an error), CS# is the chip select signal (active low), DATA0~DATA3 are data bus 0 to 3, DCLK is the data clock signal, and W25Q64 is the model number of the 64Mbit Flash memory chip.

[0054] When an FPGA is operating, it stores configuration data in SRAM. SRAM is a static storage method, meaning it can retain internal storage circuitry without needing to be refreshed, resulting in a fast storage speed, making it suitable for storing acquired partial discharge voltage data. A partial discharge online monitoring device requires 500,000 bytes of storage space to collect data from a single phase. Since all three phases may be collected simultaneously, storing all three phases' data in external SRAM requires 1.5 million bytes of storage space. The FPGA's own storage capacity is insufficient to meet this requirement, necessitating the addition of external devices. A memory chip is used to store the acquired partial discharge data. The IS61WV20488BLL-10TI chip is a 2M... The IS61WV20488BLL-10TI high-speed CMOS static RAM chip can acquire 1.5M bytes of partial discharge data in a single acquisition in the ring main unit's online partial discharge monitoring device. The application circuit of the IS61WV20488BLL-10TI is as follows: Figure 6 As shown. Figure 6 In this context, IS61WV20488BLL-10TI refers to the IS61WV20488BLL-10TI type static random access memory. A0~A20 are address lines 0 to 20, D0~D15 are data lines 0 to 15, CE is chip enable (active low), OE is output enable (active low), WE is write enable (active low), VDD is power supply (3.3V), GND is ground, NC is an unconnected pin, C15 and C16 are decoupling capacitors, and 104 is the capacitor value code, specifically 0.1μF. Figure 6 As shown, the circuit uses the IS61WV20488BLL-10TI static random access memory (SRAM) as its core for data caching and storage. Address and data bus: A0~A20 are address lines used to specify the address of the memory unit; D0~D15 are 16-bit data lines used for data reading and writing.

[0055] Control signals: CE (chip enable), OE (output enable), and WE (write enable) are used to control the read and write operations of SRAM, ensuring the timing and reliability of data transmission.

[0056] Power supply and filtering: VDD is supplied with 3.3V. C15 and C16 (0.1μF) are decoupling capacitors to filter out power supply ripple and improve circuit stability.

[0057] Unconnected pin: The NC pin is an unconnected pin, used for chip package compatibility and does not participate in circuit function.

[0058] The microprocessor module uses the STM32F407ZGT6 chip as the core processing chip of the online monitoring device. The STM32F407ZGT6 combines low cost and high performance, with a refresh rate of up to 3300W pixels / second. Therefore, the STM32F4 is suitable for systems that require FPU or DSP. It has a rich set of I / O peripheral pins to meet the needs of industrial control.

[0059] STM32F407ZGT6 microcontroller minimum system as follows Figure 7As shown, it includes a reset circuit, crystal oscillator circuit, and download circuit, which are the foundation for the normal operation of the microcontroller. The peripherals mainly used in the ring main unit partial discharge online monitoring device are FSMC (Flexible Static Memory Controller), several serial ports, and secure digital I / O ports, which are needed to communicate with FPGA, human-machine interface, RS485, etc.

[0060] Figure 7 In this code, STM32F407ZGT6 is a microcontroller model from STMicroelectronics' STM32F4 series. PA0~PA15, PB0~PB15, PC0~PC15, PD0~PD15, and PE0~PE15 are pins 0~15 of GPIO (General-Purpose Input / Output) ports A~E. USART2 / 3 / 4 are general-purpose synchronous / asynchronous transceivers (serial ports). ADC123_IN is the analog input channel of ADC1 / 2 / 3. TIMx_CHy is the channel y of timer x. SPI1 / 2 / 3 are serial peripheral interfaces. I2S2 / 3 are integrated circuit audio interfaces. I2C1 / 2 / 3 are integrated circuit buses. CAN1 / 2_TX / RX are CAN bus transmit / receive pins. ETH is an Ethernet interface. SWDIO is a serial line data input / output (debugging interface). SWCLK is a serial line clock (debugging interface). BOOT0 and BOOT1 are boot configuration pins. The pins are as follows: OSC_IN and OSC_OUT are external crystal oscillator input / output; VDD and VSS are digital power / ground; VDDA and VSSA are analog power / ground; VREF+ and VREF- are reference voltage positive / negative terminals; VBAT is backup battery power supply; RESET is reset signal; SW1 is reset button; R1, R2, R3, R4, R5, and R6 are resistors R1~R6; C1, C2, C3, C4, C5, C7, C8, and C9 are capacitors C1~9; Y1 is an 8MHz crystal oscillator; D1 and D2 are diodes D1 and D2 (1N4148); P1 / Header4 is a 4-pin SWD debugging interface; NC is an unconnected pin; and PDR_ON is a power control pin.

[0061] STM32 and FPGA communication circuit: The STM32 uses an FPGA to read partial discharge data from SRAM. Using the FSMC (Software Controller for Memory) communication accelerates the read process. The FSMC is a flexible static memory controller that can transform AHB transmission signals into compatible peripheral protocols and meet the timing conditions for accessing peripherals. The FSMC manages 1GB of memory and also features four banks for connecting to external memory. Each bank has its own chip select signal and timing configuration, and the FSMC supports a wide variety of memory types. The SRAM and FSMC logic control circuitry are generated using the LPM macromodule within the FPGA. Data transfer between the STM32 and the FPGA co-controller is accomplished using the FSMC's independent address mode on the parallel bus.

[0062] exist and When communicating, It can actually be seen as external ,so Configuration requirements and external The configurations are similar. Through of The STM32 uses the non-multiplexed mode of GPIO ports for control. The I / O port definitions in non-multiplexed mode are shown in Table 1 below. In STM32, the I / O ports in non-multiplexed mode require PIN interface definitions. The FSMC communication circuit pin connections are as follows... Figure 8 As shown, Figure 8In the diagram, EP4CE10E22C8 is the model number of the Cyclone IV series FPGA chip. BANK1, 6, 7, and 8 are I / O groups 1, 6, 7, and 8 of the FPGA, used for group management of I / O pins. IO_DIFIO is a differential input / output pin. L1n, L2p, L1p, and L2n are differential pairs (channel 1 / 2, positive and negative terminals). T20p, T20n, T19p, and T19n are transmitter differential pairs (Tx, positive and negative terminals). T11n, T10n, T11p, and T10p are transmitter differential pairs (Tx, positive and negative terminals). R4n, R4p, R3n, and R3p are receiver differential pairs (Rx, positive and negative terminals). IO.VREFBN is an I / O pin. Group O is the reference voltage (used for differential input thresholds). FSMC_A19, A18, A17, etc. are FSMC address lines. FSMC_D3, D2, D1, etc. are FSMC data lines. FSMC_CLK is the FSMC clock signal. FSMC_NADV, FSMC_NE3, FSMC_NEW, and FSMC_NOE are FSMC control signals: address valid, chip select 3, write enable, and output enable, respectively. INIT_DONE and CRC_ERROR are configuration status signals: initialization complete and CRC check error. nCE and nOE are chip enable (active low) and output enable (active low), respectively.

[0063] Table 1 Non-multiplexed I / O PSRAM / SRAM GPS module such as Figure 9 As shown, the ATK-S1216F8-BD GPS / BeiDou module is used. This module employs an advanced RF front-end architecture design, with its hardware configuration including 167 multi-satellite, multi-frequency receiving channels. It possesses weak signal acquisition capabilities on the order of -165dBm and measurement data output characteristics with a dynamic refresh rate of 75Hz. The module's dual-clock domain architecture effectively ensures nanosecond-level synchronization accuracy between the PPS pulse signal and UTC time. Parameter settings such as baud rate configuration and update rate adjustment are implemented through the UART interface, and all settings can be stored in the FLASH memory.

[0064] SkyTra_S1216F8-BD is the Tianhe S1216F8-BD GPS positioning module; RT9193-33 is the RT9193-33 low dropout linear regulator; PPS is the second pulse signal (GPS time synchronization); GPS_TXD is the GPS module's transmit data pin; GPS_RXD is the GPS module's receive data pin; VBAT is the GPS module's backup battery power supply; VCC is the power supply (3.3V); VIN is the regulator's input voltage; and VOUT is the regulator's output voltage. Output voltage (3.3V), EN is the regulator enable pin, BP is the regulator internal bandgap reference pin, IPX / IPEX is the RF antenna connector, R1, R2, R3, R4, R5, R23 are resistors, C1, C2, C3, C4 are capacitors, D1, D4 are diodes, LED is the status indicator, RSTN is the reset pin (active low), SCL, SDA are the I2C bus clock and data pins, NC is the unconnected pin, P1 / Header5 is the 5-pin GPS interface connector.

[0065] The 4G module uses the ATK-IDM750C module from Zhengdian Atom to communicate with the cloud platform. The principle of the ATK-IDM750C module is as follows: Figure 10 As shown, ATK-IDM750C / 4G-M750C is the ATK-IDM750C (4G-M750C) 4G communication module. USB_DM and USB_DP are USB differential data pins (negative / positive), SIM_VDD is the SIM card power supply pin, SIM_DATA, SIM_CLK, and SIM_RST are the SIM card data, clock, and reset pins, UART_TX and UART_RX are the serial port transmit and receive pins, 4G_TX and 4G_RX are the 4G module data transmit and receive pins, LED_LINK1~4 are link status indicator lights 1~4, KEY_WK is the wake-up button pin, LED_RST is the reset status indicator light, LED_NET is the network status indicator light, and EC6 is capacitor EC6 (470μF / 35V).

[0066] The ATK-IDM750C module from Zhengdian Atom is a high-performance, highly compatible, and highly reliable 4G DTU product. It supports a wide voltage range of 5 to 24V, making it suitable for various environments. It also provides an IPEX antenna interface and a Micro SIM card interface, supporting external antennas and various SIM cards to ensure signal stability and flexibility. The module uses 12V for power supply, and decoupling capacitors are added to the power input to enhance circuit stability. The ATK-IDM750C module itself has weak signal reception; after inserting a SIM card, a signal amplification device is still required for normal communication. The RN8302 energy metering module and adder circuit transmit the collected three-phase voltage and zero-sequence current data to the microprocessor. The microprocessor then sends the data to the 4G module via serial port every 500ms. The 4G module, based on the MQTT protocol, transmits the three-phase voltage and current data to the cloud platform.

[0067] The power metering module uses the RN8302 chip to collect the current and phase angle values ​​of the three phases.

[0068] The RN8302 energy metering module uses the RN8302 metering chip as its core, and includes a crystal oscillator circuit, a voltage sampling circuit, an SPI communication circuit, and an isolation circuit. The RN8302 energy metering chip uses an 8.192MHz passive crystal oscillator as the system clock source. The peripheral circuit design follows a high-stability configuration principle: a 10MΩ resistor is connected in parallel across the crystal oscillator, along with two 15pF capacitors to form a π-type network, which can control the crystal oscillator parameter (ESR) below 50, effectively improving the oscillation waveform and ensuring the clock generator starts oscillating. The voltage acquisition unit adopts a three-phase three-wire connection structure, acquiring the analog grid voltage signal through a voltage divider network. The analog signal is then sent to the metering chip after passing through the signal acquisition circuit. The RN8302 metering chip processes the signal to obtain electrical parameter information such as phase angle, amplitude, and voltage phase sequence, and stores this information in a dedicated register group. Data interaction uses an SPI serial interface to transmit electrical parameter information. To suppress high-frequency interference, an RC filter network is connected in parallel between the clock line and the data line. The hardware circuit of the RN8302 energy metering module is as follows: Figure 11 As shown, the SPI communication circuit is as follows: Figure 12 As shown.

[0069] Figure 11In this code, RN8302B is the RN8302B multi-functional energy metering chip; Vref is the reference voltage input; NC is an unconnected pin; REV is the reverse indicator pin; IAP and IAN are the positive / negative terminals of the A-phase current differential input; IBP and IBN are the positive / negative terminals of the B-phase current differential input; ICP and ICN are the positive / negative terminals of the C-phase current differential input; UAP and UAN are the positive / negative terminals of the A-phase voltage differential input; UBP and UBN are the positive / negative terminals of the B-phase voltage differential input; UCP and UCN are the positive / negative terminals of the C-phase voltage differential input; AVCC is the analog power supply; DVCC is the digital power supply; AGND is the analog ground; DGND is the digital ground; SCLK is the serial clock signal (SPI interface); SDO is the serial data output (SPI interface); SDI is the serial data input (SPI interface); SCSN is the chip select signal (SPI interface, active low); INTN is the interrupt request pin (active low); CF1, CF2, CF3, and CF4 are the calibration frequency output pins.

[0070] Figure 12 In this configuration, SDI is the serial data input (SPI master side); MOSI is the master output / slave input (SPI signal); SDO is the serial data output (SPI master side); MISO is the master input / slave output (SPI signal); SCLK is the serial clock signal (SPI interface); SCK is the serial clock signal (SPI slave side); SCSN is the chip select signal (SPI interface, active low); SCS is the chip select signal (SPI slave side); R23, R24, R25, and R26 are resistors; C28, C29, and C30 are capacitors; VCC-3V3 is the 3.3V power supply; and GND is ground.

[0071] The power module uses 220V / 50Hz AC power. The HIECUBE AD / DC power module HE05P15LRN is selected to convert 220V AC to 5V DC. The HE05P15LRN is characterized by its ability to operate on both AC and DC power supplies, its wide input voltage range, high reliability, low power consumption, and safety isolation. This module boasts an efficiency of up to 90% and is dustproof and waterproof, making it suitable for ring main unit environments. Since the online monitoring device operates in environments with high EMC requirements, it is necessary to add EMC peripheral circuitry to the circuit. The 220V to 5V power supply circuit is as follows: Figure 13 As shown, the electrolytic capacitor in the circuit , It is the output filter capacitor. The ceramic capacitor can eliminate high-frequency noise, while the rod-shaped inductor L1 can effectively reduce current ripple.

[0072] Figure 13 In this configuration, AC220D-L / N / PE represents the 220V AC live wire / neutral wire / protective ground; FUSE is a fuse used for overcurrent protection; NTC is a negative temperature coefficient thermistor used to suppress surge current; RV is a varistor used for surge voltage protection; RES is a resistor; CX1, CY1, and CY2 are X capacitors (differential mode filtering) / Y capacitors (common mode filtering); LCM is a common mode inductor used to suppress common mode interference; HECUBE power supply is a HECUBE brand AC / DC power module; L1 is a rod inductor used for output filtering; CX1, CX2, and CX3 are electrolytic capacitors and ceramic capacitors used for power output filtering; +5V is the 5V DC output; GND is ground.

[0073] The microprocessor requires a 3.3V power supply when downloading programs. An LM1117-3.3V low-dropout voltage regulator chip is used to convert 5V to 3.3V. The application circuit of the LM1117-3.3V is as follows: Figure 14 As shown. The LM1117 integrates overheat protection and current limiting circuitry to prevent junction overheating caused by excessively high ambient temperatures. A tantalum capacitor connected in parallel at the output can suppress ripple.

[0074] Figure 14 In the diagram, LM1117-3.3V refers to the LM1117-3.3V low dropout linear regulator; IN is the regulator's voltage input pin; OUT is the regulator's voltage output pin; GND is the ground pin; +5V is the 5V DC input voltage; +3.3V is the 3.3V DC output voltage; C41, CA1, and CA2 are capacitors; 100uf / 16V indicates the capacitor value and voltage rating (100μF / 16V); 106 is the capacitor value code, representing 10μF; 104 is the capacitor value code, representing 0.1μF.

[0075] The FPGA's I / O ports and other components require a high voltage of 3.3V for communication, while the FPGA operates at a low voltage of 2.5V. The LM1117-2.5V low-dropout linear regulator (LDO) circuit is used in this application. Figure 15 As shown, it converts the input +5V voltage to the 2.5V power supply required for FPGA operation, and uses capacitors C10, C11, and C42 to perform input or output filtering to ensure voltage stability. The phase-locked loop uses 1.2V, so the FPGA hardware requires three different voltages: 3.3V, 2.5V, and 1.2V. The circuit already has a 3.3V voltage; the LM1117 power supply chip then converts the 5V to 2.5V. The application circuit diagram for LM1117-2.5V is the same as that for LM1117-3.3V.

[0076] Figure 15In this code, LM1117-2.5V refers to the LM1117-2.5V low dropout linear regulator; IN is the regulator's voltage input pin; OUT is the regulator's voltage output pin; GND is the ground pin; +5V is the 5V DC input voltage; +2.5V is the 2.5V DC output voltage; C10, C11, and C42 are capacitors; 106 is the capacitor value code, representing 10μF; 104 is the capacitor value code, representing 0.1μF; 100uf / 16V is the capacitor value and withstand voltage (100μF / 16V).

[0077] In the 5V to 1.2V circuit, select the SPX3819M5-L-1-2 chip. This is a positive voltage regulator with low dropout and low noise output. The chip features battery reverse protection, current limiting, and thermal shutdown. Application circuits for the SPX3819M5-L-1-2 include... Figure 16 As shown.

[0078] Figure 16 In this diagram, SPX3819M5-L-1-2 is a low-dropout linear regulator of the SPX3819M5-L-1-2 type; VIN is the regulator's voltage input pin; VOUT is the regulator's voltage output pin; ADJ is the output voltage adjustment pin; EN is the regulator's enable pin; GND is the ground pin; +5V is the 5V DC input voltage; +1.2V is the 1.2V DC output voltage; C12, C13, C14, and C43 are capacitors; 104 is the capacitor value code, representing 0.1μF; 106 is the capacitor value code, representing 10μF; 100uf / 16V is the capacitor value and withstand voltage (100μF / 16V).

[0079] Since partial discharge signals have both positive and negative voltages, the MC34063A switching power supply chip is selected to convert 5V to -5V. The MC34063A voltage inversion circuit, such as... Figure 17 As shown, the MC34063A is a DC-DC converter controller that, in conjunction with components such as inductors, diodes (SS14), and capacitors, enables voltage boosting, bucking, or reversing.

[0080] Figure 17In this diagram, MC34063A is the MC34063A switching power supply controller; DRI is the drive output pin; IPK is the peak current detection pin; VCC is the power supply pin; FB is the feedback pin; SE is the detection enable pin; TC is the timing capacitor pin; SC is the switch collector pin; GND is the ground pin; RD21, RD22, and RD23 are resistors; CD15, CD16, CD17, and CD18 are capacitors; L2 and L3 are inductors (L2 is 100μH, L3 is 22μH); D1 is a diode (SS14 Schottky diode); T3 is the test point; +5V is the 5V DC input voltage; -5V is the -5V DC output voltage; AGND2 is analog ground 2.

[0081] Example 2 In this embodiment, a method for detecting grounding faults in a power distribution network is adopted. This method operates using the same grounding fault detection device as described in Embodiment 1, and the method flow is as follows: Figure 18 As shown, proceed with the following steps in sequence: BeiDou Time Synchronization: First, the system utilizes the BeiDou Navigation Satellite System for high-precision time synchronization. This ensures that monitoring equipment at different locations (both the incoming and outgoing ends) has a completely consistent time reference when collecting data, guaranteeing the accuracy of subsequent vector calculations.

[0082] Measure the vector sum of the incoming currents: At the incoming end of the monitored area, i.e. the side where the power supply flows in, measure the vector sum of the three-phase currents (phase A, phase B, and phase C).

[0083] Measure the vector sum of the currents at the outgoing terminals: At the outgoing terminals of the monitored area, i.e., the load outflow side, the vector sum of the three-phase currents is also measured.

[0084] Calculate the difference: Compare the vector sum of the three-phase currents at the incoming end with the vector sum of the three-phase currents at the outgoing end, and calculate the difference between the two. The principle is similar to differential protection. According to Kirchhoff's current law, under normal circumstances, the vector sum of the inflow and outflow currents should be equal or close to zero.

[0085] Determine the status of the difference: Scenario A (Difference is zero): If the difference is zero or within the allowable error range, it indicates that there is no leakage or grounding fault in the area. The process returns to the first step of BeiDou timing and continues to monitor in a loop.

[0086] Case B (Difference not zero): If the difference is significantly non-zero, it indicates that there is current leakage in the area, which may indicate a grounding fault. The system proceeds to the next diagnostic step.

[0087] Separate measurement of partial discharge signals: After confirming the presence of a fault, the system will detect the voltage partial discharge signals of each of the three-phase high-voltage lines. This allows for precise location of which specific phase has experienced a fault.

[0088] Fault phase identification: If there is no discharge signal phase, the phase is determined to be the phase without ground fault; if there is a discharge signal phase, the phase is determined to be the phase with ground fault.

[0089] Alarm issued: Once the specific faulty phase is confirmed, the system immediately issues an alarm signal to notify maintenance personnel to handle the situation. The process then returns to its initial state and continues monitoring.

[0090] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A grounding fault detection device for power distribution networks, characterized in that, The device includes an incoming signal acquisition device and an outgoing signal acquisition device installed at the incoming and outgoing sections of the area under test, respectively. Both include a microprocessor module, a Beidou time synchronization module, a three-phase current transformer, a signal conditioning module, and an FPGA module. The output terminal of the three-phase current transformer is connected to a power metering module. The metal casing of the three-phase current transformer serves as a voltage sensing electrode for non-contact sensing of the voltage signal of the three-phase high-voltage cable; the metal casing is connected to the input terminal of the signal conditioning module, and the output terminal of the signal conditioning module is connected to the FPGA module. The microprocessor module is configured to: compare the current vector sum of the incoming and outgoing terminals according to the BeiDou time synchronization to determine whether there is a fault, and locate the fault phase based on the high-frequency component in the voltage signal sensed by the metal casing.

2. The power distribution network grounding fault detection device according to claim 1, characterized in that, The principle of using the metal casing of the three-phase current transformer as a voltage sensing electrode includes: utilizing the first stray capacitance between the metal casing and the high-voltage cable, and the second stray capacitance between the metal casing and the ground to form a series voltage divider structure, thereby generating an induced voltage on the metal casing that is proportional to the voltage of the high-voltage cable.

3. The power distribution network grounding fault detection device according to claim 1, characterized in that, The signal conditioning module includes a high-pass filter circuit and a high-frequency signal amplification circuit connected in sequence; the cutoff frequency of the high-pass filter circuit is set to 100kHz, which is used to filter out power frequency signals and retain high-frequency partial discharge signals; the high-frequency signal amplification circuit is used to adjust the AC inductive signal into a unipolar voltage signal that is compatible with the A / D acquisition chip.

4. The power distribution network grounding fault detection device according to claim 3, characterized in that, The high-frequency signal amplification circuit specifically includes a voltage follower, an inverting proportional amplifier, and an addition / subtraction circuit; the voltage follower is used to output a stable reference voltage; the addition / subtraction circuit performs calculations on the high-pass filtered signal and the processed reference voltage, amplifies the weak AC high-frequency signal input, and superimposes a DC bias to make its output range between 0V and 2V.

5. A power distribution network grounding fault detection device according to claim 3, characterized in that, The input terminal of the high-frequency signal amplification circuit is equipped with a protection circuit, which includes two diodes connected in reverse parallel. The diodes are connected between the input signal terminal and ground and are used to conduct when the amplitude of the input signal exceeds the diode conduction threshold to protect the subsequent operational amplifier.

6. The distribution network grounding fault detection device according to claim 1, characterized in that, The data processing architecture of the device adopts a collaborative working mode of FPGA and microprocessor; the FPGA module is externally connected to an SRAM storage chip for high-speed caching of high-frequency partial discharge data sensed by the metal casing; the FPGA module and the microprocessor module communicate through the FSMC parallel bus.

7. The power distribution network grounding fault detection device according to claim 1, characterized in that, The incoming signal acquisition device and the outgoing signal acquisition device also include a power supply module. The power supply module includes a negative voltage generation circuit, which is used to convert the DC voltage input by a single power supply into a negative voltage to provide dual power supply for the operational amplifier in the signal conditioning module to process the negative half-axis part of the AC inductive signal.

8. A power distribution network grounding fault detection device according to claim 1, characterized in that, Both the incoming and outgoing signal acquisition devices are equipped with 4G communication modules. The microprocessor module connects to the cloud server through the 4G communication module to upload the acquired current difference data and high-frequency discharge signal characteristics to the cloud.

9. A method for detecting grounding faults in a power distribution network, characterized in that, The method applies the power distribution network grounding fault detection device as described in any one of claims 1-8, and the method steps include: The incoming and outgoing signal acquisition devices use the BeiDou time synchronization system for time synchronization. Simultaneously measure the vector sum of the three-phase currents at the incoming end and the vector sum of the three-phase currents at the outgoing end of the measured area; Calculate the difference between the vector sum of the three-phase currents at the incoming end of the measured area and the vector sum of the three-phase currents at the outgoing end of the measured area; Determine if the difference is zero; if the difference is zero, determine that no ground fault has occurred and return to the time synchronization step to continue monitoring; otherwise, determine that a ground fault has occurred and initiate partial discharge signal detection. The partial discharge signals of the three-phase high-voltage line voltages are measured separately. During the measurement, it is determined whether there is a discharge signal in each phase. If there is no discharge signal in a certain phase, it is determined that no ground fault has occurred in that phase; otherwise, it is determined that a ground fault has occurred in that phase.

10. A method for detecting grounding faults in a power distribution network according to claim 9, characterized in that, The method further includes: comparing the intensity of the high-frequency discharge signal of the fault phase collected at the input end and the output end; if the signal intensity at the input end is greater than that at the output end, it is determined that the fault point is closer to the input side; otherwise, it is determined that the fault point is closer to the output side.

Images