A high-integration voltage regulator

Abstract

The application discloses a high-integration-stability voltage stabilizer and relates to the technical field of integrated circuits, which comprises a bias circuit, a first-stage error amplifier, a second-stage error amplifier, a dynamic Miller compensation circuit, an adjusting tube module and a feedback resistance network. The output end of the bias circuit is electrically connected to the first-stage error amplifier and the second-stage error amplifier respectively, and the dynamic Miller compensation circuit is connected across the input end and the output end of the second-stage error amplifier. The feedback resistance network comprises a first feedback resistance, a second feedback resistance and an efuse trimming array. The first feedback resistance and the second feedback resistance are connected in series between the output end and a grounding port, and the intermediate node between the first feedback resistance and the second feedback resistance is electrically connected to the inverting input end of the first-stage error amplifier. By arranging the feedback resistance network with the trimming array, the resistance ratio requirement of different output voltages of the voltage stabilizer can be met, additional circuit design is reduced, and highly integrated packaging is achieved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to a highly integrated voltage regulator. Background Technology

[0002] Current electronic products are trending towards miniaturized designs. Traditional low-dropout linear regulators primarily consist of a voltage reference module, an error amplifier, a power transistor, and a feedback resistor network. These components are relatively large, and the size of the power transistor is directly proportional to its maximum output current, resulting in the power transistor's area accounting for 30% to 40% of the overall regulator area. To reduce operating noise, current regulators require additional digital circuits and timing control circuits, further increasing the overall regulator area and making it difficult to meet the demands of highly integrated designs. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a highly integrated voltage regulator. By integrating an efuse adjustment array into the feedback resistor network, the resistance value is controlled by the fuse of the efuse device, thereby meeting the resistance ratio requirements of different output voltages of the voltage regulator, reducing additional circuit design, and realizing a highly integrated package of the voltage regulator.

[0004] This invention provides a highly integrated voltage regulator, which includes: a bias circuit, a first-stage error amplifier, a second-stage error amplifier, a dynamic Miller compensation circuit, an adjustment transistor module, and a feedback resistor network; The output terminal of the bias circuit is electrically connected to the bias terminal of the first-stage error amplifier and the bias terminal of the second-stage error amplifier, respectively. The non-inverting input terminal of the first-stage error amplifier is electrically connected to the reference voltage, the inverting input terminal of the first-stage error amplifier is electrically connected to the feedback voltage, and the output terminal of the first-stage error amplifier is electrically connected to the input terminal of the second-stage error amplifier. The output of the second-stage error amplifier is electrically connected to the control terminal of the adjustment tube module, and the dynamic Miller compensation circuit is connected between the input and output terminals of the second-stage error amplifier. The output terminal of the regulating tube serves as the output terminal of the voltage regulator and is also electrically connected to the input terminal of the feedback resistor network. The feedback resistor network includes a first feedback resistor, a second feedback resistor, and an efuse tuning array. The first feedback resistor and the second feedback resistor are connected in series between the output terminal and the ground port. The intermediate node between the first feedback resistor and the second feedback resistor is electrically connected to the inverting input terminal of the first-stage error amplifier.

[0005] Furthermore, the second feedback resistor is composed of several basic resistors connected in series, and an efuse device is connected in parallel across each of the basic resistors.

[0006] Furthermore, the voltage regulator also includes a voltage reference module, which is configured as a depletion enhancement-mode MOSFET complementary voltage structure; The output of the voltage reference module is electrically connected to the non-inverting input of the first-stage error amplifier.

[0007] Furthermore, the depletion-enhanced MOSFET complementary voltage structure includes a depletion-mode MOSFET, an enhancement-mode MOSFET, a current mirror, and a fine-tuning resistor array; The drain of the depletion-type MOS transistor is connected to the drain of the first MOS transistor of the current mirror MOS transistor, the gate of the depletion-type MOS transistor is grounded, and the source of the depletion-type MOS transistor is grounded through an on-chip integrated fine-tuning resistor array. The enhancement-mode MOSFET adopts an on-chip integrated diode connection method, the source of the enhancement-mode MOSFET is grounded, and the drain of the enhancement-mode MOSFET is connected to the drain of the second MOSFET of the current mirror MOSFET. The power supply terminal is integrated within the source terminal of the first MOS transistor in the current mirror. The gate and drain of the first MOS transistor are connected and are also connected to the drain of the depletion-type MOS transistor.

[0008] Furthermore, the bias circuit includes: a twelfth MOSFET, a thirteenth MOSFET, and a fourteenth MOSFET; The thirteenth MOS transistor and the fourteenth MOS transistor form a first current mirror structure. The sources of the thirteenth MOS transistor and the fourteenth MOS transistor are electrically connected to the power input terminal, and the gates of the thirteenth MOS transistor and the fourteenth MOS transistor are shorted. The source of the twelfth MOS transistor is connected to the power input terminal, the gate of the twelfth MOS transistor is connected to the drain of the fourteenth MOS transistor, and the drain of the twelfth MOS transistor outputs a first bias voltage.

[0009] Furthermore, the bias circuit also includes a tenth MOS transistor, an eleventh MOS transistor, a first resistor, and a second resistor; The gate of the tenth MOS transistor is shorted to the gate of the eleventh MOS transistor, and the gate of the tenth MOS transistor is shorted to the drain of the tenth MOS transistor, forming a second current mirror structure. The drain of the tenth MOS transistor is connected to the drain of the thirteenth MOS transistor, the source of the tenth MOS transistor is connected to one end of the first resistor, and the other end of the first resistor is grounded. The drain of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor, the source of the eleventh MOS transistor is connected to one end of the second resistor, the other end of the second resistor is grounded, and the connection node between the second resistor and the source of the eleventh MOS transistor outputs a second bias voltage. The first bias voltage is electrically connected to the bias terminal of the first-stage error amplifier, and the second bias voltage is electrically connected to the bias terminal of the second-stage error amplifier.

[0010] Furthermore, the first-stage error amplifier includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, and a first compensation capacitor; The gate of the first MOSFET is electrically connected to the reference voltage, the gate of the second MOSFET is electrically connected to the feedback voltage, and the sources of the first MOSFET and the second MOSFET are connected to the drain of the fifth MOSFET. The gates of the third MOS transistor and the fourth MOS transistor are shorted, the sources of the third MOS transistor and the fourth MOS transistor are grounded, the drain of the third MOS transistor is electrically connected to the drain of the first MOS transistor, and the drain of the fourth MOS transistor is electrically connected to the drain of the second MOS transistor. One end of the first compensation capacitor is electrically connected to the drain connection node of the first MOS transistor and the third MOS transistor, and the other end of the first compensation capacitor is grounded.

[0011] Furthermore, the second-stage error amplifier includes: a sixth MOSFET, a seventh MOSFET, and an eighth MOSFET; The gate of the sixth MOS transistor serves as the input terminal of the second-stage error amplifier, and the gate of the sixth MOS transistor is electrically connected to the output terminal of the first-stage error amplifier. The source of the sixth MOS transistor is grounded. The source of the seventh MOS transistor is electrically connected to the power input terminal, and the gate of the seventh MOS transistor is electrically connected to the first bias voltage. The source of the eighth MOS transistor is electrically connected to the power input terminal, the gate of the eighth MOS transistor is electrically connected to the second bias voltage, and the drain of the eighth MOS transistor is electrically connected to the drain of the sixth MOS transistor. The drain connection node of the sixth MOS transistor and the eighth MOS transistor is set as the output terminal of the second-stage error amplifier and electrically connected to the gate of the adjustment transistor module, so as to output the amplified error signal to the adjustment transistor module.

[0012] Furthermore, the dynamic Miller compensation circuit includes a second compensation capacitor, a series resistor, and a dynamic attenuation resistor; The second compensation capacitor and the series resistor are connected in series between the gate and drain of the sixth MOS transistor; The dynamic attenuation resistor is connected in series between the drain of the eighth MOS transistor and the output of the second-stage error amplifier.

[0013] Furthermore, the voltage regulator also includes a pseudo-ESR compensation and feedforward circuit, which includes a pseudo-ESR compensation resistor, a third compensation capacitor, and a feedforward transistor. The pseudo-ESR compensation resistor and the third compensation capacitor are connected in series across the two ends of the second feedback resistor; The gate of the feedforward transistor is electrically connected to a first bias voltage, and the source and drain of the feedforward transistor are connected in parallel across the third compensation capacitor.

[0014] This invention provides a highly integrated voltage regulator. By setting a second feedback resistor with an efuse adjustment array, various output resistor combinations can be achieved based on the efuse device. Without adding additional circuit structure design, the resistance ratio requirements of various voltage output configurations can be met, thereby improving the integration of the voltage regulator. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the circuit structure of a highly integrated voltage regulator in an embodiment of the present invention; Figure 2 This is a schematic diagram of the feedback resistor network structure integrating the efuse trimming array in an embodiment of the present invention; Figure 3 This is a schematic diagram of the circuit structure of the reference voltage module of the highly integrated voltage regulator in an embodiment of the present invention; Figure 4 This is a graph showing the output voltage and temperature variation of a traditional dual-tube complementary voltage reference power supply. Figure 5 This is a graph showing the output voltage versus temperature change of the breakdown voltage module in this embodiment of the invention. Figure 6 This is a schematic diagram of the voltage regulator output noise spectrum density in an embodiment of the present invention; Figure 7 This is the integral noise diagram of the voltage regulator output in an embodiment of the present invention; Figure 8 This is a comparison diagram of the loop phase margin of the dynamic Miller compensation structure in this embodiment of the invention and the loop phase margin of the traditional Miller compensation structure. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] Please refer to Figures 1 to 8 This invention provides a highly integrated voltage regulator, which includes: a bias circuit 1, a first-stage error amplifier 2, a second-stage error amplifier 3, a dynamic Miller compensation circuit 4, an adjustment transistor module, and a feedback resistor network 6. The output terminal of the bias circuit 1 is electrically connected to the bias terminal of the first-stage error amplifier 2 and the bias terminal of the second-stage error amplifier 3, respectively. The bias circuit 1 is used to provide a stable DC operating point voltage to ensure that each transistor in the circuit is in a suitable bias state, thereby realizing the expected amplification or switching function and maintaining the stability of circuit performance.

[0018] The non-inverting input of the first-stage error amplifier 2 is electrically connected to the reference voltage, the inverting input is electrically connected to the feedback voltage, and the output is electrically connected to the input of the second-stage error amplifier 3. The first-stage error amplifier 2 is used to perform preliminary error detection and amplification in the regulator control circuit. It can accurately compare the difference between the reference voltage and the feedback voltage and use the difference signal as the input signal of the second-stage error amplifier 3. Based on the second-stage error amplifier 3, the error signal is further amplified, providing sufficient gain and drive capability to effectively control the regulating transistor module and ensure the regulator's fast response and precise adjustment to the output voltage deviation.

[0019] The output of the second-stage error amplifier 3 is electrically connected to the control terminal of the adjustment tube module, and the dynamic Miller compensation circuit 4 is connected between the input and output terminals of the second-stage error amplifier 3. The dynamic Miller compensation circuit 4 introduces a capacitor and resistor network between the amplifier stages to adaptively adjust the frequency response under different operating conditions, so as to ensure the stability of the regulator over a wide load range and avoid oscillation.

[0020] Furthermore, the dynamic Miller compensation circuit 4 is connected between the input and output of the second-stage error amplifier 3. This compensation circuit can consist of a single capacitor, used to provide frequency compensation under different load conditions to ensure the stability of the regulator over a wide load range. For example, a simple Miller capacitor can be connected between the input and output of the second-stage error amplifier 3 to introduce dominant pole compensation, thereby improving the phase margin.

[0021] The output terminal of the regulating transistor module serves as the output terminal of the voltage regulator and is also electrically connected to the input terminal of the feedback resistor network 6. By adjusting the on-resistance of the regulating transistor module, the current flowing to the load can be controlled, thereby maintaining the stability of the output voltage.

[0022] The feedback resistor network 6 includes a first feedback resistor, a second feedback resistor, and an efuse tuning array. The first feedback resistor and the second feedback resistor are connected in series between the output terminal and the ground port. The intermediate node between the first feedback resistor and the second feedback resistor is electrically connected to the inverting input terminal of the first-stage error amplifier 2.

[0023] Specifically, the second feedback resistor is composed of several basic resistors connected in series. An efuse device is connected in parallel across each of the basic resistors. The efuse device is made of polysilicon fuse. The fusing condition is set to apply a 5V voltage and maintain the voltage for 1ms. Under these conditions, the efuse device can perform a fusing operation. After the efuse device is fused, the basic resistor of the branch containing the efuse device is short-circuited. By controlling the fusing operation of the efuse devices at different positions, the resistance value of the second feedback resistor is changed, thereby changing the voltage division ratio between the first feedback resistor and the second feedback resistor, which enables the adjustment of the output voltage of the regulator.

[0024] Furthermore, the feedback resistor network 6 forms a voltage divider feedback based on the first feedback resistor and the second feedback resistor, dividing the output voltage and feeding it back to the negative input terminal of the first-stage error amplifier 2. The output voltage is stabilized through closed-loop feedback, where the closed-loop gain is: ; in, For closed-loop gain, For the first feedback resistor, This is the second feedback resistor.

[0025] Furthermore, based on the feedback resistor network 6, the output voltage of the voltage regulator is proportionally divided, and the divided voltage is sent back to the error amplifier as a feedback signal to achieve rapid adjustment of the operating voltage of the voltage regulator, thereby achieving the effect of voltage regulation for the operating voltage of electronic products.

[0026] In this embodiment of the invention, the reference voltage is set to a base value corresponding to the target 1.2V output voltage. When the regulator starts working, the output of the regulating transistor module generates an initial voltage. The feedback resistor network 6 divides this output voltage proportionally to generate a feedback voltage. In this embodiment, the output voltage is set to 1.2V, and the feedback resistor network 6 can divide it to 0.6V as the feedback voltage.

[0027] The first-stage error amplifier 2 receives this 0.6V feedback voltage and a preset 0.6V reference voltage. If the output voltage drops slightly due to load changes, for example, to 1.19V, the feedback voltage will also drop accordingly to 0.595V. The first-stage error amplifier 2 will detect an error of 0.005V and amplify it. This initially amplified error signal is then passed to the second-stage error amplifier 3.

[0028] The second-stage error amplifier 3 further amplifies the error signal and outputs it to the control terminal of the regulating transistor module. When the error signal indicates that the output voltage is too low, the second-stage error amplifier 3 outputs a signal that increases the conduction level of the regulating transistor module. Responding to this control signal, the regulating transistor module precisely calibrates the resistance ratio of the feedback resistor network 6 based on the efuse adjustment array, reducing its on-resistance and allowing more current to flow to the load, thus raising the output voltage back to 1.2V and achieving a regulated output.

[0029] Furthermore, when the load current changes rapidly, the pole frequency inside the regulator shifts, potentially causing oscillation. The dynamic Miller compensation circuit 4 adaptively adjusts the regulator's frequency response by introducing frequency compensation between the input and output of the second-stage error amplifier 3. Under light load conditions, the compensation circuit provides smaller compensation, while under heavy load conditions, it provides larger compensation, thereby ensuring that the regulator maintains sufficient phase margin across the entire load range, avoiding oscillation and achieving a fast and stable response.

[0030] Furthermore, by designing the second feedback resistor as a series connection of several basic resistors, and connecting an efuse device in parallel across each basic resistor, fine-tuning of the resistance value is achieved. During the operation of the voltage regulator, the feedback resistor network 6 divides the output voltage of the voltage regulator to generate a feedback voltage. This feedback voltage is compared with the reference voltage in the first-stage error amplifier 2 to generate an error signal. The accuracy of the second feedback resistor directly determines the accuracy of the voltage division ratio, thus affecting the output voltage accuracy of the voltage regulator.

[0031] Specifically, the voltage regulator also includes a voltage reference module, which is configured as a depletion-enhancement MOSFET complementary voltage structure. The output of the voltage reference module is electrically connected to the non-inverting input of the first-stage error amplifier 2. The voltage reference module provides a stable power supply voltage, thereby ensuring the stability and accuracy of the voltage regulator's operation. In this embodiment, the voltage reference module is a voltage reference structure built based on the characteristics of MOSFETs, forming a depletion-enhancement MOSFET complementary voltage structure. The voltage reference module is formed by combining the different characteristics of depletion-type and enhancement-type MOSFETs. A depletion-type MOSFET still has a conductive channel when the gate-source voltage is zero, while an enhancement-type MOSFET requires a positive gate-source voltage to form a conductive channel. By cleverly combining these two types of MOSFETs, effective compensation for temperature drift and process variations can be achieved.

[0032] Furthermore, by introducing a voltage reference module and configuring it as a complementary voltage structure for depletion-enhanced MOSFETs, the limitations of traditional voltage references—such as bulk effects, susceptibility to process variations, and inability to guarantee zero temperature drift across the entire temperature range—are effectively addressed. Specifically, this complementary voltage structure utilizes the electrical characteristics and temperature coefficients of both depletion-type and enhancement-type MOSFETs. Through ingenious circuit design, the temperature drift effects of the two types of MOSFETs cancel each other out, thereby providing a highly stable reference voltage over a wide temperature range. Simultaneously, this complementary structure effectively suppresses bulk effects, reduces the circuit's sensitivity to substrate bias voltage changes, and enhances tolerance to manufacturing variations, ensuring the long-term stability and consistency of the reference voltage.

[0033] Specifically, the depletion enhancement-mode MOSFET complementary voltage structure includes a depletion-mode MOSFET, an enhancement-mode MOSFET, a current mirror, and a fine-tuning resistor array; the drain of the depletion-mode MOSFET is connected to the drain of the first MOSFET of the current mirror MOSFET, and the output terminal of the depletion-mode MOSFET is coupled to the input terminal of the current mirror, so that the current generated by the depletion-mode MOSFET can be accurately replicated by the current mirror in order to construct a stable bias current and voltage.

[0034] The gate of the depletion-type MOSFET is grounded, and its gate voltage is fixed at zero, allowing the conductive channel of the MOSFET to remain open, thus forming a stable current path or voltage drop. The source of the depletion-type MOSFET is grounded through an on-chip integrated fine-tuning resistor array. By adjusting the resistance value of the fine-tuning resistor array, the source point of the depletion-type MOSFET can be precisely controlled, thereby compensating for the effects of process deviations and temperature changes on the voltage reference output.

[0035] The enhancement-mode MOSFET uses an on-chip integrated diode connection, which shorts the gate and drain of the enhancement-mode MOSFET, providing a relatively stable voltage drop. The source of the enhancement-mode MOSFET is grounded, thereby forming a stable reference potential. The drain of the enhancement-mode MOSFET is connected to the drain of the second MOSFET of the current mirror MOSFET, so that the output terminal of the enhancement-mode MOSFET is coupled to the output terminal of the current mirror, thereby enabling the current generated by the enhancement-mode MOSFET to be effectively processed and transmitted by the current mirror.

[0036] The power supply terminal integrated within the source patch of the first MOSFET in the current mirror provides a stable power supply voltage to the first MOSFET. The gate and drain of the first MOSFET are connected to the drain of the depletion-mode MOSFET, enabling the current mirror to operate in the saturation region and forming a reference current path. Simultaneously, the current characteristics of the depletion-mode MOSFET can influence the bias of the current mirror through this connection point, thereby achieving accurate current replication and temperature compensation. The depletion-enhancement-mode MOSFET complementary voltage structure, by combining the depletion-mode MOSFET, enhancement-mode MOSFET, current mirror, and fine-tuning resistor array, constructs a voltage reference insensitive to bulk effects and process variations.

[0037] Furthermore, the depletion-type MOSFET can be an N-channel depletion-type MOSFET, with its gate directly connected to the chip's digital ground. Its source is grounded through a fine-tuning resistor array consisting of multiple parallel or series-connected fuse-programmable resistors, thereby precisely adjusting the source potential of the depletion-type MOSFET. The enhancement-type MOSFET can be a P-channel enhancement-type MOSFET, with its gate and drain shorted to form a P-channel diode-connected MOSFET, and its source connected to the chip's analog ground. The current mirror can be composed of two matched PMOS transistors. The first and second MOSFETs can use the same layout size and arrangement to ensure good matching characteristics. The source of the first MOSFET is connected to the chip's power supply voltage, and its gate and drain are shorted and connected to the drain of the depletion-type MOSFET. The source of the second MOSFET is also connected to the power supply voltage, its gate is connected to the gate of the first MOSFET, and its drain is connected to the drain of the enhancement-type MOSFET. Through this specific circuit layout and component selection, a voltage reference with excellent temperature stability and adjustability can be achieved.

[0038] The voltage reference module replicates the current of the depletion-mode MOSFET to the branch of the enhancement-mode MOSFET via a current mirror, ensuring that both the depletion-mode and enhancement-mode MOSFETs operate in the saturation region. The reference voltage expression is: ; in, , The saturation current coefficient of the MOSFET. , Threshold voltage, To fine-tune the voltage drop of the resistor array, the voltage drift caused by process deviations can be compensated by adjusting the value of the fine-tuning resistor, thus achieving secondary temperature compensation.

[0039] When the temperature rises Increase The temperature compensation is achieved by reducing the complementary characteristics of the two components; the voltage drop of the fine-tuning resistor array is reduced. It increases with increasing temperature, allowing for further optimization of the temperature coefficient.

[0040] The output noise of this structure is expressed as: ; in, The transconductance of the MOSFET Mi Boltzmann's constant, Absolute temperature This represents the thermal noise figure of the MOSFET. This refers to the gate oxide capacitance per unit area of ​​the MOSFET. These represent the channel width and length of the MOSFET Mi, respectively. Simulation results show that the temperature coefficient of this voltage reference module is 29.6 ppm / °C across the entire process angle, the maximum voltage deviation is 3.6 mV, the maximum output noise density at 1 kHz is 62.6 nV / √Hz, and the area accounts for only 12% of the total area of ​​the LDO.

[0041] Specifically, the bias circuit 1 includes: a twelfth MOS transistor, a thirteenth MOS transistor, and a fourteenth MOS transistor; the bias circuit 1 is a working circuit that provides a stable operating point for active devices, and can ensure that the devices operate in a preset linear or saturation region to achieve the expected amplification, switching and other functions.

[0042] The thirteenth MOS transistor and the fourteenth MOS transistor form a first current mirror structure. The sources of the thirteenth MOS transistor and the fourteenth MOS transistor are electrically connected to the power input terminal, and the gates of the thirteenth MOS transistor and the fourteenth MOS transistor are shorted. The source of the twelfth MOSFET is connected to the power input terminal, and the gate of the twelfth MOSFET is connected to the drain of the fourteenth MOSFET. The drain of the twelfth MOSFET outputs a first bias voltage. The function of connecting the gate to the drain of the fourteenth MOSFET is to use the drain voltage of the fourteenth MOSFET as the gate control voltage of the twelfth MOSFET, thereby controlling the conduction state of the twelfth MOSFET.

[0043] Bias circuit 1 can use a resistor divider network combined with a Zener diode to provide a stable bias voltage, or it can use a bandgap reference source combined with a current mirror to generate a precise and temperature-stable bias current or voltage. The first current mirror structure is based on the thirteenth and fourteenth MOSFETs to improve output impedance and current matching accuracy. The source, electrically connected to the power input terminal, provides operating power to the MOSFETs, ensuring their normal conduction and operation. It can be directly connected to the chip's VDD power rail, or it can be connected to the power rail through a decoupling capacitor to filter out power supply noise.

[0044] Bias circuit 1 can be implemented using PMOS transistors to represent the twelfth, thirteenth, and fourteenth MOS transistors. In this case, the power input terminal can refer to the VDD power rail of the chip. The thirteenth and fourteenth MOS transistors can be designed as PMOS transistors with the same dimensions (W / L ratio) to ensure good matching of the current mirror. The gate and drain of the thirteenth MOS transistor can be shorted to form a diode-connected PMOS transistor, serving as the reference branch for the current mirror. Its gate voltage is connected to the gate of the fourteenth MOS transistor via a metal wiring. The source of the twelfth MOS transistor is connected to VDD, and its gate is connected to the drain of the fourteenth MOS transistor via a metal wiring. The drain of the twelfth MOS transistor can be connected to the bias terminal of the first-stage error amplifier 2, for example, as a current source for its differential pair transistors.

[0045] Specifically, the bias circuit 1 further includes a tenth MOSFET, an eleventh MOSFET, a first resistor, and a second resistor; the gates of the tenth MOSFET and the eleventh MOSFET are shorted together, and the gates and drains of the tenth MOSFET are shorted together, forming a second current mirror structure; the tenth and eleventh MOSFETs are metal-oxide-semiconductor field-effect transistors, which can function as switches, amplifiers, or current sources in the circuit. As part of the current mirror, they can accurately replicate the current, thereby providing a stable bias for the circuit. The tenth and eleventh MOSFETs can be N-type or P-type MOSFETs, or enhancement-mode or depletion-mode MOSFETs; the specific type selection depends on the circuit design's requirements for voltage range, power consumption, and noise performance.

[0046] The drain of the tenth MOS transistor is connected to the drain of the thirteenth MOS transistor, and the source of the tenth MOS transistor is connected to one end of the first resistor, while the other end of the first resistor is grounded. By adjusting the resistance value of the first resistor, the reference current of the tenth MOS transistor can be precisely controlled, thereby affecting the current magnitude of the entire second current mirror.

[0047] The drain of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor, the source of the eleventh MOS transistor is connected to one end of the second resistor, the other end of the second resistor is grounded, and the connection node between the second resistor and the source of the eleventh MOS transistor outputs a second bias voltage. The first bias voltage is electrically connected to the bias terminal of the first-stage error amplifier 2, and the second bias voltage is electrically connected to the bias terminal of the second-stage error amplifier 3.

[0048] The first and second resistors can be of various resistor types achievable in integrated circuit processes, such as polysilicon resistors, diffused resistors, or metal resistors. Polysilicon resistors offer good matching characteristics and a relatively small area; diffused resistors have low parasitic capacitance. The introduction of these resistors helps to accurately set the bias current or voltage and provide a stable reference potential, thereby reducing the impact of noise on the bias voltage. A second current mirror structure is an analog circuit configuration used to replicate or mirror a reference current and provide it to other parts of the circuit. A second current mirror structure typically consists of two or more matched transistors, and its core function is to ensure a precise proportional relationship between the output current and the input reference current. This structure effectively suppresses the effects of power supply voltage fluctuations and temperature changes on the bias current, thereby improving the stability of the bias voltage.

[0049] The drain of the eleventh MOSFET is connected to the drain of the twelfth MOSFET. This connection links the output current branch in the second current mirror structure to the drain of the twelfth MOSFET in the aforementioned bias circuit 1, further refining the generation of the first bias voltage, or providing a stable current load for the twelfth MOSFET to ensure the stability of its output first bias voltage. The source of the eleventh MOSFET is connected to one end of the second resistor, and the other end of the second resistor is grounded. The connection node between the second resistor and the source of the eleventh MOSFET outputs the second bias voltage. This means that the drain current of the eleventh MOSFET flows through the second resistor, generating a voltage drop across it. This voltage drop is the required second bias voltage. The first bias voltage is electrically connected to the bias terminal of the first-stage error amplifier 2, and the second bias voltage is electrically connected to the bias terminal of the second-stage error amplifier 3. These connections clarify the purpose of the generated bias voltage, ensuring that the amplifier operates in the optimal linear region and has the required gain, bandwidth, and noise performance.

[0050] Specifically, the first-stage error amplifier 2 includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a first compensation capacitor; the gate of the first MOS transistor is electrically connected to a reference voltage, the gate of the second MOS transistor is electrically connected to a feedback voltage, and the sources of the first MOS transistor and the second MOS transistor are connected to the drain of the fifth MOS transistor.

[0051] The first and second MOSFETs form a differential input pair, used to receive and amplify the difference in the input signals. These can be implemented using enhancement-mode NMOS or depletion-mode PMOS transistors. The third and fourth MOSFETs form an active load, typically implemented as a current mirror, providing a high-impedance load to the differential input pair, thereby increasing the amplifier's gain. They can be N-type or P-type MOSFETs, for example, enhancement-mode PMOS or depletion-mode NMOS transistors. The fifth MOSFET acts as a tail current source, providing a stable bias current to the differential input pair, ensuring consistent amplifier performance at different operating points. This MOSFET can also be an N-type or P-type MOSFET, for example, enhancement-mode NMOS or depletion-mode PMOS transistors. The first compensation capacitor is used for frequency compensation of the first-stage error amplifier 2 to ensure its stability over a wide frequency range.

[0052] The gates of the third MOS transistor and the fourth MOS transistor are shorted, the sources of the third MOS transistor and the fourth MOS transistor are grounded, the drain of the third MOS transistor is electrically connected to the drain of the first MOS transistor, and the drain of the fourth MOS transistor is electrically connected to the drain of the second MOS transistor. One end of the first compensation capacitor is electrically connected to the drain connection node of the first MOSFET and the third MOSFET, and the other end of the first compensation capacitor is grounded, thus introducing the first compensation capacitor to the output node of the first-stage error amplifier 2. The first compensation capacitor improves the phase margin of the amplifier by introducing a low-frequency pole to compensate for the frequency of the amplifier and prevents oscillation during closed-loop operation.

[0053] The first-stage error amplifier 2 of this application employs a combination of differential input pairs, a tail current source, and a current mirror load, supplemented by a first compensation capacitor. This effectively solves the significant 1 / f flicker noise problem introduced by traditional error amplifiers when amplifying error signals, significantly improving the accuracy of the output voltage. Specifically, the differential input structure effectively suppresses common-mode noise, while the fifth MOSFET, acting as a tail current source, ensures stable bias and reduces noise amplification. Simultaneously, the symmetrical configuration of the current mirror load further reduces mismatch noise. Furthermore, the introduction of the first compensation capacitor, especially under low load conditions, significantly improves the amplifier's phase margin, enhances the stability of the voltage regulator, and avoids the instability problem of traditional solutions under no-load or light-load conditions. Therefore, the solution of this application significantly reduces noise while ensuring high voltage regulator accuracy and broadens the stable operating range of the voltage regulator under different load conditions.

[0054] Specifically, the second-stage error amplifier 3 includes a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor. The gate of the sixth MOS transistor serves as the input terminal of the second-stage error amplifier 3, and the gate of the sixth MOS transistor is electrically connected to the output terminal of the first-stage error amplifier 2. The source of the sixth MOS transistor is grounded. The output signal of the first-stage error amplifier 2 first enters through the gate of the sixth MOS transistor. Because the source of the sixth MOS transistor is grounded, a stable input reference potential is formed, which helps to reduce the input impedance, thereby enabling the amplifier to respond quickly to signal changes.

[0055] The source of the seventh MOS transistor is electrically connected to the power input terminal, and the gate of the seventh MOS transistor is electrically connected to the first bias voltage, providing a precise bias current for the amplifier, ensuring the stability of the entire amplifier's operating point, and avoiding performance degradation caused by operating point drift.

[0056] The source of the eighth MOSFET is electrically connected to the power input terminal, the gate of the eighth MOSFET is electrically connected to the second bias voltage, and the drain of the eighth MOSFET is electrically connected to the drain of the sixth MOSFET. The connection node between the drains of the sixth and eighth MOSFETs is set as the output terminal of the second-stage error amplifier 3 and electrically connected to the gate of the regulating transistor module, used to output the amplified error signal to the regulating transistor module. Through the structural design of separating the input and output paths, pole interference within the circuit is effectively reduced, thereby significantly improving the phase margin of the voltage regulator. In this way, the second-stage error amplifier 3 can maintain high efficiency and low noise characteristics over a wide load range, ensuring stable operation of the voltage regulator under various operating conditions.

[0057] Specifically, the dynamic Miller compensation circuit 4 is a compensation technique used to improve amplifier stability, especially suitable for voltage regulators requiring stability over a wide load range. By introducing a capacitor between the amplifier's input and output, the Miller effect is used to effectively amplify the capacitance value, thereby introducing a dominant pole at a lower frequency. Combined with other components, the zero-point position is adjusted to optimize the phase margin. This circuit can dynamically adjust the compensation parameters according to changes in operating conditions to ensure sufficient system stability at different operating points. The dynamic Miller compensation circuit 4 includes a second compensation capacitor, a series resistor, and a dynamic attenuation resistor; the second compensation capacitor and the series resistor are connected in series between the gate and drain of the sixth MOS transistor. Furthermore, the second compensation capacitor can be implemented using various integrated circuit processes. For example, a metal-insulator-metal (MIM) capacitor can be used, which has good linearity and stability; alternatively, a MOSFET capacitor can be used, which has the advantage of high area efficiency and can be adjusted to a certain extent by the bias voltage. The series resistor is connected in series with the second compensation capacitor, and its main function is to introduce a zero point to cancel or shift the secondary pole introduced by the Miller capacitor, thereby improving the phase margin of the system.

[0058] The dynamic attenuation resistor is connected in series between the drain of the eighth MOS transistor and the output of the second-stage error amplifier 3. By precisely designing the resistance value of the series resistor, the zero point can be placed in a suitable position, avoiding a sharp phase drop near the crossover frequency, thereby improving the stability of the system. The series resistor can be implemented using various integrated circuit processes. For example, it can be a polysilicon resistor, which has good matching characteristics and temperature stability; or it can be a diffused resistor, which has the advantage of simple manufacturing process, but may be greatly affected by process deviations. The dynamic attenuation resistor is one of the key innovations of this dynamic Miller compensation circuit 4. Its resistance value can be dynamically adjusted according to the operating state of the voltage regulator (e.g., the load current). By dynamically adjusting the resistance value of the attenuation resistor, the equivalent impedance of the compensation network can be changed, thereby dynamically adjusting the compensation effect and ensuring that the optimal phase margin is maintained over a wide load range. The dynamic attenuation resistor is connected in series between this connection node and the output of the second-stage error amplifier 3, meaning that the resistor is directly located on the output path of the second-stage error amplifier 3. By introducing a dynamic attenuation resistor here, the output impedance of the second-stage error amplifier 3 can be dynamically adjusted, thereby affecting the position of its output poles and thus optimizing the frequency response and stability of the system under different load conditions.

[0059] Specifically, the voltage regulator further includes a pseudo-ESR compensation and feedforward circuit 5, which includes a pseudo-ESR compensation resistor, a third compensation capacitor, and a feedforward transistor. The pseudo-ESR compensation resistor and the third compensation capacitor are connected in series across the two ends of the second feedback resistor. The gate of the feedforward transistor is electrically connected to a first bias voltage, and the source and drain of the feedforward transistor are connected in parallel across the two ends of the third compensation capacitor.

[0060] The pseudo-ESR compensation and feedforward circuit 5 is an integrated circuit module used to improve the dynamic response and stability of a voltage regulator. Its main function is to simulate the equivalent series resistance (ESR) of the output capacitor, introducing a zero at high frequencies to improve phase margin, while simultaneously providing a feedforward path to accelerate the response to load transients, thereby effectively suppressing high-frequency noise and quickly responding to load changes. This circuit can be composed of resistors, capacitors, and active devices (such as MOSFETs) and can be optimized according to specific application requirements. The pseudo-ESR compensation resistor, in conjunction with the third compensation capacitor at high frequencies, introduces a zero in the feedback path to offset the output pole effect, thereby improving the phase margin of the voltage regulator and preventing oscillation. This resistor can be implemented using an on-chip integrated polysilicon resistor, diffused resistor, or metal resistor, or it can be provided by an externally connected precision resistor. The third compensation capacitor, connected in series with the pseudo-ESR compensation resistor, forms a high-frequency compensation path, which filters out high-frequency noise, smooths transient response, and reduces output ripple. This capacitor can be implemented using an on-chip integrated MOS capacitor, MIM capacitor, or an externally connected ceramic capacitor.

[0061] The solution proposed in this application improves the overall stability of the voltage regulator under high-frequency noise and load transients by introducing a pseudo-ESR compensation and feedforward circuit 5. Specifically, the pseudo-ESR compensation and feedforward circuit 5, as an integrated unit, simulates the equivalent series resistance to compensate for high-frequency phase loss in the feedback network, while providing a feedforward path to accelerate the response to load changes, thereby avoiding the shortcomings of traditional compensation mechanisms in the high-frequency range. The pseudo-ESR compensation resistor and the third compensation capacitor are connected in series across the second feedback resistor. This series structure introduces additional impedance at high frequencies, effectively suppressing noise and enhancing phase margin to prevent oscillation. The third compensation capacitor is connected in series across the feedback resistor, reducing output ripple by filtering out high-frequency interference and smoothing transient response. The gate of the feedforward transistor is electrically connected to the first bias voltage to ensure that the feedforward transistor operates under stable bias and achieves precise control. The source and drain of the feedforward transistor are connected in parallel across the third compensation capacitor, allowing for rapid current bypass and quick adjustment of the output current during load changes, minimizing overshoot or undershoot and improving dynamic performance. Through the above technical solutions, the voltage regulator significantly improves its performance in high-frequency noise suppression and load transient response while maintaining a small area and low static power consumption, thereby meeting the stringent requirements of highly integrated power management chips for stability and dynamic performance.

[0062] The bias circuit 1 of this application constructs an efficient and stable bias voltage generation mechanism by combining a 12th MOSFET, a 13th MOSFET, and a 14th MOSFET. Specifically, the 13th MOSFET and the 14th MOSFET together form a first current mirror structure. In this structure, the sources of both the 13th and 14th MOSFETs are electrically connected to the power input terminal, providing a stable power supply for the current mirror. Simultaneously, their gates are shorted together, ensuring that the two MOSFETs have the same gate voltage under ideal matching conditions. This allows the current flowing through the 14th MOSFET to accurately reflect or mirror the current flowing through the 13th MOSFET. This current mirroring mechanism is the basis for generating a stable bias, effectively suppressing the influence of power supply voltage fluctuations on the bias current. Based on this, the 12th MOSFET is configured as an output stage, with its source also connected to the power input terminal. Crucially, the gate of the 12th MOSFET is electrically connected to the drain of the 14th MOSFET. This means that the drain voltage of the 14th MOSFET, as one of the output terminals of the current mirror, directly controls the conduction level of the 12th MOSFET. Through this connection method, the drain of the twelfth MOSFET can output a stable first bias voltage. The stability of this first bias voltage benefits from the stable current provided by the first current mirror structure and the voltage follower characteristic of the twelfth MOSFET as a common-source output. The design of the bias circuit 1, especially the application of the first current mirror structure, results in a high power supply rejection ratio (PSRR) for the bias voltage generation process, effectively isolating power supply noise and thus reducing bias voltage ripple and noise. Furthermore, through the MOSFET configuration, this circuit can provide the required bias voltage with low quiescent power consumption, which is crucial for highly integrated voltage regulators. Compared to the basic solution which only mentions the bias circuit 1 providing the bias voltage, this solution provides a specific, low-noise, and low-power bias voltage generation method through explicit MOSFET configuration and current mirror structure, thereby improving the overall performance stability of the voltage regulator.

[0063] Through the above technical solution, the stability of the voltage regulator under high-frequency noise and load transients is significantly improved, effectively solving the output fluctuation problem. This solution can effectively suppress high-frequency interference, enhance phase margin, prevent oscillation, and provide fast load transient response, minimizing output voltage overshoot or undershoot. This allows the voltage regulator to maintain stable output over a wide load range, thereby improving the overall performance and reliability of the power management chip.

[0064] Specifically, in this embodiment of the invention, the voltage regulator is fabricated using CR Microelectronics' 153nm 5V CMOS process, with a layout area of ​​290μm×238μm and a total device area of ​​0.069mm². Testing revealed the following: input voltage range of 3.3V-6V, output voltage range of 1.8V-3.3V, supporting precise configuration in 0.1V steps, with an output voltage accuracy of ±0.05V, meeting the 0.1V accuracy requirement of electronic products; maximum output current of 500mA, maximum voltage drop of 200mV; quiescent current of 26.2μA; output noise density of 454.6nV / √Hz at 1kHz, and integral noise of 52μVrms from 300Hz to 50kHz; load regulation of 0.136V / A, and line regulation of 10.8mV / V; phase margin exceeding 42% across the entire load range, ensuring loop stability. The same wafer can be programmed with efuse to achieve 16 different output voltage configurations without increasing the layout area. It has strong compatibility and can achieve high integration of voltage regulators and low-noise structural design.

[0065] The highly integrated voltage regulator proposed in this embodiment of the invention, by setting a second feedback resistor with an efuse adjustment array, can achieve a combination ratio of various output resistors based on the efuse device, without adding additional circuit structure design, and can meet the resistance ratio requirements of various voltage output configurations, thereby improving the integration of the voltage regulator.

[0066] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.

[0067] Furthermore, the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A highly integrated voltage regulator, characterized in that, The voltage regulator includes: a bias circuit, a first-stage error amplifier, a second-stage error amplifier, a dynamic Miller compensation circuit, an adjustment transistor module, and a feedback resistor network; The output terminal of the bias circuit is electrically connected to the bias terminal of the first-stage error amplifier and the bias terminal of the second-stage error amplifier, respectively. The non-inverting input terminal of the first-stage error amplifier is electrically connected to the reference voltage, the inverting input terminal of the first-stage error amplifier is electrically connected to the feedback voltage, and the output terminal of the first-stage error amplifier is electrically connected to the input terminal of the second-stage error amplifier. The output of the second-stage error amplifier is electrically connected to the control terminal of the adjustment tube module, and the dynamic Miller compensation circuit is connected between the input and output terminals of the second-stage error amplifier. The output terminal of the regulating tube serves as the output terminal of the voltage regulator and is also electrically connected to the input terminal of the feedback resistor network. The feedback resistor network includes a first feedback resistor, a second feedback resistor, and an efuse tuning array. The first feedback resistor and the second feedback resistor are connected in series between the output terminal and the ground port. The intermediate node between the first feedback resistor and the second feedback resistor is electrically connected to the inverting input terminal of the first-stage error amplifier.

2. The highly integrated voltage regulator as described in claim 1, characterized in that, The second feedback resistor is composed of several basic resistors connected in series, and an efuse device is connected in parallel across each of the basic resistors.

3. The highly integrated voltage regulator as described in claim 1, characterized in that, The voltage regulator also includes a voltage reference module, which is configured as a depletion enhancement-mode MOSFET complementary voltage structure. The output of the voltage reference module is electrically connected to the non-inverting input of the first-stage error amplifier.

4. The highly integrated voltage regulator as described in claim 3, characterized in that, The depletion-enhanced MOSFET complementary voltage structure includes a depletion-mode MOSFET, an enhancement-mode MOSFET, a current mirror, and a fine-tuning resistor array; The drain of the depletion-type MOS transistor is connected to the drain of the first MOS transistor of the current mirror MOS transistor, the gate of the depletion-type MOS transistor is grounded, and the source of the depletion-type MOS transistor is grounded through an on-chip integrated fine-tuning resistor array. The enhancement-mode MOSFET adopts an on-chip integrated diode connection method, the source of the enhancement-mode MOSFET is grounded, and the drain of the enhancement-mode MOSFET is connected to the drain of the second MOSFET of the current mirror MOSFET. The power supply terminal is integrated within the source terminal of the first MOS transistor in the current mirror. The gate and drain of the first MOS transistor are connected and are also connected to the drain of the depletion-type MOS transistor.

5. The highly integrated voltage regulator as described in claim 1, characterized in that, The bias circuit includes: a twelfth MOSFET, a thirteenth MOSFET, and a fourteenth MOSFET; The thirteenth MOS transistor and the fourteenth MOS transistor form a first current mirror structure. The sources of the thirteenth MOS transistor and the fourteenth MOS transistor are electrically connected to the power input terminal, and the gates of the thirteenth MOS transistor and the fourteenth MOS transistor are shorted. The source of the twelfth MOS transistor is connected to the power input terminal, the gate of the twelfth MOS transistor is connected to the drain of the fourteenth MOS transistor, and the drain of the twelfth MOS transistor outputs a first bias voltage.

6. The highly integrated voltage regulator as described in claim 5, characterized in that, The bias circuit also includes a tenth MOSFET, an eleventh MOSFET, a first resistor, and a second resistor; The gate of the tenth MOS transistor is shorted to the gate of the eleventh MOS transistor, and the gate of the tenth MOS transistor is shorted to the drain of the tenth MOS transistor, forming a second current mirror structure. The drain of the tenth MOS transistor is connected to the drain of the thirteenth MOS transistor, the source of the tenth MOS transistor is connected to one end of the first resistor, and the other end of the first resistor is grounded. The drain of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor, the source of the eleventh MOS transistor is connected to one end of the second resistor, the other end of the second resistor is grounded, and the connection node between the second resistor and the source of the eleventh MOS transistor outputs a second bias voltage. The first bias voltage is electrically connected to the bias terminal of the first-stage error amplifier, and the second bias voltage is electrically connected to the bias terminal of the second-stage error amplifier.

7. The highly integrated voltage regulator as described in claim 1, characterized in that, The first-stage error amplifier includes a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, and a first compensation capacitor; The gate of the first MOSFET is electrically connected to the reference voltage, the gate of the second MOSFET is electrically connected to the feedback voltage, and the sources of the first MOSFET and the second MOSFET are connected to the drain of the fifth MOSFET. The gates of the third MOS transistor and the fourth MOS transistor are shorted, the sources of the third MOS transistor and the fourth MOS transistor are grounded, the drain of the third MOS transistor is electrically connected to the drain of the first MOS transistor, and the drain of the fourth MOS transistor is electrically connected to the drain of the second MOS transistor. One end of the first compensation capacitor is electrically connected to the drain connection node of the first MOS transistor and the third MOS transistor, and the other end of the first compensation capacitor is grounded.

8. The highly integrated voltage regulator as described in claim 1, characterized in that, The second-stage error amplifier includes: a sixth MOSFET, a seventh MOSFET, and an eighth MOSFET; The gate of the sixth MOS transistor serves as the input terminal of the second-stage error amplifier, and the gate of the sixth MOS transistor is electrically connected to the output terminal of the first-stage error amplifier. The source of the sixth MOS transistor is grounded. The source of the seventh MOS transistor is electrically connected to the power input terminal, and the gate of the seventh MOS transistor is electrically connected to the first bias voltage. The source of the eighth MOS transistor is electrically connected to the power input terminal, the gate of the eighth MOS transistor is electrically connected to the second bias voltage, and the drain of the eighth MOS transistor is electrically connected to the drain of the sixth MOS transistor. The drain connection node of the sixth MOS transistor and the eighth MOS transistor is set as the output terminal of the second-stage error amplifier and electrically connected to the gate of the adjustment transistor module, so as to output the amplified error signal to the adjustment transistor module.

9. The highly integrated voltage regulator as described in claim 8, characterized in that, The dynamic Miller compensation circuit includes a second compensation capacitor, a series resistor, and a dynamic attenuation resistor. The second compensation capacitor and the series resistor are connected in series between the gate and drain of the sixth MOS transistor; The dynamic attenuation resistor is connected in series between the drain of the eighth MOS transistor and the output of the second-stage error amplifier.

10. The highly integrated voltage regulator as described in claim 1, characterized in that, The voltage regulator also includes a pseudo-ESR compensation and feedforward circuit, which includes a pseudo-ESR compensation resistor, a third compensation capacitor, and a feedforward transistor. The pseudo-ESR compensation resistor and the third compensation capacitor are connected in series across the two ends of the second feedback resistor; The gate of the feedforward transistor is electrically connected to a first bias voltage, and the source and drain of the feedforward transistor are connected in parallel across the third compensation capacitor.

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