Processor scheduling method and apparatus

Abstract

The application discloses a processor scheduling method and device, and belongs to the technical field of electronic equipment. The method comprises the following steps: obtaining the job cycles of a plurality of tasks to be scheduled; determining the load evaluation window duration corresponding to each task according to the job cycles; taking the load evaluation window duration as a statistical period, respectively performing load statistics on the tasks with the same load evaluation window duration to obtain the aggregated load values corresponding to each load evaluation window duration; and determining the target working frequency of a processor according to the aggregated load values corresponding to all load evaluation window durations.

Description

Technical Field

[0001] This application belongs to the field of electronic equipment technology, specifically relating to a processor scheduling method and apparatus. Background Technology

[0002] As mobile applications become increasingly complex, system-on-chips (SoCs) in electronic devices commonly adopt heterogeneous multi-core architectures and dynamically allocate computing power through dynamic voltage and frequency scaling (DVFS) modules and task schedulers to balance performance and energy efficiency. However, in "mixed frame rate concurrency" scenarios, such as when a user performs a 30fps camera preview while simultaneously engaging in a 120Hz touch operation, the system simultaneously contains long-cycle, computationally intensive tasks and short-cycle, bursty tasks. The different computing power requirements of these two tasks pose a significant challenge to traditional scheduling methods.

[0003] The scheduling methods in related technologies typically employ a fixed load assessment strategy: using a load observation window of a fixed length, such as 20ms, within which the task scheduler calculates the percentage of busy time for the central processing unit (CPU) and uses this as a single indicator to measure system load; subsequently, the scheduler directly uses this historical average load value to predict future demand and drives the DVFS module to set the CPU's operating frequency.

[0004] However, this scheduling method based on a fixed load observation window is difficult to adapt to the different rhythms of mixed tasks: on the one hand, if the observation window is set too long to match low-frequency tasks such as camera work, it cannot accurately capture the instantaneous load changes of the user interface (UI) rendering, resulting in an inability to respond to sudden demands for UI operations in a timely manner, causing operational lag; on the other hand, if the observation window is set too short to keep up with the high-frequency rhythm of the UI, it will misjudge the continuous load of camera tasks, causing invalid spikes and drops in CPU frequency, resulting in significant power waste. This contradiction of "long window leads to lag, short window leads to power consumption" has become a key bottleneck affecting the smooth experience and battery life of electronic devices. Summary of the Invention

[0005] The purpose of this application is to provide a processor scheduling method and apparatus that can solve the performance and power consumption imbalance caused by the mismatch between fixed window and mixed load.

[0006] In a first aspect, embodiments of this application provide a processor scheduling method, the method comprising: Obtain the job cycle of each of the multiple tasks to be scheduled; Based on the job cycle, determine the load assessment window duration for each task; Using the load assessment window duration as the statistical period, load statistics are performed on the tasks with the same load assessment window duration to obtain the aggregated load value corresponding to each load assessment window duration. The target operating frequency of the processor is determined based on the aggregated load value corresponding to the duration of all load assessment windows.

[0007] Secondly, embodiments of this application provide a processor scheduling apparatus, the apparatus comprising: The acquisition module is used to acquire the job cycle of each of the multiple tasks to be scheduled. The first determining module is used to determine the load assessment window duration for each task based on the job cycle. The statistics module is used to perform load statistics on the tasks with the same load assessment window duration, using the load assessment window duration as the statistical period, and to obtain the aggregate load value corresponding to each load assessment window duration. The second determining module is used to determine the target operating frequency of the processor based on the aggregated load value corresponding to the duration of all load evaluation windows.

[0008] Thirdly, embodiments of this application provide an electronic device, which includes a processor and a memory. The memory stores programs or instructions that can run on the processor, and when the programs or instructions are executed by the processor, they implement the steps of the processor scheduling method as described in the first aspect.

[0009] Fourthly, embodiments of this application provide a computer-readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the processor scheduling method as described in the first aspect.

[0010] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the processor scheduling method as described in the first aspect.

[0011] In a sixth aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the processor scheduling method as described in the first aspect.

[0012] In this embodiment, the job cycles of multiple tasks to be scheduled are obtained; the load assessment window duration corresponding to each task is determined according to the job cycle; the load assessment window duration is used as the statistical period, and the load is statistically analyzed for tasks with the same load assessment window duration to obtain the aggregate load value corresponding to each load assessment window duration; the target operating frequency of the processor is determined according to the aggregate load value corresponding to all load assessment window durations.

[0013] As can be seen, in this embodiment of the application, by identifying and distinguishing the job cycle characteristics of different tasks, allocating appropriate load assessment windows to each task, and performing independent load statistics and multi-window fusion decision-making for tasks with the same load assessment window, it is possible to simultaneously and accurately meet the energy efficiency and stability requirements of low-frequency tasks and the instantaneous response requirements of high-frequency tasks. This solves the performance and power consumption imbalance problem caused by the mismatch between fixed windows and mixed loads, thereby improving the overall energy efficiency and user experience of electronic devices in complex concurrent scenarios. Attached Figure Description

[0014] Figure 1 This is a flowchart of a processor scheduling method provided by some embodiments of this application; Figure 2 This is a flowchart of one implementation of S101 provided in some embodiments of this application; Figure 3 This is an example diagram of one implementation of S102 provided in some embodiments of this application; Figure 4 This is a flowchart of one implementation of S103 provided in some embodiments of this application; Figure 5 This is one of the example diagrams illustrating the effect of the processor scheduling method provided in some embodiments of this application; Figure 6 This is the second example diagram illustrating the effect of the processor scheduling method provided in some embodiments of this application; Figure 7 This is a structural block diagram of a processor scheduling device provided in some embodiments of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in some embodiments of this application; Figure 9 This is a schematic diagram of the hardware structure of an electronic device that implements the various embodiments of this application. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0016] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0017] Scheduling methods in related technologies typically employ a statistical strategy of a "single fixed load observation window." This means the task scheduler presets a load observation window of a fixed length, such as 20ms, and calculates the percentage of busy CPU time within this window, using this as the basis for calculating the target frequency for the next moment. However, this method of using a single fixed load observation window to handle mixed frame rate services cannot balance power consumption and performance.

[0018] On the one hand, setting a longer load observation window to adapt to low frame rate tasks, such as camera previews with a period of about 33ms (corresponding to 30fps), can smooth out load fluctuations and improve energy efficiency. However, for concurrent high frame rate burst tasks such as UI rendering with a period of only about 8.3ms (corresponding to 120Hz), the response speed of a long window is too slow. When UI tasks burst, the task scheduler cannot respond in time based on the slow average load statistics of the long historical window, resulting in a lag in CPU frequency increase and causing frame drops and operation stuttering in the first few frames of UI rendering due to insufficient computing power.

[0019] On the other hand, setting a shorter load observation window to suit high frame rate tasks, such as UI rendering, allows for more sensitive responses and helps avoid stuttering. However, for camera preview tasks with a cycle of approximately 33ms, if the continuous computational load of a single frame is observed within an 8ms short window, it will be misinterpreted as a continuous, extremely high load peak, triggering a sudden spike in CPU frequency to an unnecessarily high point. Subsequently, during the actual execution of the camera task, the frequency will quickly drop back due to the sudden decrease in load within the short window. This violent fluctuation in CPU frequency caused by misinterpretation not only fails to improve task execution efficiency but also results in significant power consumption waste and heat generation as the processor frequently operates outside its high energy efficiency range.

[0020] To address the aforementioned technical problems, embodiments of this application provide a processor scheduling method and apparatus.

[0021] The processor scheduling method provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0022] Figure 1 This is a flowchart of a processor scheduling method provided by some embodiments of this application, such as... Figure 1 As shown, the method may include the following steps: S101, S102, S103 and S104.

[0023] In S101, the job cycles of the multiple tasks to be scheduled are obtained. In this embodiment, the multiple tasks to be scheduled refer to a set of multiple software task instances that are in the ready queue or are being executed on the processor at any scheduling moment during the operation of the electronic device. The tasks in this set usually have different periodic characteristics and their job cycles are different, thus constituting a concurrent workload scenario of "mixed frame rate" or "mixed cycle".

[0024] In this embodiment, the job cycle refers to the time interval during which a task is periodically triggered or awakened for execution, and is an inherent temporal attribute of the task. For example, the job cycle of a 30fps video processing task is approximately 33.3ms, and the job cycle of a 120Hz UI rendering task is approximately 8.3ms.

[0025] In this embodiment of the application, by obtaining the job cycles of each of the multiple tasks to be scheduled, a classification basis is provided for subsequent differentiated scheduling.

[0026] In some embodiments, differentiated acquisition strategies can be adopted based on whether the task's periodicity attribute is known or not. Specifically, the job period acquisition process may include two branch paths, such as... Figure 2 As shown, the above S101 may specifically include the following steps: S1011 and S1012.

[0027] In S1011, for a task with a known work cycle, the preset cycle value of the task is obtained as the work cycle.

[0028] In this embodiment, for tasks with a known fixed trigger period, a preset period value can be directly read from its software configuration, task descriptor, or system metadata as its job period. Such tasks are typically explicitly registered for periodicity by the operating system or application during creation.

[0029] For example, the camera image signal processing (ISP) pipeline thread is typically woken up at a fixed period synchronized with the camera frame rate, such as approximately 33.3ms for 30fps. The audio playback or recording thread's work cycle is determined by the audio sampling rate and buffer size, such as processing one frame of audio data every 10ms. Timer-triggered system background tasks, such as log uploading and status synchronization, have preset fixed execution intervals.

[0030] In this embodiment of the application, by directly reading the preset periodic parameters, the periodic characteristics of such tasks can be obtained efficiently and accurately, providing a reliable basis for subsequent differentiated scheduling.

[0031] In S1012, for a task with an unknown work cycle, the timestamp sequence of the task during multiple consecutive wake-ups is collected, and the coefficient of variation of the wake-up interval corresponding to the timestamp sequence is calculated. If the coefficient of variation is less than or equal to a preset threshold, the task is determined to be a periodic task, and the average value of the wake-up interval is determined as the work cycle of the task.

[0032] In this embodiment of the application, for tasks with unknown periodicity, the work cycle is determined by a dynamic periodicity detection process. Specifically, the timestamps of the task during multiple consecutive effective wake-ups are collected, the periodicity is determined by analyzing the stability of the wake-up time interval, and the average interval is calculated as the work cycle after the task is determined to be a periodic task.

[0033] In this embodiment, the coefficient of variation is used as the core indicator for periodicity determination. This indicator is the ratio of the standard deviation to the mean, which is a dimensionless relative volatility. It can eliminate the influence of the length of the task's own period on the absolute value of the fluctuation, thereby allowing the use of a uniform stability threshold such as 0.15 to more accurately determine the regularity of tasks with different periods, from milliseconds to hundreds of milliseconds, thus improving the robustness and adaptability of the periodicity detection algorithm.

[0034] Optionally, the above dynamic periodic detection process specifically includes the following steps: S10121 and S10122.

[0035] In S10121, valid wake-up event collection and filtering are performed.

[0036] To avoid misjudging transient scheduling caused by system noise, minor interruptions, or lightweight background activities as core business activities of a task, this application introduces a computing power consumption filtering mechanism. Specifically, at the start and end times of each scheduled task execution, the hardware performance counter of the processor core is read, and the difference between the two readings is calculated. This difference represents the number of processor cycles consumed by the task execution, denoted as the actual cost of this execution. Subsequently, the calculated cost is compared with a pre-set computing power threshold. If the cost is lower than the threshold, the wake-up is considered to have not performed any substantial computational work and is considered an invalid jitter, which is ignored and not recorded. If the cost is higher than or equal to the threshold, it is determined to be a valid wake-up, indicating that the task executed core logic with sufficient computing power consumption. At this time, a high-precision timestamp of the wake-up is recorded. This step ensures that the data used for subsequent cycle analysis originates from the critical load phase of the task, thereby improving the accuracy and robustness of cycle detection at the source.

[0037] In S10122, periodic determination and periodic calculation are performed.

[0038] Once a preset number (e.g., 8) of valid wake-up timestamps have been collected, a periodic determination calculation is automatically triggered. The absolute timestamp sequence arranged in chronological order is converted into a relative time interval sequence reflecting the task triggering rhythm, and its periodicity is determined by evaluating the stability of this interval sequence. Specifically: First, generate the interval sequence: Assume that M valid timestamps have been collected sequentially, denoted as t1, t2, ..., t M By sequentially calculating the difference between adjacent timestamps, a sequence Δ1, Δ2, ..., Δ is obtained, consisting of M-1 time intervals. M 1, where each interval Δ i =t i+1 t i .

[0039] Next, calculate the statistic: calculate the arithmetic mean of the interval series. This value characterizes the central tendency of task wake-up intervals and can be used as a hypothetical periodic baseline. The standard deviation of the interval sequence is calculated. This value quantitatively describes the absolute fluctuation range of each interval from the average value.

[0040] Finally, periodicity was determined: To further eliminate the influence of the absolute value of the period on the perceived fluctuation, the coefficient of variation K was calculated. This coefficient is a dimensionless statistic that reflects the relative volatility of the interval data. The calculated coefficient of variation K is then compared with a preset stability tolerance threshold. Comparison, for example, =0.15, meaning a relative fluctuation of 15% is allowed. If K≤ If the task wake-up exhibits good periodicity, it is determined to be a periodic task. At this point, the calculated average interval... Determine the task's work cycle. If K > If the wake-up interval fluctuates too much and lacks stable periodicity, the currently collected data set is invalid. The timestamp of this set will be cleared or ignored, and the process will return to step S10121 to continue collecting new valid wake-up events until the judgment condition is met again.

[0041] In this embodiment of the application, the above process can intelligently and accurately identify the real periodic tasks from noisy scheduling events and quantify their period, providing reliable and accurate input for subsequent adaptive scheduling based on task period.

[0042] For example, M=8, =0.15, and 8 valid wake-up timestamps were collected: [100, 110, 120, 131, 140, 149, 160, 170], in ms. First, the interval sequence was calculated: [10, 10, 11, 9, 9, 11, 10]. Then, the average interval was calculated. =10ms, standard deviation σ≈0.756ms. Then, the coefficient of variation K≈0.0756 is calculated. Finally, K is compared with... Based on the magnitude relationship, since 0.0756 < 0.15, the task is determined to be a periodic task with a job cycle of 10ms.

[0043] As can be seen, in this embodiment, the combination of dynamic and static methods takes into account both accuracy and flexibility, and can adapt to unknown or dynamically changing task loads.

[0044] In S102, the load assessment window duration for each task is determined based on the job cycle.

[0045] In this embodiment, the load assessment window duration refers to the length of the time window used by the task scheduler to observe and statistically analyze the load of a task (or task group). This duration is related to the task's job cycle, rather than being a fixed value.

[0046] In the embodiments of the present application, by adaptively allocating an appropriate load evaluation window duration for each task according to its job cycle, an accurate conversion from the inherent characteristics of the task to the scheduling policy parameters is achieved. On the one hand, it realizes customized load observation: allocating a longer window for long-cycle tasks to fully observe their overall load and smooth fluctuations, thereby optimizing energy efficiency; allocating a shorter window for short-cycle tasks to keenly capture their load mutations and respond quickly, thereby ensuring fluency. On the other hand, tasks with the same window duration are classified into the same logical group, thus creating a structural prerequisite for subsequent efficient unified load statistics and aggregation calculations within the group.

[0047] In some embodiments, the job cycle of the task can be mapped to a set of predefined discrete duration gears. Specifically, the above S102 may include the following steps: S1021.

[0048] In S1021, for each task, map the job cycle of the task to the largest gear in a predefined set of discrete duration gears that is not greater than the job cycle; determine the value of the mapped discrete duration gear as the load evaluation window duration corresponding to the task.

[0049] In the embodiments of the present application, the floor matching rule is adopted: map the job cycle to the longest gear that is not greater than the cycle.

[0050] In the embodiments of the present application, the predefined set of discrete duration gears is set to {4ms, 8ms, 16ms, 32ms}.

[0051] Exemplarily, the job cycle of the task is denoted as T. As Figure 3 shown, if 0 < T < 8ms, it is classified into the 4ms discrete duration gear; if 8 ≤ T < 16ms, it is classified into the 8ms discrete duration gear; if 16 ≤ T < 32ms, it is classified into the 16ms discrete duration gear; if T ≥ 32ms, it is classified into the 32ms discrete duration gear.

[0052] In the embodiments of the present application, the above gear design accurately matches the frame rate cycle characteristics of mainstream mobile applications: the 4ms gear can adapt to the 240Hz ultra-high refresh rate interaction, the 8ms gear corresponds to the 120Hz high refresh rate scenario, the 16ms gear covers the 60Hz baseline refresh rate, and the 32ms gear is compatible with typical low-frequency loads such as 30fps video processing. This design enables the device to use limited and fixed hardware resource configurations to efficiently cover the full-scenario task cycle range from extremely high-frequency interactions to low-frequency calculations. In summary, the gear design of {4ms, 8ms, 16ms, 32ms} is not randomly selected, but is the optimal balance point achieved among accuracy, hardware cost, and scheduling efficiency after in-depth analysis of mobile load characteristics.

[0053] For example, several predefined discrete duration levels are {4ms, 8ms, 16ms, 32ms}. For camera tasks with a 33ms job cycle, they are mapped to a 32ms load assessment window. This utilizes the faster scheduling pace of 32ms to accommodate the actual needs of 33ms, ensuring that image processing speed is always slightly faster than video stream generation speed, thus effectively preventing dropped frames or stuttering. For UI tasks with an 8ms job cycle, they are mapped to an 8ms load assessment window. For background services with a 17ms job cycle, they are mapped to a 16ms load assessment window.

[0054] As can be seen, in this embodiment, the "round-down matching" rule maps the task's work cycle to the largest predefined discrete level that is no larger than that cycle. This fundamentally ensures scheduling safety: the load assessment window allocated to the task is less than or equal to its actual work cycle, thus guaranteeing that the scheduler's assessment and response rhythm is always no slower than the task's own demand rhythm, avoiding task timeouts, frame drops, or stuttering due to response delays. Secondly, this rule enhances the predictability and stability of the device. By using a fixed mapping direction, it eliminates the potential for drastic changes in window duration and scheduling strategy caused by fluctuations in task cycle at level boundaries, effectively suppressing unnecessary performance and power consumption oscillations and providing a more stable foundation for energy efficiency optimization. Finally, this rule is logically simple and deterministic, with extremely low computational overhead and easy hardware implementation, meeting the stringent requirements of mobile devices for real-time performance and low power consumption.

[0055] In S103, the load assessment window duration is used as the statistical period. For tasks with the same load assessment window duration, load statistics are performed separately to obtain the aggregated load value corresponding to each load assessment window duration.

[0056] In this embodiment, the basic observation unit for load statistics is changed from the traditional "fixed duration" to a "load evaluation window duration" that dynamically matches the task's own work cycle. This design achieves adaptive alignment between the observation rhythm and the task rhythm, enabling the statistics window to intelligently adapt to the working characteristics of different tasks: a short window is allocated for high frame rate tasks such as UI rendering to capture instantaneous changes with high temporal resolution and ensure response speed; a long window is allocated for low-frequency tasks such as camera processing to observe the overall trend with sufficient historical depth and ensure stable decision-making.

[0057] In this embodiment, tasks with the same load assessment window duration are considered as a task group. For each task group, the system obtains the load contribution of all tasks within the group within the most recent full window duration (i.e., the corresponding load assessment window duration), performs accumulation and comprehensive calculation (such as weighted averaging), and finally generates an independent aggregated load value for each group that is adapted to its rhythm. This value represents the overall load level of the tasks in the group under the corresponding rhythm.

[0058] The following examples illustrate this mechanism: In scenario example 1, the tasks in the two different windows are as follows: Task A: Camera processing, 32ms window; Task B: UI rendering, 8ms window.

[0059] After grouping and statistical analysis, two task groups were formed: 32ms task group: Contains only task A. The system accumulates the load of task A within the last 32ms to obtain L. 32 ; 8ms task group: contains only task B. The system accumulates the load of task B in the last 8ms to obtain L8.

[0060] Finally, output load metrics: { L 32 , L8}.

[0061] In scenario example 2, the tasks in the three different windows are as follows: Task A: Camera processing, 32ms window; Task B: Background synchronization, 16ms window; Task C: UI rendering, 8ms window.

[0062] After grouping and statistical analysis, three task groups were formed: 32ms task group: Contains only task A. The system accumulates the load of task A within the last 32ms to obtain L. 32 ; 16ms group: Includes only task B. The system accumulates the load of task A within the last 16ms to obtain L. 16 ; 8ms task group: contains only task C. The system accumulates the load of task C in the last 8ms to obtain L8.

[0063] Finally, output load metrics: { L 32 , L 16 , L8}.

[0064] In scenario example 3, the tasks of the four different windows are as follows: Task A: Camera processing, 32ms window; Task B: Game logic, 16ms window; Task C: Touch response, 8ms window; Task D: Sensor processing, 4ms window; After grouping and statistical analysis, four task groups were formed, namely: 32ms task group: Contains only task A. The system accumulates the load of task A within the last 32ms to obtain L. 32 ; 16ms group: Includes only task B. The system accumulates the load of task A within the last 16ms to obtain L. 16 ; 8ms task group: contains only task C. The system accumulates the load of task C in the last 8ms to obtain L8. 4ms task group: contains only task D. The system accumulates the load of task D in the last 4ms to obtain L4.

[0065] Finally, the output load metric is: {L 32 , L 16 , L8, L4}.

[0066] In scenario example 4, two of the four tasks have the same window, namely: Tasks A1 and A2: Both are video decoding, 32ms window; Task B: UI rendering, 8ms window; Task C: Audio playback, 16ms window.

[0067] After grouping and statistical analysis, three task groups were formed: 32ms task group: Includes tasks A1 and A2. The system accumulates the total load of tasks A1 and A2 within the most recent 32ms, and obtains L. 32 ; 16ms task group: Contains only task C. The system accumulates the load of task C within the last 16ms to obtain L. 16 ; 8ms task group: contains only task B. The system accumulates the load of task B in the last 8ms to obtain L8.

[0068] Finally, output load metrics: { L 32 , L 16 , L8}.

[0069] In this embodiment, the grouping is based on the load assessment window duration, rather than the number of tasks or application type. The loads of multiple tasks within the same group are accumulated before statistical analysis and processed as a whole. The system ultimately generates an aggregated load value for each existing window duration. This mechanism ensures that the scheduler can comprehensively perceive the load status of task groups with different rhythms using the most concise set of load metrics.

[0070] In some embodiments, such as Figure 4 As shown, the above S103 may specifically include the following steps: S1031, S1032, S1033 and S1034.

[0071] In S1031, load statistics are performed with a fixed basic sampling period. Within each basic sampling period, the normalized load contribution value of each task within the basic sampling period is determined based on the effective execution time of each task on the processor and the computing power capacity of the processor during the effective execution time.

[0072] In this embodiment, the basic sampling period is the fundamental time unit for the system to perform load statistics; it is a fixed, periodic time interval. All load data collection, calculation, and updates are performed synchronously at this rhythm.

[0073] Optionally, in some embodiments, the base sampling period is 4ms. That is, the system samples the CPU load at a high speed with a 4ms interval. This period first precisely matches and exceeds the current highest display refresh rate requirement of 240Hz, ensuring zero-latency perception of extreme instantaneous interactions. Second, it forms a strict integer multiple relationship with preset load assessment window levels (4ms, 8ms, 16ms, 32ms), eliminating statistical phase deviation and simplifying the calculation of all window lengths. Furthermore, this period achieves an optimal balance between responsiveness and stability: for high-frequency tasks, it provides sufficient sampling density to capture critical mutations; for low-frequency tasks, it provides ample sample points for deep filtering. Finally, the 4ms period is highly compatible with mainstream hardware timers and operating system scheduling ticks, ensuring low-cost integration and high engineering feasibility of this solution. Therefore, the 4ms base sampling period is the optimal time benchmark established after a thorough consideration of scheduling accuracy, computational complexity, and system overhead, providing a reliable, efficient, and universal timing framework for the entire multi-layer load statistics system.

[0074] In this embodiment of the application, the effective execution time refers to the time that a task actually occupies the processor (CPU) core to execute instructions within a basic sampling period, excluding the time it spends in a sleep, waiting, or ready state.

[0075] In this embodiment, computing power capacity is a normalized representation of the computing power that the processor core can provide at its current operating frequency within the time period corresponding to the aforementioned effective execution time. The higher the frequency, the greater the computing power capacity value.

[0076] In this embodiment, the normalized load contribution value is a standardized measure of the computational load generated by a task within a single basic sampling period. Specifically, the normalized load contribution value C of a task within a single basic sampling period can be calculated according to the following formula: C = (computing capacity × effective execution time) / basic sampling period duration. This formula considers not only "how long the task ran" but also "at what performance level it ran," thereby fairly measuring the actual load pressure of different tasks at different CPU frequencies.

[0077] For example, if the basic sampling period is 4ms, and task A actually runs for 2ms within a certain 4ms period, during which the computing power capacity corresponding to the CPU frequency is 200, then the normalized load contribution value C of task A in that period is... A =(200×2ms) / 4ms=100.

[0078] In this embodiment, by calculating the normalized load contribution value, a fair load measurement benchmark is established. This calculation model eliminates the inherent measurement bias caused by CPU dynamic frequency scaling (DVFS), ensuring that the actual computing load generated by tasks executing for the same amount of time at different processor operating frequencies can be accurately quantified and distinguished. For example, tasks running at high frequencies consume more theoretical computing power, so their load contribution value will increase accordingly, thus providing a fair and consistent comparison basis for scheduling decisions. On the other hand, atomic load data units are generated. The contribution value of each task in each basic sampling period is used as an independent, accurate, and linearly accumulative basic data point, providing standardized and high-precision data input for subsequent cross-task aggregation, time series analysis, and window-level fusion calculation.

[0079] In S1032, determine the number N of continuous basic sampling periods contained in the statistical period corresponding to each load assessment window duration.

[0080] In this embodiment of the application, the number of complete base sampling periods contained in each load assessment window will be determined.

[0081] In this embodiment, N is an integer positively correlated with the duration of the load assessment window, where N = duration of the load assessment window / basic sampling period.

[0082] For example, if the base sampling period is 4ms, then for an 8ms load assessment window, N = 8ms / 4ms = 2. For a 32ms load assessment window, N = 32ms / 4ms = 8.

[0083] In this embodiment, the scheduling strategy of load assessment window is transformed into the specific operation of "how many historical sampling points need to be traced back", which is a key bridge connecting static configuration and dynamic calculation. In S1033, for each load assessment window duration, the sum of the normalized load contribution values ​​of all tasks with the same load assessment window duration in each of the most recent N consecutive basic sampling periods is calculated to obtain the total load of the N periods within the load assessment window duration.

[0084] In this embodiment, at the end of each basic sampling period, the system accumulates the normalized load contribution values ​​calculated by each task belonging to the same task group within the current period to obtain a periodic load snapshot of the task group at the current sampling time. This snapshot represents the overall load level of the task group within a single sampling period. For a given load assessment window, by traversing its corresponding N most recent consecutive basic sampling periods, a time-series data sequence [S1, S2, ..., S] consisting of N periodic load snapshots can be obtained. N ], where S1 represents the total load in the most recent sampling period, S N This indicates the total load of the furthest sampling period.

[0085] For example, assuming a base sampling period of 4ms, within a certain sampling period, the normalized contribution value C of task A (belonging to a certain group) is... A =100, the normalized contribution value C of task B in the same group. B =18.75, then the total periodic load of this group in the current basic sampling period is S=C A +C B =118.75.

[0086] In S1034, the total load of N cycles within the load assessment window is weighted and calculated according to the weighting strategy corresponding to the load assessment window duration, so as to obtain the aggregated load value corresponding to the load assessment window duration.

[0087] In this embodiment, the weighting strategy is embodied in a set of weight coefficients [W1, W2, ..., W] bound to the load assessment window duration. N ], used for the periodic load total sequence [S1, S2, ..., S N Weighted fusion is performed, where S1 represents the total load in the most recent basic sampling period, S... NThis represents the total load of the furthest (i.e., earliest) basic sampling period. By configuring differentiated weight distributions for windows of different durations, the system can extract load trend information that best matches the task characteristics of that window. The aggregated load value is a single scalar output obtained through this weighted calculation, which comprehensively represents the overall load level of the corresponding task group over the past full window duration.

[0088] Optionally, embodiments of this application provide a differentiated hierarchical weighted fusion strategy. Here, variable N represents the number of basic sampling periods contained in the sliding window, determined by the load assessment window duration (N = window duration / basic sampling period). Each task group is associated with a set of preset sampling point weights W. k In practical implementation, the following strategy is configured for typical window lengths: 4ms task group (N=1): The strategy is to directly use the most recent sampled value S1, i.e., the weight is 1, to achieve instantaneous load transfer without delay. 8ms task group (N=2): The strategy is to average the two most recent sampled values ​​S1 and S2 with equal weights, i.e., weight W1=W2=0.5, to achieve a balance between fast response and simple smoothness. 16ms task group (N=4): The strategy can adopt a differential weight configuration with heavy weights at both ends and light weights in the middle, for example, W1=W4=0.35, W2=W3=0.15. When performing head-to-tail weighting on the historical sequence (i.e., S1 and S4 are paired, S2 and S3 are paired), the newest and oldest data are given higher weights to enhance the sensitivity to changes in load trends; 32ms task group (N=8): The strategy adopts a "dumbbell-shaped" non-linear weighted distribution with high weights at the beginning and end and low weights in the middle. For example, W1=W8=0.2, W2=W3=...=W7=0.1. While the fluctuations within the deep smoothing period, the strategy takes into account both the system's memory of the long-term baseline load and its response to the latest load dynamics through the beginning and end of the significantly weighted sequence (S1 and S8).

[0089] To illustrate the calculation process, an example is provided below: Assume that the total periodic load sequence of each task group at a certain moment is shown in Table 1 (where S1 is the latest sampling point):

[0090] Table 1 The aggregate load value for each group is calculated as follows: 4ms group: L4 = S1 × 1.0 = 30 × 1.0 = 30.00; 8ms group: L8=(S1+ S2)×0.5=(10+15)×0.5=12.50; 16ms group: L 16=(S1+S4)×W1+(S2+S3)×W2=(45+25)×0.35+(15+20)×0.15= 29.75; 32ms group: L 32 =(S1+S8)×W1+(S2+S7)×W2+(S3+S6)×W3+(S4+S5)×W4=(115+50) ×0.2+(85+20)×0.1+(90+40)×0.1+(105+30)×0.1=70.00.

[0091] Through the aforementioned differentiated weighted fusion, a set of aggregated load values ​​{L4, L8, L...} that are clearly characterized and have stable trends are ultimately output. 16 , L 32 This provides high-quality input for subsequent frequency decisions.

[0092] As can be seen, in this embodiment, by configuring differentiated weighting strategies for different load assessment windows—for example, configuring a fast-response averaging strategy for short windows and a smoothing-focused nonlinear filtering strategy for long windows—targeted information extraction is achieved, thereby accurately extracting the load trend that best matches the rhythm characteristics of various tasks. This design effectively suppresses noise and smooths fluctuations. In particular, through the nonlinear weighting of long windows, it significantly filters out short-term load jitter caused by task phase switching or system interference, outputting a stable and predictable load representation, fundamentally avoiding frequency oscillations caused by misjudgment of jitter in traditional methods.

[0093] In S104, the target operating frequency of the processor is determined based on the aggregated load value corresponding to the duration of all load assessment windows.

[0094] In this embodiment, the task scheduler collects the aggregated load values ​​calculated from all task groups (i.e., all load assessment window durations) and merges them into a single overall computing power requirement index characterizing the system level. Subsequently, based on this overall computing power requirement index, the target operating frequency that the processor should achieve in the next working cycle is calculated. This target operating frequency is then sent to the Dynamic Voltage Frequency Scaling (DVFS) module for execution, thereby completing a full scheduling decision to simultaneously meet the performance requirements of tasks with different characteristics and optimize system energy efficiency.

[0095] In this embodiment, load information from different rhythm task groups is integrated, and the frequency decision made can take into account the needs of multiple parties at the same time. This achieves the global optimization of performance and energy efficiency in mixed load scenarios, fundamentally solving the pain points of stuttering, overheating, and rapid power consumption in mixed frame rate scenarios such as "playing games while recording screen" or "swiping while taking pictures", making electronic devices run more smoothly and have longer battery life.

[0096] In some embodiments, the above S104 may specifically include the following steps: S1041 and S1042.

[0097] In S1041, the sum of the aggregated load values ​​corresponding to all load assessment window durations is calculated to obtain the total load demand value.

[0098] In this embodiment of the application, the total load demand value is the fusion result of the aggregated load values ​​of the aforementioned independent task groups (divided according to different load evaluation windows), which is used to characterize the instantaneous total demand of all scheduled tasks in the system for processor computing power at the current scheduling moment.

[0099] In this embodiment, arithmetic summation is used as the fusion method. That is, the aggregated load values ​​corresponding to all load assessment window durations (such as 4ms, 8ms, 16ms, and 32ms) are directly added together, and the sum is the total system load demand value.

[0100] For example, if the aggregated load values ​​corresponding to the load assessment window durations are: 4ms: 30, 8ms: 12.5, 16ms: 29.75, and 32ms: 70, then the total load demand value = 30 + 12.5 + 29.75 + 70 = 142.25. This value is between 0 and the processor's maximum computing power capacity (e.g., 1024), and 142.25 indicates that the current system's total load accounts for approximately 13.89% of the maximum theoretical computing power.

[0101] In this embodiment, load information from different observation dimensions (windows of different lengths) is unified into a concise, global system-level load metric, providing direct input for the final one-dimensional frequency decision. Furthermore, the summation operation has extremely low computational complexity, introducing almost no additional scheduling latency and meeting real-time requirements. Simultaneously, since the aggregated load values ​​of each group already include weighting and smoothing of the task characteristics of that group, their sum can more comprehensively and stably characterize the overall system pressure, avoiding being misled by sudden loads of a single task or statistical fluctuations of individual groups.

[0102] In S1042, the target operating frequency of the processor is determined based on the total load demand, the maximum computing power capacity of the processor, and the processor operating frequency corresponding to the maximum computing power capacity.

[0103] In this embodiment, the maximum computing power capacity is used to represent the theoretical maximum computing power that the processor can provide at its maximum nominal operating frequency. For example, it is set to 1024 as a benchmark for load normalization.

[0104] In this embodiment of the application, the target operating frequency is the actual operating frequency that the scheduler sets for the processor's next operating cycle (the next basic scheduling cycle) and is expected to be achieved.

[0105] In this embodiment of the application, the target operating frequency can be calculated using the following formula: Target operating frequency = processor maximum nominal frequency × (1 + margin coefficient) × (total load requirement / maximum computing power capacity); The maximum nominal frequency of the processor, which is the processor operating frequency corresponding to the maximum computing power capacity, refers to the highest stable operating frequency supported by the CPU hardware, such as 2.4 GHz.

[0106] The margin factor is a constant greater than 0, such as 0.25, used to provide additional computing power buffer to prevent stuttering caused by a small delay in load estimation or a sudden surge in instantaneous tasks causing the CPU utilization to instantly reach 100%.

[0107] For example, with maximum computing capacity = 1024, maximum nominal frequency = 2.4 GHz, margin factor = 0.25, total load demand = 142.25, and target operating frequency = 2.4 × (1 + 0.25) × (142.25 / 1024) ≈ 0.417 GHz, the scheduler will instruct the dynamic voltage-frequency adjustment module to set the CPU frequency to approximately 0.417 GHz to handle the current load.

[0108] As can be seen, this application proposes an intelligent frequency decision mechanism that integrates proportional scaling and margin guarantee. By scaling the processor target frequency linearly with the real-time total system load, it achieves precise on-demand supply of computing power to optimize energy efficiency. At the same time, a preset performance margin is dynamically superimposed on the proportional result to build a dynamic buffer to cope with load estimation latency and instantaneous changes. Thus, it achieves optimal energy efficiency while ensuring an absolutely smooth experience, and solves the traditional contradiction between high performance and low power consumption in complex mixed load scenarios.

[0109] As can be seen from the above embodiments, in this embodiment, by identifying and distinguishing the job cycle characteristics of different tasks, a suitable load assessment window is allocated to each task, and independent load statistics and multi-window fusion decision are performed on tasks with the same load assessment window. This can simultaneously and accurately meet the energy efficiency and stability requirements of low-frequency tasks and the instantaneous response requirements of high-frequency tasks. It solves the performance and power consumption imbalance caused by the mismatch between fixed windows and mixed loads, thereby improving the overall energy efficiency and user experience of electronic devices in complex concurrent scenarios.

[0110] Through the determination logic (finer-grained load sampling) of the method provided in this application (hereinafter referred to as the method herein), the system can accurately identify load surges at the millisecond level, improving the response speed of frequency scheduling. This means that the CPU can instantly enter a high-performance state, making the user experience more responsive and smooth, eliminating latency. For example... Figure 5As shown, when the camera previews the scene (a 32ms cycle task), a UI rendering task (an 8ms cycle task) suddenly appears at 20ms. Our proposed method can respond to this task's load at 24ms, but traditional methods, due to their 16ms frequency scheduling cycle, can only respond at 32ms. The UI rendering task ends at 56ms, which our proposed method can also detect more quickly, allowing us to reduce the CPU frequency.

[0111] The method presented in this paper not only "fastly increases frequency," but also monitors the load of multi-cycle tasks to intelligently smooth CPU frequency and reduce CPU power consumption. For example... Figure 6 As shown, the scenario is set as follows: a single 32ms periodic task with a total cycle time of 32ms. The actual task load is strictly periodic, arriving at t=0ms, 32ms, 64ms… The task workload is fixed. The baseline is defined as 20ms execution time at a 1.5GHz frequency. The goal is to complete the task within 32ms without causing stuttering. The method presented in this paper uses a 4ms scheduling base cycle, with a maximum periodic task group of 32ms; the traditional method also uses a 4ms scheduling base cycle.

[0112] Traditional methods are easily misled by periodic idle periods, leading to incorrect frequency reduction due to zero historical load. The method proposed in this paper, however, achieves accurate prediction and frequency maintenance of periodic load trends through historical window smoothing, reducing CPU frequency fluctuations and enabling the same task to be handled at a more energy-efficient frequency, thus reducing CPU power consumption.

[0113] The processor scheduling method provided in this application can be executed by a processor scheduling device. This application uses the example of a processor scheduling device executing the processor scheduling method to illustrate the processor scheduling device provided in this application.

[0114] Figure 7 This is a structural block diagram of a processor scheduling device provided in some embodiments of this application, such as... Figure 7 As shown, the processor scheduling device 700 may include: an acquisition module 701, a first determination module 702, a statistics module 703, and a second determination module 704; The acquisition module 701 is used to acquire the job cycle of each of the multiple tasks to be scheduled; The first determining module 702 is used to determine the load assessment window duration for each task based on the job cycle. The statistics module 703 is used to perform load statistics on the tasks with the same load assessment window duration, using the load assessment window duration as the statistical period, to obtain the aggregate load value corresponding to each load assessment window duration. The second determining module 704 is used to determine the target operating frequency of the processor based on the aggregated load value corresponding to the duration of all load evaluation windows.

[0115] As can be seen from the above embodiments, in this embodiment, by identifying and distinguishing the job cycle characteristics of different tasks, a suitable load assessment window is allocated to each task, and independent load statistics and multi-window fusion decision are performed on tasks with the same load assessment window. This can simultaneously and accurately meet the energy efficiency and stability requirements of low-frequency tasks and the instantaneous response requirements of high-frequency tasks. It solves the performance and power consumption imbalance caused by the mismatch between fixed windows and mixed loads, thereby improving the overall energy efficiency and user experience of electronic devices in complex concurrent scenarios.

[0116] Optionally, as an embodiment, the acquisition module 701 is specifically used to acquire a preset cycle value of the task as the task cycle for a task with a known task cycle; for a task with an unknown task cycle, the module collects the timestamp sequence of the task during multiple consecutive wake-ups, calculates the coefficient of variation of the wake-up interval corresponding to the timestamp sequence, and if the coefficient of variation is less than or equal to a preset threshold, the module determines that the task is a periodic task and determines the average value of the wake-up interval as the task cycle.

[0117] Optionally, as an embodiment, the first determining module 702 is specifically used to map the job cycle of each task to the largest of a predefined plurality of discrete duration levels that is not greater than the job cycle; and to determine the value of the mapped discrete duration level as the load evaluation window duration corresponding to the task.

[0118] Optionally, as an embodiment, the statistics module 703 is specifically used to perform load statistics at a fixed basic sampling period. Within each basic sampling period, based on the effective execution time of each task on the processor and the computing power capacity of the processor during the effective execution time, the normalized load contribution value of each task within the basic sampling period is determined; the number N of consecutive basic sampling periods included in the statistical period corresponding to each load evaluation window duration is determined; for each load evaluation window duration, the sum of the normalized load contribution values ​​of all tasks with the same load evaluation window duration in the most recent N consecutive basic sampling periods is calculated to obtain the total load of the N periods within the load evaluation window duration; and the total load of the N periods within the load evaluation window duration is weighted according to the weighting strategy corresponding to the load evaluation window duration to obtain the aggregated load value corresponding to the load evaluation window duration.

[0119] Optionally, as an embodiment, the second determining module 704 is specifically used to calculate the sum of the aggregated load values ​​corresponding to all load assessment window durations to obtain the total load demand value; and to determine the target operating frequency of the processor based on the total load demand value, the maximum computing power capacity of the processor, and the processor operating frequency corresponding to the maximum computing power capacity.

[0120] The processor scheduling device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the scope of the device.

[0121] The processor scheduling device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0122] The processor scheduling device provided in this application embodiment can achieve the above-mentioned... Figure 1 To avoid repetition, the various processes implemented in the method embodiment shown will not be described again here.

[0123] Optionally, such as Figure 8 As shown, this application embodiment also provides an electronic device 800, including a processor 801 and a memory 802. The memory 802 stores a program or instructions that can run on the processor 801. When the program or instructions are executed by the processor 801, they implement the various steps of the processor scheduling method embodiment described above and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0124] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0125] Figure 9 This is a schematic diagram of the hardware structure of an electronic device that implements the various embodiments of this application.

[0126] The electronic device 900 includes, but is not limited to, components such as: radio frequency unit 901, network module 902, audio output unit 903, input unit 904, sensor 905, display unit 906, user input unit 907, interface unit 908, memory 909, and processor 910.

[0127] Those skilled in the art will understand that the electronic device 900 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 910 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 9 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0128] In some embodiments, the processor 910 is configured to acquire the job cycles of multiple tasks to be scheduled; determine the load assessment window duration corresponding to each task based on the job cycle; perform load statistics on the tasks with the same load assessment window duration using the load assessment window duration as a statistical period to obtain the aggregate load value corresponding to each load assessment window duration; and determine the target operating frequency of the processor based on the aggregate load value corresponding to all load assessment window durations.

[0129] As can be seen, in this embodiment of the application, by identifying and distinguishing the job cycle characteristics of different tasks, allocating appropriate load assessment windows to each task, and performing independent load statistics and multi-window fusion decision-making for tasks with the same load assessment window, it is possible to simultaneously and accurately meet the energy efficiency and stability requirements of low-frequency tasks and the instantaneous response requirements of high-frequency tasks. This solves the performance and power consumption imbalance problem caused by the mismatch between fixed windows and mixed loads, thereby improving the overall energy efficiency and user experience of electronic devices in complex concurrent scenarios.

[0130] Optionally, as an embodiment, the processor 910 is specifically configured to, for a task with a known work cycle, obtain a preset cycle value of the task as the work cycle; for a task with an unknown work cycle, collect the timestamp sequence of the task during multiple consecutive wake-ups, calculate the coefficient of variation of the wake-up interval corresponding to the timestamp sequence, and if the coefficient of variation is less than or equal to a preset threshold, determine that the task is a periodic task, and determine the average value of the wake-up interval as the work cycle of the task.

[0131] Optionally, as an embodiment, the processor 910 is specifically configured to, for each task, map the task's job cycle to the largest of a predefined plurality of discrete duration levels that is not greater than the job cycle; and determine the value of the mapped discrete duration level as the load assessment window duration corresponding to the task.

[0132] Optionally, as an embodiment, the processor 910 is specifically configured to perform load statistics at a fixed basic sampling period. Within each basic sampling period, based on the effective execution time of each task on the processor and the computing power capacity of the processor during the effective execution time, the processor determines the normalized load contribution value of each task within the basic sampling period; determines the number N of consecutive basic sampling periods contained in the statistical period corresponding to each load evaluation window duration; for each load evaluation window duration, the processor calculates the sum of the normalized load contribution values ​​of all tasks with the same load evaluation window duration in the most recent N consecutive basic sampling periods, obtaining the total load of the N periods within the load evaluation window duration; and performs a weighted calculation on the total load of the N periods within the load evaluation window duration according to the weighting strategy corresponding to the load evaluation window duration, obtaining the aggregated load value corresponding to the load evaluation window duration.

[0133] Optionally, as an embodiment, the processor 910 is specifically used to calculate the sum of the aggregated load values ​​corresponding to all load assessment window durations to obtain the total load demand value; and to determine the target operating frequency of the processor based on the total load demand value, the processor's maximum computing power capacity, and the processor operating frequency corresponding to the maximum computing power capacity.

[0134] It should be understood that, in this embodiment, the input unit 904 may include a graphics processing unit (GPU) 9041 and a microphone 9042. The GPU 9041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 906 may include a display panel 9061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 907 includes at least one of a touch panel 9071 and other input devices 9072. The touch panel 9071 is also called a touch screen. The touch panel 9071 may include a touch detection device and a touch controller. Other input devices 9072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0135] The memory 909 can be used to store software programs and various data. The memory 909 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 909 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (Synchlink DRAM, SLDRAM), and direct memory bus RAM (DRRAM). The memory 909 in the embodiments of this application includes, but is not limited to, these and any other suitable types of memory.

[0136] Processor 910 may include one or more processing units; optionally, processor 910 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 910.

[0137] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the processor scheduling method embodiments described above and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0138] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0139] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the processor scheduling method embodiment described above, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0140] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0141] This application provides a computer program product that is stored in a storage medium and executed by at least one processor to implement the various processes described in the processor scheduling method embodiments above, and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0142] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0143] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0144] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A processor scheduling method, characterized in that, The method includes: Obtain the job cycle of each of the multiple tasks to be scheduled; Based on the job cycle, determine the load assessment window duration for each task; Using the load assessment window duration as the statistical period, load statistics are performed on the tasks with the same load assessment window duration to obtain the aggregated load value corresponding to each load assessment window duration; The target operating frequency of the processor is determined based on the aggregated load value corresponding to the duration of all load assessment windows.

2. The method according to claim 1, characterized in that, The step of obtaining the job cycle of each of the multiple tasks to be scheduled includes: For tasks with a known work cycle, obtain the preset cycle value of the task as the work cycle; For tasks with unknown work cycles, timestamp sequences of the task during multiple consecutive wake-ups are collected, and the coefficient of variation of the wake-up interval corresponding to the timestamp sequence is calculated. If the coefficient of variation is less than or equal to a preset threshold, the task is determined to be a periodic task, and the average value of the wake-up interval is determined as the work cycle of the task.

3. The method according to claim 1, characterized in that, The step of determining the load assessment window duration for each task based on the job cycle includes: For each task, the task's work cycle is mapped to a predefined set of discrete duration levels that is no greater than the maximum work cycle level. The value of the discrete duration level to which it is mapped is determined as the load assessment window duration corresponding to the task.

4. The method according to claim 1, characterized in that, The step of using the load assessment window duration as the statistical period, performing load statistics on tasks with the same load assessment window duration to obtain the aggregated load value corresponding to each load assessment window duration includes: Load statistics are performed with a fixed basic sampling period. Within each basic sampling period, the normalized load contribution value of each task within the basic sampling period is determined based on the effective execution time of each task on the processor and the computing power capacity of the processor during the effective execution time. Determine the number N of consecutive basic sampling periods contained in the statistical period corresponding to each load assessment window duration; For each load assessment window duration, calculate the sum of the normalized load contribution values ​​of all tasks with the same load assessment window duration in each of the most recent N consecutive basic sampling periods, to obtain the total load of the N periods within the load assessment window duration. Based on the weighting strategy corresponding to the load assessment window duration, the total load of N cycles within the load assessment window duration is weighted and calculated to obtain the aggregated load value corresponding to the load assessment window duration.

5. The method according to any one of claims 1 to 4, characterized in that, The step of determining the processor's target operating frequency based on the aggregated load value corresponding to all load assessment window durations includes: Calculate the sum of the aggregated load values ​​corresponding to all load assessment window durations to obtain the total load demand value; The target operating frequency of the processor is determined based on the total load requirement, the maximum computing power capacity of the processor, and the processor operating frequency corresponding to the maximum computing power capacity.

6. A processor scheduling device, characterized in that, The device includes: The acquisition module is used to acquire the job cycle of each of the multiple tasks to be scheduled. The first determining module is used to determine the load assessment window duration for each task based on the job cycle. The statistics module is used to perform load statistics on the tasks with the same load assessment window duration, using the load assessment window duration as the statistical period, and to obtain the aggregate load value corresponding to each load assessment window duration. The second determining module is used to determine the target operating frequency of the processor based on the aggregated load value corresponding to the duration of all load evaluation windows.

7. The apparatus according to claim 6, characterized in that, The acquisition module is specifically used to acquire a preset cycle value of a task as its work cycle for a task with a known work cycle; for a task with an unknown work cycle, it collects the timestamp sequence of the task during multiple consecutive wake-ups, calculates the coefficient of variation of the wake-up interval corresponding to the timestamp sequence, and if the coefficient of variation is less than or equal to a preset threshold, it determines that the task is a periodic task and determines the average value of the wake-up interval as the work cycle of the task.

8. The apparatus according to claim 6, characterized in that, The first determining module is specifically used to map the job cycle of each task to the maximum value of the job cycle among a plurality of predefined discrete duration levels; and to determine the value of the mapped discrete duration level as the load assessment window duration corresponding to the task.

9. The apparatus according to claim 6, characterized in that, The statistics module is specifically used to perform load statistics at a fixed basic sampling period. Within each basic sampling period, based on the effective execution time of each task on the processor and the computing power capacity of the processor during the effective execution time, the normalized load contribution value of each task within the basic sampling period is determined. The number N of consecutive basic sampling periods included in the statistical period corresponding to each load evaluation window duration is determined. For each load evaluation window duration, the sum of the normalized load contribution values ​​of all tasks with the same load evaluation window duration in the most recent N consecutive basic sampling periods is calculated to obtain the total load of the N periods within the load evaluation window duration. According to the weighting strategy corresponding to the load evaluation window duration, the total load of the N periods within the load evaluation window duration is weighted and calculated to obtain the aggregated load value corresponding to the load evaluation window duration.

10. The apparatus according to any one of claims 6 to 9, characterized in that, The second determining module is specifically used to calculate the sum of the aggregated load values ​​corresponding to all load assessment window durations to obtain the total load demand value; and to determine the target operating frequency of the processor based on the total load demand value, the maximum computing power capacity of the processor, and the processor operating frequency corresponding to the maximum computing power capacity.

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